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stupid-zwl
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rtlmul

Safetensors
code
verilog
RTL
PPA-prediction
hardware-design
Model card Files
xet
 Community
rtlmul

Commit History

  1. Update README.md

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  2. Upload folder using huggingface_hub

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  3. Update README.md

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  4. Update README.md

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  1. Upload 42 files

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  2. Update README.md

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  3. initial commit

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