CLIPSeg model resources

按英文目标描述分割图片，返回原图大小的掩码和完整特征。

Board builds that Agora runs and measures on real Qualcomm boards. Try it online, without a board: https://mega.aidlux.com/models/clipseg

SoC · board	Precisions	Measured on Agora (default precision)
QCS8550 · 犀牛派 X1 (Rhino Pi X1)	W8A16	61.0 ms
QCS6490 · 犀牛派 A1 (Rhino Pi A1)	W8A16	211.0 ms

Task: 分割. Inputs: image (image), text (text). Outputs: masks (masks), out (json).

Download

export AGORA_WORKSPACE="$HOME/my-clipseg"
export AGORA_SOC='QCS8550'
hf download APLUX-Agora/CLIPSeg \
  --include "targets/$AGORA_SOC/*" --local-dir "$AGORA_WORKSPACE/resources"

Each targets/<SoC>/ holds model.json (default precision and variant paths) and one directory per precision. Context binaries are named model.bin; multi-file packages are kept as published by Model Farm.

Pre- and post-processing, the runner and an exported project: open the model on Agora and choose “部署指南”, or export any workflow that uses it.

Licence and provenance

Source model licence: see the original model's terms. Converted, deployable resources: APLUX Model Farm License (LICENSE_MODEL_FARM.pdf). See NOTICE.md and SHA256SUMS.

Downloads last month: -; Downloads are not tracked for this model. How to track