Experimentlab/olmo2-7b-silicon-rtl-eda

⚡ Vigyan-7B-Silicon-RTL-EDA: Semiconductor & Verilog Specialist

Vigyan-7B-Silicon-RTL-EDA is a domain-specialized Low-Rank Adaptation (LoRA) adapter built upon AllenAI's open-weights OLMo-2-1124-7B architecture. It is fine-tuned specifically for Electronic Design Automation (EDA), register-transfer level (RTL) Verilog synthesis, and formal verification assertions.

🛠️ Specialized Capabilities

• Verilog & SystemVerilog Generation: Synthesizable FSMs, pipelines, ALU designs, and asynchronous FIFO logic.
• Formal Verification (SVA): Generating IEEE 1800 SystemVerilog Assertions to prove clock domain crossing (CDC) safety, Gray code single-bit transitions, and bus protocol adherence.
• Timing & Synthesis Scripts: TCL scripting for open-source EDA tools (Yosys, OpenROAD).

🚀 Quickstart

from peft import PeftModel
from transformers import AutoModelForCausalLM, AutoTokenizer

base_model = "allenai/OLMo-2-1124-7B"
model = AutoModelForCausalLM.from_pretrained(base_model, torch_dtype="auto", device_map="auto")
model = PeftModel.from_pretrained(model, "shreyansh12183/olmo2-7b-silicon-rtl-eda")
tokenizer = AutoTokenizer.from_pretrained(base_model)