Renesas/BEVLaneDet-ONNX

BEVLaneDet (ONNX) – Renesas X5H

Introduction

This repository hosts BEVLaneDet, a bird's-eye-view (BEV) 3D lane-detection model, targeting the Renesas R-Car X5H platform for inference on the NPX6 NPU.

• Model Architecture: BEV-LaneDet — a single front-camera 3D lane detector that lifts front-view image features into BEV space via a learned spatial transformation ("Virtual Camera" + Spatial Transformation Pyramid), then detects lanes with a Key-Points Representation (KPR) head.
• Paper: BEV-LaneDet: An Efficient 3D Lane Detection Based on Virtual Camera via Key-Points (Wang et al., CVPR 2023; arXiv:2210.06006)
• Source Model / Repo: gigo-team/bev_lane_det

Important caveat: the official repository's source code is withheld by the authors ("closed due to intellectual property protection" per the repo's own README), and GitHub reports no license for the repo. This documentation is based on the published paper only — the exact checkpoint, backbone variant (the paper ablates both ResNet-18 and ResNet-34), training dataset, and license behind this specific export could not be independently verified and are marked TBD rather than guessed.

• Task: 3D Lane Detection (bird's-eye-view)
• Parameters: TBD — not published; source code withheld by the authors
• License: TBD — no license published on the official repository

Deployment Flow

The FP32 ONNX model is auto-cast to INT8 by the Renesas MWMX toolchain at compile time — no separate quantization step is required.

bev_lane_det_..._optimized.onnx (FP32)
        │
        └─▶  MWMX Runtime  ──▶  INT8 auto-cast  ──▶  NPX6 NPU

Provided Artifacts

Artifact	Status	Notes
FP32 (ONNX)	✅	fp32/bev_lane_det.onnx — FP32 ONNX export

Performance

Measured on Renesas R-Car X5H via the MWMX runtime (APM50 ship-performance CI pipeline).

Benchmark configuration: Single NPU · Batch size: 1 · Input resolution: 576×1024 (NCHW 1,3,576,1024)

Runtime	Precision	Device	Latency (ms)	Type
MWMX Runtime	INT8 (auto)	X5H · 1× NPU · 1 Core · 850 MHz	26.909782	Measured

Accuracy

TBD — not yet measured/published for this repo.

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Runtime Details

MWMX Runtime

• Engine: Renesas MWMX (Middleware MX) native inference runtime
• Input format: FP32 ONNX (compiled by the MWMX toolchain)
• NPU execution precision: INT8 (auto-cast by MWMX toolchain)
• Execution target: NPX6-48K NPU on R-Car X5H

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Prerequisites

To run inference on Renesas R-Car X5H, you need:

1. Renesas R-Car X5H board with NPX6 NPU
2. Renesas MWMX Runtime
3. Hugging Face CLI to download the model
4. A front-facing camera pipeline delivering 576×1024 RGB frames

Download

hf download Renesas/BEVLaneDet-ONNX --repo-type=model --include "fp32/*"

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Benchmark Methodology

• HIL runs: Hardware-in-the-loop — measured on physical R-Car X5H silicon via the MWMX runtime (metawaremx_runtime CI pipeline, "APM50" ship-performance target)
• Precision: FP32 ONNX input; INT8 execution (auto-cast by MWMX)
• Slices: only the 1 AI-core slice is available; the 12-core slice was Skipped in the source APM50 CI run for this model