Renesas/EfficientNet-B4-ONNX

EfficientNet-B4 (ONNX) – Renesas X5H

Introduction

This repository hosts EfficientNet-B4, targeting the Renesas R-Car X5H platform for image classification inference on the NPX6 NPU.

Note: The other EfficientNet sizes (B0-B3, B5-B8) each have their own sibling repo.

• Model Architecture: EfficientNet — compound-scaled convolutional network for 1000-class image classification
• Source Model: timm/tf_efficientnet_b4.ns_jft_in1k — OpenMMLab config efficientnet_b4_3rdparty_ra_noisystudent_in1k
• Task: Image Classification (ImageNet-1k, 1000 classes)
• Parameters: 19M (published EfficientNet-B4 figure (Tan & Le 2019))

Deployment Flow

The FP32 ONNX model is auto-cast to INT8 by the Renesas MWMX toolchain at compile time — no separate quantization step is required.

efficientnet_b4_3rdparty_ra_noisystudent_in1k_..._optimized.onnx (FP32)
        │
        └─▶  MWMX Runtime  ──▶  INT8 auto-cast  ──▶  NPX6 NPU

Provided Artifacts

Artifact	Status	Notes
FP32 (ONNX)	✅	fp32/efficientnet-b4_3rdparty-ra-noisystudent_in1k.onnx — FP32 ONNX export

Performance

Measured on Renesas R-Car X5H via the MWMX runtime (APM50 ship-performance CI pipeline).

Benchmark configuration: Single NPU · Batch size: 1 · Input resolution: not available from source data (TBD)

Runtime	Precision	Device	Latency (ms)	Type
MWMX Runtime	INT8 (auto)	X5H · 1× NPU · 1 Core · 850 MHz	20.210845	Measured
MWMX Runtime	INT8 (auto)	X5H · 1× NPU · 12 Cores · 850 MHz	13.338765	Measured

Accuracy

TBD — not yet measured/published for this repo.

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Runtime Details

MWMX Runtime

• Engine: Renesas MWMX (Middleware MX) native inference runtime
• Input format: FP32 ONNX (compiled by the MWMX toolchain)
• NPU execution precision: INT8 (auto-cast by MWMX toolchain)
• Execution target: NPX6-48K NPU on R-Car X5H

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Prerequisites

To run inference on Renesas R-Car X5H, you need:

1. Renesas R-Car X5H board with NPX6 NPU
2. Renesas MWMX Runtime
3. Hugging Face CLI to download the model

Download

hf download Renesas/EfficientNet-B4-ONNX --repo-type=model --include "fp32/*"

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Benchmark Methodology

• HIL runs: Hardware-in-the-loop — measured on physical R-Car X5H silicon via the MWMX runtime (metawaremx_runtime CI pipeline, "APM50" ship-performance target)
• Precision: FP32 ONNX input; INT8 execution (auto-cast by MWMX)
• Slices: results reported for both 1 AI core and 12 AI cores per NPU instance