Renesas/EfficientNet-Lite2-ONNX

EfficientNet-Lite2 (ONNX) – Renesas X5H

Introduction

This repository hosts EfficientNet-Lite2, targeting the Renesas R-Car X5H platform for image classification inference on the NPX6 NPU.

Note: EfficientNet-Lite is Google's TF-optimized variant of EfficientNet (no SE blocks, ReLU6, fixed stem/head) — an architecturally distinct family from the standard EfficientNet (V1) repos already in this collection (EfficientNet-B0-ONNX etc.). See also the sibling repo EfficientNet-Lite0-ONNX.

Resolution discrepancy note: the upstream timm/tf_efficientnet_lite2.in1k checkpoint's published native/test resolution is 260×260, but the GF benchmark run documented below was executed at 224×224. This is reported as-measured from the source benchmark export without correction — actual accuracy at 224×224 would differ from the checkpoint's published ImageNet numbers (which were measured at 260×260).

• Model Architecture: EfficientNet-Lite2 — TF-optimized, SE-free, ReLU6 compound-scaled convolutional network for 1000-class image classification
• Source Model: timm/tf_efficientnet_lite2.in1k
• Task: Image Classification (ImageNet-1k, 1000 classes)
• Parameters: 6.1M (timm model card: Params (M): 6.1, GMACs: 0.9)

Deployment Flow

The FP32 ONNX model is auto-cast to INT8 by the Renesas MWMX toolchain at compile time — no separate quantization step is required.

tf_efficientnet_lite2_..._optimized.onnx (FP32)
        │
        └─▶  MWMX Runtime  ──▶  INT8 auto-cast  ──▶  NPX6 NPU

Provided Artifacts

Artifact	Status	Notes
FP32 (ONNX)	✅	fp32/tf_efficientnet_lite2.onnx — FP32 ONNX export

Performance

Measured on Renesas R-Car X5H via the MWMX runtime (APM50 ship-performance CI pipeline).

Benchmark configuration: Single NPU · Single AI Core · Batch size: 1 · Input: 3 × 224 × 224 (below this checkpoint's published native/test resolution of 260 × 260 — see note above).

Runtime	Precision	Device	Latency (ms)	Type
MWMX Runtime	INT8 (auto)	X5H · 1× NPU · 1 Core · 850 MHz	1.499615	Measured

Only the 1-AI-core slice was run for this model in the source benchmark export — the 12-core slice was skipped, so no 12-core row is reported here.

Accuracy

TBD — not yet measured/published for this repo.

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Runtime Details

MWMX Runtime

• Engine: Renesas MWMX (Middleware MX) native inference runtime
• Input format: FP32 ONNX (compiled by the MWMX toolchain)
• NPU execution precision: INT8 (auto-cast by MWMX toolchain)
• Execution target: NPX6-48K NPU on R-Car X5H

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Prerequisites

To run inference on Renesas R-Car X5H, you need:

1. Renesas R-Car X5H board with NPX6 NPU
2. Renesas MWMX Runtime
3. Hugging Face CLI to download the model

Download

hf download Renesas/EfficientNet-Lite2-ONNX --repo-type=model --include "fp32/*"

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Benchmark Methodology

• HIL runs: Hardware-in-the-loop — measured on physical R-Car X5H silicon via the MWMX runtime (metawaremx_runtime CI pipeline, "APM50" ship-performance target)
• Precision: FP32 ONNX input; INT8 execution (auto-cast by MWMX)
• Slices: only the 1 AI core slice was run for this model; the 12-core slice was skipped in the source export