Renesas/EfficientNetV2-B2-ONNX

EfficientNetV2-B2 (ONNX) – Renesas X5H

Introduction

This repository hosts EfficientNetV2-B2, targeting the Renesas R-Car X5H platform for image classification inference on the NPX6 NPU.

Note: The other EfficientNetV2 sizes each have their own sibling repo (EfficientNetV2-B0-ONNX … EfficientNetV2-B3-ONNX), matching the EfficientNet V1 layout. This is a different architecture from EfficientNet (V1).

• Model Architecture: EfficientNetV2-B2
• Source Model: timm/tf_efficientnetv2_b2.in1k — OpenMMLab config efficientnetv2-b2_3rdparty_in1k
• Task: Image Classification (ImageNet-1k, 1000 classes)
• Input Resolution: 260 × 260
• Parameters: 10.1M (published EfficientNetV2-B2 figure)

Deployment Flow

The FP32 ONNX model is auto-cast to INT8 by the Renesas MWMX toolchain at compile time — no separate quantization step is required.

model.onnx (FP32)
        │
        └─▶  MWMX Runtime  ──▶  INT8 auto-cast  ──▶  NPX6 NPU

Provided Artifacts

Artifact	Status	Notes
FP32 (ONNX)	✅	fp32/efficientnetv2-b2_3rdparty_in1k.onnx — FP32 ONNX export

Performance

Measured on Renesas R-Car X5H via the MWMX runtime (APM50 ship-performance CI pipeline).

Benchmark configuration: Single NPU · Batch size: 1 · Input resolution: [1, 3, 224, 224]

Runtime	Precision	Device	Latency (ms)	Type
MWMX Runtime	INT8 (auto)	X5H · 1× NPU · 12 Cores · 850 MHz	4.300261	Measured
MWMX Runtime	INT8 (auto)	X5H · 1× NPU · 1 Core · 850 MHz	4.379195	Measured

Accuracy

TBD — not yet measured/published for this repo.

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Runtime Details

MWMX Runtime

• Engine: Renesas MWMX (Middleware MX) native inference runtime
• Input format: FP32 ONNX (compiled by the MWMX toolchain)
• NPU execution precision: INT8 (auto-cast by MWMX toolchain)
• Execution target: NPX6-48K NPU on R-Car X5H

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Prerequisites

To run inference on Renesas R-Car X5H, you need:

1. Renesas R-Car X5H board with NPX6 NPU
2. Renesas MWMX Runtime
3. Hugging Face CLI to download the model

Download

hf download Renesas/EfficientNetV2-B2-ONNX --repo-type=model --include "fp32/*"

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Benchmark Methodology

• HIL runs: Hardware-in-the-loop — measured on physical R-Car X5H silicon via the MWMX runtime (metawaremx_runtime CI pipeline, "APM50" ship-performance target)
• Precision: FP32 ONNX input; INT8 execution (auto-cast by MWMX)
• Slices: results are reported per NPU core count where both runs compiled