Renesas/ResNet50-C-ONNX

ResNet50-C (ONNX) – Renesas X5H

Introduction

This repository hosts ResNet50-C, targeting the Renesas R-Car X5H platform for image classification inference on the NPX6 NPU.

Distinct from ResNet50-ONNX: the existing ResNet50-ONNX repo in this collection documents onnxmodelzoo/resnet50-v1-12 — the plain ResNet-50 with the original single 7×7 stem convolution. This repo instead documents the "C" deep-stem variant, which replaces that single 7×7 convolution with three stacked 3×3 convolutions (the "ResNet-C" tweak from the "Bag of Tricks" paper). The two are architecturally different at the stem, and are expected to have slightly different compute/latency characteristics — this repo's measured 1-core latency (3.638507 ms) is indeed marginally higher than ResNet50-ONNX's 1-core MWMX latency (3.23 ms), which is consistent with (but does not by itself prove) the heavier 3-conv stem.

Source not fully confirmed: the compile-artifact filename in the source benchmark export (resnet50c_quantization_config.json) confirms the depth is 50 and the stem variant is "C", but the exact upstream repository/framework that produced this specific ONNX checkpoint (e.g. pytorchcv, GluonCV's resnet50_v1c, PaddleClas, or an internal export) could not be confidently identified via research for this page. The Source Model link below is therefore TBD — only the architectural definition (via the published paper) is confirmed.

• Model Architecture: ResNet-50 with the "C" deep-stem tweak — three 3×3 convolutions replacing the original 7×7 stem convolution, as defined in "Bag of Tricks for Image Classification with Convolutional Neural Networks" (He et al., CVPR 2019, arXiv:1812.01187)
• Source Model: TBD — not confirmed (see note above); architecture reference only: arXiv:1812.01187
• Task: Image Classification (ImageNet-1k, 1000 classes)
• Parameters: ~25.6M (approximate — the stem tweak does not materially change ResNet-50's parameter count; Bag of Tricks paper Table 5 reports ResNet-50-C at ~25M params, 4.3 GFLOPs)
• License: TBD — no confirmed upstream checkpoint/repository to attribute a license to.

Deployment Flow

The FP32 ONNX model is auto-cast to INT8 by the Renesas MWMX toolchain at compile time — no separate quantization step is required.

resnet50c_..._optimized.onnx (FP32)
        │
        └─▶  MWMX Runtime  ──▶  INT8 auto-cast  ──▶  NPX6 NPU

Provided Artifacts

Artifact	Status	Notes
FP32 (ONNX)	✅	fp32/resnet50c.onnx — FP32 ONNX export

Performance

Measured on Renesas R-Car X5H via the MWMX runtime (APM50 ship-performance CI pipeline).

Benchmark configuration: Single NPU · Single AI Core · Batch size: 1 · Input: 3 × 224 × 224

Runtime	Precision	Device	Latency (ms)	Type
MWMX Runtime	INT8 (auto)	X5H · 1× NPU · 1 Core · 850 MHz	3.638507	Measured

Only the 1-AI-core slice was run for this model in the source benchmark export — the 12-core slice was skipped, so no 12-core row is reported here. For reference, ResNet50-ONNX (plain 7×7-stem ResNet-50) measures 3.23 ms under the same MWMX/1-core/850 MHz configuration.

Accuracy

TBD — not yet measured/published for this repo.

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Runtime Details

MWMX Runtime

• Engine: Renesas MWMX (Middleware MX) native inference runtime
• Input format: FP32 ONNX (compiled by the MWMX toolchain)
• NPU execution precision: INT8 (auto-cast by MWMX toolchain)
• Execution target: NPX6-48K NPU on R-Car X5H

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Prerequisites

To run inference on Renesas R-Car X5H, you need:

1. Renesas R-Car X5H board with NPX6 NPU
2. Renesas MWMX Runtime
3. Hugging Face CLI to download the model

Download

hf download Renesas/ResNet50-C-ONNX --repo-type=model --include "fp32/*"

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Benchmark Methodology

• HIL runs: Hardware-in-the-loop — measured on physical R-Car X5H silicon via the MWMX runtime (metawaremx_runtime CI pipeline, "APM50" ship-performance target)
• Precision: FP32 ONNX input; INT8 execution (auto-cast by MWMX)
• Slices: only the 1 AI core slice was run for this model; the 12-core slice was skipped in the source export