羲和 HeliosLM HDL E4B
發佈者 Published by: Bitstar Inc.
羲和 HDL E4B 是以 Google Gemma 4 E4B-it 為基礎、針對 Verilog / SystemVerilog 硬體設計調整的模型。用途是寫 RTL、修改既有 RTL、依錯誤訊息或測試結果修 bug。
HeliosLM HDL E4B is a model for Verilog / SystemVerilog hardware design, based on Google Gemma 4 E4B-it. It is meant for writing RTL, editing existing RTL, and fixing bugs from compiler messages or failing test logs.
- 參數量 Parameters: about 8B (Gemma 4 E4B architecture, text only)
- 授權 License: Apache-2.0, same as Google Gemma 4
- 單張 16 GB 以上 GPU 可跑 bf16；8 GB 顯卡請用 GGUF 版 helioslm-hdl-e4b-GGUF。 bf16 runs on one 16 GB+ GPU; for 8 GB cards use the GGUF build linked above.
怎麼做的 How it was made
在 Gemma 4 E4B 上，用公開、可合成的 Verilog / SystemVerilog 專案做持續訓練與強化學習（以模擬測試結果當獎勵）。
把上一步與 Gemma 4 E4B 的差異，以 0.5 倍加回 Gemma 4 E4B-it（chat vector），保留原本的對話與指令能力。
再用 LoRA 做一輪小規模微調，資料是「修改既有 RTL」與「依錯誤訊息修 bug」的練習題，以及 Verilog 題目與解答。最後把 LoRA 合併進權重。
Continued training and reinforcement learning (simulation pass/fail as reward) on Gemma 4 E4B with public, synthesizable Verilog / SystemVerilog projects.
The difference from Gemma 4 E4B was added back to Gemma 4 E4B-it at 0.5x (chat vector), keeping its instruction-following ability.
A small LoRA fine-tune on RTL-editing and bug-fixing exercises plus Verilog instruction data, merged into the weights.
訓練資料 Training data (all public):
- OpenTitan (Apache-2.0), Ibex and CV32E40P (Solderpad) RTL. 編輯／修 bug 練習題是從這些程式自動產生的。Editing and bug-fix exercises were generated automatically from this code.
- 公開 GitHub Verilog / SystemVerilog 專案（The Stack 中寬鬆授權的部分，以及公開的 Verilog GitHub 資料集），只收通過 Verilator lint 與 Yosys 合成的專案。Public GitHub HDL projects (the permissively licensed part of The Stack and a public Verilog GitHub corpus), kept only when they pass Verilator lint and Yosys synthesis.
- 我們自己以 Apache-2.0 公開的 IP / VIP 程式。Our own IP / VIP code published under Apache-2.0.
- CodeV-R1-dataset (CC-BY-SA-4.0) Verilog instruction data.
評測用的題目（VerilogEval、RTLLM、CVDP 及我們保留的 OpenTitan 測試題）已從訓練資料中排除。 Benchmark problems (VerilogEval, RTLLM, CVDP and our held-out OpenTitan tasks) were removed from the training data.
使用方式 Usage
from transformers import AutoModelForCausalLM, AutoTokenizer
name = "chienhsinlin/helioslm-hdl-e4b"
tok = AutoTokenizer.from_pretrained(name)
model = AutoModelForCausalLM.from_pretrained(name, dtype="bfloat16", device_map="auto")
msgs = [{"role": "user", "content": "Write a synthesizable Verilog module for a 4-bit up/down counter with synchronous reset."}]
ids = tok.apply_chat_template(msgs, add_generation_prompt=True, return_tensors="pt").to(model.device)
out = model.generate(ids, max_new_tokens=2048, do_sample=False)
print(tok.decode(out[0][ids.shape[1]:], skip_special_tokens=True))
vLLM: vllm serve chienhsinlin/helioslm-hdl-e4b --max-model-len 16384
建議 Tips:
- 修 bug 時，把整個模組原始碼和錯誤訊息／測試 log 一起貼上，並要求輸出完整模組。Paste the whole module plus the error message or failing log, and ask for the complete fixed module.
- 產生的 RTL 一定要用自己的模擬與合成流程驗證。Always check generated RTL with your own simulation and synthesis flow.
限制 Limitations
- 這是 HDL 專用模型，不適合一般聊天或事實問答。It is specialized for HDL and is not meant for general chat or factual Q&A.
- 對完整 UVM 測試平台、UPF 低功耗描述、從規格一次寫出大型 IP，能力仍有限。Full UVM testbenches, UPF power intent and writing a large IP from a spec in one pass are still weak.
- 輸出可能有語法或功能錯誤，請勿未經驗證直接用於量產設計。Outputs can contain syntax or functional errors; do not use them in production silicon without verification.
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