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Datasets:
AbiralArch
/
hardware-cvdp-examples
Like
0
Tasks:
Text Generation
Languages:
code
Size:
1K<n<10K
Tags:
hardware
rtl
verilog
systemverilog
fpga
asic
+ 2
Dataset card
Files
Files and versions
xet
Community
main
hardware-cvdp-examples
/
analysis.json
Commit History
Aug 1, 2025
03:53
Upload analysis.json with huggingface_hub
AbiralArch
Verified signature
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