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Datasets:
AbiralArch
/
verilog-training-data
Like
1
Tasks:
Text Generation
Languages:
English
Size:
1K<n<10K
Tags:
verilog
hardware-design
hdl
fpga
asic
Dataset card
Files
Files and versions
xet
Community
main
verilog-training-data
/
cvdp_processor_problems.json
Commit History
Aug 1, 2025
03:40
Upload cvdp_processor_problems.json with huggingface_hub
AbiralArch
Verified signature
1314969
