Archive original Arduino development files (part 5)

.gitattributes

@@ -128,3 +128,9 @@ hardware/tools/avr/avr/bin/objdump.exe filter=lfs diff=lfs merge=lfs -text
 hardware/tools/avr/avr/bin/ranlib.exe filter=lfs diff=lfs merge=lfs -text
 hardware/tools/avr/avr/bin/readelf.exe filter=lfs diff=lfs merge=lfs -text
 hardware/tools/avr/avr/bin/strip.exe filter=lfs diff=lfs merge=lfs -text
+hardware/tools/avr/avr/lib/avr25/libc.a filter=lfs diff=lfs merge=lfs -text
+hardware/tools/avr/avr/lib/avr25/tiny-stack/libc.a filter=lfs diff=lfs merge=lfs -text
+hardware/tools/avr/avr/lib/avr3/libc.a filter=lfs diff=lfs merge=lfs -text
+hardware/tools/avr/avr/lib/avr31/libc.a filter=lfs diff=lfs merge=lfs -text
+hardware/tools/avr/avr/lib/avr35/libc.a filter=lfs diff=lfs merge=lfs -text
+hardware/tools/avr/avr/lib/avr4/libc.a filter=lfs diff=lfs merge=lfs -text

hardware/tools/avr/avr/include/avr/iotn5.h

@@ -0,0 +1,512 @@
+/* Copyright (c) 2009 Atmel Corporation
+   All rights reserved.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+
+   * Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+
+   * Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in
+     the documentation and/or other materials provided with the
+     distribution.
+
+   * Neither the name of the copyright holders nor the names of
+     contributors may be used to endorse or promote products derived
+     from this software without specific prior written permission.
+
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+  POSSIBILITY OF SUCH DAMAGE. */
+
+/* $Id: iotn5.h 2063 2009-11-18 22:06:28Z arcanum $ */
+
+/* avr/iotn5.h - definitions for ATtiny5 */
+
+/* This file should only be included from <avr/io.h>, never directly. */
+
+#ifndef _AVR_IO_H_
+#  error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+#  define _AVR_IOXXX_H_ "iotn5.h"
+#else
+#  error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif 
+
+
+#ifndef _AVR_ATtiny5_H_
+#define _AVR_ATtiny5_H_ 1
+
+
+/* Registers and associated bit numbers. */
+
+#define PINB _SFR_IO8(0x00)
+#define PINB0 0
+#define PINB1 1
+#define PINB2 2
+#define PINB3 3
+
+#define DDRB _SFR_IO8(0x01)
+#define DDB0 0
+#define DDB1 1
+#define DDB2 2
+#define DDB3 3
+
+#define PORTB _SFR_IO8(0x02)
+#define PORTB0 0
+#define PORTB1 1
+#define PORTB2 2
+#define PORTB3 3
+
+#define PUEB _SFR_IO8(0x03)
+#define PUEB0 0
+#define PUEB1 1
+#define PUEB2 2
+#define PUEB3 3
+
+#define PORTCR _SFR_IO8(0x0C)
+#define BBMB 1
+
+#define PCMSK _SFR_IO8(0x10)
+#define PCINT0 0
+#define PCINT1 1
+#define PCINT2 2
+#define PCINT3 3
+
+#define PCIFR _SFR_IO8(0x11)
+#define PCIF0 0
+
+#define PCICR _SFR_IO8(0x12)
+#define PCIE0 0
+
+#define EIMSK _SFR_IO8(0x13)
+#define INT0 0
+
+#define EIFR _SFR_IO8(0x14)
+#define INTF0 0
+
+#define EICRA _SFR_IO8(0x15)
+#define ISC00 0
+#define ISC01 1
+
+#define DIDR0 _SFR_IO8(0x17)
+#define ADC0D 0
+#define AIN0D 0
+#define ADC1D 1
+#define AIN1D 1
+#define ADC2D 2
+#define ADC3D 3
+
+#define ADCL _SFR_IO8(0x19)
+#define ADC0 0
+#define ADC1 1
+#define ADC2 2
+#define ADC3 3
+#define ADC4 4
+#define ADC5 5
+#define ADC6 6
+#define ADC7 7
+
+#define ADMUX _SFR_IO8(0x1B)
+#define MUX0 0
+#define MUX1 1
+
+#define ADCSRB _SFR_IO8(0x1C)
+#define ADTS0 0
+#define ADTS1 1
+#define ADTS2 2
+
+#define ADCSRA _SFR_IO8(0x1D)
+#define ADPS0 0
+#define ADPS1 1
+#define ADPS2 2
+#define ADIE 3
+#define ADIF 4
+#define ADATE 5
+#define ADSC 6
+#define ADEN 7
+
+#define ACSR _SFR_IO8(0x1F)
+#define ACIS0 0
+#define ACIS1 1
+#define ACIC 2
+#define ACIE 3
+#define ACI 4
+#define ACO 5
+#define ACD 7
+
+#define ICR0 _SFR_IO16(0x22)
+
+#define ICR0L _SFR_IO8(0x22)
+#define ICR0_0 0
+#define ICR0_1 1
+#define ICR0_2 2
+#define ICR0_3 3
+#define ICR0_4 4
+#define ICR0_5 5
+#define ICR0_6 6
+#define ICR0_7 7
+
+#define ICR0H _SFR_IO8(0x23)
+#define ICR0_8 0
+#define ICR0_9 1
+#define ICR0_10 2
+#define ICR0_11 3
+#define ICR0_12 4
+#define ICR0_13 5
+#define ICR0_14 6
+#define ICR0_15 7
+
+#define OCR0B _SFR_IO16(0x24)
+
+#define OCR0BL _SFR_IO8(0x24)
+#define OCR0B0 0
+#define OCR0B1 1
+#define OCR0B2 2
+#define OCR0B3 3
+#define OCR0B4 4
+#define OCR0B5 5
+#define OCR0B6 6
+#define OCR0B7 7
+
+#define OCR0BH _SFR_IO8(0x25)
+#define OCR0B8 0
+#define OCR0B9 1
+#define OCR0B10 2
+#define OCR0B11 3
+#define OCR0B12 4
+#define OCR0B13 5
+#define OCR0B14 6
+#define OCR0B15 7
+
+#define OCR0A _SFR_IO16(0x26)
+
+#define OCR0AL _SFR_IO8(0x26)
+#define OCR0A0 0
+#define OCR0A1 1
+#define OCR0A2 2
+#define OCR0A3 3
+#define OCR0A4 4
+#define OCR0A5 5
+#define OCR0A6 6
+#define OCR0A7 7
+
+#define OCR0AH _SFR_IO8(0x27)
+#define OCR0A8 0
+#define OCR0A9 1
+#define OCR0A10 2
+#define OCR0A11 3
+#define OCR0A12 4
+#define OCR0A13 5
+#define OCR0A14 6
+#define OCR0A15 7
+
+#define TCNT0 _SFR_IO16(0x28)
+
+#define TCNT0L _SFR_IO8(0x28)
+#define TCNT0_0 0
+#define TCNT0_1 1
+#define TCNT0_2 2
+#define TCNT0_3 3
+#define TCNT0_4 4
+#define TCNT0_5 5
+#define TCNT0_6 6
+#define TCNT0_7 7
+
+#define TCNT0H _SFR_IO8(0x29)
+#define TCNT0_8 0
+#define TCNT0_9 1
+#define TCNT0_10 2
+#define TCNT0_11 3
+#define TCNT0_12 4
+#define TCNT0_13 5
+#define TCNT0_14 6
+#define TCNT0_15 7
+
+#define TIFR0 _SFR_IO8(0x2A)
+#define TOV0 0
+#define OCF0A 1
+#define OCF0B 2
+#define ICF0 5
+
+#define TIMSK0 _SFR_IO8(0x2B)
+#define TOIE0 0
+#define OCIE0A 1
+#define OCIE0B 2
+#define ICIE0 5
+
+#define TCCR0C _SFR_IO8(0x2C)
+#define FOC0B 6
+#define FOC0A 7
+
+#define TCCR0B _SFR_IO8(0x2D)
+#define CS00 0
+#define CS01 1
+#define CS02 2
+#define WGM02 3
+#define WGM03 4
+#define ICES0 6
+#define ICNC0 7
+
+#define TCCR0A _SFR_IO8(0x2E)
+#define WGM00 0
+#define WGM01 1
+#define COM0B0 4
+#define COM0B1 5
+#define COM0A0 6
+#define COM0A1 7
+
+#define GTCCR _SFR_IO8(0x2F)
+#define PSR 0
+#define TSM 7
+
+#define WDTCSR _SFR_IO8(0x31)
+#define WDP0 0
+#define WDP1 1
+#define WDP2 2
+#define WDE 3
+#define WDP3 5
+#define WDIE 6
+#define WDIF 7
+
+#define NVMCSR _SFR_IO8(0x32)
+#define NVMBSY 7
+
+#define NVMCMD _SFR_IO8(0x33)
+#define NVMCMD0 0
+#define NVMCMD1 1
+#define NVMCMD2 2
+#define NVMCMD3 3
+#define NVMCMD4 4
+#define NVMCMD5 5
+
+#define VLMCSR _SFR_IO8(0x34)
+#define VLM0 0
+#define VLM1 1
+#define VLM2 2
+#define VLMIE 6
+#define VLMF 7
+
+#define PRR _SFR_IO8(0x35)
+#define PRTIM0 0
+#define PRADC 1
+
+#define __AVR_HAVE_PRR	((1<<PRTIM0)|(1<<PRADC))
+#define __AVR_HAVE_PRR_PRTIM0
+#define __AVR_HAVE_PRR_PRADC
+
+#define CLKPSR _SFR_IO8(0x36)
+#define CLKPS0 0
+#define CLKPS1 1
+#define CLKPS2 2
+#define CLKPS3 3
+
+#define CLKMSR _SFR_IO8(0x37)
+#define CLKMS0 0
+#define CLKMS1 1
+
+#define OSCCAL _SFR_IO8(0x39)
+#define CAL0 0
+#define CAL1 1
+#define CAL2 2
+#define CAL3 3
+#define CAL4 4
+#define CAL5 5
+#define CAL6 6
+#define CAL7 7
+
+#define SMCR _SFR_IO8(0x3A)
+#define SE 0
+#define SM0 1
+#define SM1 2
+#define SM2 3
+
+#define RSTFLR _SFR_IO8(0x3B)
+#define PORF 0
+#define EXTRF 1
+#define WDRF 3
+
+#define CCP _SFR_IO8(0x3C)
+#define CCP0 0
+#define CCP1 1
+#define CCP2 2
+#define CCP3 3
+#define CCP4 4
+#define CCP5 5
+#define CCP6 6
+#define CCP7 7
+
+
+/* Interrupt vectors */
+/* Vector 0 is the reset vector */
+#define INT0_vect_num  1
+#define INT0_vect      _VECTOR(1)  /* External Interrupt Request 0 */
+#define PCINT0_vect_num  2
+#define PCINT0_vect      _VECTOR(2)  /* Pin Change Interrupt Request 0 */
+#define TIM0_CAPT_vect_num  3
+#define TIM0_CAPT_vect      _VECTOR(3)  /* Timer/Counter0 Input Capture */
+#define TIM0_OVF_vect_num  4
+#define TIM0_OVF_vect      _VECTOR(4)  /* Timer/Counter0 Overflow */
+#define TIM0_COMPA_vect_num  5
+#define TIM0_COMPA_vect      _VECTOR(5)  /* Timer/Counter Compare Match A */
+#define TIM0_COMPB_vect_num  6
+#define TIM0_COMPB_vect      _VECTOR(6)  /* Timer/Counter Compare Match B */
+#define ANA_COMP_vect_num  7
+#define ANA_COMP_vect      _VECTOR(7)  /* Analog Comparator */
+#define WDT_vect_num  8
+#define WDT_vect      _VECTOR(8)  /* Watchdog Time-out */
+#define VLM_vect_num  9
+#define VLM_vect      _VECTOR(9)  /* Vcc Voltage Level Monitor */
+#define ADC_vect_num  10
+#define ADC_vect      _VECTOR(10)  /* ADC Conversion Complete */
+
+#define _VECTOR_SIZE 2 /* Size of individual vector. */
+#define _VECTORS_SIZE (11 * _VECTOR_SIZE)
+
+
+/* Constants */
+#define SPM_PAGESIZE (32)
+#define RAMSTART     (0x40)
+#define RAMSIZE      (32)
+#define RAMEND       (RAMSTART + RAMSIZE - 1)
+#define XRAMSTART    (NA)
+#define XRAMSIZE     (0)
+#define XRAMEND      (RAMEND)
+#define E2END        (0x0)
+#define E2PAGESIZE   (0)
+#define FLASHEND     (0x1FF)
+
+
+/* Fuses */
+#define FUSE_MEMORY_SIZE 0
+
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+
+
+/* Signature */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x90
+#define SIGNATURE_2 0x09
+
+
+/* Device Pin Definitions */
+#define SPDATA_DDR   DDRCINT
+#define SPDATA_PORT  PORTCINT
+#define SPDATA_PIN   PINCINT
+#define SPDATA_BIT   INT0
+
+#define OC0A_DDR   DDRCINT
+#define OC0A_PORT  PORTCINT
+#define OC0A_PIN   PINCINT
+#define OC0A_BIT   INT0
+
+#define ADC0_DDR   DDRCINT
+#define ADC0_PORT  PORTCINT
+#define ADC0_PIN   PINCINT
+#define ADC0_BIT   INT0
+
+#define AIN0_DDR   DDRCINT
+#define AIN0_PORT  PORTCINT
+#define AIN0_PIN   PINCINT
+#define AIN0_BIT   INT0
+
+#define PB0_DDR   DDRCINT
+#define PB0_PORT  PORTCINT
+#define PB0_PIN   PINCINT
+#define PB0_BIT   INT0
+
+#define SPCLK_DDR   DDRCINT
+#define SPCLK_PORT  PORTCINT
+#define SPCLK_PIN   PINCINT
+#define SPCLK_BIT   INT1
+
+#define CLKI_DDR   DDRCINT
+#define CLKI_PORT  PORTCINT
+#define CLKI_PIN   PINCINT
+#define CLKI_BIT   INT1
+
+#define ICP0_DDR   DDRCINT
+#define ICP0_PORT  PORTCINT
+#define ICP0_PIN   PINCINT
+#define ICP0_BIT   INT1
+
+#define OC0B_DDR   DDRCINT
+#define OC0B_PORT  PORTCINT
+#define OC0B_PIN   PINCINT
+#define OC0B_BIT   INT1
+
+#define ADC1_DDR   DDRCINT
+#define ADC1_PORT  PORTCINT
+#define ADC1_PIN   PINCINT
+#define ADC1_BIT   INT1
+
+#define AIN1_DDR   DDRCINT
+#define AIN1_PORT  PORTCINT
+#define AIN1_PIN   PINCINT
+#define AIN1_BIT   INT1
+
+#define PB1_DDR   DDRCINT
+#define PB1_PORT  PORTCINT
+#define PB1_PIN   PINCINT
+#define PB1_BIT   INT1
+
+#define CLKO_DDR   DDRT
+#define CLKO_PORT  PORTT
+#define CLKO_PIN   PINT
+#define CLKO_BIT   T0
+
+#define PCINT2_DDR   DDRT
+#define PCINT2_PORT  PORTT
+#define PCINT2_PIN   PINT
+#define PCINT2_BIT   T0
+
+#define INT0_DDR   DDRT
+#define INT0_PORT  PORTT
+#define INT0_PIN   PINT
+#define INT0_BIT   T0
+
+#define ADC2_DDR   DDRT
+#define ADC2_PORT  PORTT
+#define ADC2_PIN   PINT
+#define ADC2_BIT   T0
+
+#define PB2_DDR   DDRT
+#define PB2_PORT  PORTT
+#define PB2_PIN   PINT
+#define PB2_BIT   T0
+
+#define PCINT3_DDR   DDRRESET
+#define PCINT3_PORT  PORTRESET
+#define PCINT3_PIN   PINRESET
+#define PCINT3_BIT   RESET
+
+#define ADC3_DDR   DDRRESET
+#define ADC3_PORT  PORTRESET
+#define ADC3_PIN   PINRESET
+#define ADC3_BIT   RESET
+
+#define PB3_DDR   DDRRESET
+#define PB3_PORT  PORTRESET
+#define PB3_PIN   PINRESET
+#define PB3_BIT   RESET
+
+#define SLEEP_MODE_IDLE (0x00<<1)
+#define SLEEP_MODE_ADC (0x01<<1)
+#define SLEEP_MODE_PWR_DOWN (0x02<<1)
+#define SLEEP_MODE_STANDBY (0x04<<1)
+
+#endif /* _AVR_ATtiny5_H_ */
+

hardware/tools/avr/avr/include/avr/iotn828.h

@@ -0,0 +1,911 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2015 Atmel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ****************************************************************************/
+
+
+#ifndef _AVR_ATTINY828_H_INCLUDED
+#define _AVR_ATTINY828_H_INCLUDED
+
+
+#ifndef _AVR_IO_H_
+#  error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+#  define _AVR_IOXXX_H_ "iotn828.h"
+#else
+#  error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif
+
+/* Registers and associated bit numbers */
+
+#define PINA    _SFR_IO8(0x00)
+#define PINA7   7
+#define PINA6   6
+#define PINA5   5
+#define PINA4   4
+#define PINA3   3
+#define PINA2   2
+#define PINA1   1
+#define PINA0   0
+
+#define DDRA    _SFR_IO8(0x01)
+#define DDRA7   7
+// Inserted "DDA7" from "DDRA7" due to compatibility
+#define DDA7    7
+#define DDRA6   6
+// Inserted "DDA6" from "DDRA6" due to compatibility
+#define DDA6    6
+#define DDRA5   5
+// Inserted "DDA5" from "DDRA5" due to compatibility
+#define DDA5    5
+#define DDRA4   4
+// Inserted "DDA4" from "DDRA4" due to compatibility
+#define DDA4    4
+#define DDRA3   3
+// Inserted "DDA3" from "DDRA3" due to compatibility
+#define DDA3    3
+#define DDRA2   2
+// Inserted "DDA2" from "DDRA2" due to compatibility
+#define DDA2    2
+#define DDRA1   1
+// Inserted "DDA1" from "DDRA1" due to compatibility
+#define DDA1    1
+#define DDRA0   0
+// Inserted "DDA0" from "DDRA0" due to compatibility
+#define DDA0    0
+
+#define PORTA   _SFR_IO8(0x02)
+#define PORTA7  7
+#define PORTA6  6
+#define PORTA5  5
+#define PORTA4  4
+#define PORTA3  3
+#define PORTA2  2
+#define PORTA1  1
+#define PORTA0  0
+
+#define PUEA    _SFR_IO8(0x03)
+
+#define PINB    _SFR_IO8(0x04)
+#define PINB7   7
+#define PINB6   6
+#define PINB5   5
+#define PINB4   4
+#define PINB3   3
+#define PINB2   2
+#define PINB1   1
+#define PINB0   0
+
+#define DDRB    _SFR_IO8(0x05)
+#define DDRB7   7
+// Inserted "DDB7" from "DDRB7" due to compatibility
+#define DDB7    7
+#define DDRB6   6
+// Inserted "DDB6" from "DDRB6" due to compatibility
+#define DDB6    6
+#define DDRB5   5
+// Inserted "DDB5" from "DDRB5" due to compatibility
+#define DDB5    5
+#define DDRB4   4
+// Inserted "DDB4" from "DDRB4" due to compatibility
+#define DDB4    4
+#define DDRB3   3
+// Inserted "DDB3" from "DDRB3" due to compatibility
+#define DDB3    3
+#define DDRB2   2
+// Inserted "DDB2" from "DDRB2" due to compatibility
+#define DDB2    2
+#define DDRB1   1
+// Inserted "DDB1" from "DDRB1" due to compatibility
+#define DDB1    1
+#define DDRB0   0
+// Inserted "DDB0" from "DDRB0" due to compatibility
+#define DDB0    0
+
+#define PORTB   _SFR_IO8(0x06)
+#define PORTB7  7
+#define PORTB6  6
+#define PORTB5  5
+#define PORTB4  4
+#define PORTB3  3
+#define PORTB2  2
+#define PORTB1  1
+#define PORTB0  0
+
+#define PUEB    _SFR_IO8(0x07)
+
+#define PINC    _SFR_IO8(0x08)
+#define PINC7   7
+#define PINC6   6
+#define PINC5   5
+#define PINC4   4
+#define PINC3   3
+#define PINC2   2
+#define PINC1   1
+#define PINC0   0
+
+#define DDRC    _SFR_IO8(0x09)
+#define DDRC7   7
+// Inserted "DDC7" from "DDRC7" due to compatibility
+#define DDC7    7
+#define DDRC6   6
+// Inserted "DDC6" from "DDRC6" due to compatibility
+#define DDC6    6
+#define DDRC5   5
+// Inserted "DDC5" from "DDRC5" due to compatibility
+#define DDC5    5
+#define DDRC4   4
+// Inserted "DDC4" from "DDRC4" due to compatibility
+#define DDC4    4
+#define DDRC3   3
+// Inserted "DDC3" from "DDRC3" due to compatibility
+#define DDC3    3
+#define DDRC2   2
+// Inserted "DDC2" from "DDRC2" due to compatibility
+#define DDC2    2
+#define DDRC1   1
+// Inserted "DDC1" from "DDRC1" due to compatibility
+#define DDC1    1
+#define DDRC0   0
+// Inserted "DDC0" from "DDRC0" due to compatibility
+#define DDC0    0
+
+#define PORTC   _SFR_IO8(0x0A)
+#define PORTC7  7
+#define PORTC6  6
+#define PORTC5  5
+#define PORTC4  4
+#define PORTC3  3
+#define PORTC2  2
+#define PORTC1  1
+#define PORTC0  0
+
+#define PUEC    _SFR_IO8(0x0B)
+
+#define PIND    _SFR_IO8(0x0C)
+#define PIND3   3
+#define PIND2   2
+#define PIND1   1
+#define PIND0   0
+
+#define DDRD    _SFR_IO8(0x0D)
+#define DDRD3   3
+// Inserted "DDD3" from "DDRD3" due to compatibility
+#define DDD3    3
+#define DDRD2   2
+// Inserted "DDD2" from "DDRD2" due to compatibility
+#define DDD2    2
+#define DDRD1   1
+// Inserted "DDD1" from "DDRD1" due to compatibility
+#define DDD1    1
+#define DDRD0   0
+// Inserted "DDD0" from "DDRD0" due to compatibility
+#define DDD0    0
+
+#define PORTD   _SFR_IO8(0x0E)
+#define PORTD3  3
+#define PORTD2  2
+#define PORTD1  1
+#define PORTD0  0
+
+#define PUED    _SFR_IO8(0x0F)
+
+/* Reserved [0x10..0x13] */
+
+#define PHDE    _SFR_IO8(0x14)
+#define PHDEC   2
+
+#define TIFR0   _SFR_IO8(0x15)
+#define TOV0    0
+#define OCF0A   1
+#define OCF0B   2
+
+#define TIFR1   _SFR_IO8(0x16)
+#define TOV1    0
+#define OCF1A   1
+#define OCF1B   2
+#define ICF1    5
+
+/* Reserved [0x17..0x1A] */
+
+#define PCIFR   _SFR_IO8(0x1B)
+#define PCIF0   0
+#define PCIF1   1
+#define PCIF2   2
+#define PCIF3   3
+
+#define EIFR    _SFR_IO8(0x1C)
+#define INTF0   0
+#define INTF1   1
+
+#define EIMSK   _SFR_IO8(0x1D)
+#define INT0    0
+#define INT1    1
+
+#define GPIOR0  _SFR_IO8(0x1E)
+
+#define EECR    _SFR_IO8(0x1F)
+#define EERE    0
+#define EEPE    1
+#define EEMPE   2
+#define EERIE   3
+#define EEPM0   4
+#define EEPM1   5
+
+#define EEDR    _SFR_IO8(0x20)
+
+#define EEAR    _SFR_IO8(0x21)
+
+/* Reserved [0x22] */
+
+#define GTCCR   _SFR_IO8(0x23)
+#define PSRSYNC 0
+#define TSM     7
+
+#define TCCR0A  _SFR_IO8(0x24)
+#define WGM00   0
+#define WGM01   1
+#define COM0B0  4
+#define COM0B1  5
+#define COM0A0  6
+#define COM0A1  7
+
+#define TCCR0B  _SFR_IO8(0x25)
+#define CS00    0
+#define CS01    1
+#define CS02    2
+#define WGM02   3
+#define FOC0B   6
+#define FOC0A   7
+
+#define TCNT0   _SFR_IO8(0x26)
+
+#define OCR0A   _SFR_IO8(0x27)
+
+#define OCR0B   _SFR_IO8(0x28)
+
+/* Reserved [0x29] */
+
+#define GPIOR1  _SFR_IO8(0x2A)
+
+#define GPIOR2  _SFR_IO8(0x2B)
+
+#define SPCR    _SFR_IO8(0x2C)
+#define SPR0    0
+#define SPR1    1
+#define CPHA    2
+#define CPOL    3
+#define MSTR    4
+#define DORD    5
+#define SPE     6
+#define SPIE    7
+
+#define SPSR    _SFR_IO8(0x2D)
+#define SPI2X   0
+#define WCOL    6
+#define SPIF    7
+
+#define SPDR    _SFR_IO8(0x2E)
+
+#define ACSRB   _SFR_IO8(0x2F)
+#define ACPMUX0 0
+#define ACPMUX1 1
+#define ACNMUX0 2
+#define ACNMUX1 3
+#define HLEV    6
+#define HSEL    7
+
+#define ACSRA   _SFR_IO8(0x30)
+#define ACIS0   0
+#define ACIS1   1
+#define ACIC    2
+#define ACIE    3
+#define ACI     4
+#define ACO     5
+#define ACPMUX2 6
+#define ACD     7
+
+/* Reserved [0x31..0x32] */
+
+#define SMCR    _SFR_IO8(0x33)
+#define SE      0
+#define SM0     1
+#define SM1     2
+
+#define MCUSR   _SFR_IO8(0x34)
+#define PORF    0
+#define EXTRF   1
+#define BORF    2
+#define WDRF    3
+
+#define MCUCR   _SFR_IO8(0x35)
+#define IVSEL   1
+
+#define CCP     _SFR_IO8(0x36)
+
+#define SPMCSR  _SFR_IO8(0x37)
+#define SPMEN   0
+#define PGERS   1
+#define PGWRT   2
+#define RWFLB   3
+#define RWWSRE  4
+#define RSIG    5
+#define RWWSB   6
+#define SPMIE   7
+
+/* Reserved [0x38..0x3C] */
+
+/* SP [0x3D..0x3E] */
+
+/* SREG [0x3F] */
+
+#define WDTCSR  _SFR_MEM8(0x60)
+#define WDE     3
+#define WDP0    0
+#define WDP1    1
+#define WDP2    2
+#define WDP3    5
+#define WDIE    6
+#define WDIF    7
+
+#define CLKPR   _SFR_MEM8(0x61)
+#define CLKPS0  0
+#define CLKPS1  1
+#define CLKPS2  2
+#define CLKPS3  3
+
+/* Reserved [0x62..0x63] */
+
+#define PRR     _SFR_MEM8(0x64)
+#define PRADC   0
+#define PRUSART0 1
+#define PRSPI   2
+#define PRTIM1  3
+#define PRTIM0  5
+#define PRTWI   7
+
+#define __AVR_HAVE_PRR	((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRTIM0)|(1<<PRTWI))
+#define __AVR_HAVE_PRR_PRADC
+#define __AVR_HAVE_PRR_PRUSART0
+#define __AVR_HAVE_PRR_PRSPI
+#define __AVR_HAVE_PRR_PRTIM1
+#define __AVR_HAVE_PRR_PRTIM0
+#define __AVR_HAVE_PRR_PRTWI
+
+/* Reserved [0x65] */
+
+#define OSCCAL0 _SFR_MEM8(0x66)
+
+#define OSCCAL1 _SFR_MEM8(0x67)
+
+#define PCICR   _SFR_MEM8(0x68)
+#define PCIE0   0
+#define PCIE1   1
+#define PCIE2   2
+#define PCIE3   3
+
+#define EICRA   _SFR_MEM8(0x69)
+#define ISC00   0
+#define ISC01   1
+#define ISC10   2
+#define ISC11   3
+
+/* Reserved [0x6A] */
+
+#define PCMSK0  _SFR_MEM8(0x6B)
+#define PCINT0  0
+#define PCINT1  1
+#define PCINT2  2
+#define PCINT3  3
+#define PCINT4  4
+#define PCINT5  5
+#define PCINT6  6
+#define PCINT7  7
+
+#define PCMSK1  _SFR_MEM8(0x6C)
+#define PCINT8  0
+#define PCINT9  1
+#define PCINT10 2
+#define PCINT11 3
+#define PCINT12 4
+#define PCINT13 5
+#define PCINT14 6
+#define PCINT15 7
+
+#define PCMSK2  _SFR_MEM8(0x6D)
+#define PCINT16 0
+#define PCINT17 1
+#define PCINT18 2
+#define PCINT19 3
+#define PCINT20 4
+#define PCINT21 5
+#define PCINT22 6
+#define PCINT23 7
+
+#define TIMSK0  _SFR_MEM8(0x6E)
+#define TOIE0   0
+#define OCIE0A  1
+#define OCIE0B  2
+
+#define TIMSK1  _SFR_MEM8(0x6F)
+#define TOIE1   0
+#define OCIE1A  1
+#define OCIE1B  2
+#define ICIE1   5
+
+/* Reserved [0x70..0x72] */
+
+#define PCMSK3  _SFR_MEM8(0x73)
+#define PCINT24 0
+#define PCINT25 1
+#define PCINT26 2
+#define PCINT27 3
+
+/* Reserved [0x74..0x77] */
+
+/* Combine ADCL and ADCH */
+#ifndef __ASSEMBLER__
+#define ADC     _SFR_MEM16(0x78)
+#endif
+#define ADCW    _SFR_MEM16(0x78)
+
+#define ADCL    _SFR_MEM8(0x78)
+#define ADCH    _SFR_MEM8(0x79)
+
+#define ADCSRA  _SFR_MEM8(0x7A)
+#define ADPS0   0
+#define ADPS1   1
+#define ADPS2   2
+#define ADIE    3
+#define ADIF    4
+#define ADATE   5
+#define ADSC    6
+#define ADEN    7
+
+#define ADCSRB  _SFR_MEM8(0x7B)
+#define ADTS0   0
+#define ADTS1   1
+#define ADTS2   2
+#define ADLAR   3
+
+#define ADMUXA  _SFR_MEM8(0x7C)
+#define MUX0    0
+#define MUX1    1
+#define MUX2    2
+#define MUX3    3
+#define MUX4    4
+
+#define ADMUXB  _SFR_MEM8(0x7D)
+#define MUX5    0
+#define REFS    5
+
+#define DIDR0   _SFR_MEM8(0x7E)
+#define ADC0D   0
+#define ADC1D   1
+#define ADC2D   2
+#define ADC3D   3
+#define ADC4D   4
+#define ADC5D   5
+#define ADC6D   6
+#define ADC7D   7
+
+#define DIDR1   _SFR_MEM8(0x7F)
+#define ADC8D   0
+#define ADC9D   1
+#define ADC10D  2
+#define ADC11D  3
+#define ADC12D  4
+#define ADC13D  5
+#define ADC14D  6
+#define ADC15D  7
+
+#define TCCR1A  _SFR_MEM8(0x80)
+#define WGM10   0
+#define WGM11   1
+#define COM1B0  4
+#define COM1B1  5
+#define COM1A0  6
+#define COM1A1  7
+
+#define TCCR1B  _SFR_MEM8(0x81)
+#define CS10    0
+#define CS11    1
+#define CS12    2
+#define WGM12   3
+#define WGM13   4
+#define ICES1   6
+#define ICNC1   7
+
+#define TCCR1C  _SFR_MEM8(0x82)
+#define FOC1B   6
+#define FOC1A   7
+
+/* Reserved [0x83] */
+
+/* Combine TCNT1L and TCNT1H */
+#define TCNT1   _SFR_MEM16(0x84)
+
+#define TCNT1L  _SFR_MEM8(0x84)
+#define TCNT1H  _SFR_MEM8(0x85)
+
+/* Combine ICR1L and ICR1H */
+#define ICR1    _SFR_MEM16(0x86)
+
+#define ICR1L   _SFR_MEM8(0x86)
+#define ICR1H   _SFR_MEM8(0x87)
+
+/* Combine OCR1AL and OCR1AH */
+#define OCR1A   _SFR_MEM16(0x88)
+
+#define OCR1AL  _SFR_MEM8(0x88)
+#define OCR1AH  _SFR_MEM8(0x89)
+
+/* Combine OCR1BL and OCR1BH */
+#define OCR1B   _SFR_MEM16(0x8A)
+
+#define OCR1BL  _SFR_MEM8(0x8A)
+#define OCR1BH  _SFR_MEM8(0x8B)
+
+/* Reserved [0x8C..0xB7] */
+
+#define TWSCRA  _SFR_MEM8(0xB8)
+#define TWSME   0
+#define TWPME   1
+#define TWSIE   2
+#define TWEN    3
+#define TWASIE  4
+#define TWDIE   5
+#define TWSHE   7
+
+#define TWSCRB  _SFR_MEM8(0xB9)
+#define TWCMD0  0
+#define TWCMD1  1
+#define TWAA    2
+#define TWHNM   3
+
+#define TWSSRA  _SFR_MEM8(0xBA)
+#define TWAS    0
+#define TWDIR   1
+#define TWBE    2
+#define TWC     3
+#define TWRA    4
+#define TWCH    5
+#define TWASIF  6
+#define TWDIF   7
+
+#define TWSAM   _SFR_MEM8(0xBB)
+#define TWAE    0
+#define TWSAM1  1
+#define TWSAM2  2
+#define TWSAM3  3
+#define TWSAM4  4
+#define TWSAM5  5
+#define TWSAM6  6
+#define TWSAM7  7
+
+#define TWSA    _SFR_MEM8(0xBC)
+
+#define TWSD    _SFR_MEM8(0xBD)
+#define TWSD0   0
+#define TWSD1   1
+#define TWSD2   2
+#define TWSD3   3
+#define TWSD4   4
+#define TWSD5   5
+#define TWSD6   6
+#define TWSD7   7
+
+/* Reserved [0xBE..0xBF] */
+
+#define UCSRA   _SFR_MEM8(0xC0)
+#define MPCM    0
+#define U2X     1
+#define UPE     2
+#define DOR     3
+#define FE      4
+#define UDRE    5
+#define TXC     6
+#define RXC     7
+
+#define UCSRB   _SFR_MEM8(0xC1)
+#define TXB8    0
+#define RXB8    1
+#define UCSZ2   2
+#define TXEN    3
+#define RXEN    4
+#define UDRIE   5
+#define TXCIE   6
+#define RXCIE   7
+
+#define UCSRC   _SFR_MEM8(0xC2)
+#define UCPOL   0
+#define UCSZ0   1
+#define UCSZ1   2
+#define USBS    3
+#define UPM0    4
+#define UPM1    5
+#define UMSEL0  6
+#define UMSEL1  7
+
+#define UCSRD   _SFR_MEM8(0xC3)
+#define SFDE    5
+#define RXS     6
+#define RXSIE   7
+
+/* Combine UBRRL and UBRRH */
+#define UBRR    _SFR_MEM16(0xC4)
+
+#define UBRRL   _SFR_MEM8(0xC4)
+#define UBRRH   _SFR_MEM8(0xC5)
+
+#define UDR     _SFR_MEM8(0xC6)
+
+/* Reserved [0xC7..0xDD] */
+
+#define DIDR2   _SFR_MEM8(0xDE)
+#define ADC16D  0
+#define ADC17D  1
+#define ADC18D  2
+#define ADC19D  3
+#define ADC20D  4
+#define ADC21D  5
+#define ADC22D  6
+#define ADC23D  7
+
+#define DIDR3   _SFR_MEM8(0xDF)
+#define ADC24D  0
+#define ADC25D  1
+#define ADC26D  2
+#define ADC27D  3
+
+/* Reserved [0xE0..0xE1] */
+
+#define TOCPMCOE _SFR_MEM8(0xE2)
+#define TOCC0OE 0
+#define TOCC1OE 1
+#define TOCC2OE 2
+#define TOCC3OE 3
+#define TOCC4OE 4
+#define TOCC5OE 5
+#define TOCC6OE 6
+#define TOCC7OE 7
+
+/* Reserved [0xE3..0xE7] */
+
+#define TOCPMSA0 _SFR_MEM8(0xE8)
+#define TOCC0S0 0
+#define TOCC0S1 1
+#define TOCC1S0 2
+#define TOCC1S1 3
+#define TOCC2S0 4
+#define TOCC2S1 5
+#define TOCC3S0 6
+#define TOCC3S1 7
+
+#define TOCPMSA1 _SFR_MEM8(0xE9)
+#define TOCC4S0 0
+#define TOCC4S1 1
+#define TOCC5S0 2
+#define TOCC5S1 3
+#define TOCC6S0 4
+#define TOCC6S1 5
+#define TOCC7S0 6
+#define TOCC7S1 7
+
+/* Reserved [0xEA..0xEF] */
+
+#define OSCTCAL0A _SFR_MEM8(0xF0)
+
+#define OSCTCAL0B _SFR_MEM8(0xF1)
+
+
+
+/* Values and associated defines */
+
+
+#define SLEEP_MODE_IDLE (0x00<<1)
+#define SLEEP_MODE_ADC (0x01<<1)
+#define SLEEP_MODE_PWR_DOWN (0x02<<1)
+
+/* Interrupt vectors */
+/* Vector 0 is the reset vector */
+/* External Interrupt Request 0 */
+#define INT0_vect            _VECTOR(1)
+#define INT0_vect_num        1
+
+/* External Interrupt Request 1 */
+#define INT1_vect            _VECTOR(2)
+#define INT1_vect_num        2
+
+/* Pin Change Interrupt Request 0 */
+#define PCINT0_vect            _VECTOR(3)
+#define PCINT0_vect_num        3
+
+/* Pin Change Interrupt Request 1 */
+#define PCINT1_vect            _VECTOR(4)
+#define PCINT1_vect_num        4
+
+/* Pin Change Interrupt Request 2 */
+#define PCINT2_vect            _VECTOR(5)
+#define PCINT2_vect_num        5
+
+/* Pin Change Interrupt Request 3 */
+#define PCINT3_vect            _VECTOR(6)
+#define PCINT3_vect_num        6
+
+/* Watchdog Time-out Interrupt */
+#define WDT_vect            _VECTOR(7)
+#define WDT_vect_num        7
+
+/* Timer/Counter1 Capture Event */
+#define TIMER1_CAPT_vect            _VECTOR(8)
+#define TIMER1_CAPT_vect_num        8
+
+/* Timer/Counter1 Compare Match A */
+#define TIMER1_COMPA_vect            _VECTOR(9)
+#define TIMER1_COMPA_vect_num        9
+
+/* Timer/Counter1 Compare Match B */
+#define TIMER1_COMPB_vect            _VECTOR(10)
+#define TIMER1_COMPB_vect_num        10
+
+/* Timer/Counter1 Overflow */
+#define TIMER1_OVF_vect            _VECTOR(11)
+#define TIMER1_OVF_vect_num        11
+
+/* Timer/Counter0 Compare Match A */
+#define TIMER0_COMPA_vect            _VECTOR(12)
+#define TIMER0_COMPA_vect_num        12
+
+/* Timer/Counter0 Compare Match B */
+#define TIMER0_COMPB_vect            _VECTOR(13)
+#define TIMER0_COMPB_vect_num        13
+
+/* Timer/Counter0 Overflow */
+#define TIMER0_OVF_vect            _VECTOR(14)
+#define TIMER0_OVF_vect_num        14
+
+/* SPI Serial Transfer Complete */
+#define SPI_STC_vect            _VECTOR(15)
+#define SPI_STC_vect_num        15
+
+/* USART, Start */
+#define USART_START_vect            _VECTOR(16)
+#define USART_START_vect_num        16
+
+/* USART Rx Complete */
+#define USART_RX_vect            _VECTOR(17)
+#define USART_RX_vect_num        17
+
+/* USART, Data Register Empty */
+#define USART_UDRE_vect            _VECTOR(18)
+#define USART_UDRE_vect_num        18
+
+/* USART Tx Complete */
+#define USART_TX_vect            _VECTOR(19)
+#define USART_TX_vect_num        19
+
+/* ADC Conversion Complete */
+#define ADC_vect            _VECTOR(20)
+#define ADC_vect_num        20
+
+/* EEPROM Ready */
+#define EE_READY_vect            _VECTOR(21)
+#define EE_READY_vect_num        21
+
+/* Analog Comparator */
+#define ANALOG_COMP_vect            _VECTOR(22)
+#define ANALOG_COMP_vect_num        22
+
+/* Two-wire Serial Interface */
+#define TWI_SLAVE_vect            _VECTOR(23)
+#define TWI_SLAVE_vect_num        23
+
+/* Store Program Memory Read */
+#define SPM_Ready_vect            _VECTOR(24)
+#define SPM_Ready_vect_num        24
+
+/* Touch Sensing */
+#define QTRIP_vect            _VECTOR(25)
+#define QTRIP_vect_num        25
+
+#define _VECTORS_SIZE 52
+
+
+/* Constants */
+
+#define SPM_PAGESIZE 64
+#define FLASHSTART   0x0000
+#define FLASHEND     0x1FFF
+#define RAMSTART     0x0100
+#define RAMSIZE      512
+#define RAMEND       0x02FF
+#define E2START     0
+#define E2SIZE      256
+#define E2PAGESIZE  4
+#define E2END       0x00FF
+#define XRAMEND      RAMEND
+
+
+/* Fuses */
+
+#define FUSE_MEMORY_SIZE 3
+
+/* Low Fuse Byte */
+#define FUSE_SUT_CKSEL0  (unsigned char)~_BV(0)
+#define FUSE_SUT_CKSEL1  (unsigned char)~_BV(1)
+#define FUSE_SUT_CKSEL2  (unsigned char)~_BV(4)
+#define FUSE_SUT_CKSEL3  (unsigned char)~_BV(5)
+#define FUSE_CKOUT       (unsigned char)~_BV(6)
+#define FUSE_CKDIV8      (unsigned char)~_BV(7)
+#define LFUSE_DEFAULT    (FUSE_SUT_CKSEL0 & FUSE_SUT_CKSEL2 & FUSE_CKDIV8)
+
+
+/* High Fuse Byte */
+#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
+#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
+#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
+#define FUSE_EESAVE      (unsigned char)~_BV(3)
+#define FUSE_WDTON       (unsigned char)~_BV(4)
+#define FUSE_SPIEN       (unsigned char)~_BV(5)
+#define FUSE_DWEN        (unsigned char)~_BV(6)
+#define FUSE_RSTDISBL    (unsigned char)~_BV(7)
+#define HFUSE_DEFAULT    (FUSE_SPIEN)
+
+
+/* Extended Fuse Byte */
+#define FUSE_BOOTRST     (unsigned char)~_BV(0)
+#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
+#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
+#define FUSE_BODACT0     (unsigned char)~_BV(4)
+#define FUSE_BODACT1     (unsigned char)~_BV(5)
+#define FUSE_BODPD0      (unsigned char)~_BV(6)
+#define FUSE_BODPD1      (unsigned char)~_BV(7)
+#define EFUSE_DEFAULT    (0xFF)
+
+
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+#define __BOOT_LOCK_BITS_0_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
+
+
+/* Signature */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x93
+#define SIGNATURE_2 0x14
+
+
+#endif /* #ifdef _AVR_ATTINY828_H_INCLUDED */
+

hardware/tools/avr/avr/include/avr/iotn84.h

@@ -0,0 +1,94 @@
+/* Copyright (c) 2005, Anatoly Sokolov
+   All rights reserved.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+
+   * Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+
+   * Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in
+     the documentation and/or other materials provided with the
+     distribution.
+
+   * Neither the name of the copyright holders nor the names of
+     contributors may be used to endorse or promote products derived
+     from this software without specific prior written permission.
+
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+  POSSIBILITY OF SUCH DAMAGE. */
+
+/* $Id: iotn84.h 2417 2014-04-16 11:34:47Z pitchumani $ */
+
+/* avr/iotn84.h - definitions for ATtiny84 */
+
+#ifndef _AVR_IOTN84_H_
+#define _AVR_IOTN84_H_ 1
+
+#include <avr/iotnx4.h>
+
+/* Constants */
+#define SPM_PAGESIZE 64
+#define RAMSTART     (0x60)
+#define RAMEND       0x25F
+#define XRAMEND      RAMEND
+#define E2END        0x1FF
+#define E2PAGESIZE   4
+#define FLASHEND     0x1FFF
+
+
+/* Fuses */
+#define FUSE_MEMORY_SIZE 3
+
+/* Low Fuse Byte */
+#define FUSE_CKSEL0      (unsigned char)~_BV(0)
+#define FUSE_CKSEL1      (unsigned char)~_BV(1)
+#define FUSE_CKSEL2      (unsigned char)~_BV(2)
+#define FUSE_CKSEL3      (unsigned char)~_BV(3)
+#define FUSE_SUT0        (unsigned char)~_BV(4)
+#define FUSE_SUT1        (unsigned char)~_BV(5)
+#define FUSE_CKOUT       (unsigned char)~_BV(6)
+#define FUSE_CKDIV8      (unsigned char)~_BV(7)
+#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
+
+/* High Fuse Byte */
+#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
+#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
+#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
+#define FUSE_EESAVE      (unsigned char)~_BV(3)
+#define FUSE_WDTON       (unsigned char)~_BV(4)
+#define FUSE_SPIEN       (unsigned char)~_BV(5)
+#define FUSE_DWEN        (unsigned char)~_BV(6)
+#define FUSE_RSTDISBL    (unsigned char)~_BV(7)
+#define HFUSE_DEFAULT    (FUSE_SPIEN)
+
+/* Extended Fuse Byte */
+#define FUSE_SELFPRGEN   (unsigned char)~_BV(0)
+#define EFUSE_DEFAULT (0xFF)
+
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+
+
+/* Signature */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x93
+#define SIGNATURE_2 0x0C
+
+#define SLEEP_MODE_IDLE (0x00<<3)
+#define SLEEP_MODE_ADC (0x01<<3)
+#define SLEEP_MODE_PWR_DOWN (0x02<<3)
+#define SLEEP_MODE_STANDBY (0x03<<3)
+
+#endif /* _AVR_IOTN84_H_ */

hardware/tools/avr/avr/include/avr/iotn841.h

@@ -0,0 +1,903 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2015 Atmel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ****************************************************************************/
+
+
+#ifndef _AVR_ATTINY841_H_INCLUDED
+#define _AVR_ATTINY841_H_INCLUDED
+
+
+#ifndef _AVR_IO_H_
+#  error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+#  define _AVR_IOXXX_H_ "iotn841.h"
+#else
+#  error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif
+
+/* Registers and associated bit numbers */
+
+#define ADCSRB  _SFR_IO8(0x04)
+#define ADTS0   0
+#define ADTS1   1
+#define ADTS2   2
+#define ADLAR   3
+
+#define ADCSRA  _SFR_IO8(0x05)
+#define ADPS0   0
+#define ADPS1   1
+#define ADPS2   2
+#define ADIE    3
+#define ADIF    4
+#define ADATE   5
+#define ADSC    6
+#define ADEN    7
+
+/* Combine ADCL and ADCH */
+#ifndef __ASSEMBLER__
+#define ADC     _SFR_IO16(0x06)
+#endif
+#define ADCW    _SFR_IO16(0x06)
+
+#define ADCL    _SFR_IO8(0x06)
+#define ADCH    _SFR_IO8(0x07)
+
+#define ADMUXB  _SFR_IO8(0x08)
+#define GSEL0   0
+#define GSEL1   1
+#define REFS0   5
+#define REFS1   6
+#define REFS2   7
+
+#define ADMUXA  _SFR_IO8(0x09)
+#define MUX0    0
+#define MUX1    1
+#define MUX2    2
+#define MUX3    3
+#define MUX4    4
+#define MUX5    5
+
+#define ACSR0A  _SFR_IO8(0x0A)
+#define ACIS00  0
+#define ACIS01  1
+#define ACIC0   2
+#define ACIE0   3
+#define ACI0    4
+#define ACO0    5
+#define ACPMUX2 6
+#define ACD0    7
+
+#define ACSR0B  _SFR_IO8(0x0B)
+#define ACPMUX0 0
+#define ACPMUX1 1
+#define ACNMUX0 2
+#define ACNMUX1 3
+#define ACOE0   4
+#define HLEV0   6
+#define HSEL0   7
+
+#define ACSR1A  _SFR_IO8(0x0C)
+#define ACIS10  0
+#define ACIS11  1
+#define ACIC1   2
+#define ACIE1   3
+#define ACI1    4
+#define ACO1    5
+#define ACBG1   6
+#define ACD1    7
+
+#define ACSR1B  _SFR_IO8(0x0D)
+#define ACME1   2
+#define ACOE1   4
+#define HLEV1   6
+#define HSEL1   7
+
+#define TIFR1   _SFR_IO8(0x0E)
+#define TOV1    0
+#define OCF1A   1
+#define OCF1B   2
+#define ICF1    5
+
+#define TIMSK1  _SFR_IO8(0x0F)
+#define TOIE1   0
+#define OCIE1A  1
+#define OCIE1B  2
+#define ICIE1   5
+
+#define TIFR2   _SFR_IO8(0x10)
+#define TOV2    0
+#define OCF2A   1
+#define OCF2B   2
+#define ICF2    5
+
+#define TIMSK2  _SFR_IO8(0x11)
+#define TOIE2   0
+#define OCIE2A  1
+#define OCIE2B  2
+#define ICIE2   5
+
+#define PCMSK0  _SFR_IO8(0x12)
+#define PCINT0  0
+#define PCINT1  1
+#define PCINT2  2
+#define PCINT3  3
+#define PCINT4  4
+#define PCINT5  5
+#define PCINT6  6
+#define PCINT7  7
+
+#define GPIOR0  _SFR_IO8(0x13)
+
+#define GPIOR1  _SFR_IO8(0x14)
+
+#define GPIOR2  _SFR_IO8(0x15)
+
+#define PINB    _SFR_IO8(0x16)
+#define PINB3   3
+#define PINB2   2
+#define PINB1   1
+#define PINB0   0
+
+#define DDRB    _SFR_IO8(0x17)
+#define DDRB3   3
+// Inserted "DDB3" from "DDRB3" due to compatibility
+#define DDB3    3
+#define DDRB2   2
+// Inserted "DDB2" from "DDRB2" due to compatibility
+#define DDB2    2
+#define DDRB1   1
+// Inserted "DDB1" from "DDRB1" due to compatibility
+#define DDB1    1
+#define DDRB0   0
+// Inserted "DDB0" from "DDRB0" due to compatibility
+#define DDB0    0
+
+#define PORTB   _SFR_IO8(0x18)
+#define PORTB3  3
+#define PORTB2  2
+#define PORTB1  1
+#define PORTB0  0
+
+#define PINA    _SFR_IO8(0x19)
+#define PINA7   7
+#define PINA6   6
+#define PINA5   5
+#define PINA4   4
+#define PINA3   3
+#define PINA2   2
+#define PINA1   1
+#define PINA0   0
+
+#define DDRA    _SFR_IO8(0x1A)
+#define DDRA7   7
+// Inserted "DDA7" from "DDRA7" due to compatibility
+#define DDA7    7
+#define DDRA6   6
+// Inserted "DDA6" from "DDRA6" due to compatibility
+#define DDA6    6
+#define DDRA5   5
+// Inserted "DDA5" from "DDRA5" due to compatibility
+#define DDA5    5
+#define DDRA4   4
+// Inserted "DDA4" from "DDRA4" due to compatibility
+#define DDA4    4
+#define DDRA3   3
+// Inserted "DDA3" from "DDRA3" due to compatibility
+#define DDA3    3
+#define DDRA2   2
+// Inserted "DDA2" from "DDRA2" due to compatibility
+#define DDA2    2
+#define DDRA1   1
+// Inserted "DDA1" from "DDRA1" due to compatibility
+#define DDA1    1
+#define DDRA0   0
+// Inserted "DDA0" from "DDRA0" due to compatibility
+#define DDA0    0
+
+#define PORTA   _SFR_IO8(0x1B)
+#define PORTA7  7
+#define PORTA6  6
+#define PORTA5  5
+#define PORTA4  4
+#define PORTA3  3
+#define PORTA2  2
+#define PORTA1  1
+#define PORTA0  0
+
+#define EECR    _SFR_IO8(0x1C)
+#define EERE    0
+#define EEPE    1
+#define EEMPE   2
+#define EERIE   3
+#define EEPM0   4
+#define EEPM1   5
+
+#define EEDR    _SFR_IO8(0x1D)
+
+/* Combine EEARL and EEARH */
+#define EEAR    _SFR_IO16(0x1E)
+
+#define EEARL   _SFR_IO8(0x1E)
+#define EEARH   _SFR_IO8(0x1F)
+
+#define PCMSK1  _SFR_IO8(0x20)
+#define PCINT8  0
+#define PCINT9  1
+#define PCINT10 2
+#define PCINT11 3
+
+#define WDTCSR  _SFR_IO8(0x21)
+#define WDE     3
+#define WDP0    0
+#define WDP1    1
+#define WDP2    2
+#define WDP3    5
+#define WDIE    6
+#define WDIF    7
+
+#define TCCR1C  _SFR_IO8(0x22)
+#define FOC1B   6
+#define FOC1A   7
+
+#define GTCCR   _SFR_IO8(0x23)
+#define PSR     0
+#define TSM     7
+
+/* Combine ICR1L and ICR1H */
+#define ICR1    _SFR_IO16(0x24)
+
+#define ICR1L   _SFR_IO8(0x24)
+#define ICR1H   _SFR_IO8(0x25)
+
+/* Reserved [0x26..0x27] */
+
+/* Combine OCR1BL and OCR1BH */
+#define OCR1B   _SFR_IO16(0x28)
+
+#define OCR1BL  _SFR_IO8(0x28)
+#define OCR1BH  _SFR_IO8(0x29)
+
+/* Combine OCR1AL and OCR1AH */
+#define OCR1A   _SFR_IO16(0x2A)
+
+#define OCR1AL  _SFR_IO8(0x2A)
+#define OCR1AH  _SFR_IO8(0x2B)
+
+/* Combine TCNT1L and TCNT1H */
+#define TCNT1   _SFR_IO16(0x2C)
+
+#define TCNT1L  _SFR_IO8(0x2C)
+#define TCNT1H  _SFR_IO8(0x2D)
+
+#define TCCR1B  _SFR_IO8(0x2E)
+#define CS10    0
+#define CS11    1
+#define CS12    2
+#define WGM12   3
+#define WGM13   4
+#define ICES1   6
+#define ICNC1   7
+
+#define TCCR1A  _SFR_IO8(0x2F)
+#define WGM10   0
+#define WGM11   1
+#define COM1B0  4
+#define COM1B1  5
+#define COM1A0  6
+#define COM1A1  7
+
+#define TCCR0A  _SFR_IO8(0x30)
+#define WGM00   0
+#define WGM01   1
+#define COM0B0  4
+#define COM0B1  5
+#define COM0A0  6
+#define COM0A1  7
+
+/* Reserved [0x31] */
+
+#define TCNT0   _SFR_IO8(0x32)
+
+#define TCCR0B  _SFR_IO8(0x33)
+#define CS00    0
+#define CS01    1
+#define CS02    2
+#define WGM02   3
+#define FOC0B   6
+#define FOC0A   7
+
+#define MCUSR   _SFR_IO8(0x34)
+#define PORF    0
+#define EXTRF   1
+#define BORF    2
+#define WDRF    3
+
+#define MCUCR   _SFR_IO8(0x35)
+#define ISC00   0
+#define ISC01   1
+#define SM0     3
+#define SM1     4
+#define SE      5
+
+#define OCR0A   _SFR_IO8(0x36)
+
+#define SPMCSR  _SFR_IO8(0x37)
+#define SPMEN   0
+#define PGERS   1
+#define PGWRT   2
+#define RFLB    3
+#define CTPB    4
+#define RSIG    5
+
+#define TIFR0   _SFR_IO8(0x38)
+#define TOV0    0
+#define OCF0A   1
+#define OCF0B   2
+
+#define TIMSK0  _SFR_IO8(0x39)
+#define TOIE0   0
+#define OCIE0A  1
+#define OCIE0B  2
+
+#define GIFR    _SFR_IO8(0x3A)
+#define PCIF0   4
+#define PCIF1   5
+#define INTF0   6
+
+#define GIMSK   _SFR_IO8(0x3B)
+#define PCIE0   4
+#define PCIE1   5
+#define INT0    6
+
+#define OCR0B   _SFR_IO8(0x3C)
+
+/* SP [0x3D..0x3E] */
+
+/* SREG [0x3F] */
+
+#define DIDR0   _SFR_MEM8(0x60)
+#define ADC0D   0
+#define ADC1D   1
+#define ADC2D   2
+#define ADC3D   3
+#define ADC4D   4
+#define ADC5D   5
+#define ADC6D   6
+#define ADC7D   7
+
+#define DIDR1   _SFR_MEM8(0x61)
+#define ADC11D  0
+#define ADC10D  1
+#define ADC8D   2
+#define ADC9D   3
+
+#define PUEB    _SFR_MEM8(0x62)
+
+#define PUEA    _SFR_MEM8(0x63)
+
+#define PORTCR  _SFR_MEM8(0x64)
+#define BBMB    1
+#define BBMA    0
+
+#define REMAP   _SFR_MEM8(0x65)
+#define U0MAP   0
+#define SPIMAP  1
+
+#define TOCPMCOE _SFR_MEM8(0x66)
+#define TOCC0OE 0
+#define TOCC1OE 1
+#define TOCC2OE 2
+#define TOCC3OE 3
+#define TOCC4OE 4
+#define TOCC5OE 5
+#define TOCC6OE 6
+#define TOCC7OE 7
+
+#define TOCPMSA0 _SFR_MEM8(0x67)
+#define TOCC0S0 0
+#define TOCC0S1 1
+#define TOCC1S0 2
+#define TOCC1S1 3
+#define TOCC2S0 4
+#define TOCC2S1 5
+#define TOCC3S0 6
+#define TOCC3S1 7
+
+#define TOCPMSA1 _SFR_MEM8(0x68)
+#define TOCC4S0 0
+#define TOCC4S1 1
+#define TOCC5S0 2
+#define TOCC5S1 3
+#define TOCC6S0 4
+#define TOCC6S1 5
+#define TOCC7S0 6
+#define TOCC7S1 7
+
+/* Reserved [0x69] */
+
+#define PHDE    _SFR_MEM8(0x6A)
+#define PHDEA0  0
+#define PHDEA1  1
+
+/* Reserved [0x6B..0x6F] */
+
+#define PRR     _SFR_MEM8(0x70)
+#define PRADC   0
+#define PRTIM0  1
+#define PRTIM1  2
+#define PRTIM2  3
+#define PRSPI   4
+#define PRUSART0 5
+#define PRUSART1 6
+#define PRTWI   7
+
+#define __AVR_HAVE_PRR	((1<<PRADC)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRTIM2)|(1<<PRSPI)|(1<<PRUSART0)|(1<<PRUSART1)|(1<<PRTWI))
+#define __AVR_HAVE_PRR_PRADC
+#define __AVR_HAVE_PRR_PRTIM0
+#define __AVR_HAVE_PRR_PRTIM1
+#define __AVR_HAVE_PRR_PRTIM2
+#define __AVR_HAVE_PRR_PRSPI
+#define __AVR_HAVE_PRR_PRUSART0
+#define __AVR_HAVE_PRR_PRUSART1
+#define __AVR_HAVE_PRR_PRTWI
+
+#define CCP     _SFR_MEM8(0x71)
+
+#define CLKCR   _SFR_MEM8(0x72)
+#define CKSEL0  0
+#define CKSEL1  1
+#define CKSEL2  2
+#define CKSEL3  3
+#define SUT     4
+#define CKOUTC  5
+#define CSTR    6
+#define OSCRDY  7
+
+#define CLKPR   _SFR_MEM8(0x73)
+#define CLKPS0  0
+#define CLKPS1  1
+#define CLKPS2  2
+#define CLKPS3  3
+
+#define OSCCAL0 _SFR_MEM8(0x74)
+
+#define OSCTCAL0A _SFR_MEM8(0x75)
+
+#define OSCTCAL0B _SFR_MEM8(0x76)
+
+#define OSCCAL1 _SFR_MEM8(0x77)
+
+/* Reserved [0x78..0x7F] */
+
+#define UDR0    _SFR_MEM8(0x80)
+
+/* Combine UBRR0L and UBRR0H */
+#define UBRR0   _SFR_MEM16(0x81)
+
+#define UBRR0L  _SFR_MEM8(0x81)
+#define UBRR0H  _SFR_MEM8(0x82)
+
+#define UCSR0D  _SFR_MEM8(0x83)
+#define SFDE0   5
+#define RXS0    6
+#define RXSIE0  7
+
+#define UCSR0C  _SFR_MEM8(0x84)
+#define UCPOL0  0
+#define UCSZ00  1
+#define UCSZ01  2
+#define USBS0   3
+#define UPM00   4
+#define UPM01   5
+#define UMSEL00 6
+#define UMSEL01 7
+
+#define UCSR0B  _SFR_MEM8(0x85)
+#define TXB80   0
+#define RXB80   1
+#define UCSZ02  2
+#define TXEN0   3
+#define RXEN0   4
+#define UDRIE0  5
+#define TXCIE0  6
+#define RXCIE0  7
+
+#define UCSR0A  _SFR_MEM8(0x86)
+#define MPCM0   0
+#define U2X0    1
+#define UPE0    2
+#define DOR0    3
+#define FE0     4
+#define UDRE0   5
+#define TXC0    6
+#define RXC0    7
+
+/* Reserved [0x87..0x8F] */
+
+#define UDR1    _SFR_MEM8(0x90)
+
+/* Combine UBRR1L and UBRR1H */
+#define UBRR1   _SFR_MEM16(0x91)
+
+#define UBRR1L  _SFR_MEM8(0x91)
+#define UBRR1H  _SFR_MEM8(0x92)
+
+#define UCSR1D  _SFR_MEM8(0x93)
+#define SFDE1   5
+#define RXS1    6
+#define RXSIE1  7
+
+#define UCSR1C  _SFR_MEM8(0x94)
+#define UCPOL1  0
+#define UCSZ10  1
+#define UCSZ11  2
+#define USBS1   3
+#define UPM10   4
+#define UPM11   5
+#define UMSEL10 6
+#define UMSEL11 7
+
+#define UCSR1B  _SFR_MEM8(0x95)
+#define TXB81   0
+#define RXB81   1
+#define UCSZ12  2
+#define TXEN1   3
+#define RXEN1   4
+#define UDRIE1  5
+#define TXCIE1  6
+#define RXCIE1  7
+
+#define UCSR1A  _SFR_MEM8(0x96)
+#define MPCM1   0
+#define U2X1    1
+#define UPE1    2
+#define DOR1    3
+#define FE1     4
+#define UDRE1   5
+#define TXC1    6
+#define RXC1    7
+
+/* Reserved [0x97..0x9F] */
+
+#define TWSD    _SFR_MEM8(0xA0)
+#define TWSD0   0
+#define TWSD1   1
+#define TWSD2   2
+#define TWSD3   3
+#define TWSD4   4
+#define TWSD5   5
+#define TWSD6   6
+#define TWSD7   7
+
+#define TWSAM   _SFR_MEM8(0xA1)
+#define TWAE    0
+#define TWSAM1  1
+#define TWSAM2  2
+#define TWSAM3  3
+#define TWSAM4  4
+#define TWSAM5  5
+#define TWSAM6  6
+#define TWSAM7  7
+
+#define TWSA    _SFR_MEM8(0xA2)
+
+#define TWSSRA  _SFR_MEM8(0xA3)
+#define TWAS    0
+#define TWDIR   1
+#define TWBE    2
+#define TWC     3
+#define TWRA    4
+#define TWCH    5
+#define TWASIF  6
+#define TWDIF   7
+
+#define TWSCRB  _SFR_MEM8(0xA4)
+#define TWCMD0  0
+#define TWCMD1  1
+#define TWAA    2
+#define TWHNM   3
+
+#define TWSCRA  _SFR_MEM8(0xA5)
+#define TWSME   0
+#define TWPME   1
+#define TWSIE   2
+#define TWEN    3
+#define TWASIE  4
+#define TWDIE   5
+#define TWSHE   7
+
+/* Reserved [0xA6..0xAF] */
+
+#define SPDR    _SFR_MEM8(0xB0)
+
+#define SPSR    _SFR_MEM8(0xB1)
+#define SPI2X   0
+#define WCOL    6
+#define SPIF    7
+
+#define SPCR    _SFR_MEM8(0xB2)
+#define SPR0    0
+#define SPR1    1
+#define CPHA    2
+#define CPOL    3
+#define MSTR    4
+#define DORD    5
+#define SPE     6
+#define SPIE    7
+
+/* Reserved [0xB3..0xBF] */
+
+/* Combine ICR2L and ICR2H */
+#define ICR2    _SFR_MEM16(0xC0)
+
+#define ICR2L   _SFR_MEM8(0xC0)
+#define ICR2H   _SFR_MEM8(0xC1)
+
+/* Combine OCR2BL and OCR2BH */
+#define OCR2B   _SFR_MEM16(0xC2)
+
+#define OCR2BL  _SFR_MEM8(0xC2)
+#define OCR2BH  _SFR_MEM8(0xC3)
+
+/* Combine OCR2AL and OCR2AH */
+#define OCR2A   _SFR_MEM16(0xC4)
+
+#define OCR2AL  _SFR_MEM8(0xC4)
+#define OCR2AH  _SFR_MEM8(0xC5)
+
+/* Combine TCNT2L and TCNT2H */
+#define TCNT2   _SFR_MEM16(0xC6)
+
+#define TCNT2L  _SFR_MEM8(0xC6)
+#define TCNT2H  _SFR_MEM8(0xC7)
+
+#define TCCR2C  _SFR_MEM8(0xC8)
+#define FOC2B   6
+#define FOC2A   7
+
+#define TCCR2B  _SFR_MEM8(0xC9)
+#define CS20    0
+#define CS21    1
+#define CS22    2
+#define WGM22   3
+#define WGM23   4
+#define ICES2   6
+#define ICNC2   7
+
+#define TCCR2A  _SFR_MEM8(0xCA)
+#define WGM20   0
+#define WGM21   1
+#define COM2B0  4
+#define COM2B1  5
+#define COM2A0  6
+#define COM2A1  7
+
+
+
+/* Values and associated defines */
+
+
+#define SLEEP_MODE_IDLE (0x00<<3)
+#define SLEEP_MODE_ADC (0x01<<3)
+#define SLEEP_MODE_PWR_DOWN (0x02<<3)
+#define SLEEP_MODE_STANDBY (0x03<<3)
+
+/* Interrupt vectors */
+/* Vector 0 is the reset vector */
+/* External Interrupt Request 0 */
+#define INT0_vect            _VECTOR(1)
+#define INT0_vect_num        1
+
+/* Pin Change Interrupt Request 0 */
+#define PCINT0_vect            _VECTOR(2)
+#define PCINT0_vect_num        2
+
+/* Pin Change Interrupt Request 1 */
+#define PCINT1_vect            _VECTOR(3)
+#define PCINT1_vect_num        3
+
+/* Watchdog Time-out Interrupt */
+#define WDT_vect            _VECTOR(4)
+#define WDT_vect_num        4
+
+/* Timer/Counter1 Capture Event */
+#define TIMER1_CAPT_vect            _VECTOR(5)
+#define TIMER1_CAPT_vect_num        5
+
+/* Timer/Counter1 Compare Match A */
+#define TIMER1_COMPA_vect            _VECTOR(6)
+#define TIMER1_COMPA_vect_num        6
+
+/* Timer/Counter1 Compare Match B */
+#define TIMER1_COMPB_vect            _VECTOR(7)
+#define TIMER1_COMPB_vect_num        7
+
+/* Timer/Counter1 Overflow */
+#define TIMER1_OVF_vect            _VECTOR(8)
+#define TIMER1_OVF_vect_num        8
+
+/* TimerCounter0 Compare Match A */
+#define TIMER0_COMPA_vect            _VECTOR(9)
+#define TIMER0_COMPA_vect_num        9
+
+/* TimerCounter0 Compare Match B */
+#define TIMER0_COMPB_vect            _VECTOR(10)
+#define TIMER0_COMPB_vect_num        10
+
+/* Timer/Couner0 Overflow */
+#define TIMER0_OVF_vect            _VECTOR(11)
+#define TIMER0_OVF_vect_num        11
+
+/* Analog Comparator 0 */
+#define ANA_COMP0_vect            _VECTOR(12)
+#define ANA_COMP0_vect_num        12
+
+/* ADC Conversion Complete */
+#define ADC_vect            _VECTOR(13)
+#define ADC_vect_num        13
+
+/* EEPROM Ready */
+#define EE_RDY_vect            _VECTOR(14)
+#define EE_RDY_vect_num        14
+
+/* Analog Comparator 1 */
+#define ANA_COMP1_vect            _VECTOR(15)
+#define ANA_COMP1_vect_num        15
+
+/* Timer/Counter2 Capture Event */
+#define TIMER2_CAPT_vect            _VECTOR(16)
+#define TIMER2_CAPT_vect_num        16
+
+/* Timer/Counter2 Compare Match A */
+#define TIMER2_COMPA_vect            _VECTOR(17)
+#define TIMER2_COMPA_vect_num        17
+
+/* Timer/Counter2 Compare Match B */
+#define TIMER2_COMPB_vect            _VECTOR(18)
+#define TIMER2_COMPB_vect_num        18
+
+/* Timer/Counter2 Overflow */
+#define TIMER2_OVF_vect            _VECTOR(19)
+#define TIMER2_OVF_vect_num        19
+
+/* Serial Peripheral Interface */
+#define SPI_vect            _VECTOR(20)
+#define SPI_vect_num        20
+
+/* USART0, Start */
+#define USART0_START_vect            _VECTOR(21)
+#define USART0_START_vect_num        21
+
+/* USART0, Rx Complete */
+#define USART0_RX_vect            _VECTOR(22)
+#define USART0_RX_vect_num        22
+
+/* USART0 Data Register Empty */
+#define USART0_UDRE_vect            _VECTOR(23)
+#define USART0_UDRE_vect_num        23
+
+/* USART0, Tx Complete */
+#define USART0_TX_vect            _VECTOR(24)
+#define USART0_TX_vect_num        24
+
+/* USART1, Start */
+#define USART1_START_vect            _VECTOR(25)
+#define USART1_START_vect_num        25
+
+/* USART1, Rx Complete */
+#define USART1_RX_vect            _VECTOR(26)
+#define USART1_RX_vect_num        26
+
+/* USART1 Data Register Empty */
+#define USART1_UDRE_vect            _VECTOR(27)
+#define USART1_UDRE_vect_num        27
+
+/* USART1, Tx Complete */
+#define USART1_TX_vect            _VECTOR(28)
+#define USART1_TX_vect_num        28
+
+/* Two-wire Serial Interface */
+#define TWI_SLAVE_vect            _VECTOR(29)
+#define TWI_SLAVE_vect_num        29
+
+#define _VECTORS_SIZE 60
+
+
+/* Constants */
+
+#define SPM_PAGESIZE 16
+#define FLASHSTART   0x0000
+#define FLASHEND     0x1FFF
+#define RAMSTART     0x0100
+#define RAMSIZE      512
+#define RAMEND       0x02FF
+#define E2START     0
+#define E2SIZE      512
+#define E2PAGESIZE  4
+#define E2END       0x01FF
+#define XRAMEND      RAMEND
+
+
+/* Fuses */
+
+#define FUSE_MEMORY_SIZE 3
+
+/* Low Fuse Byte */
+#define FUSE_SUT_CKSEL0  (unsigned char)~_BV(0)
+#define FUSE_SUT_CKSEL1  (unsigned char)~_BV(1)
+#define FUSE_SUT_CKSEL2  (unsigned char)~_BV(2)
+#define FUSE_SUT_CKSEL3  (unsigned char)~_BV(3)
+#define FUSE_SUT_CKSEL4  (unsigned char)~_BV(4)
+#define FUSE_CKOUT       (unsigned char)~_BV(6)
+#define FUSE_CKDIV8      (unsigned char)~_BV(7)
+#define LFUSE_DEFAULT    (FUSE_SUT_CKSEL0 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4 & FUSE_CKDIV8)
+
+
+/* High Fuse Byte */
+#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
+#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
+#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
+#define FUSE_EESAVE      (unsigned char)~_BV(3)
+#define FUSE_WDTON       (unsigned char)~_BV(4)
+#define FUSE_SPIEN       (unsigned char)~_BV(5)
+#define FUSE_DWEN        (unsigned char)~_BV(6)
+#define FUSE_RSTDISBL    (unsigned char)~_BV(7)
+#define HFUSE_DEFAULT    (FUSE_SPIEN)
+
+
+/* Extended Fuse Byte */
+#define FUSE_SELFPRGEN   (unsigned char)~_BV(0)
+#define FUSE_BODACT0     (unsigned char)~_BV(1)
+#define FUSE_BODACT1     (unsigned char)~_BV(2)
+#define FUSE_BODPD0      (unsigned char)~_BV(3)
+#define FUSE_BODPD1      (unsigned char)~_BV(4)
+#define FUSE_ULPOSCSEL0  (unsigned char)~_BV(5)
+#define FUSE_ULPOSCSEL1  (unsigned char)~_BV(6)
+#define FUSE_ULPOSCSEL2  (unsigned char)~_BV(7)
+#define EFUSE_DEFAULT    (0xFF)
+
+
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+
+
+/* Signature */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x93
+#define SIGNATURE_2 0x15
+
+
+#endif /* #ifdef _AVR_ATTINY841_H_INCLUDED */
+

hardware/tools/avr/avr/include/avr/iotn84a.h

@@ -0,0 +1,844 @@
+/* Copyright (c) 2010 Atmel Corporation
+   All rights reserved.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+
+   * Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+
+   * Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in
+     the documentation and/or other materials provided with the
+     distribution.
+
+   * Neither the name of the copyright holders nor the names of
+     contributors may be used to endorse or promote products derived
+     from this software without specific prior written permission.
+
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+  POSSIBILITY OF SUCH DAMAGE. */
+
+/* $Id: iotn84a.h 2435 2014-08-11 10:31:52Z joerg_wunsch $ */
+
+/* avr/iotn84a.h - definitions for ATtiny84A */
+
+/* This file should only be included from <avr/io.h>, never directly. */
+
+#ifndef _AVR_IO_H_
+#  error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+#  define _AVR_IOXXX_H_ "iotn84a.h"
+#else
+#  error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif 
+
+
+#ifndef _AVR_ATtiny84A_H_
+#define _AVR_ATtiny84A_H_ 1
+
+
+/* Registers and associated bit numbers. */
+
+#define PRR _SFR_IO8(0x00)
+#define PRADC 0
+#define PRUSI 1
+#define PRTIM0 2
+#define PRTIM1 3
+
+#define __AVR_HAVE_PRR	((1<<PRADC)|(1<<PRUSI)|(1<<PRTIM0)|(1<<PRTIM1))
+#define __AVR_HAVE_PRR_PRADC
+#define __AVR_HAVE_PRR_PRUSI
+#define __AVR_HAVE_PRR_PRTIM0
+#define __AVR_HAVE_PRR_PRTIM1
+
+#define DIDR0 _SFR_IO8(0x01)
+#define ADC0D 0
+#define ADC1D 1
+#define ADC2D 2
+#define ADC3D 3
+#define ADC4D 4
+#define ADC5D 5
+#define ADC6D 6
+#define ADC7D 7
+
+#define ADCSRB _SFR_IO8(0x03)
+#define ADTS0 0
+#define ADTS1 1
+#define ADTS2 2
+#define ADLAR 4
+#define ACME 6
+#define BIN 7
+
+#ifndef __ASSEMBLER__
+#define ADC _SFR_IO16(0x04)
+#endif
+#define ADCW _SFR_IO16(0x04)
+
+#define ADCL _SFR_IO8(0x04)
+#define ADCL0 0
+#define ADCL1 1
+#define ADCL2 2
+#define ADCL3 3
+#define ADCL4 4
+#define ADCL5 5
+#define ADCL6 6
+#define ADCL7 7
+
+#define ADCH _SFR_IO8(0x05)
+#define ADCH0 0
+#define ADCH1 1
+#define ADCH2 2
+#define ADCH3 3
+#define ADCH4 4
+#define ADCH5 5
+#define ADCH6 6
+#define ADCH7 7
+
+#define ADCSRA _SFR_IO8(0x06)
+#define ADPS0 0
+#define ADPS1 1
+#define ADPS2 2
+#define ADIE 3
+#define ADIF 4
+#define ADATE 5
+#define ADSC 6
+#define ADEN 7
+
+#define ADMUX _SFR_IO8(0x07)
+#define MUX0 0
+#define MUX1 1
+#define MUX2 2
+#define MUX3 3
+#define MUX4 4
+#define MUX5 5
+#define REFS0 6
+#define REFS1 7
+
+#define ACSR _SFR_IO8(0x08)
+#define ACIS0 0
+#define ACIS1 1
+#define ACIC 2
+#define ACIE 3
+#define ACI 4
+#define ACO 5
+#define ACBG 6
+#define ACD 7
+
+#define TIFR1 _SFR_IO8(0x0B)
+#define TOV1 0
+#define OCF1A 1
+#define OCF1B 2
+#define ICF1 5
+
+#define TIMSK1 _SFR_IO8(0x0C)
+#define TOIE1 0
+#define OCIE1A 1
+#define OCIE1B 2
+#define ICIE1 5
+
+#define USICR _SFR_IO8(0x0D)
+#define USITC 0
+#define USICLK 1
+#define USICS0 2
+#define USICS1 3
+#define USIWM0 4
+#define USIWM1 5
+#define USIOIE 6
+#define USISIE 7
+
+#define USISR _SFR_IO8(0x0E)
+#define USICNT0 0
+#define USICNT1 1
+#define USICNT2 2
+#define USICNT3 3
+#define USIDC 4
+#define USIPF 5
+#define USIOIF 6
+#define USISIF 7
+
+#define USIDR _SFR_IO8(0x0F)
+#define USIDR0 0
+#define USIDR1 1
+#define USIDR2 2
+#define USIDR3 3
+#define USIDR4 4
+#define USIDR5 5
+#define USIDR6 6
+#define USIDR7 7
+
+#define USIBR _SFR_IO8(0x10)
+#define USIBR0 0
+#define USIBR1 1
+#define USIBR2 2
+#define USIBR3 3
+#define USIBR4 4
+#define USIBR5 5
+#define USIBR6 6
+#define USIBR7 7
+
+#define PCMSK0 _SFR_IO8(0x12)
+#define PCINT0 0
+#define PCINT1 1
+#define PCINT2 2
+#define PCINT3 3
+#define PCINT4 4
+#define PCINT5 5
+#define PCINT6 6
+#define PCINT7 7
+
+#define GPIOR0 _SFR_IO8(0x13)
+#define GPIOR00 0
+#define GPIOR01 1
+#define GPIOR02 2
+#define GPIOR03 3
+#define GPIOR04 4
+#define GPIOR05 5
+#define GPIOR06 6
+#define GPIOR07 7
+
+#define GPIOR1 _SFR_IO8(0x14)
+#define GPIOR10 0
+#define GPIOR11 1
+#define GPIOR12 2
+#define GPIOR13 3
+#define GPIOR14 4
+#define GPIOR15 5
+#define GPIOR16 6
+#define GPIOR17 7
+
+#define GPIOR2 _SFR_IO8(0x15)
+#define GPIOR20 0
+#define GPIOR21 1
+#define GPIOR22 2
+#define GPIOR23 3
+#define GPIOR24 4
+#define GPIOR25 5
+#define GPIOR26 6
+#define GPIOR27 7
+
+#define PINB _SFR_IO8(0x16)
+#define PINB0 0
+#define PINB1 1
+#define PINB2 2
+#define PINB3 3
+
+#define DDRB _SFR_IO8(0x17)
+#define DDB0 0
+#define DDB1 1
+#define DDB2 2
+#define DDB3 3
+
+#define PORTB _SFR_IO8(0x18)
+#define PORTB0 0
+#define PORTB1 1
+#define PORTB2 2
+#define PORTB3 3
+
+#define PINA _SFR_IO8(0x19)
+#define PINA0 0
+#define PINA1 1
+#define PINA2 2
+#define PINA3 3
+#define PINA4 4
+#define PINA5 5
+#define PINA6 6
+#define PINA7 7
+
+#define DDRA _SFR_IO8(0x1A)
+#define DDA0 0
+#define DDA1 1
+#define DDA2 2
+#define DDA3 3
+#define DDA4 4
+#define DDA5 5
+#define DDA6 6
+#define DDA7 7
+
+#define PORTA _SFR_IO8(0x1B)
+#define PORTA0 0
+#define PORTA1 1
+#define PORTA2 2
+#define PORTA3 3
+#define PORTA4 4
+#define PORTA5 5
+#define PORTA6 6
+#define PORTA7 7
+
+#define EECR _SFR_IO8(0x1C)
+#define EERE 0
+#define EEPE 1
+#define EEMPE 2
+#define EERIE 3
+#define EEPM0 4
+#define EEPM1 5
+
+#define EEDR _SFR_IO8(0x1D)
+#define EEDR0 0
+#define EEDR1 1
+#define EEDR2 2
+#define EEDR3 3
+#define EEDR4 4
+#define EEDR5 5
+#define EEDR6 6
+#define EEDR7 7
+
+#define EEAR _SFR_IO16(0x1E)
+
+#define EEARL _SFR_IO8(0x1E)
+#define EEAR0 0
+#define EEAR1 1
+#define EEAR2 2
+#define EEAR3 3
+#define EEAR4 4
+#define EEAR5 5
+#define EEAR6 6
+#define EEAR7 7
+
+#define EEARH _SFR_IO8(0x1F)
+#define EEAR8 0
+
+#define PCMSK1 _SFR_IO8(0x20)
+#define PCINT8 0
+#define PCINT9 1
+#define PCINT10 2
+#define PCINT11 3
+
+#define WDTCSR _SFR_IO8(0x21)
+#define WDP0 0
+#define WDP1 1
+#define WDP2 2
+#define WDE 3
+#define WDCE 4
+#define WDP3 5
+#define WDIE 6
+#define WDIF 7
+
+#define TCCR1C _SFR_IO8(0x22)
+#define FOC1B 6
+#define FOC1A 7
+
+#define GTCCR _SFR_IO8(0x23)
+#define PSR10 0
+#define TSM 7
+
+#define ICR1 _SFR_IO16(0x24)
+
+#define ICR1L _SFR_IO8(0x24)
+#define ICR1L0 0
+#define ICR1L1 1
+#define ICR1L2 2
+#define ICR1L3 3
+#define ICR1L4 4
+#define ICR1L5 5
+#define ICR1L6 6
+#define ICR1L7 7
+
+#define ICR1H _SFR_IO8(0x25)
+#define ICR1H0 0
+#define ICR1H1 1
+#define ICR1H2 2
+#define ICR1H3 3
+#define ICR1H4 4
+#define ICR1H5 5
+#define ICR1H6 6
+#define ICR1H7 7
+
+#define CLKPR _SFR_IO8(0x26)
+#define CLKPS0 0
+#define CLKPS1 1
+#define CLKPS2 2
+#define CLKPS3 3
+#define CLKPCE 7
+
+#define DWDR _SFR_IO8(0x27)
+
+#define OCR1B _SFR_IO16(0x28)
+
+#define OCR1BL _SFR_IO8(0x28)
+#define OCR1BL0 0
+#define OCR1BL1 1
+#define OCR1BL2 2
+#define OCR1BL3 3
+#define OCR1BL4 4
+#define OCR1BL5 5
+#define OCR1BL6 6
+#define OCR1BL7 7
+
+#define OCR1BH _SFR_IO8(0x29)
+#define OCR1BH0 0
+#define OCR1BH1 1
+#define OCR1BH2 2
+#define OCR1BH3 3
+#define OCR1BH4 4
+#define OCR1BH5 5
+#define OCR1BH6 6
+#define OCR1BH7 7
+
+#define OCR1A _SFR_IO16(0x2A)
+
+#define OCR1AL _SFR_IO8(0x2A)
+#define OCR1AL0 0
+#define OCR1AL1 1
+#define OCR1AL2 2
+#define OCR1AL3 3
+#define OCR1AL4 4
+#define OCR1AL5 5
+#define OCR1AL6 6
+#define OCR1AL7 7
+
+#define OCR1AH _SFR_IO8(0x2B)
+#define OCR1AH0 0
+#define OCR1AH1 1
+#define OCR1AH2 2
+#define OCR1AH3 3
+#define OCR1AH4 4
+#define OCR1AH5 5
+#define OCR1AH6 6
+#define OCR1AH7 7
+
+#define TCNT1 _SFR_IO16(0x2C)
+
+#define TCNT1L _SFR_IO8(0x2C)
+#define TCNT1L0 0
+#define TCNT1L1 1
+#define TCNT1L2 2
+#define TCNT1L3 3
+#define TCNT1L4 4
+#define TCNT1L5 5
+#define TCNT1L6 6
+#define TCNT1L7 7
+
+#define TCNT1H _SFR_IO8(0x2D)
+#define TCNT1H0 0
+#define TCNT1H1 1
+#define TCNT1H2 2
+#define TCNT1H3 3
+#define TCNT1H4 4
+#define TCNT1H5 5
+#define TCNT1H6 6
+#define TCNT1H7 7
+
+#define TCCR1B _SFR_IO8(0x2E)
+#define CS10 0
+#define CS11 1
+#define CS12 2
+#define WGM12 3
+#define WGM13 4
+#define ICES1 6
+#define ICNC1 7
+
+#define TCCR1A _SFR_IO8(0x2F)
+#define WGM10 0
+#define WGM11 1
+#define COM1B0 4
+#define COM1B1 5
+#define COM1A0 6
+#define COM1A1 7
+
+#define TCCR0A _SFR_IO8(0x30)
+#define WGM00 0
+#define WGM01 1
+#define COM0B0 4
+#define COM0B1 5
+#define COM0A0 6
+#define COM0A1 7
+
+#define OSCCAL _SFR_IO8(0x31)
+#define CAL0 0
+#define CAL1 1
+#define CAL2 2
+#define CAL3 3
+#define CAL4 4
+#define CAL5 5
+#define CAL6 6
+#define CAL7 7
+
+#define TCNT0 _SFR_IO8(0x32)
+#define TCNT0_0 0
+#define TCNT0_1 1
+#define TCNT0_2 2
+#define TCNT0_3 3
+#define TCNT0_4 4
+#define TCNT0_5 5
+#define TCNT0_6 6
+#define TCNT0_7 7
+
+#define TCCR0B _SFR_IO8(0x33)
+#define CS00 0
+#define CS01 1
+#define CS02 2
+#define WGM02 3
+#define FOC0B 6
+#define FOC0A 7
+
+#define MCUSR _SFR_IO8(0x34)
+#define PORF 0
+#define EXTRF 1
+#define BORF 2
+#define WDRF 3
+
+#define MCUCR _SFR_IO8(0x35)
+#define ISC00 0
+#define ISC01 1
+#define BODSE 2
+#define SM0 3
+#define SM1 4
+#define SE 5
+#define PUD 6
+#define BODS 7
+
+#define OCR0A _SFR_IO8(0x36)
+#define OCR0A_0 0
+#define OCR0A_1 1
+#define OCR0A_2 2
+#define OCR0A_3 3
+#define OCR0A_4 4
+#define OCR0A_5 5
+#define OCR0A_6 6
+#define OCR0A_7 7
+
+#define SPMCSR _SFR_IO8(0x37)
+#define SPMEN 0
+#define PGERS 1
+#define PGWRT 2
+#define RFLB 3
+#define CTPB 4
+
+#define TIFR0 _SFR_IO8(0x38)
+#define TOV0 0
+#define OCF0A 1
+#define OCF0B 2
+
+#define TIMSK0 _SFR_IO8(0x39)
+#define TOIE0 0
+#define OCIE0A 1
+#define OCIE0B 2
+
+#define GIFR _SFR_IO8(0x3A)
+#define PCIF0 4
+#define PCIF1 5
+#define INTF0 6
+
+#define GIMSK _SFR_IO8(0x3B)
+#define PCIE0 4
+#define PCIE1 5
+#define INT0 6
+
+#define OCR0B _SFR_IO8(0x3C)
+#define OCR0_0 0
+#define OCR0_1 1
+#define OCR0_2 2
+#define OCR0_3 3
+#define OCR0_4 4
+#define OCR0_5 5
+#define OCR0_6 6
+#define OCR0_7 7
+
+
+/* Interrupt vectors */
+/* Vector 0 is the reset vector */
+#define EXT_INT0_vect_num  1
+#define EXT_INT0_vect      _VECTOR(1)  /* External Interrupt Request 0 */
+#define PCINT0_vect_num  2
+#define PCINT0_vect      _VECTOR(2)  /* Pin Change Interrupt Request 0 */
+#define PCINT1_vect_num  3
+#define PCINT1_vect      _VECTOR(3)  /* Pin Change Interrupt Request 1 */
+#define WATCHDOG_vect_num  4
+#define WATCHDOG_vect      _VECTOR(4)  /* Watchdog Time-out */
+#define TIM1_CAPT_vect_num  5
+#define TIM1_CAPT_vect      _VECTOR(5)  /* Timer/Counter1 Capture Event */
+#define TIM1_COMPA_vect_num  6
+#define TIM1_COMPA_vect      _VECTOR(6)  /* Timer/Counter1 Compare Match A */
+#define TIM1_COMPB_vect_num  7
+#define TIM1_COMPB_vect      _VECTOR(7)  /* Timer/Counter1 Compare Match B */
+#define TIM1_OVF_vect_num  8
+#define TIM1_OVF_vect      _VECTOR(8)  /* Timer/Counter1 Overflow */
+#define TIM0_COMPA_vect_num  9
+#define TIM0_COMPA_vect      _VECTOR(9)  /* Timer/Counter0 Compare Match A */
+#define TIM0_COMPB_vect_num  10
+#define TIM0_COMPB_vect      _VECTOR(10)  /* Timer/Counter0 Compare Match B */
+#define TIM0_OVF_vect_num  11
+#define TIM0_OVF_vect      _VECTOR(11)  /* Timer/Counter0 Overflow */
+#define ANA_COMP_vect_num  12
+#define ANA_COMP_vect      _VECTOR(12)  /* Analog Comparator */
+#define ADC_vect_num  13
+#define ADC_vect      _VECTOR(13)  /* ADC Conversion Complete */
+#define EE_RDY_vect_num  14
+#define EE_RDY_vect      _VECTOR(14)  /* EEPROM Ready */
+#define USI_STR_vect_num  15
+#define USI_STR_vect      _VECTOR(15)  /* USI START */
+#define USI_OVF_vect_num  16
+#define USI_OVF_vect      _VECTOR(16)  /* USI Overflow */
+
+#define _VECTOR_SIZE 2 /* Size of individual vector. */
+#define _VECTORS_SIZE (17 * _VECTOR_SIZE)
+
+
+/* Constants */
+#define SPM_PAGESIZE (64)
+#define RAMSTART     (0x60)
+#define RAMSIZE      (512)
+#define RAMEND       (RAMSTART + RAMSIZE - 1)
+#define XRAMSTART    (NA)
+#define XRAMSIZE     (0)
+#define XRAMEND      (RAMEND)
+#define E2END        (0x1FF)
+#define E2PAGESIZE   (4)
+#define FLASHEND     (0x1FFF)
+
+
+/* Fuses */
+#define FUSE_MEMORY_SIZE 3
+
+/* Low Fuse Byte */
+#define FUSE_CKSEL0  (unsigned char)~_BV(0)  /* Select Clock source */
+#define FUSE_CKSEL1  (unsigned char)~_BV(1)  /* Select Clock source */
+#define FUSE_CKSEL2  (unsigned char)~_BV(2)  /* Select Clock source */
+#define FUSE_CKSEL3  (unsigned char)~_BV(3)  /* Select Clock source */
+#define FUSE_SUT0  (unsigned char)~_BV(4)  /* Select start-up time */
+#define FUSE_SUT1  (unsigned char)~_BV(5)  /* Select start-up time */
+#define FUSE_CKOUT  (unsigned char)~_BV(6)  /* Clock Output Enable */
+#define FUSE_CKDIV8  (unsigned char)~_BV(7)  /* Divide clock by 8 */
+#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
+
+/* High Fuse Byte */
+#define FUSE_BODLEVEL0  (unsigned char)~_BV(0)  /* Brown-out Detector trigger level */
+#define FUSE_BODLEVEL1  (unsigned char)~_BV(1)  /* Brown-out Detector trigger level */
+#define FUSE_BODLEVEL2  (unsigned char)~_BV(2)  /* Brown-out Detector trigger level */
+#define FUSE_EESAVE  (unsigned char)~_BV(3)  /* EEPROM memory is preserved through the Chip Erase */
+#define FUSE_WDTON  (unsigned char)~_BV(4)  /* Watchdog Timer always on */
+#define FUSE_SPIEN  (unsigned char)~_BV(5)  /* Enable Serial Program and Data Downloading */
+#define FUSE_DWEN  (unsigned char)~_BV(6)  /* DebugWIRE Enable */
+#define FUSE_RSTDISBL  (unsigned char)~_BV(7)  /* External Reset disable */
+#define HFUSE_DEFAULT (FUSE_SPIEN)
+
+/* Extended Fuse Byte */
+#define FUSE_SELFPRGEN  (unsigned char)~_BV(0)  /* Self-Programming Enable */
+#define EFUSE_DEFAULT (0xFF)
+
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+
+
+/* Signature */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x93
+#define SIGNATURE_2 0x0C
+
+
+/* Device Pin Definitions */
+#define ADC4_DDR   DDRA
+#define ADC4_PORT  PORTA
+#define ADC4_PIN   PINA
+#define ADC4_BIT   4
+
+#define USCK_DDR   DDRA
+#define USCK_PORT  PORTA
+#define USCK_PIN   PINA
+#define USCK_BIT   4
+
+#define SCL_DDR   DDRA
+#define SCL_PORT  PORTA
+#define SCL_PIN   PINA
+#define SCL_BIT   4
+
+#define T1_DDR   DDRA
+#define T1_PORT  PORTA
+#define T1_PIN   PINA
+#define T1_BIT   4
+
+#define PCINT4_DDR   DDRA
+#define PCINT4_PORT  PORTA
+#define PCINT4_PIN   PINA
+#define PCINT4_BIT   4
+
+#define ADC3_DDR   DDRA
+#define ADC3_PORT  PORTA
+#define ADC3_PIN   PINA
+#define ADC3_BIT   3
+
+#define T0_DDR   DDRA
+#define T0_PORT  PORTA
+#define T0_PIN   PINA
+#define T0_BIT   3
+
+#define PCINT3_DDR   DDRA
+#define PCINT3_PORT  PORTA
+#define PCINT3_PIN   PINA
+#define PCINT3_BIT   3
+
+#define ADC2_DDR   DDRA
+#define ADC2_PORT  PORTA
+#define ADC2_PIN   PINA
+#define ADC2_BIT   2
+
+#define AIN1_DDR   DDRA
+#define AIN1_PORT  PORTA
+#define AIN1_PIN   PINA
+#define AIN1_BIT   2
+
+#define PCINT2_DDR   DDRA
+#define PCINT2_PORT  PORTA
+#define PCINT2_PIN   PINA
+#define PCINT2_BIT   2
+
+#define ADC1_DDR   DDRA
+#define ADC1_PORT  PORTA
+#define ADC1_PIN   PINA
+#define ADC1_BIT   1
+
+#define AIN0_DDR   DDRA
+#define AIN0_PORT  PORTA
+#define AIN0_PIN   PINA
+#define AIN0_BIT   1
+
+#define PCINT1_DDR   DDRA
+#define PCINT1_PORT  PORTA
+#define PCINT1_PIN   PINA
+#define PCINT1_BIT   1
+
+#define ADC0_DDR   DDRA
+#define ADC0_PORT  PORTA
+#define ADC0_PIN   PINA
+#define ADC0_BIT   0
+
+#define PCINT0_DDR   DDRA
+#define PCINT0_PORT  PORTA
+#define PCINT0_PIN   PINA
+#define PCINT0_BIT   0
+
+#define PCINT8_DDR   DDRB
+#define PCINT8_PORT  PORTB
+#define PCINT8_PIN   PINB
+#define PCINT8_BIT   0
+
+#define PCINT9_DDR   DDRB
+#define PCINT9_PORT  PORTB
+#define PCINT9_PIN   PINB
+#define PCINT9_BIT   1
+
+#define PCINT11_DDR   DDRB
+#define PCINT11_PORT  PORTB
+#define PCINT11_PIN   PINB
+#define PCINT11_BIT   3
+
+#define dW_DDR   DDRB
+#define dW_PORT  PORTB
+#define dW_PIN   PINB
+#define dW_BIT   3
+
+#define PCINT10_DDR   DDRB
+#define PCINT10_PORT  PORTB
+#define PCINT10_PIN   PINB
+#define PCINT10_BIT   2
+
+#define INT0_DDR   DDRB
+#define INT0_PORT  PORTB
+#define INT0_PIN   PINB
+#define INT0_BIT   2
+
+#define OC0A_DDR   DDRB
+#define OC0A_PORT  PORTB
+#define OC0A_PIN   PINB
+#define OC0A_BIT   2
+
+#define CKOUT_DDR   DDRB
+#define CKOUT_PORT  PORTB
+#define CKOUT_PIN   PINB
+#define CKOUT_BIT   2
+
+#define PCINT7_DDR   DDRA
+#define PCINT7_PORT  PORTA
+#define PCINT7_PIN   PINA
+#define PCINT7_BIT   7
+
+#define ICP1_DDR   DDRA
+#define ICP1_PORT  PORTA
+#define ICP1_PIN   PINA
+#define ICP1_BIT   7
+
+#define OC0B_DDR   DDRA
+#define OC0B_PORT  PORTA
+#define OC0B_PIN   PINA
+#define OC0B_BIT   7
+
+#define ADC7_DDR   DDRA
+#define ADC7_PORT  PORTA
+#define ADC7_PIN   PINA
+#define ADC7_BIT   7
+
+#define PCINT6_DDR   DDRA
+#define PCINT6_PORT  PORTA
+#define PCINT6_PIN   PINA
+#define PCINT6_BIT   6
+
+#define OC1A_DDR   DDRA
+#define OC1A_PORT  PORTA
+#define OC1A_PIN   PINA
+#define OC1A_BIT   6
+
+#define DI_DDR   DDRA
+#define DI_PORT  PORTA
+#define DI_PIN   PINA
+#define DI_BIT   6
+
+#define SDA_DDR   DDRA
+#define SDA_PORT  PORTA
+#define SDA_PIN   PINA
+#define SDA_BIT   6
+
+#define MOSI_DDR   DDRA
+#define MOSI_PORT  PORTA
+#define MOSI_PIN   PINA
+#define MOSI_BIT   6
+
+#define ADC6_DDR   DDRA
+#define ADC6_PORT  PORTA
+#define ADC6_PIN   PINA
+#define ADC6_BIT   6
+
+#define ADC5_DDR   DDRA
+#define ADC5_PORT  PORTA
+#define ADC5_PIN   PINA
+#define ADC5_BIT   5
+
+#define DO_DDR   DDRA
+#define DO_PORT  PORTA
+#define DO_PIN   PINA
+#define DO_BIT   5
+
+#define MISO_DDR   DDRA
+#define MISO_PORT  PORTA
+#define MISO_PIN   PINA
+#define MISO_BIT   5
+
+#define OC1B_DDR   DDRA
+#define OC1B_PORT  PORTA
+#define OC1B_PIN   PINA
+#define OC1B_BIT   5
+
+#define PCINT5_DDR   DDRA
+#define PCINT5_PORT  PORTA
+#define PCINT5_PIN   PINA
+#define PCINT5_BIT   5
+
+#define SLEEP_MODE_IDLE (0x00<<3)
+#define SLEEP_MODE_ADC (0x01<<3)
+#define SLEEP_MODE_PWR_DOWN (0x02<<3)
+#define SLEEP_MODE_STANDBY (0x03<<3)
+
+#endif /* _AVR_ATtiny84A_H_ */
+

hardware/tools/avr/avr/include/avr/iotn85.h

@@ -0,0 +1,93 @@
+/* Copyright (c) 2005, Joerg Wunsch
+   All rights reserved.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+
+   * Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+
+   * Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in
+     the documentation and/or other materials provided with the
+     distribution.
+
+   * Neither the name of the copyright holders nor the names of
+     contributors may be used to endorse or promote products derived
+     from this software without specific prior written permission.
+
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+  POSSIBILITY OF SUCH DAMAGE. */
+
+/* $Id: iotn85.h 2115 2010-04-05 23:19:53Z arcanum $ */
+
+/* avr/iotn85.h - definitions for ATtiny85 */
+
+#ifndef _AVR_IOTN85_H_
+#define _AVR_IOTN85_H_ 1
+
+#include <avr/iotnx5.h>
+
+/* Constants */
+#define SPM_PAGESIZE 64
+#define RAMSTART     (0x60)
+#define RAMEND       0x25F
+#define XRAMEND      RAMEND
+#define E2END        0x1FF
+#define E2PAGESIZE   4
+#define FLASHEND     0x1FFF
+
+
+/* Fuses */
+#define FUSE_MEMORY_SIZE 3
+
+/* Low Fuse Byte */
+#define FUSE_CKSEL0      (unsigned char)~_BV(0)
+#define FUSE_CKSEL1      (unsigned char)~_BV(1)
+#define FUSE_CKSEL2      (unsigned char)~_BV(2)
+#define FUSE_CKSEL3      (unsigned char)~_BV(3)
+#define FUSE_SUT0        (unsigned char)~_BV(4)
+#define FUSE_SUT1        (unsigned char)~_BV(5)
+#define FUSE_CKOUT       (unsigned char)~_BV(6)
+#define FUSE_CKDIV8      (unsigned char)~_BV(7)
+#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
+
+/* High Fuse Byte */
+#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
+#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
+#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
+#define FUSE_EESAVE      (unsigned char)~_BV(3)
+#define FUSE_WDTON       (unsigned char)~_BV(4)
+#define FUSE_SPIEN       (unsigned char)~_BV(5)
+#define FUSE_DWEN        (unsigned char)~_BV(6)
+#define FUSE_RSTDISBL    (unsigned char)~_BV(7)
+#define HFUSE_DEFAULT (FUSE_SPIEN)
+
+/* Extended Fuse Byte */
+#define FUSE_SELFPRGEN   (unsigned char)~_BV(0)
+#define EFUSE_DEFAULT (0xFF)
+
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+
+
+/* Signature */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x93
+#define SIGNATURE_2 0x0B
+
+#define SLEEP_MODE_IDLE (0x00<<3)
+#define SLEEP_MODE_ADC (0x01<<3)
+#define SLEEP_MODE_PWR_DOWN (0x02<<3)
+
+#endif /* _AVR_IOTN85_H_ */

hardware/tools/avr/avr/include/avr/iotn861.h

@@ -0,0 +1,94 @@
+/* Copyright (c) 2006, Anatoly Sokolov
+   All rights reserved.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+
+   * Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+
+   * Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in
+     the documentation and/or other materials provided with the
+     distribution.
+
+   * Neither the name of the copyright holders nor the names of
+     contributors may be used to endorse or promote products derived
+     from this software without specific prior written permission.
+
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+  POSSIBILITY OF SUCH DAMAGE. */
+
+/* $Id: iotn861.h 2115 2010-04-05 23:19:53Z arcanum $ */
+
+/* avr/iotn861.h - definitions for ATtiny861 */
+
+#ifndef _AVR_IOTN861_H_
+#define _AVR_IOTN861_H_ 1
+
+#include <avr/iotnx61.h>
+
+/* Constants */
+#define SPM_PAGESIZE 64
+#define RAMSTART     (0x60)
+#define RAMEND       0x25F
+#define XRAMEND      RAMEND
+#define E2END        0x1FF
+#define E2PAGESIZE   4
+#define FLASHEND     0x1FFF
+
+
+/* Fuses */
+#define FUSE_MEMORY_SIZE 3
+
+/* Low Fuse Byte */
+#define FUSE_CKSEL0      (unsigned char)~_BV(0)
+#define FUSE_CKSEL1      (unsigned char)~_BV(1)
+#define FUSE_CKSEL2      (unsigned char)~_BV(2)
+#define FUSE_CKSEL3      (unsigned char)~_BV(3)
+#define FUSE_SUT0        (unsigned char)~_BV(4)
+#define FUSE_SUT1        (unsigned char)~_BV(5)
+#define FUSE_CKOUT       (unsigned char)~_BV(6)
+#define FUSE_CKDIV8      (unsigned char)~_BV(7)
+#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
+
+/* High Fuse Byte */
+#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
+#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
+#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
+#define FUSE_EESAVE      (unsigned char)~_BV(3)
+#define FUSE_WDTON       (unsigned char)~_BV(4)
+#define FUSE_SPIEN       (unsigned char)~_BV(5)
+#define FUSE_DWEN        (unsigned char)~_BV(6)
+#define FUSE_RSTDISBL    (unsigned char)~_BV(7)
+#define HFUSE_DEFAULT (FUSE_SPIEN)
+
+/* Extended Fuse Byte */
+#define FUSE_SELFPRGEN   (unsigned char)~_BV(0)
+#define EFUSE_DEFAULT (0xFF)
+
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+
+
+/* Signature */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x93
+#define SIGNATURE_2 0x0D
+
+#define SLEEP_MODE_IDLE (0x00<<3)
+#define SLEEP_MODE_ADC (0x01<<3)
+#define SLEEP_MODE_PWR_DOWN (0x02<<3)
+#define SLEEP_MODE_STANDBY (0x03<<3)
+
+#endif /* _AVR_IOTN861_H_ */

hardware/tools/avr/avr/include/avr/iotn861a.h

@@ -0,0 +1,988 @@
+/* Copyright (c) 2009 Atmel Corporation
+   All rights reserved.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+
+   * Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+
+   * Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in
+     the documentation and/or other materials provided with the
+     distribution.
+
+   * Neither the name of the copyright holders nor the names of
+     contributors may be used to endorse or promote products derived
+     from this software without specific prior written permission.
+
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+  POSSIBILITY OF SUCH DAMAGE. */
+
+/* $Id: iotn861a.h 2063 2009-11-18 22:06:28Z arcanum $ */
+
+/* avr/iotn861a.h - definitions for ATtiny861A */
+
+/* This file should only be included from <avr/io.h>, never directly. */
+
+#ifndef _AVR_IO_H_
+#  error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+#  define _AVR_IOXXX_H_ "iotn861a.h"
+#else
+#  error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif 
+
+
+#ifndef _AVR_ATtiny861A_H_
+#define _AVR_ATtiny861A_H_ 1
+
+
+/* Registers and associated bit numbers. */
+
+#define TCCR1E _SFR_IO8(0x00)
+#define OC1OE0 0
+#define OC1OE1 1
+#define OC1OE2 2
+#define OC1OE3 3
+#define OC1OE4 4
+#define OC1OE5 5
+
+#define DIDR0 _SFR_IO8(0x01)
+#define ADC0D 0
+#define ADC1D 1
+#define ADC2D 2
+#define AREFD 3
+#define ADC3D 4
+#define ADC4D 5
+#define ADC5D 6
+#define ADC6D 7
+
+#define DIDR1 _SFR_IO8(0x02)
+#define ADC7D 4
+#define ADC8D 5
+#define ADC9D 6
+#define ADC10D 7
+
+#define ADCSRB _SFR_IO8(0x03)
+#define ADTS0 0
+#define ADTS1 1
+#define ADTS2 2
+#define MUX5 3
+#define REFS2 4
+#define IPR 5
+#define GSEL 6
+#define BIN 7
+
+#ifndef __ASSEMBLER__
+#define ADC _SFR_IO16(0x04)
+#endif
+#define ADCW _SFR_IO16(0x04)
+
+#define ADCL _SFR_IO8(0x04)
+#define ADCL0 0
+#define ADCL1 1
+#define ADCL2 2
+#define ADCL3 3
+#define ADCL4 4
+#define ADCL5 5
+#define ADCL6 6
+#define ADCL7 7
+
+#define ADCH _SFR_IO8(0x05)
+#define ADCH0 0
+#define ADCH1 1
+#define ADCH2 2
+#define ADCH3 3
+#define ADCH4 4
+#define ADCH5 5
+#define ADCH6 6
+#define ADCH7 7
+
+#define ADCSRA _SFR_IO8(0x06)
+#define ADPS0 0
+#define ADPS1 1
+#define ADPS2 2
+#define ADIE 3
+#define ADIF 4
+#define ADATE 5
+#define ADSC 6
+#define ADEN 7
+
+#define ADMUX _SFR_IO8(0x07)
+#define MUX0 0
+#define MUX1 1
+#define MUX2 2
+#define MUX3 3
+#define MUX4 4
+#define ADLAR 5
+#define REFS0 6
+#define REFS1 7
+
+#define ACSRA _SFR_IO8(0x08)
+#define ACIS0 0
+#define ACIS1 1
+#define ACME 2
+#define ACIE 3
+#define ACI 4
+#define ACO 5
+#define ACBG 6
+#define ACD 7
+
+#define ACSRB _SFR_IO8(0x09)
+#define ACM0 0
+#define ACM1 1
+#define ACM2 2
+#define HLEV 6
+#define HSEL 7
+
+#define GPIOR0 _SFR_IO8(0x0A)
+#define GPIOR00 0
+#define GPIOR01 1
+#define GPIOR02 2
+#define GPIOR03 3
+#define GPIOR04 4
+#define GPIOR05 5
+#define GPIOR06 6
+#define GPIOR07 7
+
+#define GPIOR1 _SFR_IO8(0x0B)
+#define GPIOR10 0
+#define GPIOR11 1
+#define GPIOR12 2
+#define GPIOR13 3
+#define GPIOR14 4
+#define GPIOR15 5
+#define GPIOR16 6
+#define GPIOR17 7
+
+#define GPIOR2 _SFR_IO8(0x0C)
+#define GPIOR20 0
+#define GPIOR21 1
+#define GPIOR22 2
+#define GPIOR23 3
+#define GPIOR24 4
+#define GPIOR25 5
+#define GPIOR26 6
+#define GPIOR27 7
+
+#define USICR _SFR_IO8(0x0D)
+#define USITC 0
+#define USICLK 1
+#define USICS0 2
+#define USICS1 3
+#define USIWM0 4
+#define USIWM1 5
+#define USIOIE 6
+#define USISIE 7
+
+#define USISR _SFR_IO8(0x0E)
+#define USICNT0 0
+#define USICNT1 1
+#define USICNT2 2
+#define USICNT3 3
+#define USIDC 4
+#define USIPF 5
+#define USIOIF 6
+#define USISIF 7
+
+#define USIDR _SFR_IO8(0x0F)
+#define USIDR0 0
+#define USIDR1 1
+#define USIDR2 2
+#define USIDR3 3
+#define USIDR4 4
+#define USIDR5 5
+#define USIDR6 6
+#define USIDR7 7
+
+#define USIBR _SFR_IO8(0x10)
+#define USIBR0 0
+#define USIBR1 1
+#define USIBR2 2
+#define USIBR3 3
+#define USIBR4 4
+#define USIBR5 5
+#define USIBR6 6
+#define USIBR7 7
+
+#define USIPP _SFR_IO8(0x11)
+#define USIPOS 0
+
+#define OCR0B _SFR_IO8(0x12)
+#define OCR0B_0 0
+#define OCR0B_1 1
+#define OCR0B_2 2
+#define OCR0B_3 3
+#define OCR0B_4 4
+#define OCR0B_5 5
+#define OCR0B_6 6
+#define OCR0B_7 7
+
+#define OCR0A _SFR_IO8(0x13)
+#define OCR0A_0 0
+#define OCR0A_1 1
+#define OCR0A_2 2
+#define OCR0A_3 3
+#define OCR0A_4 4
+#define OCR0A_5 5
+#define OCR0A_6 6
+#define OCR0A_7 7
+
+#define TCNT0H _SFR_IO8(0x14)
+#define TCNT0H_0 0
+#define TCNT0H_1 1
+#define TCNT0H_2 2
+#define TCNT0H_3 3
+#define TCNT0H_4 4
+#define TCNT0H_5 5
+#define TCNT0H_6 6
+#define TCNT0H_7 7
+
+#define TCCR0A _SFR_IO8(0x15)
+#define WGM00 0
+#define ACIC0 3
+#define ICES0 4
+#define ICNC0 5
+#define ICEN0 6
+#define TCW0 7
+
+#define PINB _SFR_IO8(0x16)
+#define PINB0 0
+#define PINB1 1
+#define PINB2 2
+#define PINB3 3
+#define PINB4 4
+#define PINB5 5
+#define PINB6 6
+#define PINB7 7
+
+#define DDRB _SFR_IO8(0x17)
+#define DDB0 0
+#define DDB1 1
+#define DDB2 2
+#define DDB3 3
+#define DDB4 4
+#define DDB5 5
+#define DDB6 6
+#define DDB7 7
+
+#define PORTB _SFR_IO8(0x18)
+#define PORTB0 0
+#define PORTB1 1
+#define PORTB2 2
+#define PORTB3 3
+#define PORTB4 4
+#define PORTB5 5
+#define PORTB6 6
+#define PORTB7 7
+
+#define PINA _SFR_IO8(0x19)
+#define PINA0 0
+#define PINA1 1
+#define PINA2 2
+#define PINA3 3
+#define PINA4 4
+#define PINA5 5
+#define PINA6 6
+#define PINA7 7
+
+#define DDRA _SFR_IO8(0x1A)
+#define DDA0 0
+#define DDA1 1
+#define DDA2 2
+#define DDA3 3
+#define DDA4 4
+#define DDA5 5
+#define DDA6 6
+#define DDA7 7
+
+#define PORTA _SFR_IO8(0x1B)
+#define PORTA0 0
+#define PORTA1 1
+#define PORTA2 2
+#define PORTA3 3
+#define PORTA4 4
+#define PORTA5 5
+#define PORTA6 6
+#define PORTA7 7
+
+#define EECR _SFR_IO8(0x1C)
+#define EERE 0
+#define EEPE 1
+#define EEMPE 2
+#define EERIE 3
+#define EEPM0 4
+#define EEPM1 5
+
+#define EEDR _SFR_IO8(0x1D)
+#define EEDR0 0
+#define EEDR1 1
+#define EEDR2 2
+#define EEDR3 3
+#define EEDR4 4
+#define EEDR5 5
+#define EEDR6 6
+#define EEDR7 7
+
+#define EEAR _SFR_IO16(0x1E)
+
+#define EEARL _SFR_IO8(0x1E)
+#define EEAR0 0
+#define EEAR1 1
+#define EEAR2 2
+#define EEAR3 3
+#define EEAR4 4
+#define EEAR5 5
+#define EEAR6 6
+#define EEAR7 7
+
+#define EEARH _SFR_IO8(0x1F)
+#define EEAR8 0
+
+#define DWDR _SFR_IO8(0x20)
+#define DWDR0 0
+#define DWDR1 1
+#define DWDR2 2
+#define DWDR3 3
+#define DWDR4 4
+#define DWDR5 5
+#define DWDR6 6
+#define DWDR7 7
+
+#define WDTCR _SFR_IO8(0x21)
+#define WDP0 0
+#define WDP1 1
+#define WDP2 2
+#define WDE 3
+#define WDCE 4
+#define WDP3 5
+#define WDIE 6
+#define WDIF 7
+
+#define PCMSK1 _SFR_IO8(0x22)
+#define PCINT8 0
+#define PCINT9 1
+#define PCINT10 2
+#define PCINT11 3
+#define PCINT12 4
+#define PCINT13 5
+#define PCINT14 6
+#define PCINT15 7
+
+#define PCMSK0 _SFR_IO8(0x23)
+#define PCINT0 0
+#define PCINT1 1
+#define PCINT2 2
+#define PCINT3 3
+#define PCINT4 4
+#define PCINT5 5
+#define PCINT6 6
+#define PCINT7 7
+
+#define DT1 _SFR_IO8(0x24)
+#define DT1L0 0
+#define DT1L1 1
+#define DT1L2 2
+#define DT1L3 3
+#define DT1H0 4
+#define DT1H1 5
+#define DT1H2 6
+#define DT1H3 7
+
+#define TC1H _SFR_IO8(0x25)
+#define TC18 0
+#define TC19 1
+
+#define TCCR1D _SFR_IO8(0x26)
+#define WGM10 0
+#define WGM11 1
+#define FPF1 2
+#define FPAC1 3
+#define FPES1 4
+#define FPNC1 5
+#define FPEN1 6
+#define FPIE1 7
+
+#define TCCR1C _SFR_IO8(0x27)
+#define PWM1D 0
+#define FOC1D 1
+#define COM1D0 2
+#define COM1D1 3
+#define COM1B0S 4
+#define COM1B1S 5
+#define COM1A0S 6
+#define COM1A1S 7
+
+#define CLKPR _SFR_IO8(0x28)
+#define CLKPS0 0
+#define CLKPS1 1
+#define CLKPS2 2
+#define CLKPS3 3
+#define CLKPCE 7
+
+#define PLLCSR _SFR_IO8(0x29)
+#define PLOCK 0
+#define PLLE 1
+#define PCKE 2
+#define LSM 7
+
+#define OCR1D _SFR_IO8(0x2A)
+#define OCR1D0 0
+#define OCR1D1 1
+#define OCR1D2 2
+#define OCR1D3 3
+#define OCR1D4 4
+#define OCR1D5 5
+#define OCR1D6 6
+#define OCR1D7 7
+
+#define OCR1C _SFR_IO8(0x2B)
+#define OCR1C0 0
+#define OCR1C1 1
+#define OCR1C2 2
+#define OCR1C3 3
+#define OCR1C4 4
+#define OCR1C5 5
+#define OCR1C6 6
+#define OCR1C7 7
+
+#define OCR1B _SFR_IO8(0x2C)
+#define OCR1B0 0
+#define OCR1B1 1
+#define OCR1B2 2
+#define OCR1B3 3
+#define OCR1B4 4
+#define OCR1B5 5
+#define OCR1B6 6
+#define OCR1B7 7
+
+#define OCR1A _SFR_IO8(0x2D)
+#define OCR1A0 0
+#define OCR1A1 1
+#define OCR1A2 2
+#define OCR1A3 3
+#define OCR1A4 4
+#define OCR1A5 5
+#define OCR1A6 6
+#define OCR1A7 7
+
+#define TCNT1 _SFR_IO8(0x2E)
+#define TC1H_0 0
+#define TC1H_1 1
+#define TC1H_2 2
+#define TC1H_3 3
+#define TC1H_4 4
+#define TC1H_5 5
+#define TC1H_6 6
+#define TC1H_7 7
+
+#define TCCR1B _SFR_IO8(0x2F)
+#define CS10 0
+#define CS11 1
+#define CS12 2
+#define CS13 3
+#define DTPS10 4
+#define DTPS11 5
+#define PSR1 6
+#define PWM1X 7
+
+#define TCCR1A _SFR_IO8(0x30)
+#define PWM1B 0
+#define PWM1A 1
+#define FOC1B 2
+#define FOC1A 3
+#define COM1B0 4
+#define COM1B1 5
+#define COM1A0 6
+#define COM1A1 7
+
+#define OSCCAL _SFR_IO8(0x31)
+#define CAL0 0
+#define CAL1 1
+#define CAL2 2
+#define CAL3 3
+#define CAL4 4
+#define CAL5 5
+#define CAL6 6
+#define CAL7 7
+
+#define TCNT0L _SFR_IO8(0x32)
+#define TCNT0L_0 0
+#define TCNT0L_1 1
+#define TCNT0L_2 2
+#define TCNT0L_3 3
+#define TCNT0L_4 4
+#define TCNT0L_5 5
+#define TCNT0L_6 6
+#define TCNT0L_7 7
+
+#define TCCR0B _SFR_IO8(0x33)
+#define CS00 0
+#define CS01 1
+#define CS02 2
+#define PSR0 3
+#define TSM 4
+
+#define MCUSR _SFR_IO8(0x34)
+#define PORF 0
+#define EXTRF 1
+#define BORF 2
+#define WDRF 3
+
+#define MCUCR _SFR_IO8(0x35)
+#define ISC00 0
+#define ISC01 1
+#define BODSE 2
+#define SM0 3
+#define SM1 4
+#define SE 5
+#define PUD 6
+#define BODS 7
+
+#define PRR _SFR_IO8(0x36)
+#define PRADC 0
+#define PRUSI 1
+#define PRTIM0 2
+#define PRTIM1 3
+
+#define __AVR_HAVE_PRR	((1<<PRADC)|(1<<PRUSI)|(1<<PRTIM0)|(1<<PRTIM1))
+#define __AVR_HAVE_PRR_PRADC
+#define __AVR_HAVE_PRR_PRUSI
+#define __AVR_HAVE_PRR_PRTIM0
+#define __AVR_HAVE_PRR_PRTIM1
+
+#define SPMCSR _SFR_IO8(0x37)
+#define SPMEN 0
+#define PGERS 1
+#define PGWRT 2
+#define RFLB 3
+#define CTPB 4
+
+#define TIFR _SFR_IO8(0x38)
+#define ICF0 0
+#define TOV0 1
+#define TOV1 2
+#define OCF0B 3
+#define OCF0A 4
+#define OCF1B 5
+#define OCF1A 6
+#define OCF1D 7
+
+#define TIMSK _SFR_IO8(0x39)
+#define TICIE0 0
+#define TOIE0 1
+#define TOIE1 2
+#define OCIE0B 3
+#define OCIE0A 4
+#define OCIE1B 5
+#define OCIE1A 6
+#define OCIE1D 7
+
+#define GIFR _SFR_IO8(0x3A)
+#define PCIF 5
+#define INTF0 6
+#define INTF1 7
+
+#define GIMSK _SFR_IO8(0x3B)
+#define PCIE0 4
+#define PCIE1 5
+#define INT0 6
+#define INT1 7
+
+
+/* Interrupt vectors */
+/* Vector 0 is the reset vector */
+#define INT0_vect_num  1
+#define INT0_vect      _VECTOR(1)  /* External Interrupt 0 */
+#define PCINT_vect_num  2
+#define PCINT_vect      _VECTOR(2)  /* Pin Change Interrupt */
+#define TIMER1_COMPA_vect_num  3
+#define TIMER1_COMPA_vect      _VECTOR(3)  /* Timer/Counter1 Compare Match 1A */
+#define TIMER1_COMPB_vect_num  4
+#define TIMER1_COMPB_vect      _VECTOR(4)  /* Timer/Counter1 Compare Match 1B */
+#define TIMER1_OVF_vect_num  5
+#define TIMER1_OVF_vect      _VECTOR(5)  /* Timer/Counter1 Overflow */
+#define TIMER0_OVF_vect_num  6
+#define TIMER0_OVF_vect      _VECTOR(6)  /* Timer/Counter0 Overflow */
+#define USI_START_vect_num  7
+#define USI_START_vect      _VECTOR(7)  /* USI Start */
+#define USI_OVF_vect_num  8
+#define USI_OVF_vect      _VECTOR(8)  /* USI Overflow */
+#define EE_RDY_vect_num  9
+#define EE_RDY_vect      _VECTOR(9)  /* EEPROM Ready */
+#define ANA_COMP_vect_num  10
+#define ANA_COMP_vect      _VECTOR(10)  /* Analog Comparator */
+#define ADC_vect_num  11
+#define ADC_vect      _VECTOR(11)  /* ADC Conversion Complete */
+#define WDT_vect_num  12
+#define WDT_vect      _VECTOR(12)  /* Watchdog Time-Out */
+#define INT1_vect_num  13
+#define INT1_vect      _VECTOR(13)  /* External Interrupt 1 */
+#define TIMER0_COMPA_vect_num  14
+#define TIMER0_COMPA_vect      _VECTOR(14)  /* Timer/Counter0 Compare Match A */
+#define TIMER0_COMPB_vect_num  15
+#define TIMER0_COMPB_vect      _VECTOR(15)  /* Timer/Counter0 Compare Match B */
+#define TIMER0_CAPT_vect_num  16
+#define TIMER0_CAPT_vect      _VECTOR(16)  /* ADC Conversion Complete */
+#define TIMER1_COMPD_vect_num  17
+#define TIMER1_COMPD_vect      _VECTOR(17)  /* Timer/Counter1 Compare Match D */
+#define FAULT_PROTECTION_vect_num  18
+#define FAULT_PROTECTION_vect      _VECTOR(18)  /* Timer/Counter1 Fault Protection */
+
+#define _VECTOR_SIZE 2 /* Size of individual vector. */
+#define _VECTORS_SIZE (19 * _VECTOR_SIZE)
+
+
+/* Constants */
+#define SPM_PAGESIZE (64)
+#define RAMSTART     (0x60)
+#define RAMSIZE      (512)
+#define RAMEND       (RAMSTART + RAMSIZE - 1)
+#define XRAMSTART    (NA)
+#define XRAMSIZE     (0)
+#define XRAMEND      (RAMEND)
+#define E2END        (0x1FF)
+#define E2PAGESIZE   (4)
+#define FLASHEND     (0x1FFF)
+
+
+/* Fuses */
+#define FUSE_MEMORY_SIZE 3
+
+/* Low Fuse Byte */
+#define FUSE_CKSEL0  (unsigned char)~_BV(0)  /* Select Clock source */
+#define FUSE_CKSEL1  (unsigned char)~_BV(1)  /* Select Clock source */
+#define FUSE_CKSEL2  (unsigned char)~_BV(2)  /* Select Clock source */
+#define FUSE_CKSEL3  (unsigned char)~_BV(3)  /* Select Clock source */
+#define FUSE_SUT0  (unsigned char)~_BV(4)  /* Select start-up time */
+#define FUSE_SUT1  (unsigned char)~_BV(5)  /* Select start-up time */
+#define FUSE_CKOUT  (unsigned char)~_BV(6)  /* Clock Output Enable */
+#define FUSE_CKDIV8  (unsigned char)~_BV(7)  /* Divide clock by 8 */
+#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
+
+/* High Fuse Byte */
+#define FUSE_BODLEVEL0  (unsigned char)~_BV(0)  /* Brown-out Detector trigger level */
+#define FUSE_BODLEVEL1  (unsigned char)~_BV(1)  /* Brown-out Detector trigger level */
+#define FUSE_BODLEVEL2  (unsigned char)~_BV(2)  /* Brown-out Detector trigger level */
+#define FUSE_EESAVE  (unsigned char)~_BV(3)  /* EEPROM memory is preserved through the Chip Erase */
+#define FUSE_WDTON  (unsigned char)~_BV(4)  /* Watchdog Timer always on */
+#define FUSE_SPIEN  (unsigned char)~_BV(5)  /* Enable Serial Program and Data Downloading */
+#define FUSE_DWEN  (unsigned char)~_BV(6)  /* DebugWIRE Enable */
+#define FUSE_RSTDISBL  (unsigned char)~_BV(7)  /* External Reset disable */
+#define HFUSE_DEFAULT (FUSE_SPIEN)
+
+/* Extended Fuse Byte */
+#define FUSE_SELFPRGEN  (unsigned char)~_BV(0)  /* Self-Programming Enable */
+#define EFUSE_DEFAULT (0xFF)
+
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+
+
+/* Signature */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x93
+#define SIGNATURE_2 0x0D
+
+
+/* Device Pin Definitions */
+#define DI_B_DDR   DDRMOSI
+#define DI_B_PORT  PORTMOSI
+#define DI_B_PIN   PINMOSI
+#define DI_B_BIT   MOSI
+
+#define SDA_B_DDR   DDRMOSI
+#define SDA_B_PORT  PORTMOSI
+#define SDA_B_PIN   PINMOSI
+#define SDA_B_BIT   MOSI
+
+#define _OC1A_DDR   DDRMOSI
+#define _OC1A_PORT  PORTMOSI
+#define _OC1A_PIN   PINMOSI
+#define _OC1A_BIT   MOSI
+
+#define PCINT8_DDR   DDRMOSI
+#define PCINT8_PORT  PORTMOSI
+#define PCINT8_PIN   PINMOSI
+#define PCINT8_BIT   MOSI
+
+#define PB0_DDR   DDRMOSI
+#define PB0_PORT  PORTMOSI
+#define PB0_PIN   PINMOSI
+#define PB0_BIT   MOSI
+
+#define DO_B_DDR   DDRMISO
+#define DO_B_PORT  PORTMISO
+#define DO_B_PIN   PINMISO
+#define DO_B_BIT   MISO
+
+#define OC1A_DDR   DDRMISO
+#define OC1A_PORT  PORTMISO
+#define OC1A_PIN   PINMISO
+#define OC1A_BIT   MISO
+
+#define PCINT9_DDR   DDRMISO
+#define PCINT9_PORT  PORTMISO
+#define PCINT9_PIN   PINMISO
+#define PCINT9_BIT   MISO
+
+#define PB1_DDR   DDRMISO
+#define PB1_PORT  PORTMISO
+#define PB1_PIN   PINMISO
+#define PB1_BIT   MISO
+
+#define USCK_B_DDR   DDRSCK
+#define USCK_B_PORT  PORTSCK
+#define USCK_B_PIN   PINSCK
+#define USCK_B_BIT   SCK
+
+#define SCL_B_DDR   DDRSCK
+#define SCL_B_PORT  PORTSCK
+#define SCL_B_PIN   PINSCK
+#define SCL_B_BIT   SCK
+
+#define OC1B_DDR   DDRSCK
+#define OC1B_PORT  PORTSCK
+#define OC1B_PIN   PINSCK
+#define OC1B_BIT   SCK
+
+#define PCINT10_DDR   DDRSCK
+#define PCINT10_PORT  PORTSCK
+#define PCINT10_PIN   PINSCK
+#define PCINT10_BIT   SCK
+
+#define PB2_DDR   DDRSCK
+#define PB2_PORT  PORTSCK
+#define PB2_PIN   PINSCK
+#define PB2_BIT   SCK
+
+#define PCINT11_DDR   DDROC1B
+#define PCINT11_PORT  PORTOC1B
+#define PCINT11_PIN   PINOC1B
+#define PCINT11_BIT   OC1B
+
+#define PB3_DDR   DDROC1B
+#define PB3_PORT  PORTOC1B
+#define PB3_PIN   PINOC1B
+#define PB3_BIT   OC1B
+
+#define PCINT12_DDR   DDRADC
+#define PCINT12_PORT  PORTADC
+#define PCINT12_PIN   PINADC
+#define PCINT12_BIT   ADC7
+
+#define _OC1D_DDR   DDRADC
+#define _OC1D_PORT  PORTADC
+#define _OC1D_PIN   PINADC
+#define _OC1D_BIT   ADC7
+
+#define CLKI_DDR   DDRADC
+#define CLKI_PORT  PORTADC
+#define CLKI_PIN   PINADC
+#define CLKI_BIT   ADC7
+
+#define PB4_DDR   DDRADC
+#define PB4_PORT  PORTADC
+#define PB4_PIN   PINADC
+#define PB4_BIT   ADC7
+
+#define PCINT13_DDR   DDRADC
+#define PCINT13_PORT  PORTADC
+#define PCINT13_PIN   PINADC
+#define PCINT13_BIT   ADC8
+
+#define OC1D_DDR   DDRADC
+#define OC1D_PORT  PORTADC
+#define OC1D_PIN   PINADC
+#define OC1D_BIT   ADC8
+
+#define CKLO_DDR   DDRADC
+#define CKLO_PORT  PORTADC
+#define CKLO_PIN   PINADC
+#define CKLO_BIT   ADC8
+
+#define PB5_DDR   DDRADC
+#define PB5_PORT  PORTADC
+#define PB5_PIN   PINADC
+#define PB5_BIT   ADC8
+
+#define INT0_DDR   DDRADC
+#define INT0_PORT  PORTADC
+#define INT0_PIN   PINADC
+#define INT0_BIT   ADC9
+
+#define T0_DDR   DDRADC
+#define T0_PORT  PORTADC
+#define T0_PIN   PINADC
+#define T0_BIT   ADC9
+
+#define PCINT14_DDR   DDRADC
+#define PCINT14_PORT  PORTADC
+#define PCINT14_PIN   PINADC
+#define PCINT14_BIT   ADC9
+
+#define PB6_DDR   DDRADC
+#define PB6_PORT  PORTADC
+#define PB6_PIN   PINADC
+#define PB6_BIT   ADC9
+
+#define PCINT15_DDR   DDRADC1
+#define PCINT15_PORT  PORTADC1
+#define PCINT15_PIN   PINADC1
+#define PCINT15_BIT   ADC10
+
+#define PB7_DDR   DDRADC1
+#define PB7_PORT  PORTADC1
+#define PB7_PIN   PINADC1
+#define PB7_BIT   ADC10
+
+#define AIN1_DDR   DDRADC
+#define AIN1_PORT  PORTADC
+#define AIN1_PIN   PINADC
+#define AIN1_BIT   ADC6
+
+#define PCINT7_DDR   DDRADC
+#define PCINT7_PORT  PORTADC
+#define PCINT7_PIN   PINADC
+#define PCINT7_BIT   ADC6
+
+#define PA7_DDR   DDRADC
+#define PA7_PORT  PORTADC
+#define PA7_PIN   PINADC
+#define PA7_BIT   ADC6
+
+#define AIN0_DDR   DDRADC
+#define AIN0_PORT  PORTADC
+#define AIN0_PIN   PINADC
+#define AIN0_BIT   ADC5
+
+#define PCINT6_DDR   DDRADC
+#define PCINT6_PORT  PORTADC
+#define PCINT6_PIN   PINADC
+#define PCINT6_BIT   ADC5
+
+#define PA6_DDR   DDRADC
+#define PA6_PORT  PORTADC
+#define PA6_PIN   PINADC
+#define PA6_BIT   ADC5
+
+#define AIN2_DDR   DDRADC
+#define AIN2_PORT  PORTADC
+#define AIN2_PIN   PINADC
+#define AIN2_BIT   ADC4
+
+#define PCINT5_DDR   DDRADC
+#define PCINT5_PORT  PORTADC
+#define PCINT5_PIN   PINADC
+#define PCINT5_BIT   ADC4
+
+#define PA5_DDR   DDRADC
+#define PA5_PORT  PORTADC
+#define PA5_PIN   PINADC
+#define PA5_BIT   ADC4
+
+#define ICP0_DDR   DDRADC
+#define ICP0_PORT  PORTADC
+#define ICP0_PIN   PINADC
+#define ICP0_BIT   ADC3
+
+#define PCINT4_DDR   DDRADC
+#define PCINT4_PORT  PORTADC
+#define PCINT4_PIN   PINADC
+#define PCINT4_BIT   ADC3
+
+#define PA4_DDR   DDRADC
+#define PA4_PORT  PORTADC
+#define PA4_PIN   PINADC
+#define PA4_BIT   ADC3
+
+#define PCINT3_DDR   DDRAREF
+#define PCINT3_PORT  PORTAREF
+#define PCINT3_PIN   PINAREF
+#define PCINT3_BIT   AREF
+
+#define PA3_DDR   DDRAREF
+#define PA3_PORT  PORTAREF
+#define PA3_PIN   PINAREF
+#define PA3_BIT   AREF
+
+#define INT1_DDR   DDRADC
+#define INT1_PORT  PORTADC
+#define INT1_PIN   PINADC
+#define INT1_BIT   ADC2
+
+#define USCK_A_DDR   DDRADC
+#define USCK_A_PORT  PORTADC
+#define USCK_A_PIN   PINADC
+#define USCK_A_BIT   ADC2
+
+#define SCL_A_DDR   DDRADC
+#define SCL_A_PORT  PORTADC
+#define SCL_A_PIN   PINADC
+#define SCL_A_BIT   ADC2
+
+#define PCINT2_DDR   DDRADC
+#define PCINT2_PORT  PORTADC
+#define PCINT2_PIN   PINADC
+#define PCINT2_BIT   ADC2
+
+#define PA2_DDR   DDRADC
+#define PA2_PORT  PORTADC
+#define PA2_PIN   PINADC
+#define PA2_BIT   ADC2
+
+#define DO_A_DDR   DDRADC
+#define DO_A_PORT  PORTADC
+#define DO_A_PIN   PINADC
+#define DO_A_BIT   ADC1
+
+#define PCINT1_DDR   DDRADC
+#define PCINT1_PORT  PORTADC
+#define PCINT1_PIN   PINADC
+#define PCINT1_BIT   ADC1
+
+#define PA1_DDR   DDRADC
+#define PA1_PORT  PORTADC
+#define PA1_PIN   PINADC
+#define PA1_BIT   ADC1
+
+#define DI_A_DDR   DDRADC
+#define DI_A_PORT  PORTADC
+#define DI_A_PIN   PINADC
+#define DI_A_BIT   ADC0
+
+#define SDA_A_DDR   DDRADC
+#define SDA_A_PORT  PORTADC
+#define SDA_A_PIN   PINADC
+#define SDA_A_BIT   ADC0
+
+#define PCINT0_DDR   DDRADC
+#define PCINT0_PORT  PORTADC
+#define PCINT0_PIN   PINADC
+#define PCINT0_BIT   ADC0
+
+#define PA0_DDR   DDRADC
+#define PA0_PORT  PORTADC
+#define PA0_PIN   PINADC
+#define PA0_BIT   ADC0
+
+#define SLEEP_MODE_IDLE (0x00<<3)
+#define SLEEP_MODE_ADC (0x01<<3)
+#define SLEEP_MODE_PWR_DOWN (0x02<<3)
+#define SLEEP_MODE_STANDBY (0x03<<3)
+
+#endif /* _AVR_ATtiny861A_H_ */
+

hardware/tools/avr/avr/include/avr/iotn87.h

@@ -0,0 +1,859 @@
+/* Copyright (c) 2009-2010 Atmel Corporation
+   All rights reserved.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+
+   * Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+
+   * Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in
+     the documentation and/or other materials provided with the
+     distribution.
+
+   * Neither the name of the copyright holders nor the names of
+     contributors may be used to endorse or promote products derived
+     from this software without specific prior written permission.
+
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+  POSSIBILITY OF SUCH DAMAGE. */
+
+/* $Id: iotn87.h 2181 2010-08-23 03:46:23Z arcanum $ */
+
+/* avr/iotn87.h - definitions for ATtiny87 */
+
+/* This file should only be included from <avr/io.h>, never directly. */
+
+#ifndef _AVR_IO_H_
+#  error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+#  define _AVR_IOXXX_H_ "iotn87.h"
+#else
+#  error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif 
+
+
+#ifndef _AVR_ATtiny87_H_
+#define _AVR_ATtiny87_H_ 1
+
+
+/* Registers and associated bit numbers. */
+
+#define PINA _SFR_IO8(0x00)
+#define PINA0 0
+#define PINA1 1
+#define PINA2 2
+#define PINA3 3
+#define PINA4 4
+#define PINA5 5
+#define PINA6 6
+#define PINA7 7
+
+#define DDRA _SFR_IO8(0x01)
+#define DDA0 0
+#define DDA1 1
+#define DDA2 2
+#define DDA3 3
+#define DDA4 4
+#define DDA5 5
+#define DDA6 6
+#define DDA7 7
+
+#define PORTA _SFR_IO8(0x02)
+#define PORTA0 0
+#define PORTA1 1
+#define PORTA2 2
+#define PORTA3 3
+#define PORTA4 4
+#define PORTA5 5
+#define PORTA6 6
+#define PORTA7 7
+
+#define PINB _SFR_IO8(0x03)
+#define PINB0 0
+#define PINB1 1
+#define PINB2 2
+#define PINB3 3
+#define PINB4 4
+#define PINB5 5
+#define PINB6 6
+#define PINB7 7
+
+#define DDRB _SFR_IO8(0x04)
+#define DDB0 0
+#define DDB1 1
+#define DDB2 2
+#define DDB3 3
+#define DDB4 4
+#define DDB5 5
+#define DDB6 6
+#define DDB7 7
+
+#define PORTB _SFR_IO8(0x05)
+#define PORTB0 0
+#define PORTB1 1
+#define PORTB2 2
+#define PORTB3 3
+#define PORTB4 4
+#define PORTB5 5
+#define PORTB6 6
+#define PORTB7 7
+
+#define PORTCR _SFR_IO8(0x12)
+#define PUDA 0
+#define PUDB 2
+#define BBMA 4
+#define BBMB 5
+
+#define TIFR0 _SFR_IO8(0x15)
+#define TOV0 0
+#define OCF0A 1
+
+#define TIFR1 _SFR_IO8(0x16)
+#define TOV1 0
+#define OCF1A 1
+#define OCF1B 2
+#define ICF1 5
+
+#define PCIFR _SFR_IO8(0x1B)
+#define PCIF0 0
+#define PCIF1 1
+
+#define EIFR _SFR_IO8(0x1C)
+#define INTF0 0
+#define INTF1 1
+
+#define EIMSK _SFR_IO8(0x1D)
+#define INT0 0
+#define INT1 1
+
+#define GPIOR0 _SFR_IO8(0x1E)
+#define GPIOR00 0
+#define GPIOR01 1
+#define GPIOR02 2
+#define GPIOR03 3
+#define GPIOR04 4
+#define GPIOR05 5
+#define GPIOR06 6
+#define GPIOR07 7
+
+#define EECR _SFR_IO8(0x1F)
+#define EERE 0
+#define EEPE 1
+#define EEMPE 2
+#define EERIE 3
+#define EEPM0 4
+#define EEPM1 5
+
+#define EEDR _SFR_IO8(0x20)
+#define EEDR0 0
+#define EEDR1 1
+#define EEDR2 2
+#define EEDR3 3
+#define EEDR4 4
+#define EEDR5 5
+#define EEDR6 6
+#define EEDR7 7
+
+#define EEAR _SFR_IO16(0x21)
+
+#define EEARL _SFR_IO8(0x21)
+#define EEAR0 0
+#define EEAR1 1
+#define EEAR2 2
+#define EEAR3 3
+#define EEAR4 4
+#define EEAR5 5
+#define EEAR6 6
+#define EEAR7 7
+
+#define EEARH _SFR_IO8(0x22)
+#define EEAR8 0
+
+#define GTCCR _SFR_IO8(0x23)
+#define PSR1 0
+#define PSR0 1
+#define TSM 7
+
+#define TCCR0A _SFR_IO8(0x25)
+#define WGM00 0
+#define WGM01 1
+#define COM0A0 6
+#define COM0A1 7
+
+#define TCCR0B _SFR_IO8(0x26)
+#define CS00 0
+#define CS01 1
+#define CS02 2
+#define FOC0A 7
+
+#define TCNT0 _SFR_IO8(0x27)
+#define TCNT00 0
+#define TCNT01 1
+#define TCNT02 2
+#define TCNT03 3
+#define TCNT04 4
+#define TCNT05 5
+#define TCNT06 6
+#define TCNT07 7
+
+#define OCR0A _SFR_IO8(0x28)
+#define OCR00 0
+#define OCR01 1
+#define OCR02 2
+#define OCR03 3
+#define OCR04 4
+#define OCR05 5
+#define OCR06 6
+#define OCR07 7
+
+#define GPIOR1 _SFR_IO8(0x2A)
+#define GPIOR10 0
+#define GPIOR11 1
+#define GPIOR12 2
+#define GPIOR13 3
+#define GPIOR14 4
+#define GPIOR15 5
+#define GPIOR16 6
+#define GPIOR17 7
+
+#define GPIOR2 _SFR_IO8(0x2B)
+#define GPIOR20 0
+#define GPIOR21 1
+#define GPIOR22 2
+#define GPIOR23 3
+#define GPIOR24 4
+#define GPIOR25 5
+#define GPIOR26 6
+#define GPIOR27 7
+
+#define SPCR _SFR_IO8(0x2C)
+#define SPR0 0
+#define SPR1 1
+#define CPHA 2
+#define CPOL 3
+#define MSTR 4
+#define DORD 5
+#define SPE 6
+#define SPIE 7
+
+#define SPSR _SFR_IO8(0x2D)
+#define SPI2X 0
+#define WCOL 6
+#define SPIF 7
+
+#define SPDR _SFR_IO8(0x2E)
+#define SPDR0 0
+#define SPDR1 1
+#define SPDR2 2
+#define SPDR3 3
+#define SPDR4 4
+#define SPDR5 5
+#define SPDR6 6
+#define SPDR7 7
+
+#define ACSR _SFR_IO8(0x30)
+#define ACIS0 0
+#define ACIS1 1
+#define ACIC 2
+#define ACIE 3
+#define ACI 4
+#define ACO 5
+#define ACIRS 6
+#define ACD 7
+
+#define DWDR _SFR_IO8(0x31)
+#define DWDR0 0
+#define DWDR1 1
+#define DWDR2 2
+#define DWDR3 3
+#define DWDR4 4
+#define DWDR5 5
+#define DWDR6 6
+#define DWDR7 7
+
+#define SMCR _SFR_IO8(0x33)
+#define SE 0
+#define SM0 1
+#define SM1 2
+
+#define MCUSR _SFR_IO8(0x34)
+#define PORF 0
+#define EXTRF 1
+#define BORF 2
+#define WDRF 3
+
+#define MCUCR _SFR_IO8(0x35)
+#define PUD 4
+#define BODSE 5
+#define BODS 6
+
+#define SPMCSR _SFR_IO8(0x37)
+#define SPMEN 0
+#define PGERS 1
+#define PGWRT 2
+#define RFLB 3
+#define CTPB 4
+#define SIGRD 5
+#define RWWSB 6
+
+#define WDTCR _SFR_MEM8(0x60)
+#define WDP0 0
+#define WDP1 1
+#define WDP2 2
+#define WDE 3
+#define WDCE 4
+#define WDP3 5
+#define WDIE 6
+#define WDIF 7
+
+#define CLKPR _SFR_MEM8(0x61)
+#define CLKPS0 0
+#define CLKPS1 1
+#define CLKPS2 2
+#define CLKPS3 3
+#define CLKPCE 7
+
+#define CLKCSR _SFR_MEM8(0x62)
+#define CLKC0 0
+#define CLKC1 1
+#define CLKC2 2
+#define CLKC3 3
+#define CLKRDY 4
+#define CLKCCE 7
+
+#define CLKSELR _SFR_MEM8(0x63)
+#define CSEL0 0
+#define CSEL1 1
+#define CSEL2 2
+#define CSEL3 3
+#define CSUT0 4
+#define CSUT1 5
+#define COUT 6
+
+#define PRR _SFR_MEM8(0x64)
+#define PRADC 0
+#define PRUSI 1
+#define PRTIM0 2
+#define PRTIM1 3
+#define PRSPI 4
+#define PRLIN 5
+
+#define __AVR_HAVE_PRR	((1<<PRADC)|(1<<PRUSI)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRSPI)|(1<<PRLIN))
+#define __AVR_HAVE_PRR_PRADC
+#define __AVR_HAVE_PRR_PRUSI
+#define __AVR_HAVE_PRR_PRTIM0
+#define __AVR_HAVE_PRR_PRTIM1
+#define __AVR_HAVE_PRR_PRSPI
+#define __AVR_HAVE_PRR_PRLIN
+
+#define OSCCAL _SFR_MEM8(0x66)
+#define CAL0 0
+#define CAL1 1
+#define CAL2 2
+#define CAL3 3
+#define CAL4 4
+#define CAL5 5
+#define CAL6 6
+#define CAL7 7
+
+#define PCICR _SFR_MEM8(0x68)
+#define PCIE0 0
+#define PCIE1 1
+
+#define EICRA _SFR_MEM8(0x69)
+#define ISC00 0
+#define ISC01 1
+#define ISC10 2
+#define ISC11 3
+
+#define PCMSK0 _SFR_MEM8(0x6B)
+#define PCINT0 0
+#define PCINT1 1
+#define PCINT2 2
+#define PCINT3 3
+#define PCINT4 4
+#define PCINT5 5
+#define PCINT6 6
+#define PCINT7 7
+
+#define PCMSK1 _SFR_MEM8(0x6C)
+#define PCINT8 0
+#define PCINT9 1
+#define PCINT10 2
+#define PCINT11 3
+#define PCINT12 4
+#define PCINT13 5
+#define PCINT14 6
+#define PCINT15 7
+
+#define TIMSK0 _SFR_MEM8(0x6E)
+#define TOIE0 0
+#define OCIE0A 1
+
+#define TIMSK1 _SFR_MEM8(0x6F)
+#define TOIE1 0
+#define OCIE1A 1
+#define OCIE1B 2
+#define ICIE1 5
+
+#define AMISCR _SFR_MEM8(0x77)
+#define ISRCEN 0
+#define XREFEN 1
+#define AREFEN 2
+
+#ifndef __ASSEMBLER__
+#define ADC _SFR_MEM16(0x78)
+#endif
+#define ADCW _SFR_MEM16(0x78)
+
+#define ADCL _SFR_MEM8(0x78)
+#define ADCL0 0
+#define ADCL1 1
+#define ADCL2 2
+#define ADCL3 3
+#define ADCL4 4
+#define ADCL5 5
+#define ADCL6 6
+#define ADCL7 7
+
+#define ADCH _SFR_MEM8(0x79)
+#define ADCH0 0
+#define ADCH1 1
+#define ADCH2 2
+#define ADCH3 3
+#define ADCH4 4
+#define ADCH5 5
+#define ADCH6 6
+#define ADCH7 7
+
+#define ADCSRA _SFR_MEM8(0x7A)
+#define ADPS0 0
+#define ADPS1 1
+#define ADPS2 2
+#define ADIE 3
+#define ADIF 4
+#define ADATE 5
+#define ADSC 6
+#define ADEN 7
+
+#define ADCSRB _SFR_MEM8(0x7B)
+#define ADTS0 0
+#define ADTS1 1
+#define ADTS2 2
+#define ACIR0 4
+#define ACIR1 5
+#define ACME 6
+#define BIN 7
+
+#define ADMUX _SFR_MEM8(0x7C)
+#define MUX0 0
+#define MUX1 1
+#define MUX2 2
+#define MUX3 3
+#define MUX4 4
+#define ADLAR 5
+#define REFS0 6
+#define REFS1 7
+
+#define DIDR0 _SFR_MEM8(0x7E)
+#define ADC0D 0
+#define ADC1D 1
+#define ADC2D 2
+#define ADC3D 3
+#define ADC4D 4
+#define ADC5D 5
+#define ADC6D 6
+#define ADC7D 7
+
+#define DIDR1 _SFR_MEM8(0x7F)
+#define ADC8D 4
+#define ADC9D 5
+#define ADC10D 6
+
+#define TCCR1A _SFR_MEM8(0x80)
+#define WGM10 0
+#define WGM11 1
+#define COM1B0 4
+#define COM1B1 5
+#define COM1A0 6
+#define COM1A1 7
+
+#define TCCR1B _SFR_MEM8(0x81)
+#define CS10 0
+#define CS11 1
+#define CS12 2
+#define WGM12 3
+#define WGM13 4
+#define ICES1 6
+#define ICNC1 7
+
+#define TCCR1C _SFR_MEM8(0x82)
+#define FOC1B 6
+#define FOC1A 7
+
+#define TCCR1D _SFR_MEM8(0x83)
+#define OC1AU 0
+#define OC1AV 1
+#define OC1AW 2
+#define OC1AX 3
+#define OC1BU 4
+#define OC1BV 5
+#define OC1BW 6
+#define OC1BX 7
+
+#define TCNT1 _SFR_MEM16(0x84)
+
+#define TCNT1L _SFR_MEM8(0x84)
+#define TCNT1L0 0
+#define TCNT1L1 1
+#define TCNT1L2 2
+#define TCNT1L3 3
+#define TCNT1L4 4
+#define TCNT1L5 5
+#define TCNT1L6 6
+#define TCNT1L7 7
+
+#define TCNT1H _SFR_MEM8(0x85)
+#define TCNT1H0 0
+#define TCNT1H1 1
+#define TCNT1H2 2
+#define TCNT1H3 3
+#define TCNT1H4 4
+#define TCNT1H5 5
+#define TCNT1H6 6
+#define TCNT1H7 7
+
+#define ICR1 _SFR_MEM16(0x86)
+
+#define ICR1L _SFR_MEM8(0x86)
+#define ICR1L0 0
+#define ICR1L1 1
+#define ICR1L2 2
+#define ICR1L3 3
+#define ICR1L4 4
+#define ICR1L5 5
+#define ICR1L6 6
+#define ICR1L7 7
+
+#define ICR1H _SFR_MEM8(0x87)
+#define ICR1H0 0
+#define ICR1H1 1
+#define ICR1H2 2
+#define ICR1H3 3
+#define ICR1H4 4
+#define ICR1H5 5
+#define ICR1H6 6
+#define ICR1H7 7
+
+#define OCR1A _SFR_MEM16(0x88)
+
+#define OCR1AL _SFR_MEM8(0x88)
+#define OCR1AL0 0
+#define OCR1AL1 1
+#define OCR1AL2 2
+#define OCR1AL3 3
+#define OCR1AL4 4
+#define OCR1AL5 5
+#define OCR1AL6 6
+#define OCR1AL7 7
+
+#define OCR1AH _SFR_MEM8(0x89)
+#define OCR1AH0 0
+#define OCR1AH1 1
+#define OCR1AH2 2
+#define OCR1AH3 3
+#define OCR1AH4 4
+#define OCR1AH5 5
+#define OCR1AH6 6
+#define OCR1AH7 7
+
+#define OCR1B _SFR_MEM16(0x8A)
+
+#define OCR1BL _SFR_MEM8(0x8A)
+#define OCR1BL0 0
+#define OCR1BL1 1
+#define OCR1BL2 2
+#define OCR1BL3 3
+#define OCR1BL4 4
+#define OCR1BL5 5
+#define OCR1BL6 6
+#define OCR1BL7 7
+
+#define OCR1BH _SFR_MEM8(0x8B)
+#define OCR1BH0 0
+#define OCR1BH1 1
+#define OCR1BH2 2
+#define OCR1BH3 3
+#define OCR1BH4 4
+#define OCR1BH5 5
+#define OCR1BH6 6
+#define OCR1BH7 7
+
+#define ASSR _SFR_MEM8(0xB6)
+#define TCR0BUB 0
+#define TCR0AUB 1
+#define OCR0AUB 3
+#define TCN0UB 4
+#define AS0 5
+#define EXCLK 6
+
+#define USICR _SFR_MEM8(0xB8)
+#define USITC 0
+#define USICLK 1
+#define USICS0 2
+#define USICS1 3
+#define USIWM0 4
+#define USIWM1 5
+#define USIOIE 6
+#define USISIE 7
+
+#define USISR _SFR_MEM8(0xB9)
+#define USICNT0 0
+#define USICNT1 1
+#define USICNT2 2
+#define USICNT3 3
+#define USIDC 4
+#define USIPF 5
+#define USIOIF 6
+#define USISIF 7
+
+#define USIDR _SFR_MEM8(0xBA)
+#define USIDR0 0
+#define USIDR1 1
+#define USIDR2 2
+#define USIDR3 3
+#define USIDR4 4
+#define USIDR5 5
+#define USIDR6 6
+#define USIDR7 7
+
+#define USIBR _SFR_MEM8(0xBB)
+#define USIBR0 0
+#define USIBR1 1
+#define USIBR2 2
+#define USIBR3 3
+#define USIBR4 4
+#define USIBR5 5
+#define USIBR6 6
+#define USIBR7 7
+
+#define USIPP _SFR_MEM8(0xBC)
+#define USIPOS 0
+
+#define LINCR _SFR_MEM8(0xC8)
+#define LCMD0 0
+#define LCMD1 1
+#define LCMD2 2
+#define LENA 3
+#define LCONF0 4
+#define LCONF1 5
+#define LIN13 6
+#define LSWRES 7
+
+#define LINSIR _SFR_MEM8(0xC9)
+#define LRXOK 0
+#define LTXOK 1
+#define LIDOK 2
+#define LERR 3
+#define LBUSY 4
+#define LIDST0 5
+#define LIDST1 6
+#define LIDST2 7
+
+#define LINENIR _SFR_MEM8(0xCA)
+#define LENRXOK 0
+#define LENTXOK 1
+#define LENIDOK 2
+#define LENERR 3
+
+#define LINERR _SFR_MEM8(0xCB)
+#define LBERR 0
+#define LCERR 1
+#define LPERR 2
+#define LSERR 3
+#define LFERR 4
+#define LOVERR 5
+#define LTOERR 6
+#define LABORT 7
+
+#define LINBTR _SFR_MEM8(0xCC)
+#define LBT0 0
+#define LBT1 1
+#define LBT2 2
+#define LBT3 3
+#define LBT4 4
+#define LBT5 5
+#define LDISR 7
+
+#define LINBRR _SFR_MEM16(0xCD)
+
+#define LINBRRL _SFR_MEM8(0xCD)
+#define LDIV0 0
+#define LDIV1 1
+#define LDIV2 2
+#define LDIV3 3
+#define LDIV4 4
+#define LDIV5 5
+#define LDIV6 6
+#define LDIV7 7
+
+#define LINBRRH _SFR_MEM8(0xCE)
+#define LDIV8 0
+#define LDIV9 1
+#define LDIV10 2
+#define LDIV11 3
+
+#define LINDLR _SFR_MEM8(0xCF)
+#define LRXDL0 0
+#define LRXDL1 1
+#define LRXDL2 2
+#define LRXDL3 3
+#define LTXDL0 4
+#define LTXDL1 5
+#define LTXDL2 6
+#define LTXDL3 7
+
+#define LINIDR _SFR_MEM8(0xD0)
+#define LID0 0
+#define LID1 1
+#define LID2 2
+#define LID3 3
+#define LID4 4
+#define LID5 5
+#define LP0 6
+#define LP1 7
+
+#define LINSEL _SFR_MEM8(0xD1)
+#define LINDX0 0
+#define LINDX1 1
+#define LINDX2 2
+#define LAINC 3
+
+#define LINDAT _SFR_MEM8(0xD2)
+#define LDATA0 0
+#define LDATA1 1
+#define LDATA2 2
+#define LDATA3 3
+#define LDATA4 4
+#define LDATA5 5
+#define LDATA6 6
+#define LDATA7 7
+
+
+/* Interrupt vectors */
+/* Vector 0 is the reset vector */
+#define INT0_vect_num  1
+#define INT0_vect      _VECTOR(1)  /* External Interrupt Request 0 */
+#define USI_OVF_vect_num  19
+#define USI_OVF_vect      _VECTOR(19)  /* USI Overflow */
+#define INT1_vect_num  2
+#define INT1_vect      _VECTOR(2)  /* External Interrupt Request 1 */
+#define PCINT0_vect_num  3
+#define PCINT0_vect      _VECTOR(3)  /* Pin Change Interrupt Request 0 */
+#define PCINT1_vect_num  4
+#define PCINT1_vect      _VECTOR(4)  /* Pin Change Interrupt Request 1 */
+#define WDT_vect_num  5
+#define WDT_vect      _VECTOR(5)  /* Watchdog Time-Out Interrupt */
+#define TIMER1_CAPT_vect_num  6
+#define TIMER1_CAPT_vect      _VECTOR(6)  /* Timer/Counter1 Capture Event */
+#define TIMER1_COMPA_vect_num  7
+#define TIMER1_COMPA_vect      _VECTOR(7)  /* Timer/Counter1 Compare Match 1A */
+#define TIMER1_COMPB_vect_num  8
+#define TIMER1_COMPB_vect      _VECTOR(8)  /* Timer/Counter1 Compare Match 1B */
+#define TIMER1_OVF_vect_num  9
+#define TIMER1_OVF_vect      _VECTOR(9)  /* Timer/Counter1 Overflow */
+#define TIMER0_COMPA_vect_num  10
+#define TIMER0_COMPA_vect      _VECTOR(10)  /* Timer/Counter0 Compare Match 0A */
+#define TIMER0_OVF_vect_num  11
+#define TIMER0_OVF_vect      _VECTOR(11)  /* Timer/Counter0 Overflow */
+#define LIN_TC_vect_num  12
+#define LIN_TC_vect      _VECTOR(12)  /* LIN Transfer Complete */
+#define LIN_ERR_vect_num  13
+#define LIN_ERR_vect      _VECTOR(13)  /* LIN Error */
+#define SPI_STC_vect_num  14
+#define SPI_STC_vect      _VECTOR(14)  /* SPI Serial Transfer Complete */
+#define ADC_vect_num  15
+#define ADC_vect      _VECTOR(15)  /* ADC Conversion Complete */
+#define EE_RDY_vect_num  16
+#define EE_RDY_vect      _VECTOR(16)  /* EEPROM Ready */
+#define ANA_COMP_vect_num  17
+#define ANA_COMP_vect      _VECTOR(17)  /* Analog Comparator */
+#define USI_START_vect_num  18
+#define USI_START_vect      _VECTOR(18)  /* USI Start */
+
+#define _VECTOR_SIZE 2 /* Size of individual vector. */
+#define _VECTORS_SIZE (20 * _VECTOR_SIZE)
+
+
+/* Constants */
+#define SPM_PAGESIZE (128)
+#define RAMSTART     (0x0100)
+#define RAMSIZE      (512)
+#define RAMEND       (RAMSTART + RAMSIZE - 1)
+#define XRAMSTART    (NA)
+#define XRAMSIZE     (0)
+#define XRAMEND      (RAMEND)
+#define E2END        (0x1FF)
+#define E2PAGESIZE   (4)
+#define FLASHEND     (0x1FFF)
+
+
+/* Fuses */
+#define FUSE_MEMORY_SIZE 3
+
+/* Low Fuse Byte */
+#define FUSE_CKSEL0  (unsigned char)~_BV(0)  /* Select Clock source */
+#define FUSE_CKSEL1  (unsigned char)~_BV(1)  /* Select Clock source */
+#define FUSE_CKSEL2  (unsigned char)~_BV(2)  /* Select Clock source */
+#define FUSE_CKSEL3  (unsigned char)~_BV(3)  /* Select Clock source */
+#define FUSE_SUT0  (unsigned char)~_BV(4)  /* Select start-up time */
+#define FUSE_SUT1  (unsigned char)~_BV(5)  /* Select start-up time */
+#define FUSE_CKOUT  (unsigned char)~_BV(6)  /* Clock Output Enable */
+#define FUSE_CKDIV8  (unsigned char)~_BV(7)  /* Divide clock by 8 */
+#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
+
+/* High Fuse Byte */
+#define FUSE_BODLEVEL0  (unsigned char)~_BV(0)  /* Brown-out Detector trigger level */
+#define FUSE_BODLEVEL1  (unsigned char)~_BV(1)  /* Brown-out Detector trigger level */
+#define FUSE_BODLEVEL2  (unsigned char)~_BV(2)  /* Brown-out Detector trigger level */
+#define FUSE_EESAVE  (unsigned char)~_BV(3)  /* EEPROM memory is preserved through the Chip Erase */
+#define FUSE_WDTON  (unsigned char)~_BV(4)  /* Watchdog Timer always ON */
+#define FUSE_SPIEN  (unsigned char)~_BV(5)  /* Enable Serial Program and Data Downloading */
+#define FUSE_DWEN  (unsigned char)~_BV(6)  /* DebugWIRE Enable */
+#define FUSE_RSTDISBL  (unsigned char)~_BV(7)  /* External Reset disable */
+#define HFUSE_DEFAULT (FUSE_SPIEN)
+
+/* Extended Fuse Byte */
+#define FUSE_SELFPRGEN  (unsigned char)~_BV(0)  /* Self-Programming Enable */
+#define EFUSE_DEFAULT (0xFF)
+
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+
+
+/* Signature */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x93
+#define SIGNATURE_2 0x87
+
+
+#define SLEEP_MODE_IDLE (0x00<<1)
+#define SLEEP_MODE_ADC (0x01<<1)
+#define SLEEP_MODE_PWR_DOWN (0x02<<1)
+
+#endif /* _AVR_ATtiny87_H_ */
+

hardware/tools/avr/avr/include/avr/iotn88.h

@@ -0,0 +1,806 @@
+/* Copyright (c) 2007 Atmel Corporation
+   All rights reserved.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+
+   * Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+
+   * Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in
+     the documentation and/or other materials provided with the
+     distribution.
+
+   * Neither the name of the copyright holders nor the names of
+     contributors may be used to endorse or promote products derived
+     from this software without specific prior written permission.
+
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+  POSSIBILITY OF SUCH DAMAGE. 
+*/
+
+/* $Id: iotn88.h 2225 2011-03-02 16:27:26Z arcanum $ */
+
+/* avr/iotn88.h - definitions for ATtiny88 */
+
+/* This file should only be included from <avr/io.h>, never directly. */
+
+#ifndef _AVR_IO_H_
+#  error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+#  define _AVR_IOXXX_H_ "iotn88.h"
+#else
+#  error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif 
+
+
+#ifndef _AVR_IOTN88_H_
+#define _AVR_IOTN88_H_ 1
+
+/* Registers and associated bit numbers */
+
+#define PINB _SFR_IO8(0x03)
+#define PINB0 0
+#define PINB1 1
+#define PINB2 2
+#define PINB3 3
+#define PINB4 4
+#define PINB5 5
+#define PINB6 6
+#define PINB7 7
+
+#define DDRB _SFR_IO8(0x04)
+#define DDB0 0
+#define DDB1 1
+#define DDB2 2
+#define DDB3 3
+#define DDB4 4
+#define DDB5 5
+#define DDB6 6
+#define DDB7 7
+
+#define PORTB _SFR_IO8(0x05)
+#define PORTB0 0
+#define PORTB1 1
+#define PORTB2 2
+#define PORTB3 3
+#define PORTB4 4
+#define PORTB5 5
+#define PORTB6 6
+#define PORTB7 7
+
+#define PINC _SFR_IO8(0x06)
+#define PINC0 0
+#define PINC1 1
+#define PINC2 2
+#define PINC3 3
+#define PINC4 4
+#define PINC5 5
+#define PINC6 6
+#define PINC7 7
+
+#define DDRC _SFR_IO8(0x07)
+#define DDC0 0
+#define DDC1 1
+#define DDC2 2
+#define DDC3 3
+#define DDC4 4
+#define DDC5 5
+#define DDC6 6
+#define DDC7 7
+
+#define PORTC _SFR_IO8(0x08)
+#define PORTC0 0
+#define PORTC1 1
+#define PORTC2 2
+#define PORTC3 3
+#define PORTC4 4
+#define PORTC5 5
+#define PORTC6 6
+#define PORTC7 7
+
+#define PIND _SFR_IO8(0x09)
+#define PIND0 0
+#define PIND1 1
+#define PIND2 2
+#define PIND3 3
+#define PIND4 4
+#define PIND5 5
+#define PIND6 6
+#define PIND7 7
+
+#define DDRD _SFR_IO8(0x0A)
+#define DDD0 0
+#define DDD1 1
+#define DDD2 2
+#define DDD3 3
+#define DDD4 4
+#define DDD5 5
+#define DDD6 6
+#define DDD7 7
+
+#define PORTD _SFR_IO8(0x0B)
+#define PORTD0 0
+#define PORTD1 1
+#define PORTD2 2
+#define PORTD3 3
+#define PORTD4 4
+#define PORTD5 5
+#define PORTD6 6
+#define PORTD7 7
+
+#define PINA _SFR_IO8(0x0C)
+#define PINA0 0
+#define PINA1 1
+#define PINA2 2
+#define PINA3 3
+
+#define DDRA _SFR_IO8(0x0D)
+#define DDA0 0
+#define DDA1 1
+#define DDA2 2
+#define DDA3 3
+
+#define PORTA _SFR_IO8(0x0E)
+#define PORTA0 0
+#define PORTA1 1
+#define PORTA2 2
+#define PORTA3 3
+
+#define PORTCR _SFR_IO8(0x12)
+#define PUDA 0
+#define PUDB 1
+#define PUDC 2
+#define PUDD 3
+#define BBMA 4
+#define BBMB 5
+#define BBMC 6
+#define BBMD 7
+
+#define TIFR0 _SFR_IO8(0x15)
+#define TOV0 0
+#define OCF0A 1
+#define OCF0B 2
+
+#define TIFR1 _SFR_IO8(0x16)
+#define TOV1 0
+#define OCF1A 1
+#define OCF1B 2
+#define ICF1 5
+
+#define PCIFR _SFR_IO8(0x1B)
+#define PCIF0 0
+#define PCIF1 1
+#define PCIF2 2
+#define PCIF3 3
+
+#define EIFR _SFR_IO8(0x1C)
+#define INTF0 0
+#define INTF1 1
+
+#define EIMSK _SFR_IO8(0x1D)
+#define INT0 0
+#define INT1 1
+
+#define GPIOR0 _SFR_IO8(0x1E)
+#define GPIOR00 0
+#define GPIOR01 1
+#define GPIOR02 2
+#define GPIOR03 3
+#define GPIOR04 4
+#define GPIOR05 5
+#define GPIOR06 6
+#define GPIOR07 7
+
+#define EECR _SFR_IO8(0x1F)
+#define EERE 0
+#define EEPE 1
+#define EEMPE 2
+#define EERIE 3
+#define EEPM0 4
+#define EEPM1 5
+
+#define EEDR _SFR_IO8(0x20)
+#define EEDR0 0
+#define EEDR1 1
+#define EEDR2 2
+#define EEDR3 3
+#define EEDR4 4
+#define EEDR5 5
+#define EEDR6 6
+#define EEDR7 7
+
+#define EEARL _SFR_IO8(0x21)
+#define EEAR0 0
+#define EEAR1 1
+#define EEAR2 2
+#define EEAR3 3
+#define EEAR4 4
+#define EEAR5 5
+#define EEAR6 6
+#define EEAR7 7
+
+#define GTCCR _SFR_IO8(0x23)
+#define PSRSYNC 0
+#define TSM 7
+
+#define TCCR0A _SFR_IO8(0x25)
+#define CS00 0
+#define CS01 1
+#define CS02 2
+#define CTC0 3
+
+#define TCNT0 _SFR_IO8(0x26)
+#define TCNT0_0 0
+#define TCNT0_1 1
+#define TCNT0_2 2
+#define TCNT0_3 3
+#define TCNT0_4 4
+#define TCNT0_5 5
+#define TCNT0_6 6
+#define TCNT0_7 7
+
+#define OCR0A _SFR_IO8(0x27)
+#define OCR0A_0 0
+#define OCR0A_1 1
+#define OCR0A_2 2
+#define OCR0A_3 3
+#define OCR0A_4 4
+#define OCR0A_5 5
+#define OCR0A_6 6
+#define OCR0A_7 7
+
+#define OCR0B _SFR_IO8(0x28)
+#define OCR0B_0 0
+#define OCR0B_1 1
+#define OCR0B_2 2
+#define OCR0B_3 3
+#define OCR0B_4 4
+#define OCR0B_5 5
+#define OCR0B_6 6
+#define OCR0B_7 7
+
+#define GPIOR1 _SFR_IO8(0x2A)
+#define GPIOR10 0
+#define GPIOR11 1
+#define GPIOR12 2
+#define GPIOR13 3
+#define GPIOR14 4
+#define GPIOR15 5
+#define GPIOR16 6
+#define GPIOR17 7
+
+#define GPIOR2 _SFR_IO8(0x2B)
+#define GPIOR20 0
+#define GPIOR21 1
+#define GPIOR22 2
+#define GPIOR23 3
+#define GPIOR24 4
+#define GPIOR25 5
+#define GPIOR26 6
+#define GPIOR27 7
+
+#define SPCR _SFR_IO8(0x2C)
+#define SPR0 0
+#define SPR1 1
+#define CPHA 2
+#define CPOL 3
+#define MSTR 4
+#define DORD 5
+#define SPE 6
+#define SPIE 7
+
+#define SPSR _SFR_IO8(0x2D)
+#define SPI2X 0
+#define WCOL 6
+#define SPIF 7
+
+#define SPDR _SFR_IO8(0x2E)
+#define SPDR0 0
+#define SPDR1 1
+#define SPDR2 2
+#define SPDR3 3
+#define SPDR4 4
+#define SPDR5 5
+#define SPDR6 6
+#define SPDR7 7
+
+#define ACSR _SFR_IO8(0x30)
+#define ACIS0 0
+#define ACIS1 1
+#define ACIC 2
+#define ACIE 3
+#define ACI 4
+#define ACO 5
+#define ACBG 6
+#define ACD 7
+
+#define SMCR _SFR_IO8(0x33)
+#define SE 0
+#define SM0 1
+#define SM1 2
+
+#define MCUSR _SFR_IO8(0x34)
+#define PORF 0
+#define EXTRF 1
+#define BORF 2
+#define WDRF 3
+
+#define MCUCR _SFR_IO8(0x35)
+#define PUD 4
+#define BODSE 5
+#define BODS 6
+
+#define SPMCSR _SFR_IO8(0x37)
+#define SELFPRGEN 0
+#define PGERS 1
+#define PGWRT 2
+#define RFLB 3
+#define CTPB 4
+#define RWWSB 6
+
+#define WDTCSR _SFR_MEM8(0x60)
+#define WDP0 0
+#define WDP1 1
+#define WDP2 2
+#define WDE 3
+#define WDCE 4
+#define WDP3 5
+#define WDIE 6
+#define WDIF 7
+
+#define CLKPR _SFR_MEM8(0x61)
+#define CLKPS0 0
+#define CLKPS1 1
+#define CLKPS2 2
+#define CLKPS3 3
+#define CLKPCE 7
+
+#define PRR _SFR_MEM8(0x64)
+#define PRADC 0
+#define PRSPI 2
+#define PRTIM1 3
+#define PRTIM0 5
+#define PRTWI 7
+
+#define __AVR_HAVE_PRR	((1<<PRADC)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRTIM0)|(1<<PRTWI))
+#define __AVR_HAVE_PRR_PRADC
+#define __AVR_HAVE_PRR_PRSPI
+#define __AVR_HAVE_PRR_PRTIM1
+#define __AVR_HAVE_PRR_PRTIM0
+#define __AVR_HAVE_PRR_PRTWI
+
+#define OSCCAL _SFR_MEM8(0x66)
+#define CAL0 0
+#define CAL1 1
+#define CAL2 2
+#define CAL3 3
+#define CAL4 4
+#define CAL5 5
+#define CAL6 6
+#define CAL7 7
+
+#define PCICR _SFR_MEM8(0x68)
+#define PCIE0 0
+#define PCIE1 1
+#define PCIE2 2
+#define PCIE3 3
+
+#define EICRA _SFR_MEM8(0x69)
+#define ISC00 0
+#define ISC01 1
+#define ISC10 2
+#define ISC11 3
+
+#define PCMSK3 _SFR_MEM8(0x6A)
+#define PCINT24 0
+#define PCINT25 1
+#define PCINT26 2
+#define PCINT27 3
+
+#define PCMSK0 _SFR_MEM8(0x6B)
+#define PCINT0 0
+#define PCINT1 1
+#define PCINT2 2
+#define PCINT3 3
+#define PCINT4 4
+#define PCINT5 5
+#define PCINT6 6
+#define PCINT7 7
+
+#define PCMSK1 _SFR_MEM8(0x6C)
+#define PCINT8 0
+#define PCINT9 1
+#define PCINT10 2
+#define PCINT11 3
+#define PCINT12 4
+#define PCINT13 5
+#define PCINT14 6
+#define PCINT15 7
+
+#define PCMSK2 _SFR_MEM8(0x6D)
+#define PCINT16 0
+#define PCINT17 1
+#define PCINT18 2
+#define PCINT19 3
+#define PCINT20 4
+#define PCINT21 5
+#define PCINT22 6
+#define PCINT23 7
+
+#define TIMSK0 _SFR_MEM8(0x6E)
+#define TOIE0 0
+#define OCIE0A 1
+#define OCIE0B 2
+
+#define TIMSK1 _SFR_MEM8(0x6F)
+#define TOIE1 0
+#define OCIE1A 1
+#define OCIE1B 2
+#define ICIE1 5
+
+#ifndef __ASSEMBLER__
+#define ADC     _SFR_MEM16(0x78)
+#endif
+#define ADCW    _SFR_MEM16(0x78)
+
+#define ADCL _SFR_MEM8(0x78)
+#define ADCL0 0
+#define ADCL1 1
+#define ADCL2 2
+#define ADCL3 3
+#define ADCL4 4
+#define ADCL5 5
+#define ADCL6 6
+#define ADCL7 7
+
+#define ADCH _SFR_MEM8(0x79)
+#define ADCH0 0
+#define ADCH1 1
+#define ADCH2 2
+#define ADCH3 3
+#define ADCH4 4
+#define ADCH5 5
+#define ADCH6 6
+#define ADCH7 7
+
+#define ADCSRA _SFR_MEM8(0x7A)
+#define ADPS0 0
+#define ADPS1 1
+#define ADPS2 2
+#define ADIE 3
+#define ADIF 4
+#define ADATE 5
+#define ADSC 6
+#define ADEN 7
+
+#define ADCSRB _SFR_MEM8(0x7B)
+#define ADTS0 0
+#define ADTS1 1
+#define ADTS2 2
+#define ACME 6
+
+#define ADMUX _SFR_MEM8(0x7C)
+#define MUX0 0
+#define MUX1 1
+#define MUX2 2
+#define MUX3 3
+#define ADLAR 5
+#define REFS0 6
+
+#define DIDR0 _SFR_MEM8(0x7E)
+#define ADC0D 0
+#define ADC1D 1
+#define ADC2D 2
+#define ADC3D 3
+#define ADC4D 4
+#define ADC5D 5
+#define ADC6D 6
+#define ADC7D 7
+
+#define DIDR1 _SFR_MEM8(0x7F)
+#define AIN0D 0
+#define AIN1D 1
+
+#define TCCR1A _SFR_MEM8(0x80)
+#define WGM10 0
+#define WGM11 1
+#define COM1B0 4
+#define COM1B1 5
+#define COM1A0 6
+#define COM1A1 7
+
+#define TCCR1B _SFR_MEM8(0x81)
+#define CS10 0
+#define CS11 1
+#define CS12 2
+#define WGM12 3
+#define WGM13 4
+#define ICES1 6
+#define ICNC1 7
+
+#define TCCR1C _SFR_MEM8(0x82)
+#define FOC1B 6
+#define FOC1A 7
+
+#define TCNT1 _SFR_MEM16(0x84)
+
+#define TCNT1L _SFR_MEM8(0x84)
+#define TCNT1L0 0
+#define TCNT1L1 1
+#define TCNT1L2 2
+#define TCNT1L3 3
+#define TCNT1L4 4
+#define TCNT1L5 5
+#define TCNT1L6 6
+#define TCNT1L7 7
+
+#define TCNT1H _SFR_MEM8(0x85)
+#define TCNT1H0 0
+#define TCNT1H1 1
+#define TCNT1H2 2
+#define TCNT1H3 3
+#define TCNT1H4 4
+#define TCNT1H5 5
+#define TCNT1H6 6
+#define TCNT1H7 7
+
+#define ICR1 _SFR_MEM16(0x86)
+
+#define ICR1L _SFR_MEM8(0x86)
+#define ICR1L0 0
+#define ICR1L1 1
+#define ICR1L2 2
+#define ICR1L3 3
+#define ICR1L4 4
+#define ICR1L5 5
+#define ICR1L6 6
+#define ICR1L7 7
+
+#define ICR1H _SFR_MEM8(0x87)
+#define ICR1H0 0
+#define ICR1H1 1
+#define ICR1H2 2
+#define ICR1H3 3
+#define ICR1H4 4
+#define ICR1H5 5
+#define ICR1H6 6
+#define ICR1H7 7
+
+#define OCR1A _SFR_MEM16(0x88)
+
+#define OCR1AL _SFR_MEM8(0x88)
+#define OCR1AL0 0
+#define OCR1AL1 1
+#define OCR1AL2 2
+#define OCR1AL3 3
+#define OCR1AL4 4
+#define OCR1AL5 5
+#define OCR1AL6 6
+#define OCR1AL7 7
+
+#define OCR1AH _SFR_MEM8(0x89)
+#define OCR1AH0 0
+#define OCR1AH1 1
+#define OCR1AH2 2
+#define OCR1AH3 3
+#define OCR1AH4 4
+#define OCR1AH5 5
+#define OCR1AH6 6
+#define OCR1AH7 7
+
+#define OCR1B _SFR_MEM16(0x8A)
+
+#define OCR1BL _SFR_MEM8(0x8A)
+#define OCR1BL0 0
+#define OCR1BL1 1
+#define OCR1BL2 2
+#define OCR1BL3 3
+#define OCR1BL4 4
+#define OCR1BL5 5
+#define OCR1BL6 6
+#define OCR1BL7 7
+
+#define OCR1BH _SFR_MEM8(0x8B)
+#define OCR1BH0 0
+#define OCR1BH1 1
+#define OCR1BH2 2
+#define OCR1BH3 3
+#define OCR1BH4 4
+#define OCR1BH5 5
+#define OCR1BH6 6
+#define OCR1BH7 7
+
+#define TWBR _SFR_MEM8(0xB8)
+#define TWBR0 0
+#define TWBR1 1
+#define TWBR2 2
+#define TWBR3 3
+#define TWBR4 4
+#define TWBR5 5
+#define TWBR6 6
+#define TWBR7 7
+
+#define TWSR _SFR_MEM8(0xB9)
+#define TWPS0 0
+#define TWPS1 1
+#define TWS3 3
+#define TWS4 4
+#define TWS5 5
+#define TWS6 6
+#define TWS7 7
+
+#define TWAR _SFR_MEM8(0xBA)
+#define TWGCE 0
+#define TWA0 1
+#define TWA1 2
+#define TWA2 3
+#define TWA3 4
+#define TWA4 5
+#define TWA5 6
+#define TWA6 7
+
+#define TWDR _SFR_MEM8(0xBB)
+#define TWD0 0
+#define TWD1 1
+#define TWD2 2
+#define TWD3 3
+#define TWD4 4
+#define TWD5 5
+#define TWD6 6
+#define TWD7 7
+
+#define TWCR _SFR_MEM8(0xBC)
+#define TWIE 0
+#define TWEN 2
+#define TWWC 3
+#define TWSTO 4
+#define TWSTA 5
+#define TWEA 6
+#define TWINT 7
+
+#define TWAMR _SFR_MEM8(0xBD)
+#define TWAM0 1
+#define TWAM1 2
+#define TWAM2 3
+#define TWAM3 4
+#define TWAM4 5
+#define TWAM5 6
+#define TWAM6 7
+
+#define TWHSR _SFR_MEM8(0xBE)
+#define TWIHS 0
+
+
+
+/* Interrupt Vectors */
+/* Interrupt vector 0 is the reset vector. */
+
+#define INT0_vect_num     1
+#define INT0_vect         _VECTOR(1)
+
+#define INT1_vect_num     2
+#define INT1_vect         _VECTOR(2)
+
+#define PCINT0_vect_num   3
+#define PCINT0_vect       _VECTOR(3)
+
+#define PCINT1_vect_num   4
+#define PCINT1_vect       _VECTOR(4)
+
+#define PCINT2_vect_num   5
+#define PCINT2_vect       _VECTOR(5)
+
+#define PCINT3_vect_num   6
+#define PCINT3_vect       _VECTOR(6)
+
+#define WDT_vect_num      7
+#define WDT_vect          _VECTOR(7)
+
+#define TIMER1_CAPT_vect_num  8
+#define TIMER1_CAPT_vect  _VECTOR(8)
+
+#define TIMER1_COMPA_vect_num 9
+#define TIMER1_COMPA_vect _VECTOR(9)
+
+#define TIMER1_COMPB_vect_num 10
+#define TIMER1_COMPB_vect _VECTOR(10)
+
+#define TIMER1_OVF_vect_num   11
+#define TIMER1_OVF_vect   _VECTOR(11)
+
+#define TIMER0_COMPA_vect_num 12
+#define TIMER0_COMPA_vect _VECTOR(12)
+
+#define TIMER0_COMPB_vect_num 13
+#define TIMER0_COMPB_vect _VECTOR(13)
+
+#define TIMER0_OVF_vect_num   14
+#define TIMER0_OVF_vect   _VECTOR(14)
+
+#define SPI_STC_vect_num  15
+#define SPI_STC_vect      _VECTOR(15)
+
+#define ADC_vect_num      16
+#define ADC_vect          _VECTOR(16)
+
+#define EE_READY_vect_num 17
+#define EE_READY_vect     _VECTOR(17)
+
+#define ANALOG_COMP_vect_num  18
+#define ANALOG_COMP_vect  _VECTOR(18)
+
+#define TWI_vect_num      19
+#define TWI_vect          _VECTOR(19)
+
+#define _VECTORS_SIZE 40
+
+
+/* Constants */
+#define RAMEND       0x2FF
+#define RAMSTART     (0x100)
+#define XRAMSIZE     0
+#define XRAMEND      RAMEND
+#define E2END        0x3F
+#define E2PAGESIZE   4
+#define FLASHEND     0x1FFF
+#define SPM_PAGESIZE 64
+
+
+/* Fuse Information */
+#define FUSE_MEMORY_SIZE 3
+
+/* Low Fuse Byte */
+#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */
+#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */
+#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */
+#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */
+#define FUSE_SUT0   (unsigned char)~_BV(4) /* Select start-up time */
+#define FUSE_SUT1   (unsigned char)~_BV(5) /* Select start-up time */
+#define FUSE_CKOUT  (unsigned char)~_BV(6) /* Clock output */
+#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */
+#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
+
+/* High Fuse Byte */
+#define FUSE_BODLEVEL0   (unsigned char)~_BV(0) /* Brown-out Detector trigger level */
+#define FUSE_BODLEVEL1   (unsigned char)~_BV(1) /* Brown-out Detector trigger level */
+#define FUSE_BODLEVEL2   (unsigned char)~_BV(2) /* Brown-out Detector trigger level */
+#define FUSE_EESAVE      (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */
+#define FUSE_WDTON       (unsigned char)~_BV(4) /* Watchdog Timer Always On */
+#define FUSE_SPIEN       (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */
+#define FUSE_DWEN        (unsigned char)~_BV(6) /* debugWIRE Enable */
+#define FUSE_RSTDISBL    (unsigned char)~_BV(7) /* External reset disable */
+#define HFUSE_DEFAULT (FUSE_SPIEN)    
+
+/* Extended Fuse Byte */
+#define FUSE_SELFPRGEN   ~_BV(0) /* Self Programming Enable */
+#define EFUSE_DEFAULT (0xFF)
+
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+
+
+/* Signature */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x93
+#define SIGNATURE_2 0x11
+
+#define SLEEP_MODE_IDLE (0x00<<1)
+#define SLEEP_MODE_ADC (0x01<<1)
+#define SLEEP_MODE_PWR_DOWN (0x02<<1)
+#define SLEEP_MODE_PWR_SAVE (0x03<<1)
+
+#endif /* _AVR_IOTN88_H_ */

hardware/tools/avr/avr/include/avr/iotn9.h

@@ -0,0 +1,477 @@
+/* Copyright (c) 2009 Atmel Corporation
+   All rights reserved.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+
+   * Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+
+   * Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in
+     the documentation and/or other materials provided with the
+     distribution.
+
+   * Neither the name of the copyright holders nor the names of
+     contributors may be used to endorse or promote products derived
+     from this software without specific prior written permission.
+
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+  POSSIBILITY OF SUCH DAMAGE. */
+
+/* $Id: iotn9.h 2063 2009-11-18 22:06:28Z arcanum $ */
+
+/* avr/iotn9.h - definitions for ATtiny9 */
+
+/* This file should only be included from <avr/io.h>, never directly. */
+
+#ifndef _AVR_IO_H_
+#  error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+#  define _AVR_IOXXX_H_ "iotn9.h"
+#else
+#  error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif 
+
+
+#ifndef _AVR_ATtiny9_H_
+#define _AVR_ATtiny9_H_ 1
+
+
+/* Registers and associated bit numbers. */
+
+#define PINB _SFR_IO8(0x00)
+#define PINB0 0
+#define PINB1 1
+#define PINB2 2
+#define PINB3 3
+
+#define DDRB _SFR_IO8(0x01)
+#define DDB0 0
+#define DDB1 1
+#define DDB2 2
+#define DDB3 3
+
+#define PORTB _SFR_IO8(0x02)
+#define PORTB0 0
+#define PORTB1 1
+#define PORTB2 2
+#define PORTB3 3
+
+#define PUEB _SFR_IO8(0x03)
+#define PUEB0 0
+#define PUEB1 1
+#define PUEB2 2
+#define PUEB3 3
+
+#define PORTCR _SFR_IO8(0x0C)
+#define BBMB 1
+
+#define PCMSK _SFR_IO8(0x10)
+#define PCINT0 0
+#define PCINT1 1
+#define PCINT2 2
+#define PCINT3 3
+
+#define PCIFR _SFR_IO8(0x11)
+#define PCIF0 0
+
+#define PCICR _SFR_IO8(0x12)
+#define PCIE0 0
+
+#define EIMSK _SFR_IO8(0x13)
+#define INT0 0
+
+#define EIFR _SFR_IO8(0x14)
+#define INTF0 0
+
+#define EICRA _SFR_IO8(0x15)
+#define ISC00 0
+#define ISC01 1
+
+#define DIDR0 _SFR_IO8(0x17)
+#define AIN0D 0
+#define AIN1D 1
+
+#define ACSR _SFR_IO8(0x1F)
+#define ACIS0 0
+#define ACIS1 1
+#define ACIC 2
+#define ACIE 3
+#define ACI 4
+#define ACO 5
+#define ACD 7
+
+#define ICR0 _SFR_IO16(0x22)
+
+#define ICR0L _SFR_IO8(0x22)
+#define ICR0_0 0
+#define ICR0_1 1
+#define ICR0_2 2
+#define ICR0_3 3
+#define ICR0_4 4
+#define ICR0_5 5
+#define ICR0_6 6
+#define ICR0_7 7
+
+#define ICR0H _SFR_IO8(0x23)
+#define ICR0_8 0
+#define ICR0_9 1
+#define ICR0_10 2
+#define ICR0_11 3
+#define ICR0_12 4
+#define ICR0_13 5
+#define ICR0_14 6
+#define ICR0_15 7
+
+#define OCR0B _SFR_IO16(0x24)
+
+#define OCR0BL _SFR_IO8(0x24)
+#define OCR0B0 0
+#define OCR0B1 1
+#define OCR0B2 2
+#define OCR0B3 3
+#define OCR0B4 4
+#define OCR0B5 5
+#define OCR0B6 6
+#define OCR0B7 7
+
+#define OCR0BH _SFR_IO8(0x25)
+#define OCR0B8 0
+#define OCR0B9 1
+#define OCR0B10 2
+#define OCR0B11 3
+#define OCR0B12 4
+#define OCR0B13 5
+#define OCR0B14 6
+#define OCR0B15 7
+
+#define OCR0A _SFR_IO16(0x26)
+
+#define OCR0AL _SFR_IO8(0x26)
+#define OCR0A0 0
+#define OCR0A1 1
+#define OCR0A2 2
+#define OCR0A3 3
+#define OCR0A4 4
+#define OCR0A5 5
+#define OCR0A6 6
+#define OCR0A7 7
+
+#define OCR0AH _SFR_IO8(0x27)
+#define OCR0A8 0
+#define OCR0A9 1
+#define OCR0A10 2
+#define OCR0A11 3
+#define OCR0A12 4
+#define OCR0A13 5
+#define OCR0A14 6
+#define OCR0A15 7
+
+#define TCNT0 _SFR_IO16(0x28)
+
+#define TCNT0L _SFR_IO8(0x28)
+#define TCNT0_0 0
+#define TCNT0_1 1
+#define TCNT0_2 2
+#define TCNT0_3 3
+#define TCNT0_4 4
+#define TCNT0_5 5
+#define TCNT0_6 6
+#define TCNT0_7 7
+
+#define TCNT0H _SFR_IO8(0x29)
+#define TCNT0_8 0
+#define TCNT0_9 1
+#define TCNT0_10 2
+#define TCNT0_11 3
+#define TCNT0_12 4
+#define TCNT0_13 5
+#define TCNT0_14 6
+#define TCNT0_15 7
+
+#define TIFR0 _SFR_IO8(0x2A)
+#define TOV0 0
+#define OCF0A 1
+#define OCF0B 2
+#define ICF0 5
+
+#define TIMSK0 _SFR_IO8(0x2B)
+#define TOIE0 0
+#define OCIE0A 1
+#define OCIE0B 2
+#define ICIE0 5
+
+#define TCCR0C _SFR_IO8(0x2C)
+#define FOC0B 6
+#define FOC0A 7
+
+#define TCCR0B _SFR_IO8(0x2D)
+#define CS00 0
+#define CS01 1
+#define CS02 2
+#define WGM02 3
+#define WGM03 4
+#define ICES0 6
+#define ICNC0 7
+
+#define TCCR0A _SFR_IO8(0x2E)
+#define WGM00 0
+#define WGM01 1
+#define COM0B0 4
+#define COM0B1 5
+#define COM0A0 6
+#define COM0A1 7
+
+#define GTCCR _SFR_IO8(0x2F)
+#define PSR 0
+#define TSM 7
+
+#define WDTCSR _SFR_IO8(0x31)
+#define WDP0 0
+#define WDP1 1
+#define WDP2 2
+#define WDE 3
+#define WDP3 5
+#define WDIE 6
+#define WDIF 7
+
+#define NVMCSR _SFR_IO8(0x32)
+#define NVMBSY 7
+
+#define NVMCMD _SFR_IO8(0x33)
+#define NVMCMD0 0
+#define NVMCMD1 1
+#define NVMCMD2 2
+#define NVMCMD3 3
+#define NVMCMD4 4
+#define NVMCMD5 5
+
+#define VLMCSR _SFR_IO8(0x34)
+#define VLM0 0
+#define VLM1 1
+#define VLM2 2
+#define VLMIE 6
+#define VLMF 7
+
+#define PRR _SFR_IO8(0x35)
+#define PRTIM0 0
+#define PRADC 1
+
+#define __AVR_HAVE_PRR	((1<<PRTIM0)|(1<<PRADC))
+#define __AVR_HAVE_PRR_PRTIM0
+#define __AVR_HAVE_PRR_PRADC
+
+#define CLKPSR _SFR_IO8(0x36)
+#define CLKPS0 0
+#define CLKPS1 1
+#define CLKPS2 2
+#define CLKPS3 3
+
+#define CLKMSR _SFR_IO8(0x37)
+#define CLKMS0 0
+#define CLKMS1 1
+
+#define OSCCAL _SFR_IO8(0x39)
+#define CAL0 0
+#define CAL1 1
+#define CAL2 2
+#define CAL3 3
+#define CAL4 4
+#define CAL5 5
+#define CAL6 6
+#define CAL7 7
+
+#define SMCR _SFR_IO8(0x3A)
+#define SE 0
+#define SM0 1
+#define SM1 2
+#define SM2 3
+
+#define RSTFLR _SFR_IO8(0x3B)
+#define PORF 0
+#define EXTRF 1
+#define WDRF 3
+
+#define CCP _SFR_IO8(0x3C)
+#define CCP0 0
+#define CCP1 1
+#define CCP2 2
+#define CCP3 3
+#define CCP4 4
+#define CCP5 5
+#define CCP6 6
+#define CCP7 7
+
+
+/* Interrupt vectors */
+/* Vector 0 is the reset vector */
+#define INT0_vect_num  1
+#define INT0_vect      _VECTOR(1)  /* External Interrupt Request 0 */
+#define PCINT0_vect_num  2
+#define PCINT0_vect      _VECTOR(2)  /* Pin Change Interrupt Request 0 */
+#define TIM0_CAPT_vect_num  3
+#define TIM0_CAPT_vect      _VECTOR(3)  /* Timer/Counter0 Input Capture */
+#define TIM0_OVF_vect_num  4
+#define TIM0_OVF_vect      _VECTOR(4)  /* Timer/Counter0 Overflow */
+#define TIM0_COMPA_vect_num  5
+#define TIM0_COMPA_vect      _VECTOR(5)  /* Timer/Counter Compare Match A */
+#define TIM0_COMPB_vect_num  6
+#define TIM0_COMPB_vect      _VECTOR(6)  /* Timer/Counter Compare Match B */
+#define ANA_COMP_vect_num  7
+#define ANA_COMP_vect      _VECTOR(7)  /* Analog Comparator */
+#define WDT_vect_num  8
+#define WDT_vect      _VECTOR(8)  /* Watchdog Time-out */
+#define VLM_vect_num  9
+#define VLM_vect      _VECTOR(9)  /* Vcc Voltage Level Monitor */
+
+#define _VECTOR_SIZE 2 /* Size of individual vector. */
+#define _VECTORS_SIZE (10 * _VECTOR_SIZE)
+
+
+/* Constants */
+#define SPM_PAGESIZE (32)
+#define RAMSTART     (0x40)
+#define RAMSIZE      (32)
+#define RAMEND       (RAMSTART + RAMSIZE - 1)
+#define XRAMSTART    (NA)
+#define XRAMSIZE     (0)
+#define XRAMEND      (RAMEND)
+#define E2END        (0x0)
+#define E2PAGESIZE   (0)
+#define FLASHEND     (0x3FF)
+
+
+/* Fuses */
+#define FUSE_MEMORY_SIZE 0
+
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+
+
+/* Signature */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x90
+#define SIGNATURE_2 0x08
+
+
+/* Device Pin Definitions */
+#define SPDATA_DDR   DDRCINT
+#define SPDATA_PORT  PORTCINT
+#define SPDATA_PIN   PINCINT
+#define SPDATA_BIT   INT0
+
+#define OC0A_DDR   DDRCINT
+#define OC0A_PORT  PORTCINT
+#define OC0A_PIN   PINCINT
+#define OC0A_BIT   INT0
+
+#define ADC0_DDR   DDRCINT
+#define ADC0_PORT  PORTCINT
+#define ADC0_PIN   PINCINT
+#define ADC0_BIT   INT0
+
+#define AIN0_DDR   DDRCINT
+#define AIN0_PORT  PORTCINT
+#define AIN0_PIN   PINCINT
+#define AIN0_BIT   INT0
+
+#define PB0_DDR   DDRCINT
+#define PB0_PORT  PORTCINT
+#define PB0_PIN   PINCINT
+#define PB0_BIT   INT0
+
+#define SPCLK_DDR   DDRCINT
+#define SPCLK_PORT  PORTCINT
+#define SPCLK_PIN   PINCINT
+#define SPCLK_BIT   INT1
+
+#define CLKI_DDR   DDRCINT
+#define CLKI_PORT  PORTCINT
+#define CLKI_PIN   PINCINT
+#define CLKI_BIT   INT1
+
+#define ICP0_DDR   DDRCINT
+#define ICP0_PORT  PORTCINT
+#define ICP0_PIN   PINCINT
+#define ICP0_BIT   INT1
+
+#define OC0B_DDR   DDRCINT
+#define OC0B_PORT  PORTCINT
+#define OC0B_PIN   PINCINT
+#define OC0B_BIT   INT1
+
+#define ADC1_DDR   DDRCINT
+#define ADC1_PORT  PORTCINT
+#define ADC1_PIN   PINCINT
+#define ADC1_BIT   INT1
+
+#define AIN1_DDR   DDRCINT
+#define AIN1_PORT  PORTCINT
+#define AIN1_PIN   PINCINT
+#define AIN1_BIT   INT1
+
+#define PB1_DDR   DDRCINT
+#define PB1_PORT  PORTCINT
+#define PB1_PIN   PINCINT
+#define PB1_BIT   INT1
+
+#define CLKO_DDR   DDRT
+#define CLKO_PORT  PORTT
+#define CLKO_PIN   PINT
+#define CLKO_BIT   T0
+
+#define PCINT2_DDR   DDRT
+#define PCINT2_PORT  PORTT
+#define PCINT2_PIN   PINT
+#define PCINT2_BIT   T0
+
+#define INT0_DDR   DDRT
+#define INT0_PORT  PORTT
+#define INT0_PIN   PINT
+#define INT0_BIT   T0
+
+#define ADC2_DDR   DDRT
+#define ADC2_PORT  PORTT
+#define ADC2_PIN   PINT
+#define ADC2_BIT   T0
+
+#define PB2_DDR   DDRT
+#define PB2_PORT  PORTT
+#define PB2_PIN   PINT
+#define PB2_BIT   T0
+
+#define PCINT3_DDR   DDRRESET
+#define PCINT3_PORT  PORTRESET
+#define PCINT3_PIN   PINRESET
+#define PCINT3_BIT   RESET
+
+#define ADC3_DDR   DDRRESET
+#define ADC3_PORT  PORTRESET
+#define ADC3_PIN   PINRESET
+#define ADC3_BIT   RESET
+
+#define PB3_DDR   DDRRESET
+#define PB3_PORT  PORTRESET
+#define PB3_PIN   PINRESET
+#define PB3_BIT   RESET
+
+#define SLEEP_MODE_IDLE (0x00<<1)
+#define SLEEP_MODE_ADC (0x01<<1)
+#define SLEEP_MODE_PWR_DOWN (0x02<<1)
+#define SLEEP_MODE_STANDBY (0x04<<1)
+
+#endif /* _AVR_ATtiny9_H_ */
+

hardware/tools/avr/avr/include/avr/iotnx4.h

@@ -0,0 +1,482 @@
+/* Copyright (c) 2005,2007 Anatoly Sokolov
+   All rights reserved.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+
+   * Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+
+   * Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in
+     the documentation and/or other materials provided with the
+     distribution.
+
+   * Neither the name of the copyright holders nor the names of
+     contributors may be used to endorse or promote products derived
+     from this software without specific prior written permission.
+
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+  POSSIBILITY OF SUCH DAMAGE. */
+
+/* $Id: iotnx4.h 2225 2011-03-02 16:27:26Z arcanum $ */
+
+/* avr/iotnx4.h - definitions for ATtiny24, ATtiny44 and ATtiny84 */
+
+#ifndef _AVR_IOTNX4_H_
+#define _AVR_IOTNX4_H_ 1
+
+/* This file should only be included from <avr/io.h>, never directly. */
+
+#ifndef _AVR_IO_H_
+#  error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+#  define _AVR_IOXXX_H_ "iotnx4.h"
+#else
+#  error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif 
+
+/* I/O registers */
+
+#define PRR     _SFR_IO8 (0x00)
+#define PRTIM1  3
+#define PRTIM0  2
+#define PRUSI   1
+#define PRADC   0
+
+#define __AVR_HAVE_PRR	((1<<PRADC)|(1<<PRUSI)|(1<<PRTIM0)|(1<<PRTIM1))
+#define __AVR_HAVE_PRR_PRADC
+#define __AVR_HAVE_PRR_PRUSI
+#define __AVR_HAVE_PRR_PRTIM0
+#define __AVR_HAVE_PRR_PRTIM1
+
+#define DIDR0    _SFR_IO8(0x01)
+#define ADC7D   7
+#define ADC6D   6
+#define ADC5D   5
+#define ADC4D   4
+#define ADC3D   3
+#define ADC2D   2
+#define ADC1D   1 
+#define ADC0D   0
+
+/* Reserved [0x02] */
+
+#define ADCSRB  _SFR_IO8 (0x03)
+#define BIN     7
+#define ACME    6
+#define ADLAR   4
+#define ADTS2   2
+#define ADTS1   1
+#define ADTS0   0
+
+#ifndef __ASSEMBLER__
+#define ADC     _SFR_IO16(0x04)
+#endif
+#define ADCW    _SFR_IO16(0x04)
+#define ADCL    _SFR_IO8(0x04)
+#define ADCH    _SFR_IO8(0x05)
+
+#define ADCSRA  _SFR_IO8 (0x06)
+#define ADEN    7
+#define ADSC    6
+#define ADATE   5
+#define ADIF    4
+#define ADIE    3
+#define ADPS2   2
+#define ADPS1   1
+#define ADPS0   0
+
+#define ADMUX   _SFR_IO8(0x07)
+#define REFS1   7
+#define REFS0   6
+#define MUX5    5
+#define MUX4    4
+#define MUX3    3
+#define MUX2    2
+#define MUX1    1
+#define MUX0    0
+
+#define ACSR    _SFR_IO8(0x08)
+#define ACD     7
+#define ACBG    6
+#define ACO     5
+#define ACI     4
+#define ACIE    3
+#define ACIC    2
+#define ACIS1   1
+#define ACIS0   0
+
+/* Reserved [0x09..0x0A] */
+
+#define TIFR1   _SFR_IO8(0x0B)
+#define ICF1    5
+#define OCF1B   2
+#define OCF1A   1
+#define TOV1    0
+
+#define TIMSK1   _SFR_IO8(0x0C)
+#define ICIE1   5
+#define OCIE1B  2
+#define OCIE1A  1
+#define TOIE1   0
+
+#define USICR   _SFR_IO8(0x0D)
+#define USISIE  7
+#define USIOIE  6
+#define USIWM1  5
+#define USIWM0  4
+#define USICS1  3
+#define USICS0  2
+#define USICLK  1
+#define USITC   0
+
+#define USISR   _SFR_IO8(0x0E)
+#define USISIF  7 
+#define USIOIF  6
+#define USIPF   5
+#define USIDC   4
+#define USICNT3 3
+#define USICNT2 2
+#define USICNT1 1
+#define USICNT0 0
+
+#define USIDR   _SFR_IO8(0x0F)
+
+#define USIBR   _SFR_IO8(0x10)
+
+/* Reserved [0x11] */
+
+#define PCMSK0  _SFR_IO8(0x12)
+#define PCINT7  7
+#define PCINT6  6
+#define PCINT5  5
+#define PCINT4  4
+#define PCINT3  3
+#define PCINT2  2
+#define PCINT1  1
+#define PCINT0  0
+
+#define GPIOR0  _SFR_IO8(0x13)
+
+#define GPIOR1  _SFR_IO8(0x14)
+
+#define GPIOR2  _SFR_IO8(0x15)
+
+#define PINB    _SFR_IO8(0x16)
+#define PINB3   3
+#define PINB2   2
+#define PINB1   1
+#define PINB0   0
+
+#define DDRB    _SFR_IO8(0x17)
+#define DDB3    3
+#define DDB2    2
+#define DDB1    1
+#define DDB0    0
+
+#define PORTB   _SFR_IO8(0x18)
+#define PB3     3
+#define PB2     2
+#define PB1     1
+#define PB0     0
+
+#define PINA    _SFR_IO8(0x19)
+#define PINA7   7
+#define PINA6   6
+#define PINA5   5
+#define PINA4   4
+#define PINA3   3
+#define PINA2   2
+#define PINA1   1
+#define PINA0   0
+
+#define DDRA    _SFR_IO8(0x1A)
+#define DDA7    7
+#define DDA6    6
+#define DDA5    5
+#define DDA4    4
+#define DDA3    3
+#define DDA2    2
+#define DDA1    1
+#define DDA0    0
+
+#define PORTA   _SFR_IO8(0x1B)
+#define PA7     7
+#define PA6     6
+#define PA5     5
+#define PA4     4
+#define PA3     3
+#define PA2     2
+#define PA1     1
+#define PA0     0
+
+/* EEPROM Control Register EECR */
+#define EECR	_SFR_IO8(0x1C)
+#define EEPM1   5
+#define EEPM0   4
+#define EERIE   3
+#define EEMPE   2
+#define EEPE    1
+#define EERE    0
+
+/* EEPROM Data Register */
+#define EEDR	_SFR_IO8(0x1D)
+
+/* EEPROM Address Register */
+#define EEAR	_SFR_IO16(0x1E)
+#define EEARL	_SFR_IO8(0x1E)
+#define EEARH	_SFR_IO8(0x1F)
+
+#define PCMSK1  _SFR_IO8(0x20)
+#define PCINT11 3
+#define PCINT10 2
+#define PCINT9  1
+#define PCINT8  0
+
+#define WDTCSR _SFR_IO8(0x21)
+#define WDIF    7
+#define WDIE    6
+#define WDP3    5
+#define WDCE    4
+#define WDE     3
+#define WDP2    2
+#define WDP1    1
+#define WDP0    0
+
+#define TCCR1C  _SFR_IO8(0x22)
+#define FOC1A   7
+#define FOC1B   6
+
+#define GTCCR   _SFR_IO8(0x23)
+#define TSM     7
+#define PSR10   0
+
+#define ICR1    _SFR_IO16(0x24)
+#define ICR1L   _SFR_IO8(0x24)
+#define ICR1H   _SFR_IO8(0x25)
+
+#define CLKPR   _SFR_IO8(0x26)
+#define CLKPCE  7
+#define CLKPS3  3
+#define CLKPS2  2
+#define CLKPS1  1
+#define CLKPS0  0
+
+#define DWDR    _SFR_IO8(0x27)
+
+#define OCR1B   _SFR_IO16(0x28)
+#define OCR1BL  _SFR_IO8(0x28)
+#define OCR1BH  _SFR_IO8(0x29)
+
+#define OCR1A   _SFR_IO16(0x2A)
+#define OCR1AL  _SFR_IO8(0x2A)
+#define OCR1AH  _SFR_IO8(0x2B)
+
+/* keep misspelled names from avr-libc 1.4.[0..1] for compatibility */
+#define OCRB1   _SFR_IO16(0x28)
+#define OCRB1L  _SFR_IO8(0x28)
+#define OCRB1H  _SFR_IO8(0x29)
+
+#define OCRA1   _SFR_IO16(0x2A)
+#define OCRA1L  _SFR_IO8(0x2A)
+#define OCRA1H  _SFR_IO8(0x2B)
+
+#define TCNT1   _SFR_IO16(0x2C)
+#define TCNT1L  _SFR_IO8(0x2C)
+#define TCNT1H  _SFR_IO8(0x2D)
+
+#define TCCR1B  _SFR_IO8(0x2E)
+#define ICNC1   7
+#define ICES1   6
+#define WGM13   4
+#define WGM12   3
+#define CS12    2
+#define CS11    1
+#define CS10    0
+
+#define TCCR1A  _SFR_IO8(0x2F)
+#define COM1A1  7
+#define COM1A0  6
+#define COM1B1  5
+#define COM1B0  4
+#define WGM11   1
+#define WGM10   0
+
+#define TCCR0A  _SFR_IO8(0x30)
+#define COM0A1  7
+#define COM0A0  6
+#define COM0B1  5
+#define COM0B0  4
+#define WGM01   1
+#define WGM00   0
+
+#define OSCCAL  _SFR_IO8(0x31)
+
+#define TCNT0   _SFR_IO8(0x32)
+
+#define TCCR0B  _SFR_IO8(0x33)
+#define FOC0A   7
+#define FOC0B   6
+#define WGM02   3
+#define CS02    2
+#define CS01    1
+#define CS00    0
+
+#define MCUSR   _SFR_IO8(0x34)
+#define WDRF    3
+#define BORF    2
+#define EXTRF   1
+#define PORF    0
+
+#define MCUCR   _SFR_IO8(0x35)
+#define BODS    7
+#define PUD     6
+#define SE      5
+#define SM1     4
+#define SM0     3
+#define BODSE   2
+#define ISC01   1
+#define ISC00   0
+
+#define OCR0A   _SFR_IO8(0x36)
+
+#define SPMCSR  _SFR_IO8(0x37)
+#define RSIG    5
+#define CTPB    4
+#define RFLB    3
+#define PGWRT   2
+#define PGERS   1
+#define SPMEN   0
+
+#define TIFR0   _SFR_IO8(0x38)
+#define OCF0B   2
+#define OCF0A   1
+#define TOV0    0
+
+#define TIMSK0  _SFR_IO8(0x39)
+#define OCIE0B  2
+#define OCIE0A  1
+#define TOIE0   0
+
+#define GIFR    _SFR_IO8(0x3A)
+#define INTF0   6
+#define PCIF1   5
+#define PCIF0   4
+
+#define GIMSK   _SFR_IO8(0x3B)
+#define INT0    6
+#define PCIE1   5
+#define PCIE0   4
+
+#define OCR0B   _SFR_IO8(0x3C)
+
+/* 0x3D..0x3E SP  [defined in <avr/io.h>] */
+/* 0x3F SREG      [defined in <avr/io.h>] */
+
+///---
+
+/* Interrupt vectors */
+/* Interrupt vector 0 is the reset vector. */
+/* External Interrupt Request 0 */
+#define INT0_vect_num		    1
+#define INT0_vect			    _VECTOR(1)
+#define EXT_INT0_vect_num    	1
+#define EXT_INT0_vect			_VECTOR(1)
+#define SIG_INTERRUPT0			_VECTOR(1)
+
+/* Pin Change Interrupt Request 0 */
+#define PCINT0_vect_num		    2
+#define PCINT0_vect			    _VECTOR(2)
+#define SIG_PIN_CHANGE0			_VECTOR(2)
+
+/* Pin Change Interrupt Request 1 */
+#define PCINT1_vect_num		    3
+#define PCINT1_vect			    _VECTOR(3)
+#define SIG_PIN_CHANGE1			_VECTOR(3)
+
+/* Watchdog Time-out */
+#define WDT_vect_num			4
+#define WDT_vect			    _VECTOR(4)
+#define WATCHDOG_vect_num		4
+#define WATCHDOG_vect			_VECTOR(4)
+#define SIG_WATCHDOG_TIMEOUT	_VECTOR(4)
+
+/* Timer/Counter1 Capture Event */
+#define TIMER1_CAPT_vect_num	5
+#define TIMER1_CAPT_vect		_VECTOR(5)
+#define TIM1_CAPT_vect_num		5
+#define TIM1_CAPT_vect			_VECTOR(5)
+#define SIG_INPUT_CAPTURE1		_VECTOR(5)
+
+/* Timer/Counter1 Compare Match A */
+#define TIM1_COMPA_vect_num		6
+#define TIM1_COMPA_vect			_VECTOR(6)
+#define SIG_OUTPUT_COMPARE1A	_VECTOR(6)
+
+/* Timer/Counter1 Compare Match B */
+#define TIM1_COMPB_vect_num		7
+#define TIM1_COMPB_vect			_VECTOR(7)
+#define SIG_OUTPUT_COMPARE1B	_VECTOR(7)
+
+/* Timer/Counter1 Overflow */
+#define TIM1_OVF_vect_num		8
+#define TIM1_OVF_vect			_VECTOR(8)
+#define SIG_OVERFLOW1			_VECTOR(8)
+
+/* Timer/Counter0 Compare Match A */
+#define TIM0_COMPA_vect_num		9
+#define TIM0_COMPA_vect			_VECTOR(9)
+#define SIG_OUTPUT_COMPARE0A	_VECTOR(9)
+
+/* Timer/Counter0 Compare Match B */
+#define TIM0_COMPB_vect_num		10
+#define TIM0_COMPB_vect			_VECTOR(10)
+#define SIG_OUTPUT_COMPARE0B	_VECTOR(10)
+
+/* Timer/Counter0 Overflow */
+#define TIM0_OVF_vect_num		11
+#define TIM0_OVF_vect			_VECTOR(11)
+#define SIG_OVERFLOW0			_VECTOR(11)
+
+/* Analog Comparator */
+#define ANA_COMP_vect_num		12
+#define ANA_COMP_vect			_VECTOR(12)
+#define SIG_COMPARATOR			_VECTOR(12)
+
+/* ADC Conversion Complete */
+#define ADC_vect_num		    13
+#define ADC_vect			    _VECTOR(13)
+#define SIG_ADC				    _VECTOR(13)
+
+/* EEPROM Ready */
+#define EE_RDY_vect_num		    14
+#define EE_RDY_vect			    _VECTOR(14)
+#define SIG_EEPROM_READY		_VECTOR(14)
+
+/* USI START */
+#define USI_START_vect_num		15
+#define USI_START_vect			_VECTOR(15)
+#define USI_STR_vect_num		15
+#define USI_STR_vect			_VECTOR(15)
+#define SIG_USI_START			_VECTOR(15)
+
+/* USI Overflow */
+#define USI_OVF_vect_num		16
+#define USI_OVF_vect			_VECTOR(16)
+#define SIG_USI_OVERFLOW		_VECTOR(16)
+
+#define _VECTORS_SIZE 34
+
+#endif /* _AVR_IOTNX4_H_ */

hardware/tools/avr/avr/include/avr/iotnx5.h

@@ -0,0 +1,442 @@
+/* Copyright (c) 2005,2007 Anatoly Sokolov
+   All rights reserved.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+
+   * Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+
+   * Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in
+     the documentation and/or other materials provided with the
+     distribution.
+
+   * Neither the name of the copyright holders nor the names of
+     contributors may be used to endorse or promote products derived
+     from this software without specific prior written permission.
+
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+  POSSIBILITY OF SUCH DAMAGE. */
+
+/* $Id: iotnx5.h 2269 2011-12-29 08:07:25Z joerg_wunsch $ */
+
+/* avr/iotnx5.h - definitions for ATtiny25, ATtiny45 and ATtiny85 */
+
+#ifndef _AVR_IOTNX5_H_
+#define _AVR_IOTNX5_H_ 1
+
+/* This file should only be included from <avr/io.h>, never directly. */
+
+#ifndef _AVR_IO_H_
+#  error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+#  define _AVR_IOXXX_H_ "iotnx5.h"
+#else
+#  error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif 
+
+/* I/O registers */
+
+/* Reserved [0x00..0x02] */
+
+#define ADCSRB  _SFR_IO8 (0x03)
+#define BIN     7
+#define ACME    6
+#define IPR     5
+#define ADTS2   2
+#define ADTS1   1
+#define ADTS0   0
+
+#ifndef __ASSEMBLER__
+#define ADC     _SFR_IO16(0x04)
+#endif
+#define ADCW    _SFR_IO16(0x04)
+#define ADCL    _SFR_IO8(0x04)
+#define ADCH    _SFR_IO8(0x05)
+
+#define ADCSRA  _SFR_IO8 (0x06)
+#define ADEN    7
+#define ADSC    6
+#define ADATE   5
+#define ADIF    4
+#define ADIE    3
+#define ADPS2   2
+#define ADPS1   1
+#define ADPS0   0
+
+#define ADMUX   _SFR_IO8(0x07)
+#define REFS1   7
+#define REFS0   6
+#define ADLAR   5
+#define REFS2   4
+#define MUX3    3
+#define MUX2    2
+#define MUX1    1
+#define MUX0    0
+
+#define ACSR    _SFR_IO8(0x08)
+#define ACD     7
+#define ACBG    6
+#define ACO     5
+#define ACI     4
+#define ACIE    3
+#define ACIS1   1
+#define ACIS0   0
+
+/* Reserved [0x09..0x0C] */
+
+#define USICR   _SFR_IO8(0x0D)
+#define USISIE  7
+#define USIOIE  6
+#define USIWM1  5
+#define USIWM0  4
+#define USICS1  3
+#define USICS0  2
+#define USICLK  1
+#define USITC   0
+
+#define USISR   _SFR_IO8(0x0E)
+#define USISIF  7 
+#define USIOIF  6
+#define USIPF   5
+#define USIDC   4
+#define USICNT3 3
+#define USICNT2 2
+#define USICNT1 1
+#define USICNT0 0
+
+#define USIDR   _SFR_IO8(0x0F)
+#define USIBR   _SFR_IO8(0x10)
+
+#define GPIOR0  _SFR_IO8(0x11)
+#define GPIOR1  _SFR_IO8(0x12)
+#define GPIOR2  _SFR_IO8(0x13)
+
+#define DIDR0    _SFR_IO8(0x14)
+#define ADC0D   5
+#define ADC2D   4
+#define ADC3D   3
+#define ADC1D   2
+#define AIN1D   1 
+#define AIN0D   0
+
+#define PCMSK   _SFR_IO8(0x15)
+#define PCINT5  5
+#define PCINT4  4
+#define PCINT3  3
+#define PCINT2  2
+#define PCINT1  1
+#define PCINT0  0
+
+#define PINB    _SFR_IO8(0x16)
+#define PINB5   5
+#define PINB4   4
+#define PINB3   3
+#define PINB2   2
+#define PINB1   1
+#define PINB0   0
+
+#define DDRB    _SFR_IO8(0x17)
+#define DDB5    5
+#define DDB4    4
+#define DDB3    3
+#define DDB2    2
+#define DDB1    1
+#define DDB0    0
+
+#define PORTB   _SFR_IO8(0x18)
+#define PB5     5
+#define PB4     4
+#define PB3     3
+#define PB2     2
+#define PB1     1
+#define PB0     0
+
+/* Reserved [0x19..0x1B] */
+
+/* EEPROM Control Register EECR */
+#define EECR	_SFR_IO8(0x1C)
+#define EEPM1   5
+#define EEPM0   4
+#define EERIE   3
+#define EEMPE   2
+#define EEPE    1
+#define EERE    0
+
+/* EEPROM Data Register */
+#define EEDR	_SFR_IO8(0x1D)
+
+/* EEPROM Address Register */
+#define EEAR	_SFR_IO16(0x1E)
+#define EEARL	_SFR_IO8(0x1E)
+#define EEARH	_SFR_IO8(0x1F)
+
+#define PRR     _SFR_IO8(0x20)
+#define PRTIM1  3
+#define PRTIM0  2
+#define PRUSI   1
+#define PRADC   0
+
+#define __AVR_HAVE_PRR	((1<<PRADC)|(1<<PRUSI)|(1<<PRTIM0)|(1<<PRTIM1))
+#define __AVR_HAVE_PRR_PRADC
+#define __AVR_HAVE_PRR_PRUSI
+#define __AVR_HAVE_PRR_PRTIM0
+#define __AVR_HAVE_PRR_PRTIM1
+
+#define WDTCR   _SFR_IO8(0x21)
+#define WDIF    7
+#define WDIE    6
+#define WDP3    5
+#define WDCE    4
+#define WDE     3
+#define WDP2    2
+#define WDP1    1
+#define WDP0    0
+
+#define DWDR    _SFR_IO8(0x22)
+
+#define DTPS1   _SFR_IO8(0x23)
+#define DTPS11   1
+#define DTPS10   0
+
+#define DT1B    _SFR_IO8(0x24)
+#define DT1BH3  7
+#define DT1BH2  6
+#define DT1BH1  5
+#define DT1BH0  4
+#define DT1BL3  3
+#define DT1BL2  2
+#define DT1BL1  1
+#define DT1BL0  0
+
+#define DT1A    _SFR_IO8(0x25)
+#define DT1AH3  7
+#define DT1AH2  6
+#define DT1AH1  5
+#define DT1AH0  4
+#define DT1AL3  3
+#define DT1AL2  2
+#define DT1AL1  1
+#define DT1AL0  0
+
+#define CLKPR   _SFR_IO8(0x26)
+#define CLKPCE  7
+#define CLKPS3  3
+#define CLKPS2  2
+#define CLKPS1  1
+#define CLKPS0  0
+
+#define PLLCSR  _SFR_IO8(0x27)
+#define LSM     7
+#define PCKE    2
+#define PLLE    1
+#define PLOCK   0
+
+#define OCR0B   _SFR_IO8(0x28)
+
+#define OCR0A   _SFR_IO8(0x29)
+
+#define TCCR0A  _SFR_IO8(0x2A)
+#define COM0A1  7
+#define COM0A0  6
+#define COM0B1  5
+#define COM0B0  4
+#define WGM01   1
+#define WGM00   0
+
+#define OCR1B   _SFR_IO8(0x2B)
+
+#define GTCCR   _SFR_IO8(0x2C)
+#define TSM     7
+#define PWM1B   6
+#define COM1B1  5
+#define COM1B0  4
+#define FOC1B   3
+#define FOC1A   2
+#define PSR1    1
+#define PSR0    0
+
+#define OCR1C   _SFR_IO8(0x2D)
+
+#define OCR1A   _SFR_IO8(0x2E)
+
+#define TCNT1   _SFR_IO8(0x2F)
+
+#define TCCR1   _SFR_IO8(0x30)
+#define CTC1    7
+#define PWM1A   6
+#define COM1A1  5
+#define COM1A0  4
+#define CS13    3
+#define CS12    2
+#define CS11    1
+#define CS10    0
+
+#define OSCCAL  _SFR_IO8(0x31)
+
+#define TCNT0   _SFR_IO8(0x32)
+
+#define TCCR0B  _SFR_IO8(0x33)
+#define FOC0A   7
+#define FOC0B   6
+#define WGM02   3
+#define CS02    2
+#define CS01    1
+#define CS00    0
+
+#define MCUSR   _SFR_IO8(0x34)
+#define WDRF    3
+#define BORF    2
+#define EXTRF   1
+#define PORF    0
+
+#define MCUCR   _SFR_IO8(0x35)
+#define BODS    7
+#define PUD     6
+#define SE      5
+#define SM1     4
+#define SM0     3
+#define BODSE   2
+#define ISC01   1
+#define ISC00   0
+
+/* Reserved [0x36] */
+
+#define SPMCSR  _SFR_IO8(0x37)
+#define RSIG    5
+#define CTPB    4
+#define RFLB    3
+#define PGWRT   2
+#define PGERS   1
+#define SPMEN   0
+
+#define TIFR    _SFR_IO8(0x38)
+#define OCF1A   6
+#define OCF1B   5
+#define OCF0A   4
+#define OCF0B   3
+#define TOV1    2
+#define TOV0    1
+
+#define TIMSK   _SFR_IO8(0x39)
+#define OCIE1A  6
+#define OCIE1B  5
+#define OCIE0A  4
+#define OCIE0B  3
+#define TOIE1   2
+#define TOIE0   1
+
+#define GIFR    _SFR_IO8(0x3A)
+#define INTF0   6
+#define PCIF    5
+
+#define GIMSK   _SFR_IO8(0x3B)
+#define INT0    6
+#define PCIE    5
+
+/* Reserved [0x3C] */
+
+/* 0x3D..0x3E SP  [defined in <avr/io.h>] */
+/* 0x3F SREG      [defined in <avr/io.h>] */
+
+///---
+
+/* Interrupt vectors */
+/* Interrupt vector 0 is the reset vector. */
+/* External Interrupt 0 */
+#define INT0_vect_num	        1
+#define INT0_vect			    _VECTOR(1)
+#define SIG_INTERRUPT0			_VECTOR(1)
+
+/* Pin change Interrupt Request 0 */
+#define PCINT0_vect_num			2
+#define PCINT0_vect			    _VECTOR(2)
+#define SIG_PIN_CHANGE			_VECTOR(2)
+
+/* Timer/Counter1 Compare Match 1A */
+#define TIM1_COMPA_vect_num		3
+#define TIM1_COMPA_vect			_VECTOR(3)
+#define TIMER1_COMPA_vect_num	3
+#define TIMER1_COMPA_vect		_VECTOR(3)
+#define SIG_OUTPUT_COMPARE1A	_VECTOR(3)
+
+/* Timer/Counter1 Overflow */
+#define TIM1_OVF_vect_num		4
+#define TIM1_OVF_vect			_VECTOR(4)
+#define TIMER1_OVF_vect_num		4
+#define TIMER1_OVF_vect			_VECTOR(4)
+#define SIG_OVERFLOW1			_VECTOR(4)
+
+/* Timer/Counter0 Overflow */
+#define TIM0_OVF_vect_num		5
+#define TIM0_OVF_vect			_VECTOR(5)
+#define TIMER0_OVF_vect_num		5
+#define TIMER0_OVF_vect			_VECTOR(5)
+#define SIG_OVERFLOW0			_VECTOR(5)
+
+/* EEPROM Ready */
+#define EE_RDY_vect_num			6
+#define EE_RDY_vect		    	_VECTOR(6)
+#define SIG_EEPROM_READY		_VECTOR(6)
+
+/* Analog comparator */
+#define ANA_COMP_vect_num		7
+#define ANA_COMP_vect			_VECTOR(7)
+#define SIG_COMPARATOR			_VECTOR(7)
+
+/* ADC Conversion ready */
+#define ADC_vect_num    		8
+#define ADC_vect		    	_VECTOR(8)
+#define SIG_ADC				    _VECTOR(8)
+
+/* Timer/Counter1 Compare Match B */
+#define TIM1_COMPB_vect_num  	9
+#define TIM1_COMPB_vect			_VECTOR(9)
+#define TIMER1_COMPB_vect_num	9
+#define TIMER1_COMPB_vect   	_VECTOR(9)
+#define SIG_OUTPUT_COMPARE1B	_VECTOR(9)
+
+/* Timer/Counter0 Compare Match A */
+#define TIM0_COMPA_vect_num		10
+#define TIM0_COMPA_vect			_VECTOR(10)
+#define TIMER0_COMPA_vect_num	10
+#define TIMER0_COMPA_vect		_VECTOR(10)
+#define SIG_OUTPUT_COMPARE0A	_VECTOR(10)
+
+/* Timer/Counter0 Compare Match B */
+#define TIM0_COMPB_vect_num		11
+#define TIM0_COMPB_vect			_VECTOR(11)
+#define TIMER0_COMPB_vect_num	11
+#define TIMER0_COMPB_vect		_VECTOR(11)
+#define SIG_OUTPUT_COMPARE0B	_VECTOR(11)
+
+/* Watchdog Time-out */
+#define WDT_vect_num			12
+#define WDT_vect				_VECTOR(12)
+#define SIG_WATCHDOG_TIMEOUT	_VECTOR(12)
+
+/* USI START */
+#define USI_START_vect_num		13
+#define USI_START_vect			_VECTOR(13)
+#define SIG_USI_START			_VECTOR(13)
+
+/* USI Overflow */
+#define USI_OVF_vect_num		14
+#define USI_OVF_vect			_VECTOR(14)
+#define SIG_USI_OVERFLOW		_VECTOR(14)
+
+#define _VECTORS_SIZE 30
+
+#endif /* _AVR_IOTNX5_H_ */

hardware/tools/avr/avr/include/avr/iotnx61.h

@@ -0,0 +1,541 @@
+/* Copyright (c) 2006, 2007 Anatoly Sokolov
+   All rights reserved.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+
+   * Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+
+   * Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in
+     the documentation and/or other materials provided with the
+     distribution.
+
+   * Neither the name of the copyright holders nor the names of
+     contributors may be used to endorse or promote products derived
+     from this software without specific prior written permission.
+
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+  POSSIBILITY OF SUCH DAMAGE. */
+
+/* $Id: iotnx61.h 2247 2011-05-23 19:39:56Z joerg_wunsch $ */
+
+/* avr/iotnx61.h - definitions for ATtiny261, ATtiny461 and ATtiny861 */
+
+/* This file should only be included from <avr/io.h>, never directly. */
+
+#ifndef _AVR_IO_H_
+#  error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+#  define _AVR_IOXXX_H_ "iotnx61.h"
+#else
+#  error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif 
+
+#ifndef _AVR_IOTNx61_H_
+#define _AVR_IOTNx61_H_ 1
+
+/* Registers and associated bit numbers */
+
+#define TCCR1E  _SFR_IO8(0x00)
+#define OC1OE0  0
+#define OC1OE1  1
+#define OC1OE2  2
+#define OC1OE3  3
+#define OC1OE4  4
+#define OC1OE5  5
+
+#define DIDR0   _SFR_IO8(0x01)
+#define ADC0D   0
+#define ADC1D   1
+#define ADC2D   2
+#define AREFD   3
+#define ADC3D   4
+#define ADC4D   5
+#define ADC5D   6
+#define ADC6D   7
+
+#define DIDR1   _SFR_IO8(0x02)
+#define ADC7D   4
+#define ADC8D   5
+#define ADC9D   6
+#define ADC10D  7
+
+#define ADCSRB  _SFR_IO8(0x03)
+#define ADTS0   0
+#define ADTS1   1
+#define ADTS2   2
+#define MUX5    3
+#define REFS2   4
+#define IRP     5
+#define GSEL    6
+#define BIN     7
+
+#define ADCW    _SFR_IO16(0x04)
+#ifndef __ASSEMBLER__
+#define ADC     _SFR_IO16(0x04)
+#endif
+
+#define ADCL    _SFR_IO8(0x04)
+#define ADCH    _SFR_IO8(0x05)
+
+#define ADCSRA  _SFR_IO8(0x06)
+#define ADPS0   0
+#define ADPS1   1
+#define ADPS2   2
+#define ADIE    3
+#define ADIF    4
+#define ADATE   5
+#define ADSC    6
+#define ADEN    7
+
+#define ADMUX   _SFR_IO8(0x07)
+#define MUX0    0
+#define MUX1    1
+#define MUX2    2
+#define MUX3    3
+#define MUX4    4
+#define ADLAR   5
+#define REFS0   6
+#define REFS1   7
+
+#define ACSRA   _SFR_IO8(0x08)
+#define ACIS0   0
+#define ACIS1   1
+#define ACME    2
+#define ACIE    3
+#define ACI     4
+#define ACO     5
+#define ACBG    6
+#define ACD     7
+
+#define ACSRB   _SFR_IO8(0x09)
+#define ACM0    0
+#define ACM1    1
+#define ACM2    2
+#define HLEV    6
+#define HSEL    7
+
+#define GPIOR0  _SFR_IO8(0x0A)
+
+#define GPIOR1  _SFR_IO8(0x0B)
+
+#define GPIOR2  _SFR_IO8(0x0C)
+
+#define USICR   _SFR_IO8(0x0D)
+#define USITC   0
+#define USICLK  1
+#define USICS0  2
+#define USICS1  3
+#define USIWM0  4
+#define USIWM1  5
+#define USIOIE  6
+#define USISIE  7
+
+#define USISR   _SFR_IO8(0x0E)
+#define USICNT0 0
+#define USICNT1 1
+#define USICNT2 2
+#define USICNT3 3
+#define USIDC   4
+#define USIPF   5
+#define USIOIF  6
+#define USISIF  7
+
+#define USIDR   _SFR_IO8(0x0F)
+
+#define USIBR   _SFR_IO8(0x10)
+
+#define USIPP   _SFR_IO8(0x11)
+#define USIPOS  0
+
+#define OCR0B   _SFR_IO8(0x12)
+
+#define OCR0A   _SFR_IO8(0x13)
+
+#define TCNT0H  _SFR_IO8(0x14)
+
+#define TCCR0A  _SFR_IO8(0x15)
+#define WGM00   0		/* up to at least datasheet rev. B */
+#define CTC0    0		/* newer revisions; change not mentioned
+				 * in revision history */
+#define ACIC0   3
+#define ICES0   4
+#define ICNC0   5
+#define ICEN0   6
+#define TCW0    7
+
+#define PINB    _SFR_IO8(0x16)
+#define PINB0   0
+#define PINB1   1
+#define PINB2   2
+#define PINB3   3
+#define PINB4   4
+#define PINB5   5
+#define PINB6   6
+#define PINB7   7
+
+#define DDRB    _SFR_IO8(0x17)
+#define DDB0    0
+#define DDB1    1
+#define DDB2    2
+#define DDB3    3
+#define DDB4    4
+#define DDB5    5
+#define DDB6    6
+#define DDB7    7
+
+#define PORTB   _SFR_IO8(0x18)
+#define PB0     0
+#define PB1     1
+#define PB2     2
+#define PB3     3
+#define PB4     4
+#define PB5     5
+#define PB6     6
+#define PB7     7
+
+#define PINA    _SFR_IO8(0x19)
+#define PINA0   0
+#define PINA1   1
+#define PINA2   2
+#define PINA3   3
+#define PINA4   4
+#define PINA5   5
+#define PINA6   6
+#define PINA7   7
+
+#define DDRA    _SFR_IO8(0x1A)
+#define DDA0    0
+#define DDA1    1
+#define DDA2    2
+#define DDA3    3
+#define DDA4    4
+#define DDA5    5
+#define DDA6    6
+#define DDA7    7
+
+#define PORTA   _SFR_IO8(0x1B)
+#define PA0     0
+#define PA1     1
+#define PA2     2
+#define PA3     3
+#define PA4     4
+#define PA5     5
+#define PA6     6
+#define PA7     7
+
+/* EEPROM Control Register */
+#define EECR	_SFR_IO8(0x1C)
+#define EERE    0
+#define EEPE    1
+#define EEMPE   2
+#define EERIE   3
+#define EEPM0   4
+#define EEPM1   5
+
+/* EEPROM Data Register */
+#define EEDR	_SFR_IO8(0x1D)
+
+/* EEPROM Address Register */
+#define EEAR	_SFR_IO16(0x1E)
+#define EEARL	_SFR_IO8(0x1E)
+#define EEARH	_SFR_IO8(0x1F)
+
+#define DWDR    _SFR_IO8(0x20)
+
+#define WDTCR   _SFR_IO8(0x21)
+#define WDP0    0
+#define WDP1    1
+#define WDP2    2
+#define WDE     3
+#define WDCE    4
+#define WDP3    5
+#define WDIE    6
+#define WDIF    7
+
+#define PCMSK1  _SFR_IO8(0x22)
+#define PCINT8  0
+#define PCINT9  1
+#define PCINT10 2
+#define PCINT11 3
+#define PCINT12 4
+#define PCINT13 5
+#define PCINT14 6
+#define PCINT15 7
+
+#define PCMSK0  _SFR_IO8(0x23)
+#define PCINT0  0
+#define PCINT1  1
+#define PCINT2  2
+#define PCINT3  3
+#define PCINT4  4
+#define PCINT5  5
+#define PCINT6  6
+#define PCINT7  7
+
+#define DT1     _SFR_IO8(0x24)
+#define DT1L0   0
+#define DT1L1   1
+#define DT1L2   2
+#define DT1L3   3
+#define DT1H0   4
+#define DT1H1   5
+#define DT1H2   6
+#define DT1H3   7
+
+#define TC1H    _SFR_IO8(0x25)
+#define TC18    0
+#define TC19    1
+
+#define TCCR1D  _SFR_IO8(0x26)
+#define WGM10   0
+#define WGM11   1
+#define FPF1    2
+#define FPAC1   3
+#define FPES1   4
+#define FPNC1   5
+#define FPEN1   6
+#define FPIE1   7
+
+#define TCCR1C  _SFR_IO8(0x27)
+#define PWM1D   0
+#define FOC1D   1
+#define COM1D0  2
+#define COM1D1  3
+#define COM1B0S 4
+#define COM1B1S 5
+#define COM1A0S 6
+#define COM1A1S 7
+
+#define CLKPR   _SFR_IO8(0x28)
+#define CLKPS0  0
+#define CLKPS1  1
+#define CLKPS2  2
+#define CLKPS3  3
+#define CLKPCE  7
+
+#define PLLCSR  _SFR_IO8(0x29)
+#define PLOCK   0
+#define PLLE    1
+#define PCKE    2
+#define LSM     7
+
+#define OCR1D   _SFR_IO8(0x2A)
+
+#define OCR1C   _SFR_IO8(0x2B)
+
+#define OCR1B   _SFR_IO8(0x2C)
+
+#define OCR1A   _SFR_IO8(0x2D)
+
+#define TCNT1   _SFR_IO8(0x2E)
+
+#define TCCR1B  _SFR_IO8(0x2F)
+#define CS10    0
+#define CS11    1
+#define CS12    2
+#define CS13    3
+#define DTPS10  4
+#define DTPS11  5
+#define PSR1    6
+#define PWM1X   7
+
+#define TCCR1A  _SFR_IO8(0x30)
+#define PWM1B   0
+#define PWM1A   1
+#define FOC1B   2
+#define FOC1A   3
+#define COM1B0  4
+#define COM1B1  5
+#define COM1A0  6
+#define COM1A1  7
+
+#define OSCCAL  _SFR_IO8(0x31)
+
+#define TCNT0L  _SFR_IO8(0x32)
+
+#define TCCR0B  _SFR_IO8(0x33)
+#define CS00    0
+#define CS01    1
+#define CS02    2
+#define PSR0    3
+#define TSM     4
+
+#define MCUSR   _SFR_IO8(0x34)
+#define PORF    0
+#define EXTRF   1
+#define BORF    2
+#define WDRF    3
+
+#define MCUCR   _SFR_IO8(0x35)
+#define ISC00   0
+#define ISC01   1
+#define SM0     3
+#define SM1     4
+#define SE      5
+#define PUD     6
+
+#define PRR     _SFR_IO8(0x36)
+#define PRADC   0
+#define PRUSI   1
+#define PRTIM0  2
+#define PRTIM1  3
+
+#define __AVR_HAVE_PRR	((1<<PRADC)|(1<<PRUSI)|(1<<PRTIM0)|(1<<PRTIM1))
+#define __AVR_HAVE_PRR_PRADC
+#define __AVR_HAVE_PRR_PRUSI
+#define __AVR_HAVE_PRR_PRTIM0
+#define __AVR_HAVE_PRR_PRTIM1
+
+#define SPMCSR  _SFR_IO8(0x37)
+#define SPMEN   0
+#define PGERS   1
+#define PGWRT 2
+#define RFLB 3
+#define CTPB 4
+
+#define TIFR    _SFR_IO8(0x38)
+#define ICF0    0
+#define TOV0    1
+#define TOV1    2
+#define OCF0B   3
+#define OCF0A   4
+#define OCF1B   5
+#define OCF1A   6
+#define OCF1D   7
+
+#define TIMSK   _SFR_IO8(0x39)
+#define TICIE0  0
+#define TOIE0   1
+#define TOIE1   2
+#define OCIE0B  3
+#define OCIE0A  4
+#define OCIE1B  5
+#define OCIE1A  6
+#define OCIE1D  7
+
+#define GIFR    _SFR_IO8(0x3A)
+#define PCIF    5
+#define INTF0   6
+#define INTF1   7
+
+#define GIMSK   _SFR_IO8(0x3B)
+#define PCIE0   4
+#define PCIE1   5
+#define INT0    6
+#define INT1    7
+
+/* Reserved [0x3C] */
+
+/* 0x3D..0x3E SP  [defined in <avr/io.h>] */
+/* 0x3F SREG      [defined in <avr/io.h>] */
+
+
+/* Interrupt vectors */
+/* Interrupt vector 0 is the reset vector. */
+/* External Interrupt 0 */
+#define INT0_vect_num			1
+#define INT0_vect	    		_VECTOR(1)
+#define SIG_INTERRUPT0			_VECTOR(1)
+
+/* Pin Change Interrupt */
+#define PCINT_vect_num			2
+#define PCINT_vect		    	_VECTOR(2)
+#define SIG_PIN_CHANGE			_VECTOR(2)
+
+/* Timer/Counter1 Compare Match 1A */
+#define TIMER1_COMPA_vect_num	3
+#define TIMER1_COMPA_vect		_VECTOR(3)
+#define SIG_OUTPUT_COMPARE1A	_VECTOR(3)
+
+/* Timer/Counter1 Compare Match 1B */
+#define TIMER1_COMPB_vect_num	4
+#define TIMER1_COMPB_vect	    _VECTOR(4)
+#define SIG_OUTPUT_COMPARE1B	_VECTOR(4)
+
+/* Timer/Counter1 Overflow */
+#define TIMER1_OVF_vect_num		5
+#define TIMER1_OVF_vect			_VECTOR(5)
+#define SIG_OVERFLOW1			_VECTOR(5)
+
+/* Timer/Counter0 Overflow */
+#define TIMER0_OVF_vect_num 	6
+#define TIMER0_OVF_vect			_VECTOR(6)
+#define SIG_OVERFLOW0			_VECTOR(6)
+
+/* USI Start */
+#define USI_START_vect_num		7
+#define USI_START_vect			_VECTOR(7)
+#define SIG_USI_START			_VECTOR(7)
+
+/* USI Overflow */
+#define USI_OVF_vect_num		8
+#define USI_OVF_vect			_VECTOR(8)
+#define SIG_USI_OVERFLOW		_VECTOR(8)
+
+/* EEPROM Ready */
+#define EE_RDY_vect_num			9
+#define EE_RDY_vect		    	_VECTOR(9)
+#define SIG_EEPROM_READY		_VECTOR(9)
+
+/* Analog Comparator */
+#define ANA_COMP_vect_num   	10
+#define ANA_COMP_vect			_VECTOR(10)
+#define SIG_ANA_COMP			_VECTOR(10)
+#define SIG_COMPARATOR			_VECTOR(10)
+
+/* ADC Conversion Complete */
+#define ADC_vect_num			11
+#define ADC_vect	    		_VECTOR(11)
+#define SIG_ADC			    	_VECTOR(11)
+
+/* Watchdog Time-Out */
+#define WDT_vect_num			12
+#define WDT_vect	    		_VECTOR(12)
+#define SIG_WDT			    	_VECTOR(12)
+
+/* External Interrupt 1 */
+#define INT1_vect_num			13
+#define INT1_vect	    		_VECTOR(13)
+#define SIG_INTERRUPT1			_VECTOR(13)
+
+/* Timer/Counter0 Compare Match A */
+#define TIMER0_COMPA_vect_num		14
+#define TIMER0_COMPA_vect	    	_VECTOR(14)
+#define SIG_OUTPUT_COMPARE0A		_VECTOR(14)
+
+/* Timer/Counter0 Compare Match B */
+#define TIMER0_COMPB_vect_num		15
+#define TIMER0_COMPB_vect	    	_VECTOR(15)
+#define SIG_OUTPUT_COMPARE0B		_VECTOR(15)
+
+/* ADC Conversion Complete */
+#define TIMER0_CAPT_vect_num		16
+#define TIMER0_CAPT_vect	    	_VECTOR(16)
+#define SIG_INPUT_CAPTURE0		    _VECTOR(16)
+
+/* Timer/Counter1 Compare Match D */
+#define TIMER1_COMPD_vect_num       17
+#define TIMER1_COMPD_vect		    _VECTOR(17)
+#define SIG_OUTPUT_COMPARE0D		_VECTOR(17)
+
+/* Timer/Counter1 Fault Protection */
+#define FAULT_PROTECTION_vect_num	18
+#define FAULT_PROTECTION_vect		_VECTOR(18)
+
+#define _VECTORS_SIZE 38
+
+#endif  /* _AVR_IOTNx61_H_ */

hardware/tools/avr/avr/include/avr/iousb1286.h

@@ -0,0 +1,101 @@
+/* Copyright (c) 2006 Anatoly Sokolov 
+   All rights reserved.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+
+   * Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+
+   * Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in
+     the documentation and/or other materials provided with the
+     distribution.
+
+   * Neither the name of the copyright holders nor the names of
+     contributors may be used to endorse or promote products derived
+     from this software without specific prior written permission.
+
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+  POSSIBILITY OF SUCH DAMAGE. */
+
+/* $Id: iousb1286.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */
+
+/* avr/iousb1286.h - definitions for AT90USB1286 */
+
+#ifndef _AVR_AT90USB1286_H_
+#define _AVR_AT90USB1286_H_ 1
+
+#include <avr/iousbxx6_7.h>
+
+/* Constants */
+#define SPM_PAGESIZE 256
+#define RAMSTART     0x100
+#define RAMEND       0x20FF
+#define XRAMEND      0xFFFF
+#define E2END        0xFFF
+#define E2PAGESIZE   8
+#define FLASHEND     0x1FFFF
+
+
+/* Fuses */
+#define FUSE_MEMORY_SIZE 3
+
+/* Low Fuse Byte */
+#define FUSE_CKSEL0      (unsigned char)~_BV(0)
+#define FUSE_CKSEL1      (unsigned char)~_BV(1)
+#define FUSE_CKSEL2      (unsigned char)~_BV(2)
+#define FUSE_CKSEL3      (unsigned char)~_BV(3)
+#define FUSE_SUT0        (unsigned char)~_BV(4)
+#define FUSE_SUT1        (unsigned char)~_BV(5)
+#define FUSE_CKOUT       (unsigned char)~_BV(6)
+#define FUSE_CKDIV8      (unsigned char)~_BV(7)
+#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
+
+/* High Fuse Byte */
+#define FUSE_BOOTRST     (unsigned char)~_BV(0)
+#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
+#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
+#define FUSE_EESAVE      (unsigned char)~_BV(3)
+#define FUSE_WDTON       (unsigned char)~_BV(4)
+#define FUSE_SPIEN       (unsigned char)~_BV(5)
+#define FUSE_JTAGEN      (unsigned char)~_BV(6)
+#define FUSE_OCDEN       (unsigned char)~_BV(7)
+#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
+
+/* Extended Fuse Byte */
+#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
+#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
+#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
+#define FUSE_HWBE        (unsigned char)~_BV(3)
+#define EFUSE_DEFAULT (FUSE_BODLEVEL2 & FUSE_HWBE)
+
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+#define __BOOT_LOCK_BITS_0_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST 
+
+
+/* Signature */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x97
+#define SIGNATURE_2 0x82
+
+#define SLEEP_MODE_IDLE (0x00<<1)
+#define SLEEP_MODE_ADC (0x01<<1)
+#define SLEEP_MODE_PWR_DOWN (0x02<<1)
+#define SLEEP_MODE_PWR_SAVE (0x03<<1)
+#define SLEEP_MODE_STANDBY (0x06<<1)
+#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
+
+#endif /* _AVR_AT90USB1286_H_ */

hardware/tools/avr/avr/include/avr/iousb1287.h

@@ -0,0 +1,101 @@
+/* Copyright (c) 2006 Anatoly Sokolov 
+   All rights reserved.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+
+   * Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+
+   * Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in
+     the documentation and/or other materials provided with the
+     distribution.
+
+   * Neither the name of the copyright holders nor the names of
+     contributors may be used to endorse or promote products derived
+     from this software without specific prior written permission.
+
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+  POSSIBILITY OF SUCH DAMAGE. */
+
+/* $Id: iousb1287.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */
+
+/* avr/iousb1287.h - definitions for AT90USB1287 */
+
+#ifndef _AVR_AT90USB1287_H_
+#define _AVR_AT90USB1287_H_ 1
+
+#include <avr/iousbxx6_7.h>
+
+/* Constants */
+#define SPM_PAGESIZE 256
+#define RAMSTART     0x100
+#define RAMEND       0x20FF
+#define XRAMEND      0xFFFF
+#define E2END        0xFFF
+#define E2PAGESIZE   8
+#define FLASHEND     0x1FFFF
+
+
+/* Fuses */
+#define FUSE_MEMORY_SIZE 3
+
+/* Low Fuse Byte */
+#define FUSE_CKSEL0      (unsigned char)~_BV(0)
+#define FUSE_CKSEL1      (unsigned char)~_BV(1)
+#define FUSE_CKSEL2      (unsigned char)~_BV(2)
+#define FUSE_CKSEL3      (unsigned char)~_BV(3)
+#define FUSE_SUT0        (unsigned char)~_BV(4)
+#define FUSE_SUT1        (unsigned char)~_BV(5)
+#define FUSE_CKOUT       (unsigned char)~_BV(6)
+#define FUSE_CKDIV8      (unsigned char)~_BV(7)
+#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
+
+/* High Fuse Byte */
+#define FUSE_BOOTRST     (unsigned char)~_BV(0)
+#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
+#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
+#define FUSE_EESAVE      (unsigned char)~_BV(3)
+#define FUSE_WDTON       (unsigned char)~_BV(4)
+#define FUSE_SPIEN       (unsigned char)~_BV(5)
+#define FUSE_JTAGEN      (unsigned char)~_BV(6)
+#define FUSE_OCDEN       (unsigned char)~_BV(7)
+#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
+
+/* Extended Fuse Byte */
+#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
+#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
+#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
+#define FUSE_HWBE        (unsigned char)~_BV(3)
+#define EFUSE_DEFAULT (FUSE_BODLEVEL2 & FUSE_HWBE)
+
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+#define __BOOT_LOCK_BITS_0_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST 
+
+
+/* Signature */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x97
+#define SIGNATURE_2 0x82
+
+#define SLEEP_MODE_IDLE (0x00<<1)
+#define SLEEP_MODE_ADC (0x01<<1)
+#define SLEEP_MODE_PWR_DOWN (0x02<<1)
+#define SLEEP_MODE_PWR_SAVE (0x03<<1)
+#define SLEEP_MODE_STANDBY (0x06<<1)
+#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
+
+#endif /* _AVR_AT90USB1287_H_ */

hardware/tools/avr/avr/include/avr/iousb162.h

@@ -0,0 +1,101 @@
+/* Copyright (c) 2007 Anatoly Sokolov
+   Copyright (c) 2010 Atmel Corporation
+   All rights reserved.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+
+   * Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+
+   * Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in
+     the documentation and/or other materials provided with the
+     distribution.
+
+   * Neither the name of the copyright holders nor the names of
+     contributors may be used to endorse or promote products derived
+     from this software without specific prior written permission.
+
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+  POSSIBILITY OF SUCH DAMAGE. */
+
+/* $Id: iousb162.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */
+
+/* avr/iousb162.h - definitions for AT90USB162 */
+
+#ifndef _AVR_AT90USB162_H_
+#define _AVR_AT90USB162_H_ 1
+
+#include <avr/iousbxx2.h>
+
+/* Constants */
+#define SPM_PAGESIZE 128
+#define RAMSTART     0x100
+#define RAMEND       0x2FF
+#define XRAMEND      RAMEND
+#define E2END        0x1FF
+#define E2PAGESIZE   4
+#define FLASHEND     0x3FFF
+
+
+/* Fuses */
+#define FUSE_MEMORY_SIZE 3
+
+/* Low Fuse Byte */
+#define FUSE_CKSEL0      (unsigned char)~_BV(0)
+#define FUSE_CKSEL1      (unsigned char)~_BV(1)
+#define FUSE_CKSEL2      (unsigned char)~_BV(2)
+#define FUSE_CKSEL3      (unsigned char)~_BV(3)
+#define FUSE_SUT0        (unsigned char)~_BV(4)
+#define FUSE_SUT1        (unsigned char)~_BV(5)
+#define FUSE_CKOUT       (unsigned char)~_BV(6)
+#define FUSE_CKDIV8      (unsigned char)~_BV(7)
+#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_SUT1 & FUSE_CKDIV8)
+
+/* High Fuse Byte */
+#define FUSE_BOOTRST     (unsigned char)~_BV(0)
+#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
+#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
+#define FUSE_EESAVE      (unsigned char)~_BV(3)
+#define FUSE_WDTON       (unsigned char)~_BV(4)
+#define FUSE_SPIEN       (unsigned char)~_BV(5)
+#define FUSE_RSTDSBL     (unsigned char)~_BV(6)
+#define FUSE_DWEN        (unsigned char)~_BV(7)
+#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN)
+
+/* Extended Fuse Byte */
+#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
+#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
+#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
+#define FUSE_HWBE        (unsigned char)~_BV(3)
+#define EFUSE_DEFAULT (FUSE_BODLEVEL0 & FUSE_BODLEVEL1 & FUSE_HWBE)
+
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+#define __BOOT_LOCK_BITS_0_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST 
+
+
+/* Signature */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x94
+#define SIGNATURE_2 0x82
+
+#define SLEEP_MODE_IDLE (0x00<<1)
+#define SLEEP_MODE_PWR_DOWN (0x02<<1)
+#define SLEEP_MODE_PWR_SAVE (0x03<<1)
+#define SLEEP_MODE_STANDBY (0x06<<1)
+#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
+
+#endif /* _AVR_AT90USB162_H_ */

hardware/tools/avr/avr/include/avr/iousb646.h

@@ -0,0 +1,102 @@
+/* Copyright (c) 2006 Anatoly Sokolov
+   Copyright (c) 2010 Atmel Corporation
+   All rights reserved.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+
+   * Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+
+   * Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in
+     the documentation and/or other materials provided with the
+     distribution.
+
+   * Neither the name of the copyright holders nor the names of
+     contributors may be used to endorse or promote products derived
+     from this software without specific prior written permission.
+
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+  POSSIBILITY OF SUCH DAMAGE. */
+
+/* $Id: iousb646.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */
+
+/* avr/iousb646.h - definitions for AT90USB646 */
+
+#ifndef _AVR_AT90USB646_H_
+#define _AVR_AT90USB646_H_ 1
+
+#include <avr/iousbxx6_7.h>
+
+/* Constants */
+#define SPM_PAGESIZE 256
+#define RAMSTART     0x100
+#define RAMEND       0x10FF
+#define XRAMEND      0xFFFF
+#define E2END        0x7FF
+#define E2PAGESIZE   8
+#define FLASHEND     0xFFFF
+
+
+/* Fuses */
+#define FUSE_MEMORY_SIZE 3
+
+/* Low Fuse Byte */
+#define FUSE_CKSEL0      (unsigned char)~_BV(0)
+#define FUSE_CKSEL1      (unsigned char)~_BV(1)
+#define FUSE_CKSEL2      (unsigned char)~_BV(2)
+#define FUSE_CKSEL3      (unsigned char)~_BV(3)
+#define FUSE_SUT0        (unsigned char)~_BV(4)
+#define FUSE_SUT1        (unsigned char)~_BV(5)
+#define FUSE_CKOUT       (unsigned char)~_BV(6)
+#define FUSE_CKDIV8      (unsigned char)~_BV(7)
+#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
+
+/* High Fuse Byte */
+#define FUSE_BOOTRST     (unsigned char)~_BV(0)
+#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
+#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
+#define FUSE_EESAVE      (unsigned char)~_BV(3)
+#define FUSE_WDTON       (unsigned char)~_BV(4)
+#define FUSE_SPIEN       (unsigned char)~_BV(5)
+#define FUSE_JTAGEN      (unsigned char)~_BV(6)
+#define FUSE_OCDEN       (unsigned char)~_BV(7)
+#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
+
+/* Extended Fuse Byte */
+#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
+#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
+#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
+#define FUSE_HWBE        (unsigned char)~_BV(3)
+#define EFUSE_DEFAULT (FUSE_BODLEVEL2 & FUSE_HWBE)
+
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+#define __BOOT_LOCK_BITS_0_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST 
+
+
+/* Signature */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x96
+#define SIGNATURE_2 0x82
+
+#define SLEEP_MODE_IDLE (0x00<<1)
+#define SLEEP_MODE_ADC (0x01<<1)
+#define SLEEP_MODE_PWR_DOWN (0x02<<1)
+#define SLEEP_MODE_PWR_SAVE (0x03<<1)
+#define SLEEP_MODE_STANDBY (0x06<<1)
+#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
+
+#endif /* _AVR_AT90USB646_H_ */

hardware/tools/avr/avr/include/avr/iousb647.h

@@ -0,0 +1,102 @@
+/* Copyright (c) 2006 Anatoly Sokolov
+   Copyright (c) 2010 Atmel Corporation 
+   All rights reserved.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+
+   * Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+
+   * Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in
+     the documentation and/or other materials provided with the
+     distribution.
+
+   * Neither the name of the copyright holders nor the names of
+     contributors may be used to endorse or promote products derived
+     from this software without specific prior written permission.
+
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+  POSSIBILITY OF SUCH DAMAGE. */
+
+/* $Id: iousb647.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */
+
+/* avr/iousb647.h - definitions for AT90USB647 */
+
+#ifndef _AVR_AT90USB647_H_
+#define _AVR_AT90USB647_H_ 1
+
+#include <avr/iousbxx6_7.h>
+
+/* Constants */
+#define SPM_PAGESIZE 256
+#define RAMSTART     0x100
+#define RAMEND       0x10FF
+#define XRAMEND      0xFFFF
+#define E2END        0x7FF
+#define E2PAGESIZE   8
+#define FLASHEND     0xFFFF
+
+
+/* Fuses */
+#define FUSE_MEMORY_SIZE 3
+
+/* Low Fuse Byte */
+#define FUSE_CKSEL0      (unsigned char)~_BV(0)
+#define FUSE_CKSEL1      (unsigned char)~_BV(1)
+#define FUSE_CKSEL2      (unsigned char)~_BV(2)
+#define FUSE_CKSEL3      (unsigned char)~_BV(3)
+#define FUSE_SUT0        (unsigned char)~_BV(4)
+#define FUSE_SUT1        (unsigned char)~_BV(5)
+#define FUSE_CKOUT       (unsigned char)~_BV(6)
+#define FUSE_CKDIV8      (unsigned char)~_BV(7)
+#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
+
+/* High Fuse Byte */
+#define FUSE_BOOTRST     (unsigned char)~_BV(0)
+#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
+#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
+#define FUSE_EESAVE      (unsigned char)~_BV(3)
+#define FUSE_WDTON       (unsigned char)~_BV(4)
+#define FUSE_SPIEN       (unsigned char)~_BV(5)
+#define FUSE_JTAGEN      (unsigned char)~_BV(6)
+#define FUSE_OCDEN       (unsigned char)~_BV(7)
+#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
+
+/* Extended Fuse Byte */
+#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
+#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
+#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
+#define FUSE_HWBE        (unsigned char)~_BV(3)
+#define EFUSE_DEFAULT (FUSE_BODLEVEL2 & FUSE_HWBE)
+
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+#define __BOOT_LOCK_BITS_0_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST 
+
+
+/* Signature */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x96
+#define SIGNATURE_2 0x82
+
+#define SLEEP_MODE_IDLE (0x00<<1)
+#define SLEEP_MODE_ADC (0x01<<1)
+#define SLEEP_MODE_PWR_DOWN (0x02<<1)
+#define SLEEP_MODE_PWR_SAVE (0x03<<1)
+#define SLEEP_MODE_STANDBY (0x06<<1)
+#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
+
+#endif /* _AVR_AT90USB647_H_ */

hardware/tools/avr/avr/include/avr/iousb82.h

@@ -0,0 +1,95 @@
+/* Copyright (c) 2007 Anatoly Sokolov
+   Copyright (c) 2010 Atmel Corporation
+   All rights reserved.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+
+   * Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+
+   * Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in
+     the documentation and/or other materials provided with the
+     distribution.
+
+   * Neither the name of the copyright holders nor the names of
+     contributors may be used to endorse or promote products derived
+     from this software without specific prior written permission.
+
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+  POSSIBILITY OF SUCH DAMAGE. */
+
+/* $Id: iousb82.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */
+
+/* avr/iousb82.h - definitions for AT90USB82 */
+
+#ifndef _AVR_AT90USB82_H_
+#define _AVR_AT90USB82_H_ 1
+
+#include <avr/iousbxx2.h>
+
+/* Constants */
+#define SPM_PAGESIZE 128
+#define RAMSTART     0x100
+#define RAMEND       0x2FF
+#define XRAMEND      RAMEND
+#define E2END        0x1FF
+#define E2PAGESIZE   4
+#define FLASHEND     0x1FFF
+
+
+/* Fuses */
+#define FUSE_MEMORY_SIZE 3
+
+/* Low Fuse Byte */
+#define FUSE_CKSEL0      (unsigned char)~_BV(0)
+#define FUSE_CKSEL1      (unsigned char)~_BV(1)
+#define FUSE_CKSEL2      (unsigned char)~_BV(2)
+#define FUSE_CKSEL3      (unsigned char)~_BV(3)
+#define FUSE_SUT0        (unsigned char)~_BV(4)
+#define FUSE_SUT1        (unsigned char)~_BV(5)
+#define FUSE_CKOUT       (unsigned char)~_BV(6)
+#define FUSE_CKDIV8      (unsigned char)~_BV(7)
+#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_SUT1 & FUSE_CKDIV8)
+
+/* High Fuse Byte */
+#define FUSE_BOOTRST     (unsigned char)~_BV(0)
+#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
+#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
+#define FUSE_EESAVE      (unsigned char)~_BV(3)
+#define FUSE_WDTON       (unsigned char)~_BV(4)
+#define FUSE_SPIEN       (unsigned char)~_BV(5)
+#define FUSE_RSTDSBL     (unsigned char)~_BV(6)
+#define FUSE_DWEN        (unsigned char)~_BV(7)
+#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN)
+
+/* Extended Fuse Byte */
+#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
+#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
+#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
+#define FUSE_HWBE        (unsigned char)~_BV(3)
+#define EFUSE_DEFAULT (FUSE_BODLEVEL0 & FUSE_BODLEVEL1 & FUSE_HWBE)
+
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+#define __BOOT_LOCK_BITS_0_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST 
+
+#define SLEEP_MODE_IDLE (0x00<<1)
+#define SLEEP_MODE_PWR_DOWN (0x02<<1)
+#define SLEEP_MODE_PWR_SAVE (0x03<<1)
+#define SLEEP_MODE_STANDBY (0x06<<1)
+#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
+
+#endif /* _AVR_AT90USB82_H_ */

hardware/tools/avr/avr/include/avr/iousbxx2.h

@@ -0,0 +1,807 @@
+/* Copyright (c) 2007 Anatoly Sokolov 
+   All rights reserved.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+
+   * Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+
+   * Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in
+     the documentation and/or other materials provided with the
+     distribution.
+
+   * Neither the name of the copyright holders nor the names of
+     contributors may be used to endorse or promote products derived
+     from this software without specific prior written permission.
+
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+  POSSIBILITY OF SUCH DAMAGE. */
+
+/* $Id: iousbxx2.h 2246 2011-05-14 20:02:02Z joerg_wunsch $ */
+
+/* iousbxx2.h - definitions for AT90USB82 and AT90USB162.  */
+
+#ifndef _AVR_IOUSBXX2_H_
+#define _AVR_IOUSBXX2_H_ 1
+
+/* This file should only be included from <avr/io.h>, never directly. */
+
+#ifndef _AVR_IO_H_
+#  error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+#  define _AVR_IOXXX_H_ "iousbxx2.h"
+#else
+#  error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif 
+
+/* Registers and associated bit numbers */
+
+/* Reserved [0x00..0x02] */
+
+#define PINB    _SFR_IO8(0X03)
+#define PINB7   7
+#define PINB6   6
+#define PINB5   5
+#define PINB4   4
+#define PINB3   3
+#define PINB2   2
+#define PINB1   1
+#define PINB0   0
+
+#define DDRB    _SFR_IO8(0x04)
+#define DDB7    7
+#define DDB6    6
+#define DDB5    5
+#define DDB4    4
+#define DDB3    3
+#define DDB2    2
+#define DDB1    1
+#define DDB0    0
+
+#define PORTB   _SFR_IO8(0x05)
+#define PB7     7
+#define PB6     6
+#define PB5     5
+#define PB4     4
+#define PB3     3
+#define PB2     2
+#define PB1     1
+#define PB0     0
+
+#define PINC    _SFR_IO8(0x06)
+#define PINC7   7
+#define PINC6   6
+#define PINC5   5
+#define PINC4   4
+#define PINC2   2
+#define PINC1   1
+#define PINC0   0
+
+#define DDRC    _SFR_IO8(0x07)
+#define DDC7    7
+#define DDC6    6
+#define DDC5    5
+#define DDC4    4
+#define DDC2    2
+#define DDC1    1
+#define DDC0    0
+
+#define PORTC   _SFR_IO8(0x08)
+#define PC7     7
+#define PC6     6
+#define PC5     5
+#define PC4     4
+#define PC2     2
+#define PC1     1
+#define PC0     0
+
+#define PIND    _SFR_IO8(0x09)
+#define PIND7   7
+#define PIND6   6
+#define PIND5   5
+#define PIND4   4
+#define PIND3   3
+#define PIND2   2
+#define PIND1   1
+#define PIND0   0
+
+#define DDRD    _SFR_IO8(0x0A)
+#define DDD7    7
+#define DDD6    6
+#define DDD5    5
+#define DDD4    4
+#define DDD3    3
+#define DDD2    2
+#define DDD1    1
+#define DDD0    0
+
+#define PORTD   _SFR_IO8(0x0B)
+#define PD7     7
+#define PD6     6
+#define PD5     5
+#define PD4     4
+#define PD3     3
+#define PD2     2
+#define PD1     1
+#define PD0     0
+
+/* Reserved [0xC..0x14] */
+
+#define TIFR0   _SFR_IO8(0x15)
+#define OCF0B   2
+#define OCF0A   1
+#define TOV0    0
+
+#define TIFR1   _SFR_IO8(0x16)
+#define ICF1    5
+#define OCF1C   3
+#define OCF1B   2
+#define OCF1A   1
+#define TOV1    0
+
+/* Reserved [0x17..0x1A] */
+
+#define PCIFR   _SFR_IO8(0x1B)
+#define PCIF1   1
+#define PCIF0   0
+
+#define EIFR    _SFR_IO8(0x1C)
+#define INTF7   7
+#define INTF6   6
+#define INTF5   5
+#define INTF4   4
+#define INTF3   3
+#define INTF2   2
+#define INTF1   1
+#define INTF0   0
+
+#define EIMSK   _SFR_IO8(0x1D)
+#define INT7    7
+#define INT6    6
+#define INT5    5
+#define INT4    4
+#define INT3    3
+#define INT2    2
+#define INT1    1 
+#define INT0    0
+
+#define GPIOR0  _SFR_IO8(0x1E)
+
+#define EECR    _SFR_IO8(0x1F)
+#define EEPM1   5
+#define EEPM0   4
+#define EERIE   3
+#define EEMPE   2
+#define EEPE    1
+#define EERE    0
+
+#define EEDR    _SFR_IO8(0x20)
+
+#define EEAR    _SFR_IO16(0x21)
+#define EEARL   _SFR_IO8(0x21)
+#define EEARH   _SFR_IO8(0x22)
+
+/* 6-char sequence denoting where to find the EEPROM registers in memory space.
+   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
+   subroutines.
+   First two letters:  EECR address.
+   Second two letters: EEDR address.
+   Last two letters:   EEAR address.  */
+#define __EEPROM_REG_LOCATIONS__ 1F2021
+
+#define GTCCR   _SFR_IO8(0x23)
+#define TSM     7
+#define PSRASY  1
+#define PSRSYNC 0
+
+#define TCCR0A  _SFR_IO8(0x24)
+#define COM0A1  7
+#define COM0A0  6
+#define COM0B1  5
+#define COM0B0  4
+#define WGM01   1
+#define WGM00   0
+
+#define TCCR0B  _SFR_IO8(0x25)
+#define FOC0A   7
+#define FOC0B   6
+#define WGM02   3
+#define CS02    2
+#define CS01    1
+#define CS00    0
+
+#define TCNT0   _SFR_IO8(0X26)
+
+#define OCR0A   _SFR_IO8(0x27)
+
+#define OCR0B   _SFR_IO8(0X28)
+
+#define PLLCSR  _SFR_IO8(0x29)
+#define PLLP2   4
+#define PLLP1   3
+#define PLLP0   2
+#define PLLE    1
+#define PLOCK   0
+
+#define GPIOR1  _SFR_IO8(0x2A)
+
+#define GPIOR2  _SFR_IO8(0x2B)
+
+#define SPCR    _SFR_IO8(0x2C)
+#define SPIE    7
+#define SPE     6
+#define DORD    5
+#define MSTR    4
+#define CPOL    3
+#define CPHA    2
+#define SPR1    1
+#define SPR0    0
+
+#define SPSR    _SFR_IO8(0x2D)
+#define SPIF    7
+#define WCOL    6
+#define SPI2X   0
+
+#define SPDR    _SFR_IO8(0x2E)
+
+/* Reserved [0x2F] */
+
+#define ACSR    _SFR_IO8(0x30)
+#define ACD     7
+#define ACBG    6
+#define ACO     5
+#define ACI     4
+#define ACIE    3
+#define ACIC    2
+#define ACIS1   1
+#define ACIS0   0
+
+#define DWDR    _SFR_IO8(0x31)
+#define IDRD    7
+
+/* Reserved [0x32] */
+
+#define SMCR    _SFR_IO8(0x33)
+#define SM2     3
+#define SM1     2
+#define SM0     1
+#define SE      0
+
+#define MCUSR   _SFR_IO8(0x34)
+#define USBRF   5
+#define WDRF    3
+#define BORF    2
+#define EXTRF   1
+#define PORF    0
+
+#define MCUCR   _SFR_IO8(0x35)
+#define PUD     4
+#define IVSEL   1
+#define IVCE    0
+
+/* Reserved [0x36] */
+
+#define SPMCSR  _SFR_IO8(0x37)
+#define SPMIE   7
+#define RWWSB   6
+#define SIGRD   5
+#define RWWSRE  4
+#define BLBSET  3
+#define PGWRT   2
+#define PGERS   1
+#define SPMEN   0
+
+/* Reserved [0x38..0x3C] */
+
+/* SP [0x3D..0x3E] */
+/* SREG [0x3F] */
+
+#define WDTCSR  _SFR_MEM8(0x60)
+#define WDIF    7
+#define WDIE    6
+#define WDP3    5
+#define WDCE    4
+#define WDE     3
+#define WDP2    2
+#define WDP1    1
+#define WDP0    0
+
+#define CLKPR   _SFR_MEM8(0x61)
+#define CLKPCE  7
+#define CLKPS3  3
+#define CLKPS2  2
+#define CLKPS1  1
+#define CLKPS0  0
+
+#define WDTCKD  _SFR_MEM8(0x62)
+#define WDEWIF  3
+#define WDEWIE  2
+#define WCLKD1  1
+#define WCLKD0  0
+
+#define REGCR   _SFR_MEM8(0x63)
+#define REGDIS  0
+
+#define PRR0    _SFR_MEM8(0x64)
+#define PRTIM0  5
+#define PRTIM1  3
+#define PRSPI   2
+
+#define __AVR_HAVE_PRR0	((1<<PRSPI)|(1<<PRTIM1)|(1<<PRTIM0))
+#define __AVR_HAVE_PRR0_PRSPI
+#define __AVR_HAVE_PRR0_PRTIM1
+#define __AVR_HAVE_PRR0_PRTIM0
+
+#define PRR1    _SFR_MEM8(0x65)
+#define PRUSB   7
+#define PRUSART1 0
+
+#define __AVR_HAVE_PRR1	((1<<PRUSART1)|(1<<PRUSB))
+#define __AVR_HAVE_PRR1_PRUSART1
+#define __AVR_HAVE_PRR1_PRUSB
+
+#define OSCCAL  _SFR_MEM8(0x66)
+
+/* Reserved [0x67] */
+
+#define PCICR   _SFR_MEM8(0x68)
+#define PCIE1   1
+#define PCIE0   0
+
+#define EICRA   _SFR_MEM8(0x69)
+#define ISC31   7
+#define ISC30   6
+#define ISC21   5
+#define ISC20   4
+#define ISC11   3
+#define ISC10   2
+#define ISC01   1
+#define ISC00   0
+
+#define EICRB   _SFR_MEM8(0x6A)
+#define ISC71   7
+#define ISC70   6
+#define ISC61   5
+#define ISC60   4
+#define ISC51   3
+#define ISC50   2
+#define ISC41   1
+#define ISC40   0
+
+#define PCMSK0  _SFR_MEM8(0x6B)
+#define PCINT7  7
+#define PCINT6  6
+#define PCINT5  5
+#define PCINT4  4
+#define PCINT3  3
+#define PCINT2  2
+#define PCINT1  1
+#define PCINT0  0
+
+#define PCMSK1  _SFR_MEM8(0x6C)
+#define PCINT12 4
+#define PCINT11 3
+#define PCINT10 2
+#define PCINT9  1
+#define PCINT8  0
+
+/* Reserved [0x6D] */
+
+#define TIMSK0  _SFR_MEM8(0x6E)
+#define OCIE0B  2
+#define OCIE0A  1
+#define TOIE0   0
+
+#define TIMSK1  _SFR_MEM8(0x6F)
+#define ICIE1   5
+#define OCIE1C  3
+#define OCIE1B  2
+#define OCIE1A  1
+#define TOIE1   0
+
+/* Reserved [0x70..0x7F] */
+
+#define TCCR1A  _SFR_MEM8(0x80)
+#define COM1A1  7
+#define COM1A0  6
+#define COM1B1  5
+#define COM1B0  4
+#define COM1C1  3
+#define COM1C0  2
+#define WGM11   1
+#define WGM10   0
+
+#define TCCR1B  _SFR_MEM8(0x81)
+#define ICNC1   7
+#define ICES1   6
+#define WGM13   4
+#define WGM12   3
+#define CS12    2
+#define CS11    1
+#define CS10    0
+
+#define TCCR1C  _SFR_MEM8(0x82)
+#define FOC1A   7
+#define FOC1B   6
+#define FOC1C   5
+
+/* Reserved [0x83] */
+
+/* Combine TCNT1L and TCNT1H */
+#define TCNT1   _SFR_MEM16(0x84)
+
+#define TCNT1L  _SFR_MEM8(0x84)
+#define TCNT1H  _SFR_MEM8(0x85)
+
+/* Combine ICR1L and ICR1H */
+#define ICR1    _SFR_MEM16(0x86)
+
+#define ICR1L   _SFR_MEM8(0x86)
+#define ICR1H   _SFR_MEM8(0x87)
+
+/* Combine OCR1AL and OCR1AH */
+#define OCR1A   _SFR_MEM16(0x88)
+
+#define OCR1AL  _SFR_MEM8(0x88)
+#define OCR1AH  _SFR_MEM8(0x89)
+
+/* Combine OCR1BL and OCR1BH */
+#define OCR1B   _SFR_MEM16(0x8A)
+
+#define OCR1BL  _SFR_MEM8(0x8A)
+#define OCR1BH  _SFR_MEM8(0x8B)
+
+/* Combine OCR1CL and OCR1CH */
+#define OCR1C   _SFR_MEM16(0x8C)
+
+#define OCR1CL  _SFR_MEM8(0x8C)
+#define OCR1CH  _SFR_MEM8(0x8D)
+
+/* Reserved [0x8E..0xC7] */
+
+#define UCSR1A  _SFR_MEM8(0xC8)
+#define RXC1    7
+#define TXC1    6
+#define UDRE1   5
+#define FE1     4
+#define DOR1    3
+#define UPE1    2
+#define U2X1    1
+#define MPCM1   0
+
+#define UCSR1B  _SFR_MEM8(0XC9)
+#define RXCIE1  7
+#define TXCIE1  6
+#define UDRIE1  5
+#define RXEN1   4
+#define TXEN1   3
+#define UCSZ12  2
+#define RXB81   1
+#define TXB81   0
+
+#define UCSR1C  _SFR_MEM8(0xCA)
+#define UMSEL11 7
+#define UMSEL10 6
+#define UPM11   5
+#define UPM10   4
+#define USBS1   3
+#define UCSZ11  2
+#define UCSZ10  1
+#define UCPOL1  0
+
+#define UCSR1D  _SFR_MEM8(0xCB)
+#define CTSEN   1
+#define RTSEN   0
+
+/* Combine UBRR1L and UBRR1H */
+#define UBRR1   _SFR_MEM16(0xCC)
+
+#define UBRR1L  _SFR_MEM8(0xCC)
+#define UBRR1H  _SFR_MEM8(0xCD)
+
+#define UDR1    _SFR_MEM8(0XCE)
+
+/* Reserved [0xCF] */
+
+#define CKSEL0  _SFR_MEM8(0XD0)	/* old name; up to AVR Studio v 4.13 */
+#define CLKSEL0 _SFR_MEM8(0XD0)	/* since AVR Studio v 4.14 */
+#define RCSUT1  7
+#define RCSUT0  6
+#define EXSUT1  5
+#define EXSUT0  4
+#define RCE     3
+#define EXTE    2
+#define CLKS    0
+
+#define CKSEL1  _SFR_MEM8(0XD1)	/* old name */
+#define CLKSEL1 _SFR_MEM8(0XD1)
+#define RCCKSEL3 7
+#define RCCKSEL2 6
+#define RCCKSEL1 5
+#define RCCKSEL0 4
+#define EXCKSEL3 3
+#define EXCKSEL2 2
+#define EXCKSEL1 1
+#define EXCKSEL0 0
+
+#define CKSTA   _SFR_MEM8(0XD2)	/* old name */
+#define CLKSTA  _SFR_MEM8(0XD2)
+#define RCON    1
+#define EXTON   0
+
+/* Reserved [0xD3..0xD7] */
+
+#define USBCON  _SFR_MEM8(0XD8)
+#define USBE    7
+#define FRZCLK  5
+
+/* Reserved [0xD9..0xDA] */
+
+/* Combine UDPADDL and UDPADDH */
+#define UDPADD  _SFR_MEM16(0xDB)
+
+#define UDPADDL _SFR_MEM8(0xDB)
+#define UDPADDH _SFR_MEM8(0xDC)
+#define DPACC   7
+
+/* Reserved [0xDD..0xDF] */
+
+#define UDCON   _SFR_MEM8(0XE0)
+#define RSTCPU  2
+#define RMWKUP  1
+#define DETACH  0
+
+#define UDINT   _SFR_MEM8(0XE1)
+#define UPRSMI  6
+#define EORSMI  5
+#define WAKEUPI 4
+#define EORSTI  3
+#define SOFI    2
+#define SUSPI   0
+
+#define UDIEN   _SFR_MEM8(0XE2)
+#define UPRSME  6
+#define EORSME  5
+#define WAKEUPE 4
+#define EORSTE  3
+#define SOFE    2
+#define SUSPE   0
+
+#define UDADDR  _SFR_MEM8(0XE3)
+#define ADDEN   7
+
+/* Combine UDFNUML and UDFNUMH */
+#define UDFNUM  _SFR_MEM16(0xE4)
+
+#define UDFNUML _SFR_MEM8(0xE4)
+#define UDFNUMH _SFR_MEM8(0xE5)
+
+#define UDMFN   _SFR_MEM8(0XE6)
+#define FNCERR  4
+
+/* Reserved [0xE7] */
+
+#define UEINTX  _SFR_MEM8(0XE8)
+#define FIFOCON 7
+#define NAKINI  6
+#define RWAL    5
+#define NAKOUTI 4
+#define RXSTPI  3
+#define RXOUTI  2
+#define STALLEDI 1
+#define TXINI   0
+
+#define UENUM   _SFR_MEM8(0XE9)
+#define EPNUM2  2
+#define EPNUM1  1
+#define EPNUM0  0
+
+#define UERST   _SFR_MEM8(0XEA)
+#define EPRST4  4
+#define EPRST3  3
+#define EPRST2  2
+#define EPRST1  1
+#define EPRST0  0
+
+#define UECONX  _SFR_MEM8(0XEB)
+#define STALLRQ 5
+#define STALLRQC 4
+#define RSTDT   3
+#define EPEN    0
+
+#define UECFG0X _SFR_MEM8(0XEC)
+#define EPTYPE1 7
+#define EPTYPE0 6
+#define EPDIR   0
+
+#define UECFG1X  _SFR_MEM8(0XED)
+#define EPSIZE2 6
+#define EPSIZE1 5
+#define EPSIZE0 4
+#define EPBK1   3
+#define EPBK0   2
+#define ALLOC   1
+
+#define UESTA0X _SFR_MEM8(0XEE)
+#define CFGOK   7
+#define OVERFI  6
+#define UNDERFI 5
+#define DTSEQ1  3
+#define DTSEQ0  2
+#define NBUSYBK1 1
+#define NBUSYBK0 0
+
+#define UESTA1X _SFR_MEM8(0XEF)
+#define CTRLDIR 2
+#define CURRBK1 1
+#define CURRBK0 0
+
+#define UEIENX  _SFR_MEM8(0XF0)
+#define FLERRE  7
+#define NAKINE  6
+#define NAKOUTE 4
+#define RXSTPE  3
+#define RXOUTE  2
+#define STALLEDE 1
+#define TXINE   0
+
+#define UEDATX  _SFR_MEM8(0XF1)
+
+#define UEBCLX  _SFR_MEM8(0xF2)
+
+/* Reserved [0xF3] */
+
+#define UEINT   _SFR_MEM8(0XF4)
+#define EPINT4  4
+#define EPINT3  3
+#define EPINT2  2
+#define EPINT1  1
+#define EPINT0  0
+
+/* Reserved [0xF5..0xF9] */
+
+#define PS2CON  _SFR_MEM8(0XFA)
+#define PS2EN   0
+
+#define UPOE    _SFR_MEM8(0XFB)
+#define UPWE1   7
+#define UPWE0   6
+#define UPDRV1  5
+#define UPDRV0  4
+#define SCKI    3
+#define DATAI   2
+#define DPI     1
+#define DMI     0
+
+/* Reserved [0xFC..0xFF] */
+
+/* Interrupt vectors */
+
+/* External Interrupt Request 0 */
+#define INT0_vect_num		1
+#define INT0_vect			_VECTOR(1)
+
+/* External Interrupt Request 1 */
+#define INT1_vect_num		2
+#define INT1_vect			_VECTOR(2)
+
+/* External Interrupt Request 2 */
+#define INT2_vect_num		3
+#define INT2_vect			_VECTOR(3)
+
+/* External Interrupt Request 3 */
+#define INT3_vect_num		4
+#define INT3_vect			_VECTOR(4)
+
+/* External Interrupt Request 4 */
+#define INT4_vect_num		5
+#define INT4_vect			_VECTOR(5)
+
+/* External Interrupt Request 5 */
+#define INT5_vect_num		6
+#define INT5_vect			_VECTOR(6)
+
+/* External Interrupt Request 6 */
+#define INT6_vect_num   	7
+#define INT6_vect			_VECTOR(7)
+
+/* External Interrupt Request 7 */
+#define INT7_vect_num		8
+#define INT7_vect			_VECTOR(8)
+
+/* Pin Change Interrupt Request 0 */
+#define PCINT0_vect_num		9
+#define PCINT0_vect			_VECTOR(9)
+
+/* Pin Change Interrupt Request 1 */
+#define PCINT1_vect_num		10
+#define PCINT1_vect			_VECTOR(10)
+
+/* USB General Interrupt Request */
+#define USB_GEN_vect_num    	11
+#define USB_GEN_vect			_VECTOR(11)
+
+/* USB Endpoint/Pipe Interrupt Communication Request */
+#define USB_COM_vect_num		12
+#define USB_COM_vect			_VECTOR(12)
+
+/* Watchdog Time-out Interrupt */
+#define WDT_vect_num		13
+#define WDT_vect			_VECTOR(13)
+
+/* Timer/Counter2 Capture Event */
+#define TIMER1_CAPT_vect_num	14
+#define TIMER1_CAPT_vect		_VECTOR(14)
+
+/* Timer/Counter2 Compare Match B */
+#define TIMER1_COMPA_vect_num	15
+#define TIMER1_COMPA_vect		_VECTOR(15)
+
+/* Timer/Counter2 Compare Match B */
+#define TIMER1_COMPB_vect_num	16
+#define TIMER1_COMPB_vect		_VECTOR(16)
+
+/* Timer/Counter2 Compare Match C */
+#define TIMER1_COMPC_vect_num	17
+#define TIMER1_COMPC_vect		_VECTOR(17)
+
+/* Timer/Counter1 Overflow */
+#define TIMER1_OVF_vect_num		18
+#define TIMER1_OVF_vect			_VECTOR(18)
+
+/* Timer/Counter0 Compare Match A */
+#define TIMER0_COMPA_vect_num	19
+#define TIMER0_COMPA_vect		_VECTOR(19)
+
+/* Timer/Counter0 Compare Match B */
+#define TIMER0_COMPB_vect_num	20
+#define TIMER0_COMPB_vect		_VECTOR(20)
+
+/* Timer/Counter0 Overflow */
+#define TIMER0_OVF_vect_num		21
+#define TIMER0_OVF_vect			_VECTOR(21)
+
+/* SPI Serial Transfer Complete */
+#define SPI_STC_vect_num		22
+#define SPI_STC_vect			_VECTOR(22)
+
+/* USART1, Rx Complete */
+#define USART1_RX_vect_num		23
+#define USART1_RX_vect			_VECTOR(23)
+
+/* USART1 Data register Empty */
+#define USART1_UDRE_vect_num	24
+#define USART1_UDRE_vect		_VECTOR(24)
+
+/* USART1, Tx Complete */
+#define USART1_TX_vect_num		25
+#define USART1_TX_vect			_VECTOR(25)
+
+/* Analog Comparator */
+#define ANALOG_COMP_vect_num	26
+#define ANALOG_COMP_vect		_VECTOR(26)
+
+/* EEPROM Ready */
+#define EE_READY_vect_num		27
+#define EE_READY_vect			_VECTOR(27)
+
+/* Store Program Memory Read */
+#define SPM_READY_vect_num   	28
+#define SPM_READY_vect			_VECTOR(28)
+
+#define _VECTORS_SIZE 116
+
+#endif  /* _AVR_IOUSBXX2_H_ */

hardware/tools/avr/avr/include/avr/iousbxx6_7.h

@@ -0,0 +1,1336 @@
+/* Copyright (c) 2006, Anatoly Sokolov 
+   All rights reserved.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+
+   * Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+
+   * Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in
+     the documentation and/or other materials provided with the
+     distribution.
+
+   * Neither the name of the copyright holders nor the names of
+     contributors may be used to endorse or promote products derived
+     from this software without specific prior written permission.
+
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+  POSSIBILITY OF SUCH DAMAGE. */
+
+/* $Id: iousbxx6_7.h 2225 2011-03-02 16:27:26Z arcanum $ */
+
+/* iousbxx6_7.h - definitions for AT90USB646, AT90USB647, AT90USB1286 
+   and AT90USB1287 */
+
+#ifndef _AVR_IOUSBXX6_7_H_
+#define _AVR_IOUSBXX6_7_H_ 1
+
+/* This file should only be included from <avr/io.h>, never directly. */
+
+#ifndef _AVR_IO_H_
+#  error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+#  define _AVR_IOXXX_H_ "iousbxx6_7.h"
+#else
+#  error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif 
+
+#if defined(__AVR_AT90USB646__) || defined(__AVR_AT90USB1286__)
+#  define __AT90USBxx6__ 1
+#elif defined(__AVR_AT90USB647__) || defined(__AVR_AT90USB1287__)
+#  define __AT90USBxx7__ 1
+#endif
+
+/* Registers and associated bit numbers */
+
+#define PINA    _SFR_IO8(0X00)
+#define PINA7   7
+#define PINA6   6
+#define PINA5   5
+#define PINA4   4
+#define PINA3   3
+#define PINA2   2
+#define PINA1   1
+#define PINA0   0
+
+#define DDRA    _SFR_IO8(0X01)
+#define DDA7    7
+#define DDA6    6
+#define DDA5    5
+#define DDA4    4
+#define DDA3    3
+#define DDA2    2
+#define DDA1    1
+#define DDA0    0
+
+#define PORTA   _SFR_IO8(0X02)
+#define PA7  7
+#define PA6  6
+#define PA5  5
+#define PA4  4
+#define PA3  3
+#define PA2  2
+#define PA1  1
+#define PA0  0
+
+#define PINB    _SFR_IO8(0X03)
+#define PINB7   7
+#define PINB6   6
+#define PINB5   5
+#define PINB4   4
+#define PINB3   3
+#define PINB2   2
+#define PINB1   1
+#define PINB0   0
+
+#define DDRB    _SFR_IO8(0x04)
+#define DDB7    7
+#define DDB6    6
+#define DDB5    5
+#define DDB4    4
+#define DDB3    3
+#define DDB2    2
+#define DDB1    1
+#define DDB0    0
+
+#define PORTB   _SFR_IO8(0x05)
+#define PB7  7
+#define PB6  6
+#define PB5  5
+#define PB4  4
+#define PB3  3
+#define PB2  2
+#define PB1  1
+#define PB0  0
+
+#define PINC    _SFR_IO8(0x06)
+#define PINC7   7
+#define PINC6   6
+#define PINC5   5
+#define PINC4   4
+#define PINC3   3
+#define PINC2   2
+#define PINC1   1
+#define PINC0   0
+
+#define DDRC    _SFR_IO8(0x07)
+#define DDC7    7
+#define DDC6    6
+#define DDC5    5
+#define DDC4    4
+#define DDC3    3
+#define DDC2    2
+#define DDC1    1
+#define DDC0    0
+
+#define PORTC   _SFR_IO8(0x08)
+#define PC7  7
+#define PC6  6
+#define PC5  5
+#define PC4  4
+#define PC3  3
+#define PC2  2
+#define PC1  1
+#define PC0  0
+
+#define PIND    _SFR_IO8(0x09)
+#define PIND7   7
+#define PIND6   6
+#define PIND5   5
+#define PIND4   4
+#define PIND3   3
+#define PIND2   2
+#define PIND1   1
+#define PIND0   0
+
+#define DDRD    _SFR_IO8(0x0A)
+#define DDD7    7
+#define DDD6    6
+#define DDD5    5
+#define DDD4    4
+#define DDD3    3
+#define DDD2    2
+#define DDD1    1
+#define DDD0    0
+
+#define PORTD   _SFR_IO8(0x0B)
+#define PD7  7
+#define PD6  6
+#define PD5  5
+#define PD4  4
+#define PD3  3
+#define PD2  2
+#define PD1  1
+#define PD0  0
+
+#define PINE    _SFR_IO8(0x0C)
+#define PINE7   7
+#define PINE6   6
+#define PINE5   5
+#define PINE4   4
+#define PINE3   3
+#define PINE2   2
+#define PINE1   1
+#define PINE0   0
+
+#define DDRE    _SFR_IO8(0x0D)
+#define DDE7    7
+#define DDE6    6
+#define DDE5    5
+#define DDE4    4
+#define DDE3    3
+#define DDE2    2
+#define DDE1    1
+#define DDE0    0
+
+#define PORTE   _SFR_IO8(0x0E)
+#define PE7  7
+#define PE6  6
+#define PE5  5
+#define PE4  4
+#define PE3  3
+#define PE2  2
+#define PE1  1
+#define PE0  0
+
+#define PINF    _SFR_IO8(0x0F)
+#define PINF7   7
+#define PINF6   6
+#define PINF5   5
+#define PINF4   4
+#define PINF3   3
+#define PINF2   2
+#define PINF1   1
+#define PINF0   0
+
+#define DDRF    _SFR_IO8(0x10)
+#define DDF7    7
+#define DDF6    6
+#define DDF5    5
+#define DDF4    4
+#define DDF3    3
+#define DDF2    2
+#define DDF1    1
+#define DDF0    0
+
+#define PORTF   _SFR_IO8(0x11)
+#define PF7  7
+#define PF6  6
+#define PF5  5
+#define PF4  4
+#define PF3  3
+#define PF2  2
+#define PF1  1
+#define PF0  0
+
+/* Reserved [0x12..0x14] */
+
+#define TIFR0   _SFR_IO8(0x15)
+#define OCF0B   2
+#define OCF0A   1
+#define TOV0    0
+
+#define TIFR1   _SFR_IO8(0x16)
+#define ICF1    5
+#define OCF1C   3
+#define OCF1B   2
+#define OCF1A   1
+#define TOV1    0
+
+#define TIFR2   _SFR_IO8(0x17)
+#define OCF2B   2
+#define OCF2A   1
+#define TOV2    0
+
+#define TIFR3   _SFR_IO8(0x18)
+#define ICF3    5
+#define OCF3C   3
+#define OCF3B   2
+#define OCF3A   1
+#define TOV3    0
+
+/* Reserved [0x19..0x1A] */
+
+#define PCIFR   _SFR_IO8(0x1B)
+#define PCIF0   0
+
+#define EIFR    _SFR_IO8(0x1C)
+#define INTF7   7
+#define INTF6   6
+#define INTF5   5
+#define INTF4   4
+#define INTF3   3
+#define INTF2   2
+#define INTF1   1
+#define INTF0   0
+
+#define EIMSK   _SFR_IO8(0x1D)
+#define INT7    7
+#define INT6    6
+#define INT5    5
+#define INT4    4
+#define INT3    3
+#define INT2    2
+#define INT1    1 
+#define INT0    0
+
+#define GPIOR0  _SFR_IO8(0x1E)
+
+#define EECR    _SFR_IO8(0x1F)
+#define EEPM1   5
+#define EEPM0   4
+#define EERIE   3
+#define EEMPE   2
+#define EEPE    1
+#define EERE    0
+
+#define EEDR    _SFR_IO8(0x20)
+
+#define EEAR    _SFR_IO16(0x21)
+#define EEARL   _SFR_IO8(0x21)
+#define EEARH   _SFR_IO8(0x22)
+
+/* 6-char sequence denoting where to find the EEPROM registers in memory space.
+   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
+   subroutines.
+   First two letters:  EECR address.
+   Second two letters: EEDR address.
+   Last two letters:   EEAR address.  */
+#define __EEPROM_REG_LOCATIONS__ 1F2021
+
+#define GTCCR   _SFR_IO8(0x23)
+#define TSM     7
+#define PSRASY  1
+#define PSRSYNC 0
+
+#define TCCR0A  _SFR_IO8(0x24)
+#define COM0A1  7
+#define COM0A0  6
+#define COM0B1  5
+#define COM0B0  4
+#define WGM01   1
+#define WGM00   0
+
+#define TCCR0B  _SFR_IO8(0x25)
+#define FOC0A   7
+#define FOC0B   6
+#define WGM02   3
+#define CS02    2
+#define CS01    1
+#define CS00    0
+
+#define TCNT0   _SFR_IO8(0X26)
+
+#define OCR0A   _SFR_IO8(0x27)
+
+#define OCR0B   _SFR_IO8(0X28)
+
+#define PLLCSR  _SFR_IO8(0x29)
+#define PLLP2   4
+#define PLLP1   3
+#define PLLP0   2
+#define PLLE    1
+#define PLOCK   0
+
+#define GPIOR1  _SFR_IO8(0x2A)
+
+#define GPIOR2  _SFR_IO8(0x2B)
+
+#define SPCR    _SFR_IO8(0x2C)
+#define SPIE    7
+#define SPE     6
+#define DORD    5
+#define MSTR    4
+#define CPOL    3
+#define CPHA    2
+#define SPR1    1
+#define SPR0    0
+
+#define SPSR    _SFR_IO8(0x2D)
+#define SPIF    7
+#define WCOL    6
+#define SPI2X   0
+
+#define SPDR    _SFR_IO8(0x2E)
+
+/* Reserved [0x2F] */
+
+#define ACSR    _SFR_IO8(0x30)
+#define ACD     7
+#define ACBG    6
+#define ACO     5
+#define ACI     4
+#define ACIE    3
+#define ACIC    2
+#define ACIS1   1
+#define ACIS0   0
+
+#define MONDR   _SFR_IO8(0x31)
+#define OCDR    _SFR_IO8(0x31)
+#define IDRD    7
+#define OCDR7   7
+#define OCDR6   6
+#define OCDR5   5
+#define OCDR4   4
+#define OCDR3   3
+#define OCDR2   2
+#define OCDR1   1
+#define OCDR0   0
+
+/* Reserved [0x32] */
+
+#define SMCR    _SFR_IO8(0x33)
+#define SM2     3
+#define SM1     2
+#define SM0     1
+#define SE      0
+
+#define MCUSR   _SFR_IO8(0x34)
+#define JTRF    4
+#define WDRF    3
+#define BORF    2
+#define EXTRF   1
+#define PORF    0
+
+#define MCUCR   _SFR_IO8(0x35)
+#define JTD     7
+#define PUD     4
+#define IVSEL   1
+#define IVCE    0
+
+/* Reserved [0x36] */
+
+#define SPMCSR  _SFR_IO8(0x37)
+#define SPMIE   7
+#define RWWSB   6
+#define SIGRD   5
+#define RWWSRE  4
+#define BLBSET  3
+#define PGWRT   2
+#define PGERS   1
+#define SPMEN   0
+
+/* Reserved [0x38..0x3A] */
+
+#if defined(__AVR_AT90USB1286__) || defined(__AVR_AT90USB1287__)
+#define RAMPZ   _SFR_IO8(0x3B)
+#endif
+
+/* Reserved [0x3C] */
+
+/* SP [0x3D..0x3E] */
+/* SREG [0x3F] */
+
+#define WDTCSR  _SFR_MEM8(0x60)
+#define WDIF    7
+#define WDIE    6
+#define WDP3    5
+#define WDCE    4
+#define WDE     3
+#define WDP2    2
+#define WDP1    1
+#define WDP0    0
+
+#define CLKPR   _SFR_MEM8(0x61)
+#define CLKPCE  7
+#define CLKPS3  3
+#define CLKPS2  2
+#define CLKPS1  1
+#define CLKPS0  0
+
+/* Reserved [0x62..0x63] */
+
+#define PRR0    _SFR_MEM8(0x64)
+#define PRTWI   7
+#define PRTIM2  6
+#define PRTIM0  5
+#define PRTIM1  3
+#define PRSPI   2
+#define PRADC   0
+
+#define __AVR_HAVE_PRR0	((1<<PRADC)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI))
+#define __AVR_HAVE_PRR0_PRADC
+#define __AVR_HAVE_PRR0_PRSPI
+#define __AVR_HAVE_PRR0_PRTIM1
+#define __AVR_HAVE_PRR0_PRTIM0
+#define __AVR_HAVE_PRR0_PRTIM2
+#define __AVR_HAVE_PRR0_PRTWI
+
+#define PRR1    _SFR_MEM8(0x65)
+#define PRUSB   7
+#define PRTIM3  3
+#define PRUSART1 0
+
+#define __AVR_HAVE_PRR1	((1<<PRUSART1)|(1<<PRTIM3)|(1<<PRUSB))
+#define __AVR_HAVE_PRR1_PRUSART1
+#define __AVR_HAVE_PRR1_PRTIM3
+#define __AVR_HAVE_PRR1_PRUSB
+
+#define OSCCAL  _SFR_MEM8(0x66)
+
+/* Reserved [0x67] */
+
+#define PCICR   _SFR_MEM8(0x68)
+#define PCIE0   0
+
+#define EICRA   _SFR_MEM8(0x69)
+#define ISC31   7
+#define ISC30   6
+#define ISC21   5
+#define ISC20   4
+#define ISC11   3
+#define ISC10   2
+#define ISC01   1
+#define ISC00   0
+
+#define EICRB   _SFR_MEM8(0x6A)
+#define ISC71   7
+#define ISC70   6
+#define ISC61   5
+#define ISC60   4
+#define ISC51   3
+#define ISC50   2
+#define ISC41   1
+#define ISC40   0
+
+#define PCMSK0  _SFR_MEM8(0x6B)
+#define PCINT7  7
+#define PCINT6  6
+#define PCINT5  5
+#define PCINT4  4
+#define PCINT3  3
+#define PCINT2  2
+#define PCINT1  1
+#define PCINT0  0
+
+/* Reserved [0x6C..0x6D] */
+
+#define TIMSK0  _SFR_MEM8(0x6E)
+#define OCIE0B  2
+#define OCIE0A  1
+#define TOIE0   0
+
+#define TIMSK1  _SFR_MEM8(0x6F)
+#define ICIE1   5
+#define OCIE1C  3
+#define OCIE1B  2
+#define OCIE1A  1
+#define TOIE1   0
+
+#define TIMSK2  _SFR_MEM8(0x70)
+#define OCIE2B  2
+#define OCIE2A  1
+#define TOIE2   0
+
+#define TIMSK3  _SFR_MEM8(0x71)
+#define ICIE3   5
+#define OCIE3C  3
+#define OCIE3B  2
+#define OCIE3A  1
+#define TOIE3   0
+
+/* Reserved [0x72..0x73] */
+
+#define XMCRA   _SFR_MEM8(0x74)
+#define SRE     7
+#define SRL2    6
+#define SRL1    5
+#define SRL0    4
+#define SRW11   3
+#define SRW10   2
+#define SRW01   1
+#define SRW00   0
+
+#define XMCRB   _SFR_MEM8(0x75)
+#define XMBK    7
+#define XMM2    2
+#define XMM1    1
+#define XMM0    0
+
+/* Reserved [0x76..0x77] */
+
+/* RegDef:  ADC Data Register */
+#ifndef __ASSEMBLER__
+#define ADC    _SFR_MEM16(0x78)
+#endif
+#define ADCW   _SFR_MEM16(0x78)
+#define ADCL   _SFR_MEM8(0x78)
+#define ADCH   _SFR_MEM8(0x79)
+
+#define ADCSRA  _SFR_MEM8(0x7A)
+#define ADEN    7
+#define ADSC    6
+#define ADATE   5
+#define ADIF    4
+#define ADIE    3
+#define ADPS2   2
+#define ADPS1   1
+#define ADPS0   0
+
+#define ADCSRB  _SFR_MEM8(0x7B)
+#define ADHSM  7
+#define ACME    6
+#define ADTS2   2
+#define ADTS1   1
+#define ADTS0   0
+
+#define ADMUX   _SFR_MEM8(0x7C)
+#define REFS1   7
+#define REFS0   6
+#define ADLAR   5
+#define MUX4    4
+#define MUX3    3
+#define MUX2    2
+#define MUX1    1
+#define MUX0    0
+
+/* Reserved [0x7D] */
+
+#define DIDR0   _SFR_MEM8(0x7E)
+#define ADC7D   7
+#define ADC6D   6
+#define ADC5D   5
+#define ADC4D   4
+#define ADC3D   3
+#define ADC2D   2
+#define ADC1D   1
+#define ADC0D   0
+
+#define DIDR1   _SFR_MEM8(0x7F)
+#define AIN1D   1
+#define AIN0D   0
+
+#define TCCR1A  _SFR_MEM8(0x80)
+#define COM1A1  7
+#define COM1A0  6
+#define COM1B1  5
+#define COM1B0  4
+#define COM1C1  3
+#define COM1C0  2
+#define WGM11   1
+#define WGM10   0
+
+#define TCCR1B  _SFR_MEM8(0x81)
+#define ICNC1   7
+#define ICES1   6
+#define WGM13   4
+#define WGM12   3
+#define CS12    2
+#define CS11    1
+#define CS10    0
+
+#define TCCR1C  _SFR_MEM8(0x82)
+#define FOC1A   7
+#define FOC1B   6
+#define FOC1C   5
+
+/* Reserved [0x83] */
+
+/* Combine TCNT1L and TCNT1H */
+#define TCNT1   _SFR_MEM16(0x84)
+
+#define TCNT1L  _SFR_MEM8(0x84)
+#define TCNT1H  _SFR_MEM8(0x85)
+
+/* Combine ICR1L and ICR1H */
+#define ICR1    _SFR_MEM16(0x86)
+
+#define ICR1L   _SFR_MEM8(0x86)
+#define ICR1H   _SFR_MEM8(0x87)
+
+/* Combine OCR1AL and OCR1AH */
+#define OCR1A   _SFR_MEM16(0x88)
+
+#define OCR1AL  _SFR_MEM8(0x88)
+#define OCR1AH  _SFR_MEM8(0x89)
+
+/* Combine OCR1BL and OCR1BH */
+#define OCR1B   _SFR_MEM16(0x8A)
+
+#define OCR1BL  _SFR_MEM8(0x8A)
+#define OCR1BH  _SFR_MEM8(0x8B)
+
+/* Combine OCR1CL and OCR1CH */
+#define OCR1C   _SFR_MEM16(0x8C)
+
+#define OCR1CL  _SFR_MEM8(0x8C)
+#define OCR1CH  _SFR_MEM8(0x8D)
+
+/* Reserved [0x8E..0x8F] */
+
+#define TCCR3A  _SFR_MEM8(0x90)
+#define COM3A1  7
+#define COM3A0  6
+#define COM3B1  5
+#define COM3B0  4
+#define COM3C1  3
+#define COM3C0  2
+#define WGM31   1
+#define WGM30   0
+
+#define TCCR3B  _SFR_MEM8(0x91)
+#define ICNC3   7
+#define ICES3   6
+#define WGM33   4
+#define WGM32   3
+#define CS32    2
+#define CS31    1
+#define CS30    0
+
+#define TCCR3C  _SFR_MEM8(0x92)
+#define FOC3A   7
+#define FOC3B   6
+#define FOC3C   5
+
+/* Reserved [0x93] */
+
+/* Combine TCNT3L and TCNT3H */
+#define TCNT3   _SFR_MEM16(0x94)
+
+#define TCNT3L  _SFR_MEM8(0x94)
+#define TCNT3H  _SFR_MEM8(0x95)
+
+/* Combine ICR3L and ICR3H */
+#define ICR3    _SFR_MEM16(0x96)
+
+#define ICR3L   _SFR_MEM8(0x96)
+#define ICR3H   _SFR_MEM8(0x97)
+
+/* Combine OCR3AL and OCR3AH */
+#define OCR3A   _SFR_MEM16(0x98)
+
+#define OCR3AL  _SFR_MEM8(0x98)
+#define OCR3AH  _SFR_MEM8(0x99)
+
+/* Combine OCR3BL and OCR3BH */
+#define OCR3B   _SFR_MEM16(0x9A)
+
+#define OCR3BL  _SFR_MEM8(0x9A)
+#define OCR3BH  _SFR_MEM8(0x9B)
+
+/* Combine OCR3CL and OCR3CH */
+#define OCR3C   _SFR_MEM16(0x9C)
+
+#define OCR3CL  _SFR_MEM8(0x9C)
+#define OCR3CH  _SFR_MEM8(0x9D)
+
+#if defined(__AT90USBxx7__)
+
+#define UHCON   _SFR_MEM8(0x9E)
+#define RESUME  2
+#define RESET   1
+#define SOFEN   0
+
+#define UHINT   _SFR_MEM8(0x9F)
+#define HWUPI   6
+#define HSOFI   5
+#define RXRSMI  4
+#define RSMEDI  3
+#define RSTI    2
+#define DDISCI  1
+#define DCONNI  0
+
+#define UHIEN   _SFR_MEM8(0xA0)
+#define HWUPE   6
+#define HSOFE   5
+#define RXRSME  4
+#define RSMEDE  3
+#define RSTE    2
+#define DDISCE  1
+#define DCONNE  0
+
+#define UHADDR  _SFR_MEM8(0xA1)
+
+/* Combine UHFNUML and UHFNUMH */
+#define UHFNUM  _SFR_MEM16(0xA2)
+
+#define UHFNUML _SFR_MEM8(0xA2)
+#define UHFNUMH _SFR_MEM8(0xA3)
+
+#define UHFLEN  _SFR_MEM8(0xA4)
+
+#define UPINRQX _SFR_MEM8(0xA5)
+
+#define UPINTX  _SFR_MEM8(0xA6)
+#define FIFOCON 7
+#define NAKEDI  6
+#define RWAL    5
+#define PERRI   4
+#define TXSTPI  3
+#define TXOUTI  2
+#define RXSTALLI 1
+#define RXINI   0
+
+#define UPNUM   _SFR_MEM8(0xA7)
+
+#define UPRST   _SFR_MEM8(0xA8)
+#define PRST6   6
+#define PRST5   5
+#define PRST4   4
+#define PRST3   3
+#define PRST2   2
+#define PRST1   1
+#define PRST0   0
+
+#define UPCONX  _SFR_MEM8(0xA9)
+#define PFREEZE 6
+#define INMODE  5
+/* #define AUTOSW  4 */ /* Reserved */
+#define RSTDT   3
+#define PEN     0
+
+#define UPCFG0X _SFR_MEM8(0XAA)
+#define PTYPE1  7
+#define PTYPE0  6
+#define PTOKEN1 5
+#define PTOKEN0 4
+#define PEPNUM3 3
+#define PEPNUM2 2
+#define PEPNUM1 1
+#define PEPNUM0 0
+
+#define UPCFG1X _SFR_MEM8(0XAB)
+#define PSIZE2  6
+#define PSIZE1  5
+#define PSIZE0  4
+#define PBK1    3
+#define PBK0    2
+#define ALLOC   1
+
+#define UPSTAX  _SFR_MEM8(0XAC)
+#define CFGOK   7
+#define OVERFI  6
+#define UNDERFI 5
+#define DTSEQ1  3
+#define DTSEQ0  2
+#define NBUSYBK1 1
+#define NBUSYBK0 0
+
+#define UPCFG2X _SFR_MEM8(0XAD)
+
+#define UPIENX  _SFR_MEM8(0XAE)
+#define FLERRE  7
+#define NAKEDE  6
+#define PERRE   4
+#define TXSTPE  3
+#define TXOUTE  2
+#define RXSTALLE 1
+#define RXINE   0
+
+#define UPDATX  _SFR_MEM8(0XAF)
+
+#endif /* __AT90USBxx7__ */
+
+#define TCCR2A  _SFR_MEM8(0xB0)
+#define COM2A1  7
+#define COM2A0  6
+#define COM2B1  5
+#define COM2B0  4
+#define WGM21   1
+#define WGM20   0
+
+#define TCCR2B  _SFR_MEM8(0xB1)
+#define FOC2A   7
+#define FOC2B   6
+#define WGM22   3
+#define CS22    2
+#define CS21    1
+#define CS20    0
+
+#define TCNT2   _SFR_MEM8(0xB2)
+
+#define OCR2A   _SFR_MEM8(0xB3)
+
+#define OCR2B   _SFR_MEM8(0xB4)
+
+/* Reserved [0xB5] */
+
+#define ASSR    _SFR_MEM8(0xB6)
+#define EXCLK   6
+#define AS2     5
+#define TCN2UB  4
+#define OCR2AUB 3
+#define OCR2BUB 2
+#define TCR2AUB 1
+#define TCR2BUB 0
+
+/* Reserved [0xB7] */
+
+#define TWBR    _SFR_MEM8(0xB8)
+
+#define TWSR    _SFR_MEM8(0xB9)
+#define TWS7    7
+#define TWS6    6
+#define TWS5    5
+#define TWS4    4
+#define TWS3    3
+#define TWPS1   1
+#define TWPS0   0
+
+#define TWAR    _SFR_MEM8(0xBA)
+#define TWA6    7
+#define TWA5    6
+#define TWA4    5
+#define TWA3    4
+#define TWA2    3
+#define TWA1    2
+#define TWA0    1
+#define TWGCE   0
+
+#define TWDR    _SFR_MEM8(0xBB)
+
+#define TWCR    _SFR_MEM8(0xBC)
+#define TWINT   7
+#define TWEA    6
+#define TWSTA   5
+#define TWSTO   4
+#define TWWC    3
+#define TWEN    2
+#define TWIE    0
+
+#define TWAMR   _SFR_MEM8(0xBD)
+#define TWAM6   7
+#define TWAM5   6
+#define TWAM4   5
+#define TWAM3   4
+#define TWAM2   3
+#define TWAM1   2
+#define TWAM0   1
+
+/* Reserved [0xBE..0xC7] */
+
+#define UCSR1A  _SFR_MEM8(0xC8)
+#define RXC1    7
+#define TXC1    6
+#define UDRE1   5
+#define FE1     4
+#define DOR1    3
+#define UPE1    2
+#define U2X1    1
+#define MPCM1   0
+
+#define UCSR1B  _SFR_MEM8(0XC9)
+#define RXCIE1  7
+#define TXCIE1  6
+#define UDRIE1  5
+#define RXEN1   4
+#define TXEN1   3
+#define UCSZ12  2
+#define RXB81   1
+#define TXB81   0
+
+#define UCSR1C  _SFR_MEM8(0xCA)
+#define UMSEL11 7
+#define UMSEL10 6
+#define UPM11   5
+#define UPM10   4
+#define USBS1   3
+#define UCSZ11  2
+#define UCSZ10  1
+#define UCPOL1  0
+
+/* Reserved [0xCB] */
+
+/* Combine UBRR1L and UBRR1H */
+#define UBRR1   _SFR_MEM16(0xCC)
+
+#define UBRR1L  _SFR_MEM8(0xCC)
+#define UBRR1H  _SFR_MEM8(0xCD)
+
+#define UDR1    _SFR_MEM8(0XCE)
+
+/* Reserved [0xCF..0xD6] */
+
+#define UHWCON  _SFR_MEM8(0XD7)
+#define UIMOD   7
+#define UIDE    6
+#define UVCONE  4
+#define UVREGE  0
+
+#define USBCON  _SFR_MEM8(0XD8)
+#define USBE    7
+#define HOST    6
+#define FRZCLK  5
+#define OTGPADE 4
+#define IDTE    1
+#define VBUSTE  0
+
+#define USBSTA  _SFR_MEM8(0XD9)
+#define SPEED   3
+#define ID      1
+#define VBUS    0
+
+#define USBINT  _SFR_MEM8(0XDA)
+#define IDTI    1
+#define VBUSTI  0
+
+/* Combine UDPADDL and UDPADDH */
+#define UDPADD  _SFR_MEM16(0xDB)
+
+#define UDPADDL _SFR_MEM8(0xDB)
+#define UDPADDH _SFR_MEM8(0xDC)
+#define DPACC   7
+
+#if defined(__AT90USBxx7__)
+
+#define OTGCON  _SFR_MEM8(0XDD)
+#define HNPREQ  5
+#define SRPREQ  4
+#define SRPSEL  3
+#define VBUSHWC 2
+#define VBUSREQ 1
+#define VBUSRQC 0
+
+#define OTGIEN  _SFR_MEM8(0XDE)
+#define STOE    5
+#define HNPERRE 4
+#define ROLEEXE 3
+#define BCERRE  2
+#define VBERRE  1
+#define SRPE    0
+
+#define OTGINT  _SFR_MEM8(0XDF)
+#define STOI    5
+#define HNPERRI 4
+#define ROLEEXI 3
+#define BCERRI  2
+#define VBERRI  1
+#define SRPI    0
+
+#endif /* __AT90USBxx7__ */
+
+#define UDCON   _SFR_MEM8(0XE0)
+#define LSM     2
+#define RMWKUP  1
+#define DETACH  0
+
+#define UDINT   _SFR_MEM8(0XE1)
+#define UPRSMI  6
+#define EORSMI  5
+#define WAKEUPI 4
+#define EORSTI  3
+#define SOFI    2
+/* #define MSOFI   1 */ /* Reserved */
+#define SUSPI   0
+
+#define UDIEN   _SFR_MEM8(0XE2)
+#define UPRSME  6
+#define EORSME  5
+#define WAKEUPE 4
+#define EORSTE  3
+#define SOFE    2
+/* #define MSOFE   1 */ /* Reserved */
+#define SUSPE   0
+
+#define UDADDR  _SFR_MEM8(0XE3)
+#define ADDEN   7
+
+/* Combine UDFNUML and UDFNUMH */
+#define UDFNUM  _SFR_MEM16(0xE4)
+
+#define UDFNUML _SFR_MEM8(0xE4)
+#define UDFNUMH _SFR_MEM8(0xE5)
+
+#define UDMFN   _SFR_MEM8(0XE6)
+#define FNCERR  4
+
+#define UDTST   _SFR_MEM8(0XE7)
+#define OPMODE2 5
+#define TSTPCKT 4
+#define TSTK    3
+#define TSTJ    2
+
+#define UEINTX  _SFR_MEM8(0XE8)
+#define FIFOCON 7
+#define NAKINI  6
+#define RWAL    5
+#define NAKOUTI 4
+#define RXSTPI  3
+#define RXOUTI  2
+#define STALLEDI 1
+#define TXINI   0
+
+#define UENUM   _SFR_MEM8(0XE9)
+
+#define UERST   _SFR_MEM8(0XEA)
+#define EPRST6  6
+#define EPRST5  5
+#define EPRST4  4
+#define EPRST3  3
+#define EPRST2  2
+#define EPRST1  1
+#define EPRST0  0
+
+#define UECONX  _SFR_MEM8(0XEB)
+#define STALLRQ 5
+#define STALLRQC 4
+#define RSTDT   3
+#define EPEN    0
+
+#define UECFG0X _SFR_MEM8(0XEC)
+#define EPTYPE1 7
+#define EPTYPE0 6
+/* #define ISOSW   3 */ /* Reserved */
+/* #define AUTOSW  2 */ /* Reserved */
+/* #define NYETSDIS 1 */ /* Reserved */
+#define EPDIR   0
+
+#define UECFG1X  _SFR_MEM8(0XED)
+#define EPSIZE2 6
+#define EPSIZE1 5
+#define EPSIZE0 4
+#define EPBK1   3
+#define EPBK0   2
+#define ALLOC   1
+
+#define UESTA0X _SFR_MEM8(0XEE)
+#define CFGOK   7
+#define OVERFI  6
+#define UNDERFI 5
+#define ZLPSEEN 4
+#define DTSEQ1  3
+#define DTSEQ0  2
+#define NBUSYBK1 1
+#define NBUSYBK0 0
+
+#define UESTA1X _SFR_MEM8(0XEF)
+#define CTRLDIR 2
+#define CURRBK1 1
+#define CURRBK0 0
+
+#define UEIENX  _SFR_MEM8(0XF0)
+#define FLERRE  7
+#define NAKINE  6
+#define NAKOUTE 4
+#define RXSTPE  3
+#define RXOUTE  2
+#define STALLEDE 1
+#define TXINE   0
+
+#define UEDATX  _SFR_MEM8(0XF1)
+
+/* Combine UEBCLX and UEBCHX */
+#define UEBCX   _SFR_MEM16(0xF2)
+
+#define UEBCLX  _SFR_MEM8(0xF2)
+#define UEBCHX  _SFR_MEM8(0xF3)
+
+#define UEINT   _SFR_MEM8(0XF4)
+#define EPINT6  6
+#define EPINT5  5
+#define EPINT4  4
+#define EPINT3  3
+#define EPINT2  2
+#define EPINT1  1
+#define EPINT0  0
+
+#if defined(__AT90USBxx7__)
+
+#define UPERRX  _SFR_MEM8(0XF5)
+#define COUNTER1 6
+#define COUNTER0 5
+#define CRC16    4
+#define TIMEOUT  3
+#define PID      2
+#define DATAPID  1
+#define DATATGL  0
+
+/* Combine UPBCLX and UPBCHX */
+#define UPBCX   _SFR_MEM16(0xF6)
+
+#define UPBCLX  _SFR_MEM8(0xF6)
+#define UPBCHX  _SFR_MEM8(0xF7)
+
+#define UPINT   _SFR_MEM8(0XF8)
+#define PINT6   6
+#define PINT5   5
+#define PINT4   4
+#define PINT3   3
+#define PINT2   2
+#define PINT1   1
+#define PINT0   0
+
+#define OTGTCON _SFR_MEM8(0XF9)
+#define PAGE1   6
+#define PAGE0   5
+#define VALUE1  1
+#define VALUE0  0
+
+#endif /* __AT90USBxx7__ */
+
+/* Reserved [0xFA..0xFF] */
+
+/* Interrupt vectors */
+
+/* External Interrupt Request 0 */
+#define INT0_vect_num			1
+#define INT0_vect	    		_VECTOR(1)
+
+/* External Interrupt Request 1 */
+#define INT1_vect_num			2
+#define INT1_vect	    		_VECTOR(2)
+
+/* External Interrupt Request 2 */
+#define INT2_vect_num			3
+#define INT2_vect	    		_VECTOR(3)
+
+/* External Interrupt Request 3 */
+#define INT3_vect_num			4
+#define INT3_vect	    		_VECTOR(4)
+
+/* External Interrupt Request 4 */
+#define INT4_vect_num			5
+#define INT4_vect	    		_VECTOR(5)
+
+/* External Interrupt Request 5 */
+#define INT5_vect_num			6
+#define INT5_vect	    		_VECTOR(6)
+
+/* External Interrupt Request 6 */
+#define INT6_vect_num			7
+#define INT6_vect	    		_VECTOR(7)
+
+/* External Interrupt Request 7 */
+#define INT7_vect_num			8
+#define INT7_vect	    		_VECTOR(8)
+
+/* Pin Change Interrupt Request 0 */
+#define PCINT0_vect_num			9
+#define PCINT0_vect		    	_VECTOR(9)
+
+/* USB General Interrupt Request */
+#define USB_GEN_vect_num		10
+#define USB_GEN_vect			_VECTOR(10)
+
+/* USB Endpoint/Pipe Interrupt Communication Request */
+#define USB_COM_vect_num		11
+#define USB_COM_vect			_VECTOR(11)
+
+/* Watchdog Time-out Interrupt */
+#define WDT_vect_num			12
+#define WDT_vect	    		_VECTOR(12)
+
+/* Timer/Counter2 Compare Match A */
+#define TIMER2_COMPA_vect_num	13
+#define TIMER2_COMPA_vect		_VECTOR(13)
+
+/* Timer/Counter2 Compare Match B */
+#define TIMER2_COMPB_vect_num	14
+#define TIMER2_COMPB_vect		_VECTOR(14)
+
+/* Timer/Counter2 Overflow */
+#define TIMER2_OVF_vect_num		15
+#define TIMER2_OVF_vect			_VECTOR(15)
+
+/* Timer/Counter1 Capture Event */
+#define TIMER1_CAPT_vect_num	16
+#define TIMER1_CAPT_vect		_VECTOR(16)
+
+/* Timer/Counter1 Compare Match A */
+#define TIMER1_COMPA_vect_num	17
+#define TIMER1_COMPA_vect		_VECTOR(17)
+
+/* Timer/Counter1 Compare Match B */
+#define TIMER1_COMPB_vect_num	18
+#define TIMER1_COMPB_vect		_VECTOR(18)
+
+/* Timer/Counter1 Compare Match C */
+#define TIMER1_COMPC_vect_num	19
+#define TIMER1_COMPC_vect		_VECTOR(19)
+
+/* Timer/Counter1 Overflow */
+#define TIMER1_OVF_vect_num		20
+#define TIMER1_OVF_vect			_VECTOR(20)
+
+/* Timer/Counter0 Compare Match A */
+#define TIMER0_COMPA_vect_num	21
+#define TIMER0_COMPA_vect		_VECTOR(21)
+
+/* Timer/Counter0 Compare Match B */
+#define TIMER0_COMPB_vect_num	22
+#define TIMER0_COMPB_vect		_VECTOR(22)
+
+/* Timer/Counter0 Overflow */
+#define TIMER0_OVF_vect_num		23
+#define TIMER0_OVF_vect			_VECTOR(23)
+
+/* SPI Serial Transfer Complete */
+#define SPI_STC_vect_num		24
+#define SPI_STC_vect			_VECTOR(24)
+
+/* USART1, Rx Complete */
+#define USART1_RX_vect_num		25
+#define USART1_RX_vect			_VECTOR(25)
+
+/* USART1 Data register Empty */
+#define USART1_UDRE_vect_num    26
+#define USART1_UDRE_vect		_VECTOR(26)
+
+/* USART1, Tx Complete */
+#define USART1_TX_vect_num		27
+#define USART1_TX_vect			_VECTOR(27)
+
+/* Analog Comparator */
+#define ANALOG_COMP_vect_num	28
+#define ANALOG_COMP_vect		_VECTOR(28)
+
+/* ADC Conversion Complete */
+#define ADC_vect_num			29
+#define ADC_vect	    		_VECTOR(29)
+
+/* EEPROM Ready */
+#define EE_READY_vect_num		30
+#define EE_READY_vect			_VECTOR(30)
+
+/* Timer/Counter3 Capture Event */
+#define TIMER3_CAPT_vect_num	31
+#define TIMER3_CAPT_vect		_VECTOR(31)
+
+/* Timer/Counter3 Compare Match A */
+#define TIMER3_COMPA_vect_num	32
+#define TIMER3_COMPA_vect		_VECTOR(32)
+
+/* Timer/Counter3 Compare Match B */
+#define TIMER3_COMPB_vect_num	33
+#define TIMER3_COMPB_vect		_VECTOR(33)
+
+/* Timer/Counter3 Compare Match C */
+#define TIMER3_COMPC_vect_num	34
+#define TIMER3_COMPC_vect		_VECTOR(34)
+
+/* Timer/Counter3 Overflow */
+#define TIMER3_OVF_vect_num		35
+#define TIMER3_OVF_vect			_VECTOR(35)
+
+/* 2-wire Serial Interface */
+#define TWI_vect_num			36
+#define TWI_vect			    _VECTOR(36)
+
+/* Store Program Memory Read */
+#define SPM_READY_vect_num		37
+#define SPM_READY_vect			_VECTOR(37)
+
+#define _VECTORS_SIZE 152
+
+#if defined(__AT90USBxx6__)
+# undef __AT90USBxx6__
+#endif /* __AT90USBxx6__ */
+
+#if defined(__AT90USBxx7__)
+# undef __AT90USBxx7__
+#endif /* __AT90USBxx7__ */
+
+#endif  /* _AVR_IOUSBXX6_7_H_ */