repo_name stringlengths 1 62 | dataset stringclasses 1
value | lang stringclasses 11
values | pr_id int64 1 20.1k | owner stringlengths 2 34 | reviewer stringlengths 2 39 | diff_hunk stringlengths 15 262k | code_review_comment stringlengths 1 99.6k |
|---|---|---|---|---|---|---|---|
neural-speed | github_2023 | cpp | 176 | intel | zhewang1-intc | @@ -500,22 +565,22 @@ void dequantize_gemm_run(int iter) {
{bias_d, bias_add_shape}});
typename gemm_op_t::template arguments_t<compute_policy::quant_type>
- gemm_arg(matrix_m, matrix_k, matrix_n, A_d, matrix_k, B_d, matrix_n,
- C_d, matrix_n, scale_d, matrix_n, Acc_d, ... | emm, will we just delete this impl check in the future or fix the internal logic? |
neural-speed | github_2023 | cpp | 176 | intel | DDEle | @@ -353,6 +356,21 @@ class gemm_t<
}
private:
+ inline void reorder_matA(matA_t &matA) {
+ constexpr uint32_t num_block_x = tile_size_x_a / block_size_x_a;
+ constexpr uint32_t num_block_y = tile_size_y_a / block_size_y_a;
+ for (int i = 0; i < num_block_y * num_block_x; i++) {
+ ... | Should be able to handle cases where `block_size_y_a != block_size_x_a` with the following changes
```suggestion
for (uint32_t i = 0; i < num_block_y * num_block_x; i++) {
auto dst_blk = matA.reg.xetla_select<matA_t::block_elems, 1>(
i * matA_t::block_elems);
x... |
neural-speed | github_2023 | cpp | 176 | intel | airMeng | @@ -71,7 +71,7 @@ __XETLA_API int32_t xetla_get_subdevice_id() {
namespace gpu::xetla {
-enum class gpu_arch : uint8_t { Dg2 = 0, Xe = 1 };
+enum class gpu_arch : uint8_t { Igpu = 0, Dg2 = 1, Xe = 2 }; | suggest to be more specific, ```xelpg``` or ```lpg``` or ```mtl``` |
neural-speed | github_2023 | cpp | 176 | intel | airMeng | @@ -86,6 +106,13 @@ struct mma_attr_t<gpu_arch::Dg2> {
static constexpr uint32_t mma_k_in_bytes = 32;
};
+template <>
+struct mma_attr_t<gpu_arch::Igpu> {
+ static constexpr uint32_t mma_m_in_elem = 8;
+ static constexpr uint32_t mma_n_in_elem = 8;
+ static constexpr uint32_t mma_k_in_bytes = 32; | no xmx support for MTL, is these needed? |
neural-speed | github_2023 | cpp | 176 | intel | DDEle | @@ -128,6 +128,42 @@ struct xetla_nbarrier_t<num_producers, num_consumers, arch_tag,
wait();
}
};
+template <uint8_t num_producers, uint8_t num_consumers>
+struct xetla_nbarrier_t<num_producers, num_consumers, gpu_arch::Igpu> {
+ ///
+ /// @brief Description of named barrier objection.
+ /// Str... | No need anymore. This specialization will be covered by
``` c++
template <uint8_t num_producers, uint8_t num_consumers, gpu_arch arch_tag>
struct xetla_nbarrier_t<num_producers, num_consumers, arch_tag,std::enable_if_t<arch_tag != gpu_arch::Xe>>
``` |
neural-speed | github_2023 | cpp | 176 | intel | DDEle | @@ -461,6 +461,37 @@ vnni_transform(T_dst &dst, T_src &src) {
dst.reg = reg_dst;
}
+/// @brief Converts tiled layout to transpose_tiled layout.
+///
+/// @tparam T Is the tile data type.
+/// @param mat_Acc Is the reference of the tile object.
+/// @return No return, update the data in-place.
+template <typena... | It should work for B mat from col-major global memory.
We tried the following case in `tests/unit/tile_load_store/main.cpp`
```c++
cl::sycl::nd_range<1> nd_range({1}, {1});
auto result_validate
= std::bind(tile_load_store_result_validate<half, false, true>, _1,
_2, _3, 12... |
neural-speed | github_2023 | others | 176 | intel | airMeng | @@ -46,7 +46,7 @@ endif ()
add_compile_options(-fsycl)
add_link_options(-fsycl)
if(UNIX)
- add_compile_options(-fp-model=precise -Wall -Wextra -Werror)
+ add_compile_options(-fp-model=precise -Wall -Wextra -ftemplate-backtrace-limit=0) | Try to add AOT option, aligned with IPEX.
AOT targets of PVC, Arc, MTL are ```pvc, ats-m150, xe-lpg``` |
neural-speed | github_2023 | cpp | 176 | intel | airMeng | @@ -80,15 +97,25 @@ struct mma_attr_t<gpu_arch::Xe> {
};
template <>
-struct mma_attr_t<gpu_arch::Dg2> {
- static constexpr uint32_t mma_m_in_elem = 8;
- static constexpr uint32_t mma_n_in_elem = 8;
- static constexpr uint32_t mma_k_in_bytes = 32;
+struct mma_attr_t<gpu_arch::Dg2> : public client_mma_atr_b... | mtl has no xmx support, please set all to zero |
neural-speed | github_2023 | cpp | 176 | intel | DDEle | @@ -133,6 +133,30 @@ struct compute_policy_default_fpu<compute_attr_, perf_tuning_knob_, arch_tag_,
static constexpr uint32_t block_size_y_b = block_size_x_a;
};
+/// @brief Specialized for Xe architecture.
+template <typename compute_attr_, typename perf_tuning_knob_>
+struct compute_policy_default_fpu<compute... | Wrong `/// @brief`
In addition, should it for dg2 and igpu? |
neural-speed | github_2023 | others | 176 | intel | DDEle | @@ -2,7 +2,7 @@ include_directories(${CMAKE_SOURCE_DIR}/include)
include_directories(${CMAKE_SOURCE_DIR})
# Creates a separate device code module for each SYCL* kernel
-# so that kernel for Dg2 and Xe will be JIT separately
+# so that kernel for XeHpg and Xe will be JIT separately | ```suggestion
# so that kernel for XeHpc, XeHpg, and XeLpg will be JIT separately
```
or
```suggestion
# so that kernel for different device architectures will be JIT separately
```
|
neural-speed | github_2023 | cpp | 176 | intel | DDEle | @@ -451,9 +451,8 @@ class gemm_universal_t<
static cl::sycl::range<3> get_local_range() {
uint32_t local_range_m = (wg_tile_m + sg_tile_m - 1) / sg_tile_m;
uint32_t local_range_n = (wg_tile_n + sg_tile_n - 1) / sg_tile_n;
- // std::cout << "Local range: {" << num_local_kslicing << ", " <<
- // local_... | Add macro to disable it in IPEX (preferably disable by default and enable in NS). |
neural-speed | github_2023 | others | 176 | intel | airMeng | @@ -46,6 +46,8 @@ endif ()
add_compile_options(-fsycl)
add_link_options(-fsycl)
if(UNIX)
+ # add_compile_options(-fsycl-targets=spir64_gen)
+ # add_link_options(-fsycl-targets=spir64_gen -Xs "-device 0x7d55") # MTL | Can AOT work now? |
neural-speed | github_2023 | cpp | 176 | intel | zhewang1-intc | @@ -676,4 +676,22 @@ layout_convert(T_dst& dst, T_src& src) {
}
}
}
+
+template <typename T>
+void dump_mat(
+ T mat,
+ size_t tile_x = T::tile_size_x,
+ size_t tile_y = T::tile_size_y) {
+#pragma unroll
+ for (size_t row = 0; row < tile_x; row++) { | emmm, swap the tile_x & tile_y |
neural-speed | github_2023 | cpp | 176 | intel | airMeng | @@ -451,9 +451,11 @@ class gemm_universal_t<
static cl::sycl::range<3> get_local_range() {
uint32_t local_range_m = (wg_tile_m + sg_tile_m - 1) / sg_tile_m;
uint32_t local_range_n = (wg_tile_n + sg_tile_n - 1) / sg_tile_n;
- // std::cout << "Local range: {" << num_local_kslicing << ", " <<
- // local... | remove |
neural-speed | github_2023 | cpp | 176 | intel | airMeng | @@ -471,8 +473,11 @@ class gemm_universal_t<
uint32_t group_range_m = (matrix_m + wg_tile_m - 1) / wg_tile_m;
uint32_t group_range_n = (matrix_n + wg_tile_n - 1) / wg_tile_n;
group_swizzle_t::update_group_range(group_range_m, group_range_n);
- // std::cout << "Group range: {" << num_global_kslicing <<... | remove |
neural-speed | github_2023 | cpp | 176 | intel | airMeng | @@ -531,6 +533,77 @@ tile_load(tile_t& tile, payload_t& payload) {
}
}
+/// @brief This function loads data from unaligned-2D memory surface.
+/// Loads an array of rectangular regions (X,Y)..(X+W,Y+H) from memory into
+/// registers. Each block will be loaded serially by its corresponding payload.
+/// @tparam t... | how about align to https://github.com/intel-innersource/frameworks.ai.pytorch.ipex-gpu/pull/4100
```suggestion
!arch_has_2d_load_store(payload_t::arch_tag)
``` |
neural-speed | github_2023 | cpp | 176 | intel | DDEle | @@ -33,24 +33,24 @@ TYPED_TEST_P(fp16_gemm_test, esimd) {
}
REGISTER_TYPED_TEST_SUITE_P(fp16_gemm_test, esimd);
using tests = ::testing::Types<
- Test0,
- Test1,
- Test2,
- Test3,
- Test4,
- Test5,
- Test6,
- Test7,
- Test8,
- Test9,
- Test10,
- Test11,
- Test12,
- Test13,
-... | Revert changes on UT for testing |
neural-speed | github_2023 | cpp | 176 | intel | DDEle | @@ -46,16 +46,17 @@ class TestBase {
return name;
}
static constexpr mma_engine engine = mma_engine::xmx;
+ static constexpr gpu_arch gpu_arch = gpu_arch::XeHpg;
};
class Test0 : public TestBase {
public:
static constexpr size_t mat_m = 256;
static constexpr size_t mat_n = 256;
static constex... | Revert changes on UT for testing. If we do need this case, then we should add it rather than change from an existing one. |
neural-speed | github_2023 | cpp | 176 | intel | DDEle | @@ -30,7 +30,7 @@ template <
class Test,
typename validate_func,
typename KERNEL,
- int SLMSIZE = 128 * 1024,
+ int SLMSIZE = Test::gpu_arch >= gpu_arch::XeHpc ? 128 * 1024 : 64 * 1024, | I think there is a field for slm side in arch_config |
neural-speed | github_2023 | cpp | 176 | intel | airMeng | @@ -19,21 +19,68 @@
// #define UT_DEBUG 1
using namespace gpu::xetla;
// The number of times the kernel is executed
-constexpr int ITER = 100;
+constexpr int ITER = 1000;
-class test1 {
+class test1_xehpg {
public:
// Extract the parameters required by different test cases
- static constexpr size_t mat_m = 1... | at least the following cases are needed:
```
seq length = 1, 32, 1024
ic = 4096, 16384
oc = 1024, 4096, 12288, 16384
``` |
neural-speed | github_2023 | cpp | 176 | intel | luoyu-intel | @@ -33,24 +33,24 @@ TYPED_TEST_P(fp16_gemm_test, esimd) {
}
REGISTER_TYPED_TEST_SUITE_P(fp16_gemm_test, esimd);
using tests = ::testing::Types<
- Test0,
- Test1,
- Test2,
- Test3,
- Test4,
- Test5,
- Test6,
- Test7,
- Test8,
- Test9,
- Test10,
- Test11,
- Test12,
- Test13,
-... | uncomment these cases. |
neural-speed | github_2023 | python | 227 | intel | a32543254 | @@ -402,6 +403,12 @@ def generate(self,
def is_token_end(self):
return self.model.is_token_end()
+ def reset_kv_cache(self):
+ if self.model is None:
+ return | if self.model is None:
may be we could throw a warning log like:
The model is not inited yet, then return |
neural-speed | github_2023 | python | 227 | intel | a32543254 | @@ -434,6 +441,7 @@ def __call__(self, model_input, reinit=False, logits_all=False, **kwargs):
logits_seq_len_dim = model_input.shape[1] if logits_all else 1
self.reinit_from_bin = False
self._check_max_request_num(batch_size, **kwargs)
+ self._check_ctx_size(kwargs.get... | multi_round=(not reinit) ?
should be bool right? |
neural-speed | github_2023 | cpp | 227 | intel | a32543254 | @@ -65,7 +65,7 @@ void Llama::init(const char* path_model, model_context* ctx, int n_gpu_layer_, b
auto& hparams = model.hparams;
n_ff = hparams.ffn_hidden_size;
fprintf(stderr, "%s: n_vocab = %u\n", __func__, hparams.n_vocab);
- fprintf(stderr, "%s: n_ctx = %u\n", __func__, hparams.max_seq_len);
+ f... | what is the default value of lctx.n_ctx ? |
neural-speed | github_2023 | cpp | 225 | intel | a32543254 | @@ -79,12 +79,6 @@ static bool llama_model_eval_internal(model_context* ctx, const model_input* inp
n_pasts[i] = inputs[i].n_past;
n_totals[i] = inputs[i].n_total;
block_ids[i] = inputs[i].request_idx * beam_size + inputs[i].beam_idx;
- // enforce that the first token is BOS
- if (n_totals[i] == 0 ... | why delete here? |
neural-speed | github_2023 | python | 225 | intel | a32543254 | @@ -0,0 +1,1639 @@
+#!/usr/bin/env python3
+# Copyright (c) 2024 Intel Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+... | how about use convert llama, rather than add new script. |
neural-speed | github_2023 | others | 223 | intel | DDEle | @@ -46,7 +46,9 @@ endif ()
add_compile_options(-fsycl)
add_link_options(-fsycl)
if(UNIX)
- add_compile_options(-fp-model=precise -Wall -Wextra -Werror) | add back werror |
neural-speed | github_2023 | cpp | 223 | intel | airMeng | @@ -23,7 +23,7 @@
namespace gpu::xetla::group {
-enum quant_mode : uint8_t { S4_ASYM, S4_FULLRANGE_NO_ZP };
+enum weight_dtype : uint8_t { S4_ASYM, S4_FULLRANGE_NO_ZP, NF4 }; | please consider merging S4_ASYM and S4_FULLRANG_NO_ZP
<html xmlns:o="urn:schemas-microsoft-com:office:office"
xmlns:w="urn:schemas-microsoft-com:office:word"
xmlns:m="http://schemas.microsoft.com/office/2004/12/omml"
xmlns="http://www.w3.org/TR/REC-html40">
<head>
<meta name=ProgId content=Word.Document>
<... |
neural-speed | github_2023 | others | 223 | intel | DDEle | @@ -2,7 +2,7 @@ include_directories(${CMAKE_SOURCE_DIR}/include)
include_directories(${CMAKE_SOURCE_DIR})
# Creates a separate device code module for each SYCL* kernel
-# so that kernel for Dg2 and Xe will be JIT separately
+# so that kernel for gpu_arch::XeHpg and Xe will be JIT separately | unnecessay change |
neural-speed | github_2023 | cpp | 223 | intel | DDEle | @@ -113,7 +113,7 @@ struct gru_layer {
using perf_tuning_knob =
perf_tuning_knob_t<sg_tile_k, prefetch_distance, periodic_sync_interval>;
- using compute_attr = xetla::group::compute_attr_t<T, T, Act_T>;
+ using compute_attr = group::compute_attr_t<T, T, Act_T>; | will it compile? I added it as it confuses with sycl::group |
neural-speed | github_2023 | cpp | 223 | intel | DDEle | @@ -76,4 +76,4 @@ struct conversion_func {
layout_convert(data_tile, linear_data_tile); // linear to tiled
tile_store(data_tile, result_payload);
}
-};
+}; | Please go thought the diff and revert unnecessary changes |
neural-speed | github_2023 | cpp | 223 | intel | DDEle | @@ -180,8 +180,8 @@ class cooperative_reduce_t<
nbarrier.wait();
if (is_valid_post_process_wg()) {
- // nbarrier.init_nbarrier(nbar_id, nbarrier_role::consumer);
- // nbarrier.arrive();
+ nbarrier.init_nbarrier(nbar_id, nbarrier_role::consumer);
+ nbarrier.arrive(); | Is it necessary? If so, where is its `wait()`? |
neural-speed | github_2023 | cpp | 223 | intel | DDEle | @@ -380,8 +380,6 @@ class gemm_t<
SW_BARRIER();
subgroup::tile_load<cache_hint::cached, cache_hint::cached>(
matA, matA_payload);
- if constexpr (!is_col_major_a)
- reorder_matA(matA); | I think you need to change accordingly in load_xe to keep the fmha correct |
neural-speed | github_2023 | cpp | 223 | intel | DDEle | @@ -156,147 +157,12 @@ class gemm_universal_t<
arch_tag>;
public:
- /// @brief GEMM arguments.
- /// This is the interface for users to pass the application-related runtime
- /// variables.
- template <group::quant_mode quant_mode = group::S4_FULLRANGE_NO_ZP>
- struct arguments_t {
- /// @brief Is th... | typo
```suggestion
struct optional_arguments_t {
``` |
neural-speed | github_2023 | cpp | 211 | intel | luoyu-intel | @@ -63,7 +63,8 @@ void bestla_fusion_attn_int8_forward(const attn_int8_fwd_args_t* params) {
}
size_t bestla_fusion_attn_workspace_size(const attn_shape_t* params) {
const auto& p = *params; // TODO(Yi): Better way to get tmp size?
- return size_t(ne_threading::get()->num_threads() * sizeof(float) * 16) * padto(... | ne_threading::get()->num_threads() should be the actual threads? why change it to device's threads? |
neural-speed | github_2023 | cpp | 211 | intel | luoyu-intel | @@ -30,6 +30,36 @@ using thread_func = std::function<void(int tid)>;
class IThreading {
public:
explicit IThreading(int nthreads, bool supportPE) : mThreadNum(nthreads), isSupportPE(supportPE) {}
+
+ // equal to "for(int i=begin1;i<end1;i+=step1)"
+ void parallel_for_collapse(const int& begin1, const int& end1,... | what does this `std::min(tidx, block_remain)` mean? |
neural-speed | github_2023 | cpp | 47 | intel | sunjiweiswift | @@ -508,14 +506,14 @@ class gemm_t<compute_policy_int4_dequantize_xmx<compute_attr_,
//2: int8 includes 2 4bits data.
xetla_vector<uint8_t, block_size_x_b * block_size_y_b> cvt_blk;
- cvt_blk.xetla_select<matB_t::block_elems, 2>(0)
- = matB_blk &... | & 0x0f and >> 4
For the two quant methods, it seems that they can be reused |
neural-speed | github_2023 | python | 212 | intel | zhentaoyu | @@ -156,12 +156,9 @@ def init(self,
quant_desc += "_pc"
else:
quant_desc += "_g{}".format(group_size)
- if use_gptq:
- quant_desc = "gptq"
- if use_awq:
- quant_desc = "awq"
- if use_awq:
- quant_desc = "autoround"
+
+ ... | ```suggestion
if 'quantization_config' not in config:
print("Error: no quantization_config in low-bits model...")
exit(0)
quant_desc = config['quantation_config'].get("quant_method", None)
if quant_desc is None:
print("Error: No quant_method info...")
exit(0)
``` |
neural-speed | github_2023 | cpp | 178 | intel | zhewang1-intc | @@ -252,6 +252,123 @@ class DequanS8FP {
};
class DecompresssS3 { | should be named DecompressS3 ... my bad.... |
neural-speed | github_2023 | cpp | 202 | intel | a32543254 | @@ -1805,7 +1805,17 @@ std::vector<std::pair<std::string, struct ne_tensor*>>& model_internal_get_tenso
static void ne_model_kv_cache_seq_cpy(struct model_context* ctx, const model_seq_id& seq_id_src,
const model_seq_id& seq_id_dst, const model_pos& p0, const model_pos& p1) {
... | LGTM |
neural-speed | github_2023 | python | 196 | intel | VincyZhang | @@ -229,6 +233,25 @@ def check_submodules():
]
cmdclass={'build_ext': CMakeBuild}
+ install_requires = [
+ "accelerate",
+ "cmake",
+ "datasets",
+ "einops",
+ "gguf",
+ "matplotlib",
+ "numpy",
+ "peft",
+ "protobuf<3.20",
+ "py-c... | need install requirements.txt when setup, or torch will not install as we expected |
neural-speed | github_2023 | others | 198 | intel | DDEle | @@ -16,3 +16,4 @@ torch==2.1.0+cpu; sys_platform == "linux"
torch == 2.*; sys_platform != "linux"
transformers
transformers_stream_generator
+zipfile38 | Maybe put model specific requirements inside https://github.com/intel/neural-speed/tree/main/neural_speed/models/requirements ? |
neural-speed | github_2023 | others | 186 | intel | a32543254 | @@ -0,0 +1,159 @@
+Continuous Batching
+=======
+
+Continuous batching is a more efficient batching mechanism in LLM server system when compared with static batching input and output. It has two main characteristics:
+- concat input sequences in `seq_len` dimension (omit padding token) for `linear` operation and split ... | could you also add [Magicoder-6.7B](https://huggingface.co/ise-uiuc/Magicoder-S-DS-6.7B)
here for support list ? |
neural-speed | github_2023 | python | 184 | intel | a32543254 | @@ -106,7 +106,8 @@ def main(args_in: Optional[List[str]] = None) -> None:
out_path = args.outfile.as_posix()
model_path = args.model.as_posix()
- model, config, quantize_config = load_quantized_model(model_path)
+ #model, config, quantize_config = load_quantized_model(model_path) | remove unuse code |
neural-speed | github_2023 | python | 184 | intel | a32543254 | @@ -215,6 +217,51 @@ def unpack_weight(qweight, scales, qzeros, q_config):
raise ValueError(f"Unsupported quant_method: {quant_method}")
+def unpack_gptq_weight_8bits(qweight, scales, qzeros, q_config):
+ sym = q_config['sym']
+ group_size = q_config['group_size']
+ bits = q_config['bits']
+ s32_bi... | iteam > item |
neural-speed | github_2023 | python | 184 | intel | a32543254 | @@ -215,6 +217,51 @@ def unpack_weight(qweight, scales, qzeros, q_config):
raise ValueError(f"Unsupported quant_method: {quant_method}")
+def unpack_gptq_weight_8bits(qweight, scales, qzeros, q_config):
+ sym = q_config['sym']
+ group_size = q_config['group_size']
+ bits = q_config['bits']
+ s32_bi... | it's seems not straight forward ? why don't let inc return a int8 for asym ? |
neural-speed | github_2023 | python | 171 | intel | airMeng | @@ -106,6 +106,7 @@ def main(args_in: Optional[List[str]] = None) -> None:
fout.write(struct.pack("i", 0))
fout.write(struct.pack("i", 0)) # n_experts
fout.write(struct.pack("i", 0)) # n_expert_used
+ fout.write(struct.pack("i", 0)) # n_embd_head_k for gemma | can we have some wiser solution instead of placeholder for each model? |
neural-speed | github_2023 | others | 171 | intel | a32543254 | @@ -432,7 +439,7 @@ function main() {
else
real_ctx=$ctx # TODO(Zhenzhong): use same ctx for chatglm & baichuan
[[ "${model}" == "chatglm2" || "${model}" == "chatglm-6b" ||
- "${model}" == "baichuan-13b" || "${model}" == ... | why change baichuan real_ctx here ? |
neural-speed | github_2023 | cpp | 171 | intel | zhentaoyu | @@ -684,6 +684,11 @@ bool bestla_fusion_FFN_SiLu_f32f32_support(void* w1ptr, void* w2ptr, void* w3ptr
return ffn_3w::bestla_fusion_ffn_f32f32_support(w1ptr, w2ptr, w3ptr, seq, fin, fmid, fout);
}
+bool bestla_fusion_FFN_Gelu_Mul_f32f32_support(void* w1ptr, void* w2ptr, void* w3ptr, int seq, int fin, int fmid, | Does it mean gemma FFN-8W matmul? or I misunderstanding? And what is the difference between `Gelu_Mul` and `Gelu`? |
neural-speed | github_2023 | others | 171 | intel | a32543254 | @@ -271,6 +271,17 @@ Neural Speed supports the following models:
<td> </td>
<td> </td>
<td>Latest</td>
+ </tr>
+ <tr>
+ <td><a href="https://huggingface.co/google/gemma-2b-it" target="_blank" rel="noopener noreferrer">gemma-2b-it </a>,
+ <a href="https://huggingface.co/google/gemma-7b" target="... | format is worry, please fix the md format. |
neural-speed | github_2023 | others | 171 | intel | a32543254 | @@ -97,6 +98,9 @@ set(mymap_phi 16)
set(mymap_stablelm 17)
set(mymap_whisper 18)
set(mymap_mixtral 19)
+set(mymap_gemma 20)
+
+ | remove unused line |
neural-speed | github_2023 | others | 171 | intel | a32543254 | @@ -271,6 +271,17 @@ Neural Speed supports the following models:
<td> </td>
<td> </td>
<td>Latest</td>
+ </tr>
+ <tr>
+ <td><a href="https://huggingface.co/google/gemma-2b-it" target="_blank" rel="noopener noreferrer">gemma-2b-it </a>,
+ <a href="https://huggingface.co/google/gemma-7b" target="... | and do we support gguf of this model ?
https://huggingface.co/mlabonne/gemma-2b-GGUF/tree/main |
neural-speed | github_2023 | others | 171 | intel | a32543254 | @@ -271,6 +271,17 @@ Neural Speed supports the following models:
<td> </td>
<td> </td>
<td>Latest</td>
+ </tr>
+ <tr>
+ <td><a href="https://huggingface.co/google/gemma-2b-it" target="_blank" rel="noopener noreferrer">gemma-2b-it </a>, |
there is no structure difference between gemma-2b and gemma-2b-it right ?
[gemma-2b](https://huggingface.co/google/gemma-2b) |
neural-speed | github_2023 | cpp | 182 | intel | a32543254 | @@ -238,9 +238,12 @@ int main(int argc, char** argv) { // NOLINT
std::vector<std::string> prompts;
prompts.push_back(params.prompt);
std::string prompt = build_prompt_glm2(prompts);
+ std::cout << "prompt = " << prompt << std::endl;
+ | why we need cout here? |
neural-speed | github_2023 | others | 182 | intel | a32543254 | @@ -0,0 +1,81 @@
+# Prompt template
+
+This document will show some examples to introduce how to correctly use prompt templates in Neural Speed and [ITREX](https://github.com/intel/intel-extension-for-transformers).
+
+For the base model (without SFT for pre-training), prompt can be directly encoded into token ids with... | LLaMA2
>>
LLaMa2
why capitalize second A ? |
neural-speed | github_2023 | cpp | 173 | intel | luoyu-intel | @@ -72,7 +72,9 @@ bool bestla_reordered_attn_fp32_support(const attn_shape_t* params) {
// TODO(Yi): check K V's layout
if (_cd->AMX_BF16()) return true;
#endif
- return !_cd->AVX512F() || _cd->AVX2(); // use avx2 and f16c on avx2 platforms
+ // use avx2 and f16c on avx2 platforms
+ // todo: check avx2 mha o... | what does this mean? no avx512f but has avx2. Does it mean that MHA_AVX512F is not ready? |
neural-speed | github_2023 | python | 156 | intel | a32543254 | @@ -21,13 +21,12 @@
model_maps = {"gpt_neox": "gptneox", "gpt_bigcode": "starcoder", "whisper": "whisper", "qwen2": "qwen"}
-def convert_model(model, outfile, outtype="f32", model_hub="huggingface", use_quantized_model=False):
+def convert_model(model, outfile, outtype="f32", format="NE", model_hub="huggingface", ... | why add new args? |
neural-speed | github_2023 | cpp | 156 | intel | a32543254 | @@ -0,0 +1,428 @@
+// Copyright (c) 2023 Intel Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless re... | have you test on SPR with MHA FFN fusion is enabled? |
neural-speed | github_2023 | c | 156 | intel | intellinjun | @@ -12602,4 +12602,4 @@ int ne_cpu_has_sse3(void) {
int ne_cpu_has_vsx(void) { return 0; }
-////////////////////////////////////////////////////////////////////////////////
+//////////////////////////////////////////////////////////////////////////////// | Add EOF symbols, which are also required in other files |
neural-speed | github_2023 | cpp | 120 | intel | airMeng | @@ -106,6 +106,13 @@ static bool baichuan_model_eval_internal(model_context* ctx, const model_input*
// otherwise, the threads are spin-lock waiting for the BLAS calls and are degrading the performance
ne_cgraph gf = {};
gf.n_threads = N >= 32 && ne_cpu_has_blas() ? 1 : n_threads;
+ if (hparams.ftype == NE_FT... | I will prefer to subtract out these logic so you can keep improving within bestla
```cpp
// ne_bestla.cpp
int bestla_get_best_thread_num(ne_ftype ft){
if (ftype == NE_FTYPE_MOSTLY_NF4 && bestla_is_hybrid()) return bestla_get_Pcore_number();
else return ${max_thread_num}
}
// various models.cpp
int best_... |
neural-speed | github_2023 | cpp | 120 | intel | zhewang1-intc | @@ -47,3 +49,21 @@ int32_t get_num_physical_cores() {
unsigned int n_threads = std::thread::hardware_concurrency();
return n_threads > 0 ? (n_threads <= 4 ? n_threads : n_threads / 2) : 4;
}
+
+int get_best_thread(const ne_ftype ftype, const int n_threads, const int N) {
+ int res;
+ if (N >= 32 && ne_cpu_has_... | why cpplint not thrown a warning? |
neural-speed | github_2023 | cpp | 159 | intel | airMeng | @@ -120,6 +120,7 @@ struct arch_attr_t<gpu_arch::Xe> {
using mma_attr = mma_attr_t<gpu_arch::Xe>;
static constexpr uint32_t max_wg_num = 64;
+ static constexpr uint32_t local_mem_size = 128 * 1024; | are difference sku of PVC all equipped with same size of local mem? |
neural-speed | github_2023 | cpp | 159 | intel | airMeng | @@ -227,3 +233,68 @@ void kernel_run(auto nd_range, auto validate_result) {
free(B_host);
free(C_host);
}
+
+/// @brief Using gpu_arch of current machine to run F<arch>::exec
+///
+/// @tparam F The gpu_arch-templated function wrapper
+///
+/// @example example usage in /examples/01 or /examples/02
+template... | seems no meteorlake support, can you raise an issue to them? |
neural-speed | github_2023 | cpp | 159 | intel | sunjiweiswift | @@ -227,3 +233,68 @@ void kernel_run(auto nd_range, auto validate_result) {
free(B_host);
free(C_host);
}
+
+/// @brief Using gpu_arch of current machine to run F<arch>::exec
+///
+/// @tparam F The gpu_arch-templated function wrapper
+///
+/// @example example usage in /examples/01 or /examples/02
+template... | AOT is not supported |
neural-speed | github_2023 | cpp | 159 | intel | sunjiweiswift | @@ -173,8 +173,8 @@ class batch_gemm_t {
/// @return The size of local memory required.
__XETLA_API static constexpr uint32_t get_slm_size() {
constexpr uint32_t size = gemm_t::slm_size + epilogue_t::slm_size;
- static_assert(size <= (128 * 1024),
- "The local memory size should... | local_mem_size Can this parameter be printed? |
neural-speed | github_2023 | cpp | 159 | intel | sunjiweiswift | @@ -161,10 +165,11 @@ void sdp_fwd_run(uint32_t iter) {
constexpr uint32_t matrix_n_sv = head_size;
constexpr uint32_t matrix_k_sv = sequence_len;
- constexpr uint32_t wg_tile_m_sv = 64;
- constexpr uint32_t wg_tile_n_sv = 64;
+ // constexpr uint32_t wg_tile_m_sv = 64;
+ constexpr uint32_t wg_ti... | Hardware related parameters can be modified centrally in arch_config |
neural-speed | github_2023 | cpp | 159 | intel | sunjiweiswift | @@ -231,243 +271,223 @@ void sdp_fwd_run(uint32_t iter) {
cl::sycl::range<3> local_range {1, subgroup_range_m, subgroup_range_n};
cl::sycl::nd_range<3> nd_range(group_range * local_range, local_range);
- constexpr uint32_t warmup = 10;
- int64_t ops = int64_t(4 * batch_num * head_num * sequence_len) *... | Should need to be aligned |
neural-speed | github_2023 | cpp | 159 | intel | sunjiweiswift | @@ -106,23 +111,15 @@ struct xetla_nbarrier_t<num_producers, num_consumers, gpu_arch::Dg2> {
/// @brief Generic work-group split barrier.
///
- __XETLA_API void arrive() {
- __ESIMD_ENS::split_barrier<__ESIMD_ENS::split_barrier_action::signal>();
- }
+ __XETLA_API void arrive() { __ESIMD_NS:... | Is there anything wrong with split_barrier_action? |
neural-speed | github_2023 | cpp | 159 | intel | sunjiweiswift | @@ -106,23 +111,15 @@ struct xetla_nbarrier_t<num_producers, num_consumers, gpu_arch::Dg2> {
/// @brief Generic work-group split barrier.
///
- __XETLA_API void arrive() {
- __ESIMD_ENS::split_barrier<__ESIMD_ENS::split_barrier_action::signal>();
- }
+ __XETLA_API void arrive() { __ESIMD_NS:... | Are arrive and wait implemented in the same way? |
neural-speed | github_2023 | cpp | 159 | intel | sunjiweiswift | @@ -53,7 +54,7 @@ struct compute_policy_default_xmx<compute_attr_, perf_tuning_knob_,
= block_bytes_x_a / sizeof(dtype_mma_a);
static constexpr uint32_t block_size_y_a = 16;
- static constexpr uint32_t block_size_x_b = 16;
+ static constexpr uint32_t block_size_x_b = arch_tag < gpu_arch::Xe ? ... | arch_config。. |
neural-speed | github_2023 | cpp | 159 | intel | sunjiweiswift | @@ -68,45 +98,28 @@ enum class tune_key_value : uint8_t {
// parameter optimizer
enum class param_optimizer_tag : uint8_t { kernel, work_group };
+// optimizer_mode (currently only useful with param_optimizer_decision_tree)
+enum class param_optimizer_mode : uint8_t { | param_optimizer_level is it a better name？ |
neural-speed | github_2023 | cpp | 159 | intel | sunjiweiswift | @@ -264,53 +264,47 @@ struct kslicing_handler {
};
} // namespace decision_tree_rule
-template <typename dict_t_, typename opt_dict_t_>
+template <typename dict, typename opt_dict> | Everything else is dict_t
Type name general ’t‘ suffix |
neural-speed | github_2023 | cpp | 159 | intel | sunjiweiswift | @@ -151,26 +158,25 @@ struct default_gemm_selector_config_t
wg_shape>,
elem_v_t<tune_key::wg_tile_k, wg_tile_k>,
elem_v_t<tune_key::gpu_arch,
- gpu_ar... | Why did use derivation before? This modification looks better. |
neural-speed | github_2023 | cpp | 159 | intel | sunjiweiswift | @@ -1308,7 +1308,8 @@ struct prefetch_payload_t<
tile_desc_t<tile_size_x_, tile_size_y_, block_size_x_, block_size_y_,
reg_layout_>,
num_coop_sg_, arch_tag_,
- std::enable_if_t<(arch_tag_ == gpu_arch::Dg2)>> {
+ std::enable_if_t<(arch_tag_ <= gpu_arch::Dg2
+ ... | Is there something wrong here? To exclude==1 |
neural-speed | github_2023 | cpp | 159 | intel | luoyu-intel | @@ -220,6 +255,11 @@ void sdp_fwd_run(uint32_t iter) {
constexpr uint32_t subgroup_range_m = wg_tile_m_qk / sg_tile_m_qk;
constexpr uint32_t subgroup_range_n = wg_tile_n_qk / sg_tile_n_qk;
+ constexpr uint32_t slm_size
+ = wg_tile_m_qk * wg_tile_n_qk * sizeof(dtype_sfx);
+ static_assert(slm... | I remember this is checked somewhere else. |
neural-speed | github_2023 | cpp | 157 | intel | zhentaoyu | @@ -911,7 +911,7 @@ struct model_context* model_init_from_file(const char* path_model, struct model_
}
ctx->cont_batching = params.cont_batching;
ctx->generation_conf = params.gen_conf;
- ctx->model_scratch_enlarge_scale = params.model_scratch_enlarge_scale;
+ ctx->model_scratch_size_ratio = params.model_scr... | just a advice
```suggestion
ctx->model_scratch_size_ratio = ctx->batch_size > 1 ? params.model_scratch_size_ratio * params.max_request_num * params.beam_size : params.model_scratch_size_ratio * params.beam_size;
``` |
neural-speed | github_2023 | cpp | 118 | intel | luoyu-intel | @@ -581,84 +834,131 @@ class SchedulerKBlockS : public SchedulerBase<_GemmCore_T> {
int mKBlock{0};
};
-} // namespace gemm
-using thread_func = std::function<void(int tid)>;
-
-class IThreading {
- public:
- explicit IThreading(int nthreads) : mThreadNum(nthreads) {}
- virtual void parallel_for(const thread_f... | use std::shared_ptr instead |
neural-speed | github_2023 | others | 118 | intel | DDEle | @@ -11,7 +11,7 @@ log_path=${log_dir}/clangtidy.log
cd ${REPO_DIR}
mkdir build
cd build
-cmake .. -G Ninja -DNS_USE_CLANG_TIDY=CHECK -DBTLA_USE_OPENMP=OFF
+cmake .. -G Ninja -DNS_USE_CLANG_TIDY=CHECK -DBTLA_ENABLE_OPENMP=OFF -DNS_USE_OMP=OFF | `-DNS_USE_OMP=OFF` only should be enough |
neural-speed | github_2023 | cpp | 118 | intel | zhewang1-intc | @@ -23,10 +24,238 @@
namespace bestla {
namespace parallel {
+
+using thread_func = std::function<void(int tid)>;
+
+class IThreading {
+ public:
+ explicit IThreading(int nthreads, bool supportPE) : mThreadNum(nthreads), isSupportPE(supportPE) {}
+ virtual void parallel_for(const thread_func& func) = 0;
+ virtu... | why func(0) not func(tidx)? |
neural-speed | github_2023 | cpp | 118 | intel | zhewang1-intc | @@ -23,10 +24,238 @@
namespace bestla {
namespace parallel {
+
+using thread_func = std::function<void(int tid)>;
+
+class IThreading {
+ public:
+ explicit IThreading(int nthreads, bool supportPE) : mThreadNum(nthreads), isSupportPE(supportPE) {}
+ virtual void parallel_for(const thread_func& func) = 0;
+ virtu... | could this timer be disabled? |
neural-speed | github_2023 | cpp | 118 | intel | zhewang1-intc | @@ -23,10 +24,238 @@
namespace bestla {
namespace parallel {
+
+using thread_func = std::function<void(int tid)>;
+
+class IThreading {
+ public:
+ explicit IThreading(int nthreads, bool supportPE) : mThreadNum(nthreads), isSupportPE(supportPE) {}
+ virtual void parallel_for(const thread_func& func) = 0;
+ virtu... | i see many dbg log, better to remove it? |
neural-speed | github_2023 | cpp | 118 | intel | zhewang1-intc | @@ -23,10 +24,238 @@
namespace bestla {
namespace parallel {
+
+using thread_func = std::function<void(int tid)>;
+
+class IThreading {
+ public:
+ explicit IThreading(int nthreads, bool supportPE) : mThreadNum(nthreads), isSupportPE(supportPE) {}
+ virtual void parallel_for(const thread_func& func) = 0;
+ virtu... | why we call func in create_thread? |
neural-speed | github_2023 | cpp | 118 | intel | zhewang1-intc | @@ -1115,3 +1116,4 @@ static UT_GEMM_AMXINT8 sUT_GEMM_AMXINT8;
#endif
} // namespace ut
} // namespace bestla
+#endif | remove it. |
neural-speed | github_2023 | cpp | 118 | intel | zhewang1-intc | @@ -206,3 +208,4 @@ static UT_SchedulerGemmKBlockNew sUT_SchedulerGemmKBlockNew;
#endif
} // namespace ut
} // namespace bestla
+#endif | as above, pls check the format in this pr? |
neural-speed | github_2023 | others | 153 | intel | DDEle | @@ -411,7 +411,7 @@ function main() {
else
real_ctx=$ctx # TODO(Zhenzhong): use same ctx for chatglm & baichuan
[[ "${model}" == "chatglm2" || "${model}" == "chatglm-6b" ||
- "${model}" == "baichuan-13b" || "${model}" == ... | If the special `$real_ctx` is no longer necessary for chatglm & baichuan, we should just remove everything about `real_ctx` for clearity.
```suggestion
NEURAL_SPEED_VERBOSE=1 OMP_NUM_THREADS=$cores_per_instance numactl -m 0 -C 0-$(($cores_per_instance - 1)) \
$infe... |
neural-speed | github_2023 | cpp | 153 | intel | zhentaoyu | @@ -26,7 +26,7 @@ enum chatglm_model {
static const model_scratch chatglm_mem_req(int n_layers) {
switch (n_layers) {
case 28:
- return {2048ull * MB, 2048ull * MB, 4096ull * MB};
+ return {4096ull * MB, 4096ull * MB, 8192ull * MB}; | Does it still need the larger memory when `MAX_REQUEST_NUM=1`? |
neural-speed | github_2023 | python | 160 | intel | a32543254 | @@ -110,6 +110,8 @@ def main(args_in: Optional[List[str]] = None) -> None:
parser = argparse.ArgumentParser(description="Convert a model to a NE compatible file")
parser.add_argument("--outtype", choices=["f32", "f16"], help="output format (default: based on input)")
parser.add_argument("--outfile", type... | model scope also have gptq model ? |
neural-speed | github_2023 | python | 146 | intel | a32543254 | @@ -0,0 +1,187 @@
+# Copyright (c) 2024 Intel Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by appl... | could combine the convert_qwen and convert_qwen2 together ? |
neural-speed | github_2023 | cpp | 146 | intel | Zhenzhong1 | @@ -150,6 +163,34 @@ void QWEN::load(model_context* ctx, model_progress_callback progress_callback, v
layer.ffn[1] = ml->get_tensor(layers_i + ".mlp.w2.weight", {n_embd, n_ff}, backend);
layer.ffn[2] = ml->get_tensor(layers_i + ".mlp.c_proj.weight", {n_ff, n_embd}, backend);
}
+ } else { | There are so many if-elses, can we split those if-else or add comments to make it clear whether it is qwen1, qwen2, gguf or bin? |
neural-speed | github_2023 | cpp | 146 | intel | zhentaoyu | @@ -102,6 +102,12 @@ static bool qwen_model_eval_internal(model_context* ctx, const model_input* inpu
const int n_vocab = hparams.n_vocab;
const int n_rot = hparams.n_rot;
const int head_dim = n_embd / n_head;
+ int qwen_version = 0; | `max_seq_len` seems a hacky code. We can consider adding `model_version` in the model bin file later. |
neural-speed | github_2023 | python | 145 | intel | airMeng | @@ -20,7 +20,7 @@
"I want to learn how to play the piano.",
]
-model_name = "EleutherAI/gpt-j-6b" # model_name from huggingface or local model path | how do we maintain the availability of continuous batching? do we have set up related CI? |
neural-speed | github_2023 | cpp | 145 | intel | a32543254 | @@ -82,6 +104,7 @@ static bool llama_model_eval_internal(model_context* ctx, const model_input* inp
const int n_ctx = lctx.n_ctx; // max number fo tokens to keep in the kv-cache
const int n_keep = lctx.n_keep;
const bool shift_roped_k = lctx.shift_roped_k;
+ MODEL_ASSERT(("continuous batching mechanism doesn... | could we auto disable continuous batch when consumer enable shift rope rathe than assert false? |
neural-speed | github_2023 | cpp | 145 | intel | a32543254 | @@ -26,18 +26,38 @@ enum llama_model {
LLAMA_65B,
};
-static const model_scratch llama_mem_req(int n_layers) {
+static const model_scratch llama_mem_req(int n_layers, float enlarge_scale = 1.0f) { | could we based on batch auto set the enlarge scale ?
Therefore costumes won't need consider this args. |
neural-speed | github_2023 | cpp | 145 | intel | zhenwei-intel | @@ -82,7 +82,7 @@ void init_gpt_params(gpt_params* params, const std::string& model_path, int max_
float temperature = 0.8, int min_new_tokens = 0, float length_penalty = 1.0f,
bool early_stopping = false, int n_keep = 0, int n_discard = -1, bool shift_roped_k = false,
... | Isn't it necessary to write this way `const bool&`？https://stackoverflow.com/questions/11932614/in-c-is-it-bad-to-pass-a-const-bool-by-reference |
neural-speed | github_2023 | cpp | 138 | intel | DDEle | @@ -176,10 +192,24 @@ void Llama::load(model_context* ctx, model_progress_callback progress_callback,
layer.norm[1] = ml->get_tensor(layers_i + ".ffn_norm.weight", {n_embd}, backend);
// ffn GEMM
- layer.ffn[0] = ml->get_tensor(layers_i + ".feed_forward.w1.weight", {n_embd, n_ff}, backend);
- ... | Assert n_expert and n_expert_used to be zero here? |
neural-speed | github_2023 | cpp | 138 | intel | DDEle | @@ -347,17 +356,64 @@ static bool llama_model_eval_internal(model_context* ctx, const model_input* inp
// cur = cur*ffn_norm(broadcasted)
cur = ne_mul(ctx0, cur, model.layers[il].norm[1]);
}
-
- if (bestla_fusion_FFN_SiLu_f32f32_support(model.layers[il].ffn[0]->data, model.layers[il].ffn[1... | Unnecessary to explicitly build graph for `selected_experts` as it is an operand of `ne_get_rows` ? |
neural-speed | github_2023 | python | 138 | intel | airMeng | @@ -96,6 +96,8 @@ def main(args_in: Optional[List[str]] = None) -> None:
fout.write(struct.pack("i", 0)) # word_embed_proj_dim (for opt)
fout.write(struct.pack("i", 0)) # do_layer_norm_before (for opt)
+ fout.write(struct.pack("i", 0))
+ fout.write(struct.pack("i", 0)) | a lot zeros, I know they are placeholders, can you give some comments that what are they? |
neural-speed | github_2023 | c | 138 | intel | airMeng | @@ -6889,157 +6959,809 @@ static void ne_compute_forward_mul_mat_bias_q_f32_bestla(const struct ne_compute
NE_ASSERT(nb0 <= nb1);
NE_ASSERT(nb1 <= nb2);
NE_ASSERT(nb2 <= nb3);
-
- NE_ASSERT(ne0 == ne01);
- NE_ASSERT(ne1 == ne11);
- NE_ASSERT(ne2 == ne02);
- NE_ASSERT(ne3 == ne03);
+ const int id = dst->op... | you can separate this function into another file like GEMM, ```layers/reduce/argsort.cpp``` and call std::sort instead |
neural-speed | github_2023 | cpp | 138 | intel | DDEle | @@ -347,17 +356,64 @@ static bool llama_model_eval_internal(model_context* ctx, const model_input* inp
// cur = cur*ffn_norm(broadcasted)
cur = ne_mul(ctx0, cur, model.layers[il].norm[1]);
}
-
- if (bestla_fusion_FFN_SiLu_f32f32_support(model.layers[il].ffn[0]->data, model.layers[il].ffn[1... | Probably it is unnecessary to explicitly build graph for `moe_out` as it is an operand of `ne_add` / used as cur later? |
neural-speed | github_2023 | cpp | 138 | intel | a32543254 | @@ -48,6 +48,7 @@ enum ne_op {
NE_OP_MUL_MAT,
NE_OP_MUL_MAT_BIAS,
+ NE_OP_MUL_MAT_ID, | what the difference between NE_OP_MUL_MAT_ID and NE_OP_MUL_MAT |
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