tasks/freepdk45/OpenRAM/cases/write_driver/problem.md

# Complementary SRAM Write Driver Layout Task

## Objective

Implement the supplied complementary tri-state write driver: with WEN=1, BL=DIN and BR=NOT DIN; with WEN=0, both outputs are disabled. Preserve authoritative netlist models, W/L, interface and connections; top cell is `write_driver`.

## Inputs and Interface

Ordered SPICE ports: `din bl br wen vdd gnd`. Names are case-insensitive, but different names are not interchangeable. Inputs are this description, `materials/circuit.spice` and `materials/testbench.spice`. The reviewed resource package supplies models and extraction resources; reference geometry and qualification evidence are not solver inputs.

## Operating Conditions

Use nominal FreePDK45 BSIM4 models at **1.0 V and 27 C**, with ground at 0 V. Every transistor has channel length 50 nm; widths and model types follow the netlist.

BL/BR each connect to 10 fF and a 100 kohm resistor to 0.5 V. DIN is initially low, rises at 500 ps and falls at 1 ns, with 10 ps edges and period 1 ns. WEN remains high until 2 ns, then falls over 10 ps. Sample complementary enabled outputs at 300 ps and 710 ps and both disabled outputs at 11.9 ns. Passive midpoint loads check high impedance through external ports; average DUT supply power over 0–2 ns.

The deck precisely defines stimuli and observation times, testing only through external ports. Validation covers these nominal conditions, excluding PVT, mismatch, array integration, substrate noise and manufacturing signoff.

## Physical Requirements

Submit a nonempty GDSII no larger than 10 MiB. Enable every check in the supplied KLayout DRC deck, including grid and antenna checks, without waivers. Strict LVS checks named ports, models, W/L and physical well/contact connectivity, with library-specific implicit or global power connections disabled. The upstream deck does not implement its documented spacing rule for wells at different potentials and does not provide complete foundry signoff.

The hard functional-outline limit is 100 um × 100 um. Its bounding box includes all functional geometry on drawing layers 1/0–29/0: active regions, wells, implants, threshold markers, poly, contacts, ten metal layers and nine via layers. Area is scored in um2. Keep functional geometry on these layers, excluding pin-purpose and annotation geometry. Electrical labels use poly or metal drawing layers (9/0, 11/0, 13/0, …, 29/0); nonelectrical annotation text is not extracted.

Translation, equivalent hierarchy and internal instance renaming are allowed. LVS permits source/drain exchange and equivalent parallel devices; the candidate must still pass the same RC electrical evaluation. Preserve top-level port identities and explicit body connections.

## Electrical Requirements and Scoring

Extract the candidate GDS only after file, DRC, LVS and geometry checks pass. Simulate its Magic RC netlist directly, with independent source simulation supplying the scoring baseline. Independent LVS first checks VTG/VTL device types, then uses the matching extraction configuration. Extraction includes poly/metal sheet resistance, contacts/vias, geometry-dependent coupling and ground capacitance, and device junction areas/perimeters. Wells use lumped connectivity; BSIM4 describes device and junction behavior. Interconnect RC uses estimated coefficients and native capacitance placement from the fixed community FreePDK45 Magic technology. The adapter binds VTG/VTL models, preserves annotation layers and corrects dimension-unit conversion. This is a predictive approximation without field-solver signoff accuracy.

Physical checks and the declared functional bounds must pass. Quality scoring imposes no fixed degradation allowance. Each `source_*` job and its corresponding candidate extracted circuit use exactly the same testbench, model resources, parameters, loads and measurement windows. Independent source observations remain required evidence; the quality targets below set the scoring anchors without depending on the submitted GDS. Reports retain every source/candidate pair.

Let x be the post-layout measurement and b the declared quality target, or the same-condition source measurement when no target is declared:

- Ratio normalization: maximize with q = x/b and minimize with q = b/x. When a numerical scale s is declared, use (x+s)/(b+s) and its reciprocal, respectively. The scale handles zero values as a normalization floor; it is neither an allowed degradation nor an acceptance bound.
- Amplitude in dB: maximize with q = 10^((x-b)/20) and minimize with its reciprocal.
- Target normalization: q = 1/(1+abs(x-b)/s), where s is the declared physical scale. Signed or zero-valued operating points are not divided directly.

Use `layout` scoring. First compute each metric's raw quality q from the worst paired condition, with raw area quality q_area = area_target / candidate_functional_area. Credit c_i = min(1, q_i) for every positively weighted metric, then compute S = 100 * product(c_i ** w_i). The weights sum to 1 and the score is bounded by 100. An improvement beyond one target cannot compensate for missing another target. Physical or functional rejection scores zero; missing or invalid measurements leave the score unknown, and zero-weight observations must also be valid. Reaching every positively weighted target scores 100; a feasible reference may score far below 100. Weights express quality tradeoffs, not acceptance bounds.

| Metric | Definition / observation | Unit | Quality normalization | Functional range | Scale |
| --- | --- | --- | --- | --- | --- |
| `bl_low` | `find v(bl) at=300p` | V | functional check | −∞ … 0.1 | — |
| `br_high` | `find v(br) at=300p` | V | functional check | 0.9 … +∞ | — |
| `bl_high` | `find v(bl) at=710p` | V | functional check | 0.9 … +∞ | — |
| `br_low` | `find v(br) at=710p` | V | functional check | −∞ … 0.1 | — |
| `z_bl` | `find v(bl) at=11.9n` | V | functional check | 0.45 … 0.55 | — |
| `z_br` | `find v(br) at=11.9n` | V | functional check | 0.45 … 0.55 | — |
| `supply` | `avg par('-v(vdd)*i(Vdd)') from=0 to=2n` | W | minimize / ratio | 0 … +∞ | 1e-12 |
| `data_delay` | Worst source-paired DIN-to-output delay over both directions: DIN rising to BL rising / BR falling at 0.5 V, and DIN falling to BL falling / BR rising at 0.5 V. | s | minimize / ratio | 0 … +∞ | — |

The area scoring target is **1.8 um2**. It is a continuous quality goal, not a hard limit, process minimum or a percentage of the current feasibility witness.

- `data_delay`: **7e-11 s**. Complete every enabled data-to-bitline transition within 70 ps under the declared 10 fF and 100 kohm loads.

The 1.8 um2 area goal rewards sharing in the two complementary tristate branches, without changing their 12 transistors. Delay receives 50% because four loaded transitions expose routing imbalance; area receives 40% and supply power 10%. The 70 ps timing goal is close to the slowest source transition (about 68 ps); disabled high-impedance behavior remains a functional check.

Quality targets do not impose additional functional cutoffs. Metrics without an explicit target retain their same-condition source anchors.

The capability coefficient is **3**, independent of this task's reference-normalized score.

### Score weights

| Metric | Weight |
| --- | ---: |
| `functional_area` | 0.4 |
| `data_delay` | 0.5 |
| `supply` | 0.1 |

## Tools and Submission

Solve budget: **1 hour**.

Use the reviewed FreePDK45 KLayout, Magic and ngspice resources in `/protocol/resources.json`. Magic RC extraction uses `/resources/support/magic-vtg/freepdk45.tech`, including model and unit adaptation. `/protocol/task.json` supplies consistent constraints, measurements and scoring; `/task` contains only declared inputs. Write `/workspace/output/final.gds`, then run `python -I /protocol/submit.py` to submit explicitly. If `process-feedback` is provided, intermediate checks use the frozen plan and backend identities; their snapshots are not final submissions.