Publish all 81 ICLayout-Bench tasks with core membership

.gitattributes

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 # Video files - compressed
 *.mp4 filter=lfs diff=lfs merge=lfs -text
 *.webm filter=lfs diff=lfs merge=lfs -text
+tasks/gf180mcuD/analog-db/cases/amp_004_folded_cascode/reference/amp_004_folded_cascode.gds filter=lfs diff=lfs merge=lfs -text
+tasks/gf180mcuD/analog-db/cases/amp_017_tan_clia/reference/amp_017_tan_clia.gds filter=lfs diff=lfs merge=lfs -text
+tasks/gf180mcuD/analog-db/cases/amp_019_ti_ldo_error/reference/amp_019_ti_ldo_error.gds filter=lfs diff=lfs merge=lfs -text
+tasks/gf180mcuD/analog-db/cases/amp_032_ti_ldo_error_selfbias/reference/amp_032_ti_ldo_error_selfbias.gds filter=lfs diff=lfs merge=lfs -text
+tasks/gf180mcuD/analog-db/cases/amp_033_ti_ldo_ref_selfbias/reference/amp_033_ti_ldo_ref_selfbias.gds filter=lfs diff=lfs merge=lfs -text
+tasks/gf180mcuD/analog-db/cases/cmfb_003_5t_nmos_input/reference/cmfb_003_5t_nmos_input.gds filter=lfs diff=lfs merge=lfs -text
+tasks/gf180mcuD/analog-db/cases/cmp_001_hyst_diffpair/reference/cmp_001_hyst_diffpair.gds filter=lfs diff=lfs merge=lfs -text
+tasks/gf180mcuD/analog-db/cases/cmp_002_strongarm/reference/cmp_002_strongarm.gds filter=lfs diff=lfs merge=lfs -text
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+tasks/gf180mcuD/analog-db/cases/ldo_003_analoggym_simple/reference/ldo_003_analoggym_simple.gds filter=lfs diff=lfs merge=lfs -text
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+tasks/gf180mcuD/analog-db/cases/ldo_007_pmos/reference/ldo_007_pmos.gds filter=lfs diff=lfs merge=lfs -text
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+tasks/gf180mcuD/analog-db/cases/tsn_001_ptat_2t/reference/tsn_001_ptat_2t.gds filter=lfs diff=lfs merge=lfs -text
+tasks/gf180mcuD/tt_tnt_gf_vco/cases/vco/reference/vco.gds filter=lfs diff=lfs merge=lfs -text
+tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/comparator/reference/DIFF_COMPARATOR.gds filter=lfs diff=lfs merge=lfs -text
+tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/full_OTA/reference/two_stage_OTA_layout.gds filter=lfs diff=lfs merge=lfs -text

LICENSE

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+MIT License
+
+Copyright (c) 2026 Layout-Bench contributors
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.

README.md

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+---
+language:
+- en
+tags:
+- integrated-circuits
+- electronic-design-automation
+- benchmark
+license: other
+license_name: component-specific
+license_link: https://huggingface.co/datasets/MAI716/ICLayout-Bench/blob/main/README.md#licensing
+configs:
+- config_name: default
+  data_files:
+  - split: test
+    path: data.jsonl
+---
+
+# ICLayout-Bench Dataset
+
+81 circuit-layout tasks across FreePDK45, GF180MCU and IHP SG13G2, for the
+[ICLayout-Bench evaluator](https://github.com/lizhangmai/ICLayout-Bench).
+Each task supplies a netlist, layout requirements, test stimuli, scoring contract
+and a reference layout. Available on [Hugging Face](https://huggingface.co/datasets/MAI716/ICLayout-Bench).
+
+## Load and select
+
+```python
+from datasets import load_dataset
+
+repo_id = "MAI716/ICLayout-Bench"
+tasks = load_dataset(repo_id, split="test")  # Complete corpus.
+core = tasks.filter(lambda task: task["in_core"])  # Current 16-task benchmark.
+print(tasks[0]["problem"])
+```
+
+`data.jsonl` contains every task, sorted by stable ID. The boolean `in_core`
+field is generated from the same field in each `case.toml`;
+changing this selection never removes tasks from the corpus. See the
+[selection rationale](#core-selection-rationale). Participant experiments can choose
+`name = "all"` and a `tasks` filter without changing core.
+
+Rows contain `id`, `in_core`, `title`, `category`, `summary`, `pdk`, `collection`, `task_kind`,
+`status`, `source_url`, `problem`, and relative paths/digests for task files,
+netlists, process declarations and licenses. The JSONL table is a generated view;
+`case.toml` owns task metadata and requirements.
+
+For assets, use a local checkout or `huggingface_hub.snapshot_download` with
+`repo_type="dataset"`. Pin the table and assets to the same repository commit
+using `revision` in both loading calls. A local checkout is also supported. When reloading an edited local checkout directly through
+`datasets`, pass `download_mode="reuse_cache_if_exists"` to refresh cached tables.
+
+## Contents
+
+```text
+tasks/<pdk>/
+  pdk.toml        # Pinned process resources and profiles
+  README.md       # Process scope and limitations, where documented
+  <collection>/
+    LICENSE         # Collection terms
+    NOTICE          # Required attribution, where applicable
+    cases/<case>/
+      case.toml       # Metadata, input identities and evaluation contract
+      problem.md      # Complete participant-facing requirements
+      materials/      # Netlist, test stimuli and declared presentation assets
+      reference/      # Reference layout; excluded from standard solver inputs
+data.jsonl        # Complete corpus with generated in_core membership
+```
+
+Source attribution is in `case.toml`; process and collection follow the directory
+hierarchy.
+
+## Licensing
+
+The root [LICENSE](LICENSE) covers original project metadata and documentation.
+Task materials retain the terms in each `tasks/<pdk>/<collection>/LICENSE` and,
+where present, `NOTICE`; the table exposes the corresponding license paths.
+Terms vary by collection, including noncommercial restrictions for analog-db
+materials. Retain applicable licenses, notices, source attribution and modification
+notices when redistributing materials. External PDKs and EDA tools have their own
+licenses. Technical qualification does not establish redistribution permission.
+
+## Scope and validation
+
+The problem and contract specify each task's operating points, physical checks,
+measurement definitions and score. Process scope for [GF180MCU](tasks/gf180mcuD/README.md) and
+[FreePDK45](tasks/freepdk45/README.md) describes resource assumptions and limitations. These are block-level benchmarks, not
+manufacturing signoff or evidence of model performance.
+
+The current core has passed direct reference evaluation, participant checking,
+final submission and numerical repeatability checks. The remaining corpus retains
+historical reference observations; these do not claim fresh three-path checks
+against the current evaluator. Full reports and acceptance records stay with the
+author. References are available for independent verification and are excluded
+from standard solver inputs.
+
+Install the evaluator separately to run a reference:
+
+```bash
+python -m benchmarking.engine.preview --dataset . run \
+  --case freepdk45.nangate45-pdk.NAND2_X1 --output build/reference-check
+```
+
+The command creates local reports under the requested output directory. Setup,
+index generation and publication checks are documented in the evaluator's
+[tools guide](https://github.com/lizhangmai/ICLayout-Bench/blob/main/docs/tools.md)
+and [task qualification guide](https://github.com/lizhangmai/ICLayout-Bench/blob/main/docs/tasks.md#qualification).
+
+## Core selection rationale
+
+The core is a secondary selection of the complete corpus, chosen for capability
+coverage. Its size is not a limit on the available tasks.
+
+<details>
+<summary>Detailed capabilities, alternatives and selection methodology</summary>
+
+
+Case-level `in_core` flags and scoring contracts own membership and weights. This document
+records the rationale for the secondary core selection from the full Dataset,
+independently of engine releases. All accepted tasks remain available in the default `test` table;
+being outside core does not mean a task is unfinished or excluded from Dataset.
+
+### Selected capabilities
+
+The current set contains 16 cases across three PDKs. Each link gives the full
+requirements and coefficient rationale.
+Coefficients below are the existing case coefficients, not new selection weights.
+
+| PDK | Selected case | Coefficient | Distinct contribution |
+| --- | --- | ---: | --- |
+| FreePDK45 | [NAND2](tasks/freepdk45/nangate45-pdk/cases/NAND2_X1/problem.md) | 1 | Basic connectivity, loaded logic levels and timing; an entry-level anchor. |
+| FreePDK45 | [SRAM write driver](tasks/freepdk45/OpenRAM/cases/write_driver/problem.md) | 3 | Complementary loaded outputs and enabled/disabled drive states. |
+| FreePDK45 | [6T SRAM cell](tasks/freepdk45/OpenRAM/cases/cell_6t/problem.md) | 6 | Storage integrity coupled to read and write access. |
+| GF180MCU | [Five-transistor OTA](tasks/gf180mcuD/Jianxun-OTA/cases/ota_5t/problem.md) | 4 | Compact differential gain and bias, with the declared dummy-device connectivity. |
+| GF180MCU | [Scan DFF](tasks/gf180mcuD/voidwalkers-scandff/cases/scan_dff/problem.md) | 5 | Clocked digital state and scan/data selection. |
+| GF180MCU | [R-2R DAC](tasks/gf180mcuD/gf-r2r-dac/cases/r2r/problem.md) | 4 | A physical resistor ladder: weighted conversion under zero, one-hot and full-scale codes. |
+| GF180MCU | [StrongARM comparator](tasks/gf180mcuD/analog-db/cases/cmp_002_strongarm/problem.md) | 6 | Regenerative decisions in both polarities at two input common modes, with precharge, delay and slew measurements. |
+| GF180MCU | [Classic PTAT](tasks/gf180mcuD/analog-db/cases/tsn_002_ptat_classic/problem.md) | 6 | Temperature-dependent bias, isolated body connections and a coupled startup branch. |
+| GF180MCU | [Basic PMOS LDO](tasks/gf180mcuD/analog-db/cases/ldo_004_basic_pmos/problem.md) | 7 | Intermediate regulation: PSRR, output impedance, dropout and recovery under changing load. |
+| GF180MCU | [Four-phase VCO](tasks/gf180mcuD/tt_tnt_gf_vco/cases/vco/problem.md) | 8 | Self-oscillation, tuning and relative output phases at two control voltages. |
+| IHP SG13G2 | [NMOS track-and-hold](tasks/ihp-sg13g2/analog-db/cases/smp_001_nmos_th/problem.md) | 5 | Physical charge storage, pedestal, drift, feedthrough and reacquisition across input/temperature conditions. |
+| IHP SG13G2 | [Binary capacitor bank](tasks/ihp-sg13g2/analog-db/cases/sw_003_binary_capbank/problem.md) | 5 | Physical 1:1:2:4 MIM weighting, eight fixed codes and parasitic-dependent gain/step accuracy. |
+| IHP SG13G2 | [SiGe PAM4 driver](tasks/ihp-sg13g2/analog-db/cases/drv_001_pam4_sige_dac/problem.md) | 4 | Weighted HBT current steering with gain and port-reflection observations extending to 50 GHz. |
+| IHP SG13G2 | [Fully differential two-stage OTA](tasks/ihp-sg13g2/analog-db/cases/amp_023_fer_fd2s/problem.md) | 9 | Coupled differential and common-mode control with compensation and transient response. |
+| IHP SG13G2 | [Mirror-OTA LDO](tasks/ihp-sg13g2/analog-db/cases/ldo_008_fer_mirror_ota/problem.md) | 9 | Complex regulation combining return-ratio crossings, startup, line/load response and recovery. |
+| IHP SG13G2 | [Chopper IA with CMFB](tasks/ihp-sg13g2/analog-db/cases/ia_006_fan_chopper_cmfb/problem.md) | 10 | Clock modulation, signal feedback and actual common-mode feedback operating together. |
+
+The coefficient bands 1–4, 5–7 and 8–10 contain five, seven and four cases,
+respectively. Their coefficient sums are 16, 40 and 36. This gives a compact
+foundation, substantial intermediate coverage and a smaller demanding tail.
+The RF driver remains coefficient 4 because its contract covers a compact
+feedforward circuit; its specialized devices and extraction flow do not make
+the coefficient an estimate of participant effort. Coefficients are capability
+categories, not a measured difficulty scale.
+
+### Boundaries and alternatives
+
+The five-transistor OTA and the fully differential OTA form a deliberate
+progression from compact gain/bias to interacting signal and common-mode loops.
+The two LDOs similarly distinguish intermediate regulation from a broader
+startup/return-ratio/recovery contract. Multiple compensated OTA variants and
+same-PDK LDO alternatives remain available in the full Dataset: topology diversity alone
+does not justify repeatedly weighting similar control objectives in the total.
+
+NAND2 supplies the basic logic anchor; AOI21 adds less incremental coverage than
+controlled drive, scan state and SRAM access. The separate SRAM sense amplifier
+overlaps the regenerative-decision capability represented by the StrongARM
+comparator. StrongARM is preferred over the other comparator cases for its
+explicit precharge, slew and two-common-mode measurements. The standalone
+chopper switch overlaps clock modulation in the complete chopper IA; the
+track-and-hold remains because retention and reacquisition are different goals.
+
+The resistor ladder and MIM bank exercise different passive networks. The MIM
+bank measures all eight fixed codes but does not evaluate live code switching
+or a complete SAR ADC. The resistor ladder samples ten codes, not a full
+256-code linearity sweep. Small gain stages, bias/reference cells, variable
+resistors, standalone CMFB blocks and simpler temperature cells remain useful
+focused exercises; their incremental coverage has lower priority in this core
+set than the selected complete circuits and their coupled requirements.
+
+The SiGe driver supplies explicitly measured high-frequency behavior. In
+particular, the case named `DC_to_130_GHz_TIA.design_1` currently measures AC
+behavior only through 100 MHz, so its name is not evidence of 130 GHz benchmark
+coverage. The selected driver uses KLayout-PEX capacitance extraction; it does
+not establish distributed interconnect resistance/inductance, eye quality or
+complete RF signoff. Likewise, the VCO contract does not measure phase noise or
+jitter. These limits apply when describing benchmark coverage.
+
+### Evidence and revision
+
+This selection is a structural coverage judgment grounded in published case
+contracts and validation associations. It does not yet establish empirical
+participant discrimination. Validate that separately with complete runs from
+multiple participants and repeated trials: compare per-case success rates,
+score spread, completion cost and correlations between related cases. Separate
+tool errors from physical/electrical failures; do not treat unknown scores as
+zero. A universally easy or hard case can still serve as an anchor, but it
+should not dominate the suite through redundant companions.
+
+Revisit membership when evidence shows redundant outcomes or a missing
+capability. Configuration and task-contract digests identify changes automatically; retain
+archived definitions and avoid tuning case coefficients to obtain a preferred
+ranking.
+
+</details>

tasks/freepdk45/OpenRAM/LICENSE

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+                       Version 3, 29 June 2007
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+Public License instead of this License.  But first, please read
+<http://www.gnu.org/philosophy/why-not-lgpl.html>.

tasks/freepdk45/OpenRAM/NOTICE

@@ -0,0 +1,28 @@
+OpenRAM FreePDK45 circuit notices
+
+Source: https://github.com/ferdous313/OpenRAM/tree/420a33e731d7d80bf9c7cd54ffbeec3603259847
+Selected circuit: technology/freepdk45/sp_lib/cell_6t.sp (cell_6t)
+The accompanying LICENSE is the source repository's GPL-3.0 license.
+Layout-Bench netlist modification: none to the SPICE bytes.
+The candidate reference GDS is a selected-cell export of technology/freepdk45/gds_lib/cell_6t.gds; Geometry and netlist are unchanged.
+No model files, Cadence technology files or Calibre SVRF are distributed here.
+FreePDK45 process collateral has separate upstream terms; the repository license
+must not be treated as a license grant for separately sourced PDK assets.
+
+Source: https://github.com/ferdous313/OpenRAM/tree/420a33e731d7d80bf9c7cd54ffbeec3603259847
+Selected circuit: technology/freepdk45/sp_lib/sense_amp.sp (sense_amp)
+The accompanying LICENSE is the source repository's GPL-3.0 license.
+Layout-Bench netlist modification: none to the SPICE bytes.
+The candidate reference GDS is a selected-cell export of technology/freepdk45/gds_lib/sense_amp.gds; Six overlapping duplicate contacts are removed; transistor geometry and circuit parameters are unchanged.
+No model files, Cadence technology files or Calibre SVRF are distributed here.
+FreePDK45 process collateral has separate upstream terms; the repository license
+must not be treated as a license grant for separately sourced PDK assets.
+
+Source: https://github.com/ferdous313/OpenRAM/tree/420a33e731d7d80bf9c7cd54ffbeec3603259847
+Selected circuit: technology/freepdk45/sp_lib/write_driver.sp (write_driver)
+The accompanying LICENSE is the source repository's GPL-3.0 license.
+Layout-Bench netlist modification: none to the SPICE bytes.
+The candidate reference GDS is a selected-cell export of technology/freepdk45/gds_lib/write_driver.gds; The enable label is wen, matching the authoritative SPICE port; conductor and transistor geometry are unchanged.
+No model files, Cadence technology files or Calibre SVRF are distributed here.
+FreePDK45 process collateral has separate upstream terms; the repository license
+must not be treated as a license grant for separately sourced PDK assets.

tasks/freepdk45/OpenRAM/cases/cell_6t/case.toml

@@ -0,0 +1,592 @@
+in_core = true
+kind = "layout_case"
+id = "freepdk45.OpenRAM.cell_6t"
+title = "Six-Transistor SRAM Bitcell"
+status = "qualified"
+
+[[assets]]
+path = "materials/schematic.svg"
+role = "schematic"
+visibility = "maintainer"
+format = "svg"
+sha256 = "38ce484f184eaac9f1ec0de9455efc1e4ef2b6ef27cd0e8a9176cebb9bc47329"
+
+[[assets]]
+path = "reference/cell_6t.gds"
+role = "reference"
+visibility = "maintainer"
+format = "gds"
+sha256 = "400d0f5640f07266e4b17b4d3d765ca04ffbabe03dd1122195f277e5ea558fdc"
+
+[task]
+hours = 3
+kind = "netlist_to_gds"
+family = "freepdk45_cell_6t"
+coefficient = 6
+environment = "freepdk45-nominal-predictive-rc"
+
+[task.inputs.description]
+path = "problem.md"
+sha256 = "89d9934e6f3bca7303ae3d06d6bd78f4aaf5791e9cf28be79888e6ffc4050e02"
+format = "text"
+
+[task.inputs.netlist]
+path = "materials/circuit.spice"
+sha256 = "18518f33516076c2bdca25c7036319734470c7757e3b1a2ab5c8e93b21fb4488"
+format = "spice"
+subcircuit = "cell_6t"
+
+[task.inputs.performance]
+path = "materials/testbench.spice"
+format = "spice"
+sha256 = "bc0034d4bde558134f21b5ad453623f4cd93862d8fe7761a1a8752ba21051006"
+
+[task.constraints]
+quality = [
+    { id = "area", type = "functional_bbox_area", layers_from = "outline" },
+]
+
+[[task.constraints.hard]]
+id = "outline"
+type = "bbox_max"
+functional_layers = [
+    [
+        1,
+        0,
+    ],
+    [
+        2,
+        0,
+    ],
+    [
+        3,
+        0,
+    ],
+    [
+        4,
+        0,
+    ],
+    [
+        5,
+        0,
+    ],
+    [
+        6,
+        0,
+    ],
+    [
+        7,
+        0,
+    ],
+    [
+        8,
+        0,
+    ],
+    [
+        9,
+        0,
+    ],
+    [
+        10,
+        0,
+    ],
+    [
+        11,
+        0,
+    ],
+    [
+        12,
+        0,
+    ],
+    [
+        13,
+        0,
+    ],
+    [
+        14,
+        0,
+    ],
+    [
+        15,
+        0,
+    ],
+    [
+        16,
+        0,
+    ],
+    [
+        17,
+        0,
+    ],
+    [
+        18,
+        0,
+    ],
+    [
+        19,
+        0,
+    ],
+    [
+        20,
+        0,
+    ],
+    [
+        21,
+        0,
+    ],
+    [
+        22,
+        0,
+    ],
+    [
+        23,
+        0,
+    ],
+    [
+        24,
+        0,
+    ],
+    [
+        25,
+        0,
+    ],
+    [
+        26,
+        0,
+    ],
+    [
+        27,
+        0,
+    ],
+    [
+        28,
+        0,
+    ],
+    [
+        29,
+        0,
+    ],
+]
+max_width_um = 100
+max_height_um = 100
+
+[task.output]
+path = "output/final.gds"
+format = "gds"
+top_cell = "cell_6t"
+max_bytes = 10485760
+
+[task.evaluation]
+mode = "post_layout"
+
+[[task.evaluation.jobs]]
+id = "artifact"
+stage = "check"
+operation = "layout.artifact"
+gate = "artifact"
+
+[task.evaluation.jobs.inputs]
+layout = "candidate"
+task = "task"
+
+[[task.evaluation.jobs]]
+id = "drc"
+stage = "check"
+operation = "layout.drc"
+gate = "drc"
+
+[task.evaluation.jobs.inputs]
+layout = "candidate"
+task = "task"
+
+[[task.evaluation.jobs]]
+id = "lvs"
+stage = "check"
+operation = "layout.lvs"
+gate = "lvs"
+
+[task.evaluation.jobs.inputs]
+layout = "candidate"
+task = "task"
+netlist = "input:netlist"
+
+[task.evaluation.jobs.outputs]
+database = "klayout-lvs"
+binding = "json"
+
+[[task.evaluation.jobs]]
+id = "geometry"
+stage = "check"
+operation = "layout.geometry"
+gate = "constraint"
+requires = [
+    "artifact",
+    "drc",
+    "lvs",
+]
+
+[task.evaluation.jobs.inputs]
+layout = "candidate"
+task = "task"
+constraints = "input:constraints"
+database = "job:lvs:database"
+binding = "job:lvs:binding"
+
+[[task.evaluation.jobs]]
+id = "parasitics"
+stage = "extract"
+operation = "layout.extract_rc"
+requires = [
+    "artifact",
+    "drc",
+    "lvs",
+    "geometry",
+]
+
+[task.evaluation.jobs.inputs]
+layout = "candidate"
+task = "task"
+
+[task.evaluation.jobs.outputs]
+netlist = "spice"
+
+[task.evaluation.jobs.parameters]
+ports = [
+    "bl",
+    "br",
+    "wl",
+    "vdd",
+    "gnd",
+]
+
+[[task.evaluation.jobs]]
+id = "nominal"
+stage = "simulate"
+operation = "circuit.simulate"
+
+[task.evaluation.jobs.inputs]
+deck = "input:performance"
+dut = "job:parasitics:netlist"
+
+[task.evaluation.jobs.outputs]
+waveform = "ngspice-raw"
+
+[task.evaluation.jobs.parameters.exports]
+waveform = "waveform.raw"
+
+[task.evaluation.jobs.parameters.measurements]
+read0 = "V"
+repeat0 = "V"
+read1 = "V"
+repeat1 = "V"
+supply = "W"
+read_delay_0_1 = "s"
+read_delay_0_2 = "s"
+read_delay_1_5 = "s"
+read_delay_1_6 = "s"
+
+[[task.evaluation.metrics]]
+id = "functional_area"
+category = "physical"
+observations = [
+    "geometry:area",
+]
+unit = "um2"
+direction = "minimize"
+aggregation = "max"
+
+[[task.evaluation.metrics]]
+id = "read0"
+category = "performance"
+observations = [
+    "nominal:read0",
+]
+unit = "V"
+direction = "maximize"
+aggregation = "min"
+lower = 0.3
+
+[[task.evaluation.metrics]]
+id = "repeat0"
+category = "performance"
+observations = [
+    "nominal:repeat0",
+]
+unit = "V"
+direction = "maximize"
+aggregation = "min"
+lower = 0.3
+
+[[task.evaluation.metrics]]
+id = "read1"
+category = "performance"
+observations = [
+    "nominal:read1",
+]
+unit = "V"
+direction = "maximize"
+aggregation = "min"
+lower = 0.3
+
+[[task.evaluation.metrics]]
+id = "repeat1"
+category = "performance"
+observations = [
+    "nominal:repeat1",
+]
+unit = "V"
+direction = "maximize"
+aggregation = "min"
+lower = 0.3
+
+[[task.evaluation.metrics]]
+id = "supply"
+category = "performance"
+observations = [
+    "nominal:supply",
+]
+unit = "W"
+direction = "minimize"
+aggregation = "max"
+dimension = "supply"
+baseline = [
+    "source_nominal:supply",
+]
+normalization = "ratio"
+lower = 0
+scale = 1e-12
+
+[[task.evaluation.metrics]]
+id = "read_delay"
+category = "performance"
+observations = [
+    "nominal:read_delay_0_1",
+    "nominal:read_delay_0_2",
+    "nominal:read_delay_1_5",
+    "nominal:read_delay_1_6",
+]
+baseline = [
+    "source_nominal:read_delay_0_1",
+    "source_nominal:read_delay_0_2",
+    "source_nominal:read_delay_1_5",
+    "source_nominal:read_delay_1_6",
+]
+unit = "s"
+direction = "minimize"
+aggregation = "max"
+dimension = "response"
+normalization = "ratio"
+lower = 0.0
+
+[task.evaluation.scoring]
+method = "layout"
+area_metric = "functional_area"
+area_target = 1.46
+rationale = "SRAM cell: read delay 64%; supply power 16%; area 20%. Each objective's weight is divided equally among its metrics."
+
+[task.evaluation.scoring.weights]
+functional_area = 0.2
+read_delay = 0.64
+supply = 0.16
+
+[task.evaluation.pre_layout]
+source_report_sha256 = "6910725e38dfe44770306a9966be0dd2bf875ecba4f0800cc29753c831e398d2"
+
+[task.evaluation.pre_layout.backends]
+"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"ef9cb87fa27b849376472663b7362673979b89e012f161ba47bb5f6af6ede8eb\", \"compatibility\": null, \"execution_sha256\": \"5424b579002782bfddf0a729715b8fbf2a5f7f2b4cf14982d7616e352d5de9be\", \"image_id\": \"sha256:6562558774d43c085a289bbba696c55959eb8051a0996f96633451fbeb9c652d\", \"limits\": {\"cpus\": 4, \"memory_mb\": 4096, \"pids\": 256}, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"7fc8a0cde0f7d722e87c34a1115c13986b3db8fecba4b7dadb0a1edf171df62b\", \"timeout_seconds\": 120.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}"
+
+[task.evaluation.pre_layout.jobs.source_nominal]
+operation = "circuit.simulate"
+
+[task.evaluation.pre_layout.jobs.source_nominal.inputs]
+deck = "input:performance"
+dut = "input:netlist"
+
+[task.evaluation.pre_layout.jobs.source_nominal.outputs]
+waveform = "ngspice-raw"
+
+[task.evaluation.pre_layout.jobs.source_nominal.parameters.exports]
+waveform = "waveform.raw"
+
+[task.evaluation.pre_layout.jobs.source_nominal.parameters.measurements]
+read0 = "V"
+repeat0 = "V"
+read1 = "V"
+repeat1 = "V"
+supply = "W"
+read_delay_0_1 = "s"
+read_delay_0_2 = "s"
+read_delay_1_5 = "s"
+read_delay_1_6 = "s"
+
+[task.evaluation.pre_layout.jobs.source_nominal.input_sha256]
+deck = "bc0034d4bde558134f21b5ad453623f4cd93862d8fe7761a1a8752ba21051006"
+dut = "18518f33516076c2bdca25c7036319734470c7757e3b1a2ab5c8e93b21fb4488"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.read0]
+value = 0.7858571
+unit = "V"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.read1]
+value = 0.7858571
+unit = "V"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.read_delay_0_1]
+value = 1.317565e-11
+unit = "s"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.read_delay_0_2]
+value = 1.317565e-11
+unit = "s"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.read_delay_1_5]
+value = 1.317565e-11
+unit = "s"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.read_delay_1_6]
+value = 1.317565e-11
+unit = "s"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.repeat0]
+value = 0.7858571
+unit = "V"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.repeat1]
+value = 0.7858571
+unit = "V"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.supply]
+value = 5.942012e-06
+unit = "W"
+
+[toolchain.backends.artifact]
+type = "klayout-docker"
+
+[toolchain.backends.artifact.settings]
+image = "iclayout-bench-tools:local"
+check = "artifact"
+timeout_seconds = 120
+
+[toolchain.backends.drc]
+type = "klayout-docker"
+
+[toolchain.backends.drc.settings]
+image = "iclayout-bench-tools:local"
+check = "drc"
+timeout_seconds = 120
+support = "build/support/freepdk45-klayout"
+profile = "drc.json"
+
+[toolchain.backends.drc.support_profiles]
+support = "klayout"
+
+[toolchain.backends.lvs]
+type = "klayout-docker"
+
+[toolchain.backends.lvs.settings]
+image = "iclayout-bench-tools:local"
+check = "lvs"
+timeout_seconds = 120
+support = "build/support/freepdk45-klayout"
+profile = "strict-lvs.json"
+
+[toolchain.backends.lvs.support_profiles]
+support = "klayout"
+
+[toolchain.backends.geometry]
+type = "klayout-geometry-docker"
+
+[toolchain.backends.geometry.settings]
+image = "iclayout-bench-tools:local"
+timeout_seconds = 60
+
+[toolchain.backends.rc]
+type = "magic-rc-docker"
+
+[toolchain.backends.rc.settings]
+image = "iclayout-bench-tools:local"
+support = "build/support/freepdk45-magic-vtg"
+technology = "freepdk45.tech"
+tech_name = "freepdk45"
+style = "spice3(sim)"
+gds_readonly = false
+case_insensitive_ports = true
+label_layers = [
+    [
+        9,
+        0,
+    ],
+    [
+        11,
+        0,
+    ],
+    [
+        13,
+        0,
+    ],
+    [
+        15,
+        0,
+    ],
+    [
+        17,
+        0,
+    ],
+    [
+        19,
+        0,
+    ],
+    [
+        21,
+        0,
+    ],
+    [
+        23,
+        0,
+    ],
+    [
+        25,
+        0,
+    ],
+    [
+        27,
+        0,
+    ],
+    [
+        29,
+        0,
+    ],
+]
+timeout_seconds = 120
+
+[toolchain.backends.rc.support_profiles]
+support = "magic-vtg"
+
+[toolchain.backends.ngspice]
+type = "ngspice-docker"
+
+[toolchain.backends.ngspice.settings]
+image = "iclayout-bench-tools:local"
+support = "build/support/freepdk45-models"
+timeout_seconds = 120
+
+[toolchain.backends.ngspice.support_profiles]
+support = "models"
+
+[toolchain.bindings]
+"layout.artifact" = "artifact"
+"layout.drc" = "drc"
+"layout.lvs" = "lvs"
+"layout.geometry" = "geometry"
+"layout.extract_rc" = "rc"
+"circuit.simulate" = "ngspice"
+
+[qualification]
+reference = "reference/cell_6t.gds"
+
+[origin]
+url = "https://github.com/ferdous313/OpenRAM/blob/420a33e731d7d80bf9c7cd54ffbeec3603259847/technology/freepdk45/sp_lib/cell_6t.sp"
+
+[presentation]
+category = "Logic & memory"
+summary = "Stores one bit using cross-coupled inverters and wordline-controlled access transistors."

tasks/freepdk45/OpenRAM/cases/cell_6t/materials/circuit.spice

@@ -0,0 +1,10 @@
+
+.SUBCKT cell_6t bl br wl vdd gnd
+MM3 bl wl net10 gnd NMOS_VTG W=135.00n L=50n
+MM2 br wl net4 gnd NMOS_VTG W=135.00n L=50n 
+MM1 net10 net4 gnd gnd NMOS_VTG W=205.00n L=50n 
+MM0 net4 net10 gnd gnd NMOS_VTG W=205.00n L=50n 
+MM5 net10 net4 vdd vdd PMOS_VTG W=90n L=50n 
+MM4 net4 net10 vdd vdd PMOS_VTG W=90n L=50n 
+.ENDS cell_6t
+

tasks/freepdk45/OpenRAM/cases/cell_6t/materials/testbench.spice

@@ -0,0 +1,41 @@
+* cell_6t nominal characterization
+.include /workspace/support/models.spice
+.include dut.spice
+.temp 27
+Vdd vdd 0 1
+Xdut BL BR WL vdd gnd cell_6t
+.model sw SW(Ron=10 Roff=1e12 Vt=.5 Vh=0)
+Cbl bl 0 10f
+Cbr br 0 10f
+Vdata data 0 PWL(0 0 4n 0 4.01n 1)
+Bbar bar 0 v=1-v(data)
+Vwrite wr 0 PWL(0 1 500p 1 510p 0 4n 0 4.01n 1 4.5n 1 4.51n 0)
+Swl bl data wr 0 sw
+Swr br bar wr 0 sw
+Vpre pre 0 PWL(0 0 600p 0 610p 1 990p 1 1n 0 1.5n 0 1.51n 1 1.99n 1 2n 0 4.6n 0 4.61n 1 4.99n 1 5n 0 5.5n 0 5.51n 1 5.99n 1 6n 0)
+Spl bl vdd pre 0 sw
+Spr br vdd pre 0 sw
+Vwl wl 0 PWL(0 1 490p 1 500p 0 1n 0 1.01n 1 1.3n 1 1.31n 0 2n 0 2.01n 1 2.3n 1 2.31n 0 4n 0 4.02n 1 4.49n 1 4.5n 0 5n 0 5.01n 1 5.3n 1 5.31n 0 6n 0 6.01n 1 6.3n 1 6.31n 0)
+Bdiff0 diff0 0 v=v(br)-v(bl)
+Bdiff1 diff1 0 v=v(bl)-v(br)
+.tran 1p 7n
+.meas tran read0 find par('v(br)-v(bl)') at=1110p
+.meas tran repeat0 find par('v(br)-v(bl)') at=2110p
+.meas tran read1 find par('v(bl)-v(br)') at=5110p
+.meas tran repeat1 find par('v(bl)-v(br)') at=6110p
+.meas tran supply avg par('-v(vdd)*i(Vdd)') from=0 to=7n
+
+.meas tran read_delay_0_1 trig v(wl) val=.5 rise=1 td=1n targ v(diff0) val=.1 rise=1 td=1n
+
+.meas tran read_delay_0_2 trig v(wl) val=.5 rise=1 td=2n targ v(diff0) val=.1 rise=1 td=2n
+
+.meas tran read_delay_1_5 trig v(wl) val=.5 rise=1 td=5n targ v(diff1) val=.1 rise=1 td=5n
+
+.meas tran read_delay_1_6 trig v(wl) val=.5 rise=1 td=6n targ v(diff1) val=.1 rise=1 td=6n
+
+.control
+run
+write waveform.raw v(bl) v(br) v(wl) v(vdd) i(Vdd)
+quit
+.endc
+.end

tasks/freepdk45/OpenRAM/cases/cell_6t/problem.md

@@ -0,0 +1,85 @@
+# Six-Transistor SRAM Bitcell Layout Task
+
+## Objective
+
+Implement the supplied six-transistor SRAM bitcell, including cross-coupled storage, complementary bitlines and a common wordline. Preserve the authoritative netlist's model classes, W/L, interface and connectivity. Submit top cell `cell_6t`.
+
+## Inputs and Interface
+
+Ordered SPICE ports: `bl br wl vdd gnd`. Names are case-insensitive; different names are not interchangeable. The delivered inputs are this problem, `materials/circuit.spice`, and `materials/testbench.spice`. The model and extraction resources are supplied as reviewed support bundles. Reference geometry and qualification evidence are maintainer materials, excluded from solver inputs.
+
+## Operating Conditions
+
+Use the nominal FreePDK45 BSIM4 models at **1.0 V and 27 C**, with ground at 0 V. All transistor lengths are 50 nm; widths and model classes come from the netlist.
+
+Each bitline has 10 fF. Ideal external switches (10 ohm on, 1e12 ohm off) implement write and precharge. Write BL=0/BR=1 during 0–500 ps, then precharge and read at 1 ns and 2 ns; write the opposite value at 4–4.5 ns, then read at 5 ns and 6 ns. Sample differential bitline voltage 110 ps after each read starts. Wordline transitions take 10 ps; read pulses last 300 ps. The second read checks retention after a nondestructive read and idle interval. The supplied deck gives every switch edge. Power includes DUT supply current and the precharge supply over 0–7 ns.
+
+The deck defines stimuli and observation times exactly. Tests use only external ports. Qualification covers these nominal conditions, not PVT, mismatch, array abutment, substrate noise or manufacturing signoff.
+
+## Physical Requirements
+
+Submit a nonempty GDSII of at most 10 MiB. Enable all checks present in the supplied KLayout DRC deck, including grid and antenna checks, with no waivers. Strict LVS checks named ports, models, W/L and actual well/tap connectivity; library-specific implicit or global rail connections are disabled. The upstream deck does not implement its documented different-potential well-spacing rule; it is not a complete foundry signoff deck.
+
+The hard functional envelope is 100 um by 100 um. Its bounding rectangle includes every drawing layer 1/0 through 29/0: active, wells, implants, threshold markers, poly, contacts, all ten metals and all nine vias. It supplies the scored footprint in um2. Put functional geometry on these layers; pin-purpose and annotation geometry is excluded. Electrical labels use poly or metal drawing layers (9/0 and 11/0, 13/0, ..., 29/0). Non-electrical annotation text is ignored by extraction.
+
+Translation, equivalent hierarchy and internal instance renaming are allowed. LVS permits source/drain exchange and equivalent parallel devices; any such layout must also pass the same RC-based electrical requirements. Preserve top-level port identities and explicit body connections.
+
+## Electrical Requirements and Scoring
+
+Artifact, DRC, LVS and geometry gates precede candidate GDS extraction. Simulation consumes the candidate's Magic RC netlist unchanged; source simulation supplies the independent scoring baseline. VTG/VTL device classes are checked by independent LVS before the matching extraction profile is used. Extraction includes poly/metal sheet resistance, contacts/vias, geometry-dependent coupling and ground capacitance, and device junction area/perimeter. Wells are lumped connections; BSIM4 supplies device/junction behavior. Interconnect resistance and capacitance use the pinned community FreePDK45 Magic technology's estimated coefficients and native capacitance placement. The extraction adapter binds VTG/VTL models, preserves annotation layers and corrects the technology's dimensional unit conversion. This is a predictive approximation without field-solver signoff accuracy.
+
+Physical checks and declared functional bounds remain mandatory. Quality has no
+fixed allowed-degradation threshold. Each `source_*` job simulates the declared
+source circuit with exactly the same testbench, model resources, parameters,
+load and measurement window as its paired extracted-candidate job. A source
+observation is the 100-point electrical baseline; it is independent of the
+submitted GDS. All individual pairs are retained in the evaluation report.
+
+For a post-layout observation x and its source observation b:
+
+- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,
+  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;
+  s is a normalization floor, not an allowed degradation or pass threshold.
+- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.
+- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and
+  zero-valued operating points are never divided directly.
+
+Scoring uses `layout`. A metric uses its worst paired quality q. The score is
+S = 100 * product(q_i ** w_i), including area quality
+q_area = area_reference / candidate_functional_area. The weights below sum to
+one. Dimensions describe measurements but do not determine their weights.
+Physical or functional rejection scores zero; missing or invalid measurements
+produce an unknown score, including measurements with zero weight.
+Source-equivalent performance at the area reference scores 100; improvements
+can exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.
+
+| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale |
+| --- | --- | --- | --- | --- | --- |
+| `read0` | `find par('v(br)-v(bl)') at=1110p` | V | functional check | 0.3 … +∞ | — |
+| `repeat0` | `find par('v(br)-v(bl)') at=2110p` | V | functional check | 0.3 … +∞ | — |
+| `read1` | `find par('v(bl)-v(br)') at=5110p` | V | functional check | 0.3 … +∞ | — |
+| `repeat1` | `find par('v(bl)-v(br)') at=6110p` | V | functional check | 0.3 … +∞ | — |
+| `supply` | `avg par('-v(vdd)*i(Vdd)') from=0 to=7n` | W | minimize / ratio | 0 … +∞ | 1e-12 |
+| `read_delay` | WL rising through 0.5 V to signed bitline difference reaching 0.1 V, for read edges at 1, 2, 5 and 6 ns (distinct from the 0.3 V sampled-level requirement). | s | minimize / ratio | 0 … +∞ | — |
+
+Area reference: **1.46 um2**. 6 expanded device instances; sum of device/contact envelopes 0.6670 um2, per-side envelope allowance 0.12 um, 50% routing allowance and total outer width/height allowance 0.24 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.
+
+The capability coefficient remains **6**; it is independent of
+the reference-relative task score.
+
+
+### Score weights
+
+SRAM cell: read delay 64%; supply power 16%; area 20%. Each objective's weight is divided equally among its metrics.
+
+| Metric | Weight |
+| --- | ---: |
+| `functional_area` | 0.2 |
+| `read_delay` | 0.640000000000 |
+| `supply` | 0.160000000000 |
+
+## Tools and Submission
+
+Solve budget: **3 hours**.
+
+Use the reviewed FreePDK45 KLayout, Magic and ngspice resources from `/protocol/resources.json`. For Magic RC extraction, use `/resources/support/magic-vtg/freepdk45.tech`, which includes the required model and unit adaptations. Runtime `/protocol/task.json` publishes the same constraints, measurements and scoring. Only declared inputs appear under `/task`. Write `/workspace/output/final.gds`, then explicitly submit with `python -I /protocol/submit.py`. A harness that declares `process-feedback` uses the same frozen plan and backend identities for process checks; those snapshots do not count as final submissions.

tasks/freepdk45/OpenRAM/cases/sense_amp/case.toml

@@ -0,0 +1,535 @@
+in_core = false
+kind = "layout_case"
+id = "freepdk45.OpenRAM.sense_amp"
+title = "Clocked SRAM Sense Amplifier"
+status = "qualified"
+
+[[assets]]
+path = "materials/schematic.svg"
+role = "schematic"
+visibility = "maintainer"
+format = "svg"
+sha256 = "a1d1470e1bc4f21f8e205ff75a416e5aaedd678159f003c35e9fdc10a098ce4e"
+
+[[assets]]
+path = "reference/sense_amp.gds"
+role = "reference"
+visibility = "maintainer"
+format = "gds"
+sha256 = "07b246b1f11d26f2bb268c6f60f2f93b90b91228d479c7af3fa831431df8ffaa"
+
+[task]
+hours = 3
+kind = "netlist_to_gds"
+family = "freepdk45_sense_amp"
+coefficient = 5
+environment = "freepdk45-nominal-predictive-rc"
+
+[task.inputs.description]
+path = "problem.md"
+sha256 = "4d05195bfe1882c03fd03769b23822a985e73985f95227f93e213a6887980ac4"
+format = "text"
+
+[task.inputs.netlist]
+path = "materials/circuit.spice"
+sha256 = "f5a25305dc9184f778cad474f697091f37bfc8b30cf045e46306ce0927c5565f"
+format = "spice"
+subcircuit = "sense_amp"
+
+[task.inputs.performance]
+path = "materials/testbench.spice"
+format = "spice"
+sha256 = "1d96a4f3ff79ab3e154911210b637de1419e5572e31aabe6e98550f381edb761"
+
+[task.constraints]
+quality = [
+    { id = "area", type = "functional_bbox_area", layers_from = "outline" },
+]
+
+[[task.constraints.hard]]
+id = "outline"
+type = "bbox_max"
+functional_layers = [
+    [
+        1,
+        0,
+    ],
+    [
+        2,
+        0,
+    ],
+    [
+        3,
+        0,
+    ],
+    [
+        4,
+        0,
+    ],
+    [
+        5,
+        0,
+    ],
+    [
+        6,
+        0,
+    ],
+    [
+        7,
+        0,
+    ],
+    [
+        8,
+        0,
+    ],
+    [
+        9,
+        0,
+    ],
+    [
+        10,
+        0,
+    ],
+    [
+        11,
+        0,
+    ],
+    [
+        12,
+        0,
+    ],
+    [
+        13,
+        0,
+    ],
+    [
+        14,
+        0,
+    ],
+    [
+        15,
+        0,
+    ],
+    [
+        16,
+        0,
+    ],
+    [
+        17,
+        0,
+    ],
+    [
+        18,
+        0,
+    ],
+    [
+        19,
+        0,
+    ],
+    [
+        20,
+        0,
+    ],
+    [
+        21,
+        0,
+    ],
+    [
+        22,
+        0,
+    ],
+    [
+        23,
+        0,
+    ],
+    [
+        24,
+        0,
+    ],
+    [
+        25,
+        0,
+    ],
+    [
+        26,
+        0,
+    ],
+    [
+        27,
+        0,
+    ],
+    [
+        28,
+        0,
+    ],
+    [
+        29,
+        0,
+    ],
+]
+max_width_um = 100
+max_height_um = 100
+
+[task.output]
+path = "output/final.gds"
+format = "gds"
+top_cell = "sense_amp"
+max_bytes = 10485760
+
+[task.evaluation]
+mode = "post_layout"
+
+[[task.evaluation.jobs]]
+id = "artifact"
+stage = "check"
+operation = "layout.artifact"
+gate = "artifact"
+
+[task.evaluation.jobs.inputs]
+layout = "candidate"
+task = "task"
+
+[[task.evaluation.jobs]]
+id = "drc"
+stage = "check"
+operation = "layout.drc"
+gate = "drc"
+
+[task.evaluation.jobs.inputs]
+layout = "candidate"
+task = "task"
+
+[[task.evaluation.jobs]]
+id = "lvs"
+stage = "check"
+operation = "layout.lvs"
+gate = "lvs"
+
+[task.evaluation.jobs.inputs]
+layout = "candidate"
+task = "task"
+netlist = "input:netlist"
+
+[task.evaluation.jobs.outputs]
+database = "klayout-lvs"
+binding = "json"
+
+[[task.evaluation.jobs]]
+id = "geometry"
+stage = "check"
+operation = "layout.geometry"
+gate = "constraint"
+requires = [
+    "artifact",
+    "drc",
+    "lvs",
+]
+
+[task.evaluation.jobs.inputs]
+layout = "candidate"
+task = "task"
+constraints = "input:constraints"
+database = "job:lvs:database"
+binding = "job:lvs:binding"
+
+[[task.evaluation.jobs]]
+id = "parasitics"
+stage = "extract"
+operation = "layout.extract_rc"
+requires = [
+    "artifact",
+    "drc",
+    "lvs",
+    "geometry",
+]
+
+[task.evaluation.jobs.inputs]
+layout = "candidate"
+task = "task"
+
+[task.evaluation.jobs.outputs]
+netlist = "spice"
+
+[task.evaluation.jobs.parameters]
+ports = [
+    "bl",
+    "br",
+    "dout",
+    "sclk",
+    "vdd",
+    "gnd",
+]
+
+[[task.evaluation.jobs]]
+id = "nominal"
+stage = "simulate"
+operation = "circuit.simulate"
+
+[task.evaluation.jobs.inputs]
+deck = "input:performance"
+dut = "job:parasitics:netlist"
+
+[task.evaluation.jobs.outputs]
+waveform = "ngspice-raw"
+
+[task.evaluation.jobs.parameters.exports]
+waveform = "waveform.raw"
+
+[task.evaluation.jobs.parameters.measurements]
+low = "V"
+high = "V"
+supply = "W"
+decision_delay_fall = "s"
+
+[[task.evaluation.metrics]]
+id = "functional_area"
+category = "physical"
+observations = [
+    "geometry:area",
+]
+unit = "um2"
+direction = "minimize"
+aggregation = "max"
+
+[[task.evaluation.metrics]]
+id = "low"
+category = "performance"
+observations = [
+    "nominal:low",
+]
+unit = "V"
+direction = "minimize"
+aggregation = "max"
+upper = 0.1
+
+[[task.evaluation.metrics]]
+id = "high"
+category = "performance"
+observations = [
+    "nominal:high",
+]
+unit = "V"
+direction = "maximize"
+aggregation = "min"
+lower = 0.9
+
+[[task.evaluation.metrics]]
+id = "supply"
+category = "performance"
+observations = [
+    "nominal:supply",
+]
+unit = "W"
+direction = "minimize"
+aggregation = "max"
+dimension = "supply"
+baseline = [
+    "source_nominal:supply",
+]
+normalization = "ratio"
+lower = 0
+scale = 1e-12
+
+[[task.evaluation.metrics]]
+id = "decision_delay_fall"
+category = "performance"
+observations = [
+    "nominal:decision_delay_fall",
+]
+baseline = [
+    "source_nominal:decision_delay_fall",
+]
+unit = "s"
+direction = "minimize"
+aggregation = "max"
+dimension = "response"
+normalization = "ratio"
+lower = 0.0
+
+[task.evaluation.scoring]
+method = "layout"
+area_metric = "functional_area"
+area_target = 2.82
+rationale = "SRAM periphery: peripheral delay 68%; supply power 17%; area 15%. Each objective's weight is divided equally among its metrics."
+
+[task.evaluation.scoring.weights]
+functional_area = 0.15
+decision_delay_fall = 0.68
+supply = 0.17
+
+[task.evaluation.pre_layout]
+source_report_sha256 = "092e85048c56d9acc523fdb6eb8b64acff106fcd5fb777345c691b5dede84ef7"
+
+[task.evaluation.pre_layout.backends]
+"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"ef9cb87fa27b849376472663b7362673979b89e012f161ba47bb5f6af6ede8eb\", \"compatibility\": null, \"execution_sha256\": \"5424b579002782bfddf0a729715b8fbf2a5f7f2b4cf14982d7616e352d5de9be\", \"image_id\": \"sha256:6562558774d43c085a289bbba696c55959eb8051a0996f96633451fbeb9c652d\", \"limits\": {\"cpus\": 4, \"memory_mb\": 4096, \"pids\": 256}, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"7fc8a0cde0f7d722e87c34a1115c13986b3db8fecba4b7dadb0a1edf171df62b\", \"timeout_seconds\": 120.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}"
+
+[task.evaluation.pre_layout.jobs.source_nominal]
+operation = "circuit.simulate"
+
+[task.evaluation.pre_layout.jobs.source_nominal.inputs]
+deck = "input:performance"
+dut = "input:netlist"
+
+[task.evaluation.pre_layout.jobs.source_nominal.outputs]
+waveform = "ngspice-raw"
+
+[task.evaluation.pre_layout.jobs.source_nominal.parameters.exports]
+waveform = "waveform.raw"
+
+[task.evaluation.pre_layout.jobs.source_nominal.parameters.measurements]
+low = "V"
+high = "V"
+supply = "W"
+decision_delay_fall = "s"
+
+[task.evaluation.pre_layout.jobs.source_nominal.input_sha256]
+deck = "1d96a4f3ff79ab3e154911210b637de1419e5572e31aabe6e98550f381edb761"
+dut = "f5a25305dc9184f778cad474f697091f37bfc8b30cf045e46306ce0927c5565f"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.decision_delay_fall]
+value = 1.248627e-11
+unit = "s"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.high]
+value = 0.999996
+unit = "V"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.low]
+value = 2.338873e-05
+unit = "V"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.supply]
+value = 1.395456e-06
+unit = "W"
+
+[toolchain.backends.artifact]
+type = "klayout-docker"
+
+[toolchain.backends.artifact.settings]
+image = "iclayout-bench-tools:local"
+check = "artifact"
+timeout_seconds = 120
+
+[toolchain.backends.drc]
+type = "klayout-docker"
+
+[toolchain.backends.drc.settings]
+image = "iclayout-bench-tools:local"
+check = "drc"
+timeout_seconds = 120
+support = "build/support/freepdk45-klayout"
+profile = "drc.json"
+
+[toolchain.backends.drc.support_profiles]
+support = "klayout"
+
+[toolchain.backends.lvs]
+type = "klayout-docker"
+
+[toolchain.backends.lvs.settings]
+image = "iclayout-bench-tools:local"
+check = "lvs"
+timeout_seconds = 120
+support = "build/support/freepdk45-klayout"
+profile = "strict-lvs.json"
+
+[toolchain.backends.lvs.support_profiles]
+support = "klayout"
+
+[toolchain.backends.geometry]
+type = "klayout-geometry-docker"
+
+[toolchain.backends.geometry.settings]
+image = "iclayout-bench-tools:local"
+timeout_seconds = 60
+
+[toolchain.backends.rc]
+type = "magic-rc-docker"
+
+[toolchain.backends.rc.settings]
+image = "iclayout-bench-tools:local"
+support = "build/support/freepdk45-magic-vtg"
+technology = "freepdk45.tech"
+tech_name = "freepdk45"
+style = "spice3(sim)"
+gds_readonly = false
+case_insensitive_ports = true
+label_layers = [
+    [
+        9,
+        0,
+    ],
+    [
+        11,
+        0,
+    ],
+    [
+        13,
+        0,
+    ],
+    [
+        15,
+        0,
+    ],
+    [
+        17,
+        0,
+    ],
+    [
+        19,
+        0,
+    ],
+    [
+        21,
+        0,
+    ],
+    [
+        23,
+        0,
+    ],
+    [
+        25,
+        0,
+    ],
+    [
+        27,
+        0,
+    ],
+    [
+        29,
+        0,
+    ],
+]
+timeout_seconds = 120
+
+[toolchain.backends.rc.support_profiles]
+support = "magic-vtg"
+
+[toolchain.backends.ngspice]
+type = "ngspice-docker"
+
+[toolchain.backends.ngspice.settings]
+image = "iclayout-bench-tools:local"
+support = "build/support/freepdk45-models"
+timeout_seconds = 120
+
+[toolchain.backends.ngspice.support_profiles]
+support = "models"
+
+[toolchain.bindings]
+"layout.artifact" = "artifact"
+"layout.drc" = "drc"
+"layout.lvs" = "lvs"
+"layout.geometry" = "geometry"
+"layout.extract_rc" = "rc"
+"circuit.simulate" = "ngspice"
+
+[qualification]
+reference = "reference/sense_amp.gds"
+
+[origin]
+url = "https://github.com/ferdous313/OpenRAM/blob/420a33e731d7d80bf9c7cd54ffbeec3603259847/technology/freepdk45/sp_lib/sense_amp.sp"
+
+[presentation]
+category = "Logic & memory"
+summary = "Resolves a small bitline voltage difference into a clocked digital decision."

tasks/freepdk45/OpenRAM/cases/sense_amp/materials/circuit.spice

@@ -0,0 +1,11 @@
+
+.SUBCKT sense_amp bl br dout sclk vdd gnd
+M_1 dout net_1 vdd vdd pmos_vtg w=540.0n l=50.0n
+M_3 net_1 dout vdd vdd pmos_vtg w=540.0n l=50.0n
+M_2 dout net_1 net_2 gnd nmos_vtg w=270.0n l=50.0n
+M_8 net_1 dout net_2 gnd nmos_vtg w=270.0n l=50.0n
+M_5 bl sclk dout vdd pmos_vtg w=720.0n l=50.0n
+M_6 br sclk net_1 vdd pmos_vtg w=720.0n l=50.0n
+M_7 net_2 sclk gnd gnd nmos_vtg w=270.0n l=50.0n
+.ENDS sense_amp
+

tasks/freepdk45/OpenRAM/cases/sense_amp/materials/testbench.spice

@@ -0,0 +1,24 @@
+* sense_amp nominal characterization
+.include /workspace/support/models.spice
+.include dut.spice
+.temp 27
+Vdd vdd 0 1
+Xdut BL BR Dout SCLK vdd gnd sense_amp
+Vbl bl 0 PWL(0 .8 1n .8 1.01n 1)
+Vbr br 0 PWL(0 1 1n 1 1.01n .8)
+Vs sclk 0 PULSE(0 1 500p 10p 10p 480p 1n)
+Cl dout 0 .5f
+.tran 0.5p 2n
+.meas tran low find v(dout) at=610p
+.meas tran high find v(dout) at=1610p
+.meas tran supply avg par('-v(vdd)*i(Vdd)') from=0 to=2n
+
+.meas tran decision_delay_fall trig v(sclk) val=.5 rise=1 td=0.5n targ v(dout) val=.5 fall=1 td=0.5n
+
+
+.control
+run
+write waveform.raw v(bl) v(br) v(dout) v(sclk) v(vdd) i(Vdd)
+quit
+.endc
+.end

tasks/freepdk45/OpenRAM/cases/sense_amp/problem.md

@@ -0,0 +1,87 @@
+# Clocked SRAM Sense Amplifier Layout Task
+
+## Objective
+
+Implement the supplied clocked regenerative sense amplifier. A lower sampled BL than BR must produce a low Dout; the opposite differential must produce a high Dout. Preserve the authoritative netlist's model classes, W/L, interface and connectivity. Submit top cell `sense_amp`.
+
+## Inputs and Interface
+
+Ordered SPICE ports: `bl br dout sclk vdd gnd`. Names are case-insensitive; different names are not interchangeable. The delivered inputs are this problem, `materials/circuit.spice`, and `materials/testbench.spice`. The model and extraction resources are supplied as reviewed support bundles. Reference geometry and qualification evidence are maintainer materials, excluded from solver inputs.
+
+## Operating Conditions
+
+Use the nominal FreePDK45 BSIM4 models at **1.0 V and 27 C**, with ground at 0 V. All transistor lengths are 50 nm; widths and model classes come from the netlist.
+
+BL/BR are 0.8/1.0 V for the first decision and 1.0/0.8 V for the second. SCLK is low while sampling and rises at 500 ps and 1500 ps with 10 ps edges; it stays high for 480 ps. Dout drives 0.5 fF. Sample Dout at 610 ps and 1610 ps. Average supply power over 0–2 ns. This is a 200 mV differential, loaded decision task; 50 mV sensitivity is not specified.
+
+The deck defines stimuli and observation times exactly. Tests use only external ports. Qualification covers these nominal conditions, not PVT, mismatch, array abutment, substrate noise or manufacturing signoff.
+
+## Physical Requirements
+
+Submit a nonempty GDSII of at most 10 MiB. Enable all checks present in the supplied KLayout DRC deck, including grid and antenna checks, with no waivers. Strict LVS checks named ports, models, W/L and actual well/tap connectivity; library-specific implicit or global rail connections are disabled. The upstream deck does not implement its documented different-potential well-spacing rule; it is not a complete foundry signoff deck.
+
+The hard functional envelope is 100 um by 100 um. Its bounding rectangle includes every drawing layer 1/0 through 29/0: active, wells, implants, threshold markers, poly, contacts, all ten metals and all nine vias. It supplies the scored footprint in um2. Put functional geometry on these layers; pin-purpose and annotation geometry is excluded. Electrical labels use poly or metal drawing layers (9/0 and 11/0, 13/0, ..., 29/0). Non-electrical annotation text is ignored by extraction.
+
+Translation, equivalent hierarchy and internal instance renaming are allowed. LVS permits source/drain exchange and equivalent parallel devices; any such layout must also pass the same RC-based electrical requirements. Preserve top-level port identities and explicit body connections.
+
+## Electrical Requirements and Scoring
+
+Artifact, DRC, LVS and geometry gates precede candidate GDS extraction. Simulation consumes the candidate's Magic RC netlist unchanged; source simulation supplies the independent scoring baseline. VTG/VTL device classes are checked by independent LVS before the matching extraction profile is used. Extraction includes poly/metal sheet resistance, contacts/vias, geometry-dependent coupling and ground capacitance, and device junction area/perimeter. Wells are lumped connections; BSIM4 supplies device/junction behavior. Interconnect resistance and capacitance use the pinned community FreePDK45 Magic technology's estimated coefficients and native capacitance placement. The extraction adapter binds VTG/VTL models, preserves annotation layers and corrects the technology's dimensional unit conversion. This is a predictive approximation without field-solver signoff accuracy.
+
+Physical checks and declared functional bounds remain mandatory. Quality has no
+fixed allowed-degradation threshold. Each `source_*` job simulates the declared
+source circuit with exactly the same testbench, model resources, parameters,
+load and measurement window as its paired extracted-candidate job. A source
+observation is the 100-point electrical baseline; it is independent of the
+submitted GDS. All individual pairs are retained in the evaluation report.
+
+For a post-layout observation x and its source observation b:
+
+- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,
+  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;
+  s is a normalization floor, not an allowed degradation or pass threshold.
+- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.
+- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and
+  zero-valued operating points are never divided directly.
+
+Scoring uses `layout`. A metric uses its worst paired quality q. The score is
+S = 100 * product(q_i ** w_i), including area quality
+q_area = area_reference / candidate_functional_area. The weights below sum to
+one. Dimensions describe measurements but do not determine their weights.
+Physical or functional rejection scores zero; missing or invalid measurements
+produce an unknown score, including measurements with zero weight.
+Source-equivalent performance at the area reference scores 100; improvements
+can exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.
+
+| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale |
+| --- | --- | --- | --- | --- | --- |
+| `low` | `find v(dout) at=610p` | V | functional check | −∞ … 0.1 | — |
+| `high` | `find v(dout) at=1610p` | V | functional check | 0.9 … +∞ | — |
+| `supply` | `avg par('-v(vdd)*i(Vdd)') from=0 to=2n` | W | minimize / ratio | 0 … +∞ | 1e-12 |
+| `decision_delay_fall` | SCLK 50% to Dout 50% decision delay; see testbench window. | s | minimize / ratio | 0.0 … +∞ | — |
+
+Area reference: **2.82 um2**. 7 expanded device instances; sum of device/contact envelopes 1.4529 um2, per-side envelope allowance 0.12 um, 50% routing allowance and total outer width/height allowance 0.24 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.
+
+The capability coefficient remains **5**; it is independent of
+the reference-relative task score.
+
+
+### Score weights
+
+SRAM periphery: peripheral delay 68%; supply power 17%; area 15%. Each objective's weight is divided equally among its metrics.
+
+| Metric | Weight |
+| --- | ---: |
+| `functional_area` | 0.15 |
+| `decision_delay_fall` | 0.680000000000 |
+| `supply` | 0.170000000000 |
+
+Only the falling output decision delay contributes to timing quality. Both
+decision polarities must satisfy their sampled final-level checks; rising
+decision timing is outside this task's measured objective.
+
+## Tools and Submission
+
+Solve budget: **3 hours**.
+
+Use the reviewed FreePDK45 KLayout, Magic and ngspice resources from `/protocol/resources.json`. For Magic RC extraction, use `/resources/support/magic-vtg/freepdk45.tech`, which includes the required model and unit adaptations. Runtime `/protocol/task.json` publishes the same constraints, measurements and scoring. Only declared inputs appear under `/task`. Write `/workspace/output/final.gds`, then explicitly submit with `python -I /protocol/submit.py`. A harness that declares `process-feedback` uses the same frozen plan and backend identities for process checks; those snapshots do not count as final submissions.

tasks/freepdk45/OpenRAM/cases/write_driver/case.toml

@@ -0,0 +1,613 @@
+in_core = true
+kind = "layout_case"
+id = "freepdk45.OpenRAM.write_driver"
+title = "Complementary SRAM Write Driver"
+status = "qualified"
+
+[[assets]]
+path = "materials/schematic.svg"
+role = "schematic"
+visibility = "maintainer"
+format = "svg"
+sha256 = "651fc9f4dbffb8f1512c92cee69ff3c7dc9ae4513e2fab8e092949c527287b0d"
+
+[[assets]]
+path = "reference/write_driver.gds"
+role = "reference"
+visibility = "maintainer"
+format = "gds"
+sha256 = "2465c2b5293b138226ebc396cc13dd19bca4b8aba3268dfead8f83893316ba78"
+
+[task]
+hours = 3
+kind = "netlist_to_gds"
+family = "freepdk45_write_driver"
+coefficient = 3
+environment = "freepdk45-nominal-predictive-rc"
+
+[task.inputs.description]
+path = "problem.md"
+sha256 = "c107911cb0ae72200a1aaa9baa1cda5c3ff12f89fba4e4ffba1a146a33be1e3d"
+format = "text"
+
+[task.inputs.netlist]
+path = "materials/circuit.spice"
+sha256 = "40cf5d0d27b138b06a7b6b0bbdffefbf6a0569fae6092f1fd6d64c5501a952b4"
+format = "spice"
+subcircuit = "write_driver"
+
+[task.inputs.performance]
+path = "materials/testbench.spice"
+format = "spice"
+sha256 = "a07fc802d7506c35db325b6aa8256ec558c5d606003547a22e9e8b5236a98ecf"
+
+[task.constraints]
+quality = [
+    { id = "area", type = "functional_bbox_area", layers_from = "outline" },
+]
+
+[[task.constraints.hard]]
+id = "outline"
+type = "bbox_max"
+functional_layers = [
+    [
+        1,
+        0,
+    ],
+    [
+        2,
+        0,
+    ],
+    [
+        3,
+        0,
+    ],
+    [
+        4,
+        0,
+    ],
+    [
+        5,
+        0,
+    ],
+    [
+        6,
+        0,
+    ],
+    [
+        7,
+        0,
+    ],
+    [
+        8,
+        0,
+    ],
+    [
+        9,
+        0,
+    ],
+    [
+        10,
+        0,
+    ],
+    [
+        11,
+        0,
+    ],
+    [
+        12,
+        0,
+    ],
+    [
+        13,
+        0,
+    ],
+    [
+        14,
+        0,
+    ],
+    [
+        15,
+        0,
+    ],
+    [
+        16,
+        0,
+    ],
+    [
+        17,
+        0,
+    ],
+    [
+        18,
+        0,
+    ],
+    [
+        19,
+        0,
+    ],
+    [
+        20,
+        0,
+    ],
+    [
+        21,
+        0,
+    ],
+    [
+        22,
+        0,
+    ],
+    [
+        23,
+        0,
+    ],
+    [
+        24,
+        0,
+    ],
+    [
+        25,
+        0,
+    ],
+    [
+        26,
+        0,
+    ],
+    [
+        27,
+        0,
+    ],
+    [
+        28,
+        0,
+    ],
+    [
+        29,
+        0,
+    ],
+]
+max_width_um = 100
+max_height_um = 100
+
+[task.output]
+path = "output/final.gds"
+format = "gds"
+top_cell = "write_driver"
+max_bytes = 10485760
+
+[task.evaluation]
+mode = "post_layout"
+
+[[task.evaluation.jobs]]
+id = "artifact"
+stage = "check"
+operation = "layout.artifact"
+gate = "artifact"
+
+[task.evaluation.jobs.inputs]
+layout = "candidate"
+task = "task"
+
+[[task.evaluation.jobs]]
+id = "drc"
+stage = "check"
+operation = "layout.drc"
+gate = "drc"
+
+[task.evaluation.jobs.inputs]
+layout = "candidate"
+task = "task"
+
+[[task.evaluation.jobs]]
+id = "lvs"
+stage = "check"
+operation = "layout.lvs"
+gate = "lvs"
+
+[task.evaluation.jobs.inputs]
+layout = "candidate"
+task = "task"
+netlist = "input:netlist"
+
+[task.evaluation.jobs.outputs]
+database = "klayout-lvs"
+binding = "json"
+
+[[task.evaluation.jobs]]
+id = "geometry"
+stage = "check"
+operation = "layout.geometry"
+gate = "constraint"
+requires = [
+    "artifact",
+    "drc",
+    "lvs",
+]
+
+[task.evaluation.jobs.inputs]
+layout = "candidate"
+task = "task"
+constraints = "input:constraints"
+database = "job:lvs:database"
+binding = "job:lvs:binding"
+
+[[task.evaluation.jobs]]
+id = "parasitics"
+stage = "extract"
+operation = "layout.extract_rc"
+requires = [
+    "artifact",
+    "drc",
+    "lvs",
+    "geometry",
+]
+
+[task.evaluation.jobs.inputs]
+layout = "candidate"
+task = "task"
+
+[task.evaluation.jobs.outputs]
+netlist = "spice"
+
+[task.evaluation.jobs.parameters]
+ports = [
+    "din",
+    "bl",
+    "br",
+    "wen",
+    "vdd",
+    "gnd",
+]
+
+[[task.evaluation.jobs]]
+id = "nominal"
+stage = "simulate"
+operation = "circuit.simulate"
+
+[task.evaluation.jobs.inputs]
+deck = "input:performance"
+dut = "job:parasitics:netlist"
+
+[task.evaluation.jobs.outputs]
+waveform = "ngspice-raw"
+
+[task.evaluation.jobs.parameters.exports]
+waveform = "waveform.raw"
+
+[task.evaluation.jobs.parameters.measurements]
+bl_low = "V"
+br_high = "V"
+bl_high = "V"
+br_low = "V"
+z_bl = "V"
+z_br = "V"
+supply = "W"
+data_delay_bl = "s"
+data_delay_br = "s"
+
+[[task.evaluation.metrics]]
+id = "functional_area"
+category = "physical"
+observations = [
+    "geometry:area",
+]
+unit = "um2"
+direction = "minimize"
+aggregation = "max"
+
+[[task.evaluation.metrics]]
+id = "bl_low"
+category = "performance"
+observations = [
+    "nominal:bl_low",
+]
+unit = "V"
+direction = "minimize"
+aggregation = "max"
+upper = 0.1
+
+[[task.evaluation.metrics]]
+id = "br_high"
+category = "performance"
+observations = [
+    "nominal:br_high",
+]
+unit = "V"
+direction = "maximize"
+aggregation = "min"
+lower = 0.9
+
+[[task.evaluation.metrics]]
+id = "bl_high"
+category = "performance"
+observations = [
+    "nominal:bl_high",
+]
+unit = "V"
+direction = "maximize"
+aggregation = "min"
+lower = 0.9
+
+[[task.evaluation.metrics]]
+id = "br_low"
+category = "performance"
+observations = [
+    "nominal:br_low",
+]
+unit = "V"
+direction = "minimize"
+aggregation = "max"
+upper = 0.1
+
+[[task.evaluation.metrics]]
+id = "z_bl"
+category = "performance"
+observations = [
+    "nominal:z_bl",
+]
+unit = "V"
+direction = "target"
+aggregation = "max"
+lower = 0.45
+upper = 0.55
+
+[[task.evaluation.metrics]]
+id = "z_br"
+category = "performance"
+observations = [
+    "nominal:z_br",
+]
+unit = "V"
+direction = "target"
+aggregation = "max"
+lower = 0.45
+upper = 0.55
+
+[[task.evaluation.metrics]]
+id = "supply"
+category = "performance"
+observations = [
+    "nominal:supply",
+]
+unit = "W"
+direction = "minimize"
+aggregation = "max"
+dimension = "supply"
+baseline = [
+    "source_nominal:supply",
+]
+normalization = "ratio"
+lower = 0
+scale = 1e-12
+
+[[task.evaluation.metrics]]
+id = "data_delay"
+category = "performance"
+observations = [
+    "nominal:data_delay_bl",
+    "nominal:data_delay_br",
+]
+baseline = [
+    "source_nominal:data_delay_bl",
+    "source_nominal:data_delay_br",
+]
+unit = "s"
+direction = "minimize"
+aggregation = "max"
+dimension = "response"
+normalization = "ratio"
+lower = 0.0
+
+[task.evaluation.scoring]
+method = "layout"
+area_metric = "functional_area"
+area_target = 3.36
+rationale = "SRAM periphery: peripheral delay 68%; supply power 17%; area 15%. Each objective's weight is divided equally among its metrics."
+
+[task.evaluation.scoring.weights]
+functional_area = 0.15
+data_delay = 0.68
+supply = 0.17
+
+[task.evaluation.pre_layout]
+source_report_sha256 = "4c7f16eb4faca05c47621e31e3a9511f8fa6bd470ad784766c7eb76c0adbfd1f"
+
+[task.evaluation.pre_layout.backends]
+"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"ef9cb87fa27b849376472663b7362673979b89e012f161ba47bb5f6af6ede8eb\", \"compatibility\": null, \"execution_sha256\": \"5424b579002782bfddf0a729715b8fbf2a5f7f2b4cf14982d7616e352d5de9be\", \"image_id\": \"sha256:6562558774d43c085a289bbba696c55959eb8051a0996f96633451fbeb9c652d\", \"limits\": {\"cpus\": 4, \"memory_mb\": 4096, \"pids\": 256}, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"7fc8a0cde0f7d722e87c34a1115c13986b3db8fecba4b7dadb0a1edf171df62b\", \"timeout_seconds\": 120.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}"
+
+[task.evaluation.pre_layout.jobs.source_nominal]
+operation = "circuit.simulate"
+
+[task.evaluation.pre_layout.jobs.source_nominal.inputs]
+deck = "input:performance"
+dut = "input:netlist"
+
+[task.evaluation.pre_layout.jobs.source_nominal.outputs]
+waveform = "ngspice-raw"
+
+[task.evaluation.pre_layout.jobs.source_nominal.parameters.exports]
+waveform = "waveform.raw"
+
+[task.evaluation.pre_layout.jobs.source_nominal.parameters.measurements]
+bl_low = "V"
+br_high = "V"
+bl_high = "V"
+br_low = "V"
+z_bl = "V"
+z_br = "V"
+supply = "W"
+data_delay_bl = "s"
+data_delay_br = "s"
+
+[task.evaluation.pre_layout.jobs.source_nominal.input_sha256]
+deck = "a07fc802d7506c35db325b6aa8256ec558c5d606003547a22e9e8b5236a98ecf"
+dut = "40cf5d0d27b138b06a7b6b0bbdffefbf6a0569fae6092f1fd6d64c5501a952b4"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.bl_high]
+value = 0.9860666
+unit = "V"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.bl_low]
+value = 0.0150365
+unit = "V"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.br_high]
+value = 0.9886259
+unit = "V"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.br_low]
+value = 0.02670905
+unit = "V"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.data_delay_bl]
+value = 5.409058e-11
+unit = "s"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.data_delay_br]
+value = 6.295051e-11
+unit = "s"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.supply]
+value = 2.174283e-05
+unit = "W"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.z_bl]
+value = 0.5015592
+unit = "V"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.z_br]
+value = 0.502349
+unit = "V"
+
+[toolchain.backends.artifact]
+type = "klayout-docker"
+
+[toolchain.backends.artifact.settings]
+image = "iclayout-bench-tools:local"
+check = "artifact"
+timeout_seconds = 120
+
+[toolchain.backends.drc]
+type = "klayout-docker"
+
+[toolchain.backends.drc.settings]
+image = "iclayout-bench-tools:local"
+check = "drc"
+timeout_seconds = 120
+support = "build/support/freepdk45-klayout"
+profile = "drc.json"
+
+[toolchain.backends.drc.support_profiles]
+support = "klayout"
+
+[toolchain.backends.lvs]
+type = "klayout-docker"
+
+[toolchain.backends.lvs.settings]
+image = "iclayout-bench-tools:local"
+check = "lvs"
+timeout_seconds = 120
+support = "build/support/freepdk45-klayout"
+profile = "strict-lvs.json"
+
+[toolchain.backends.lvs.support_profiles]
+support = "klayout"
+
+[toolchain.backends.geometry]
+type = "klayout-geometry-docker"
+
+[toolchain.backends.geometry.settings]
+image = "iclayout-bench-tools:local"
+timeout_seconds = 60
+
+[toolchain.backends.rc]
+type = "magic-rc-docker"
+
+[toolchain.backends.rc.settings]
+image = "iclayout-bench-tools:local"
+support = "build/support/freepdk45-magic-vtg"
+technology = "freepdk45.tech"
+tech_name = "freepdk45"
+style = "spice3(sim)"
+gds_readonly = false
+case_insensitive_ports = true
+label_layers = [
+    [
+        9,
+        0,
+    ],
+    [
+        11,
+        0,
+    ],
+    [
+        13,
+        0,
+    ],
+    [
+        15,
+        0,
+    ],
+    [
+        17,
+        0,
+    ],
+    [
+        19,
+        0,
+    ],
+    [
+        21,
+        0,
+    ],
+    [
+        23,
+        0,
+    ],
+    [
+        25,
+        0,
+    ],
+    [
+        27,
+        0,
+    ],
+    [
+        29,
+        0,
+    ],
+]
+timeout_seconds = 120
+
+[toolchain.backends.rc.support_profiles]
+support = "magic-vtg"
+
+[toolchain.backends.ngspice]
+type = "ngspice-docker"
+
+[toolchain.backends.ngspice.settings]
+image = "iclayout-bench-tools:local"
+support = "build/support/freepdk45-models"
+timeout_seconds = 120
+
+[toolchain.backends.ngspice.support_profiles]
+support = "models"
+
+[toolchain.bindings]
+"layout.artifact" = "artifact"
+"layout.drc" = "drc"
+"layout.lvs" = "lvs"
+"layout.geometry" = "geometry"
+"layout.extract_rc" = "rc"
+"circuit.simulate" = "ngspice"
+
+[qualification]
+reference = "reference/write_driver.gds"
+
+[origin]
+url = "https://github.com/ferdous313/OpenRAM/blob/420a33e731d7d80bf9c7cd54ffbeec3603259847/technology/freepdk45/sp_lib/write_driver.sp"
+
+[presentation]
+category = "Logic & memory"
+summary = "Drives complementary bitlines during a write and releases them when disabled."

tasks/freepdk45/OpenRAM/cases/write_driver/materials/circuit.spice

@@ -0,0 +1,21 @@
+
+.SUBCKT write_driver din bl br wen vdd gnd
+*inverters for enable and data input
+minP bl_bar din vdd vdd pmos_vtg w=360.000000n l=50.000000n
+minN bl_bar din gnd gnd nmos_vtg w=180.000000n l=50.000000n
+moutP wen_bar wen vdd vdd pmos_vtg w=360.000000n l=50.000000n
+moutN wen_bar wen gnd gnd nmos_vtg w=180.000000n l=50.000000n
+
+*tristate for BL
+mout0P int1 bl_bar vdd vdd pmos_vtg w=360.000000n l=50.000000n
+mout0P2 bl wen_bar int1 vdd pmos_vtg w=360.000000n l=50.000000n
+mout0N bl wen int2 gnd nmos_vtg w=180.000000n l=50.000000n
+mout0N2 int2 bl_bar gnd gnd nmos_vtg w=180.000000n l=50.000000n
+
+*tristate for BR
+mout1P int3 din vdd vdd pmos_vtg w=360.000000n l=50.000000n
+mout1P2 br wen_bar int3 vdd pmos_vtg w=360.000000n l=50.000000n
+mout1N br wen int4 gnd nmos_vtg w=180.000000n l=50.000000n
+mout1N2 int4 din gnd gnd nmos_vtg w=180.000000n l=50.000000n
+.ENDS write_driver
+

tasks/freepdk45/OpenRAM/cases/write_driver/materials/testbench.spice

@@ -0,0 +1,32 @@
+* write_driver nominal characterization
+.include /workspace/support/models.spice
+.include dut.spice
+.temp 27
+Vdd vdd 0 1
+Xdut din BL BR wen vdd gnd write_driver
+Vdin din 0 PULSE(0 1 500p 10p 10p 490p 1n)
+Ven wen 0 PWL(0 1 2n 1 2.01n 0)
+Cl bl 0 10f
+Cr br 0 10f
+Vmid mid 0 .5
+Rl bl mid 100k
+Rr br mid 100k
+.tran 1p 12n
+.meas tran bl_low find v(bl) at=300p
+.meas tran br_high find v(br) at=300p
+.meas tran bl_high find v(bl) at=710p
+.meas tran br_low find v(br) at=710p
+.meas tran z_bl find v(bl) at=11.9n
+.meas tran z_br find v(br) at=11.9n
+.meas tran supply avg par('-v(vdd)*i(Vdd)') from=0 to=2n
+
+.meas tran data_delay_bl trig v(din) val=.5 rise=1 td=.5n targ v(bl) val=.5 rise=1 td=.5n
+
+.meas tran data_delay_br trig v(din) val=.5 rise=1 td=.5n targ v(br) val=.5 fall=1 td=.5n
+
+.control
+run
+write waveform.raw v(din) v(bl) v(br) v(wen) v(vdd) i(Vdd)
+quit
+.endc
+.end

tasks/freepdk45/OpenRAM/cases/write_driver/problem.md

@@ -0,0 +1,87 @@
+# Complementary SRAM Write Driver Layout Task
+
+## Objective
+
+Implement the supplied complementary tri-state write driver: WEN=1 drives BL=DIN and BR=NOT DIN; WEN=0 disables both outputs. Preserve the authoritative netlist's model classes, W/L, interface and connectivity. Submit top cell `write_driver`.
+
+## Inputs and Interface
+
+Ordered SPICE ports: `din bl br wen vdd gnd`. Names are case-insensitive; different names are not interchangeable. The delivered inputs are this problem, `materials/circuit.spice`, and `materials/testbench.spice`. The model and extraction resources are supplied as reviewed support bundles. Reference geometry and qualification evidence are maintainer materials, excluded from solver inputs.
+
+## Operating Conditions
+
+Use the nominal FreePDK45 BSIM4 models at **1.0 V and 27 C**, with ground at 0 V. All transistor lengths are 50 nm; widths and model classes come from the netlist.
+
+BL and BR each drive 10 fF and a 100 kohm resistor to 0.5 V. DIN starts low, rises at 500 ps and falls at 1 ns, with 10 ps edges and a 1 ns period. WEN is high until 2 ns and falls over 10 ps. Sample the enabled complementary outputs at 300 ps and 710 ps, and both disabled outputs at 11.9 ns. The passive midpoint loads test high impedance without accessing internal nodes. Average DUT supply power over 0–2 ns.
+
+The deck defines stimuli and observation times exactly. Tests use only external ports. Qualification covers these nominal conditions, not PVT, mismatch, array abutment, substrate noise or manufacturing signoff.
+
+## Physical Requirements
+
+Submit a nonempty GDSII of at most 10 MiB. Enable all checks present in the supplied KLayout DRC deck, including grid and antenna checks, with no waivers. Strict LVS checks named ports, models, W/L and actual well/tap connectivity; library-specific implicit or global rail connections are disabled. The upstream deck does not implement its documented different-potential well-spacing rule; it is not a complete foundry signoff deck.
+
+The hard functional envelope is 100 um by 100 um. Its bounding rectangle includes every drawing layer 1/0 through 29/0: active, wells, implants, threshold markers, poly, contacts, all ten metals and all nine vias. It supplies the scored footprint in um2. Put functional geometry on these layers; pin-purpose and annotation geometry is excluded. Electrical labels use poly or metal drawing layers (9/0 and 11/0, 13/0, ..., 29/0). Non-electrical annotation text is ignored by extraction.
+
+Translation, equivalent hierarchy and internal instance renaming are allowed. LVS permits source/drain exchange and equivalent parallel devices; any such layout must also pass the same RC-based electrical requirements. Preserve top-level port identities and explicit body connections.
+
+## Electrical Requirements and Scoring
+
+Artifact, DRC, LVS and geometry gates precede candidate GDS extraction. Simulation consumes the candidate's Magic RC netlist unchanged; source simulation supplies the independent scoring baseline. VTG/VTL device classes are checked by independent LVS before the matching extraction profile is used. Extraction includes poly/metal sheet resistance, contacts/vias, geometry-dependent coupling and ground capacitance, and device junction area/perimeter. Wells are lumped connections; BSIM4 supplies device/junction behavior. Interconnect resistance and capacitance use the pinned community FreePDK45 Magic technology's estimated coefficients and native capacitance placement. The extraction adapter binds VTG/VTL models, preserves annotation layers and corrects the technology's dimensional unit conversion. This is a predictive approximation without field-solver signoff accuracy.
+
+Physical checks and declared functional bounds remain mandatory. Quality has no
+fixed allowed-degradation threshold. Each `source_*` job simulates the declared
+source circuit with exactly the same testbench, model resources, parameters,
+load and measurement window as its paired extracted-candidate job. A source
+observation is the 100-point electrical baseline; it is independent of the
+submitted GDS. All individual pairs are retained in the evaluation report.
+
+For a post-layout observation x and its source observation b:
+
+- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,
+  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;
+  s is a normalization floor, not an allowed degradation or pass threshold.
+- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.
+- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and
+  zero-valued operating points are never divided directly.
+
+Scoring uses `layout`. A metric uses its worst paired quality q. The score is
+S = 100 * product(q_i ** w_i), including area quality
+q_area = area_reference / candidate_functional_area. The weights below sum to
+one. Dimensions describe measurements but do not determine their weights.
+Physical or functional rejection scores zero; missing or invalid measurements
+produce an unknown score, including measurements with zero weight.
+Source-equivalent performance at the area reference scores 100; improvements
+can exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.
+
+| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale |
+| --- | --- | --- | --- | --- | --- |
+| `bl_low` | `find v(bl) at=300p` | V | functional check | −∞ … 0.1 | — |
+| `br_high` | `find v(br) at=300p` | V | functional check | 0.9 … +∞ | — |
+| `bl_high` | `find v(bl) at=710p` | V | functional check | 0.9 … +∞ | — |
+| `br_low` | `find v(br) at=710p` | V | functional check | −∞ … 0.1 | — |
+| `z_bl` | `find v(bl) at=11.9n` | V | functional check | 0.45 … 0.55 | — |
+| `z_br` | `find v(br) at=11.9n` | V | functional check | 0.45 … 0.55 | — |
+| `supply` | `avg par('-v(vdd)*i(Vdd)') from=0 to=2n` | W | minimize / ratio | 0 … +∞ | 1e-12 |
+| `data_delay` | DIN rising through 0.5 V after 0.5 ns to BL rising or BR falling through 0.5 V; both arcs are source-paired. | s | minimize / ratio | 0 … +∞ | — |
+
+Area reference: **3.36 um2**. 12 expanded device instances; sum of device/contact envelopes 1.7748 um2, per-side envelope allowance 0.12 um, 50% routing allowance and total outer width/height allowance 0.24 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.
+
+The capability coefficient remains **3**; it is independent of
+the reference-relative task score.
+
+
+### Score weights
+
+SRAM periphery: peripheral delay 68%; supply power 17%; area 15%. Each objective's weight is divided equally among its metrics.
+
+| Metric | Weight |
+| --- | ---: |
+| `functional_area` | 0.15 |
+| `data_delay` | 0.680000000000 |
+| `supply` | 0.170000000000 |
+
+## Tools and Submission
+
+Solve budget: **3 hours**.
+
+Use the reviewed FreePDK45 KLayout, Magic and ngspice resources from `/protocol/resources.json`. For Magic RC extraction, use `/resources/support/magic-vtg/freepdk45.tech`, which includes the required model and unit adaptations. Runtime `/protocol/task.json` publishes the same constraints, measurements and scoring. Only declared inputs appear under `/task`. Write `/workspace/output/final.gds`, then explicitly submit with `python -I /protocol/submit.py`. A harness that declares `process-feedback` uses the same frozen plan and backend identities for process checks; those snapshots do not count as final submissions.

tasks/freepdk45/README.md

@@ -0,0 +1,58 @@
+# FreePDK45 Process Scope
+
+Process manifests pin resources; each case contract defines its operating conditions.
+For installation, caching and reference execution, use the evaluator
+[tools guide](https://github.com/lizhangmai/ICLayout-Bench/blob/main/docs/tools.md).
+
+The selected FreePDK45 tasks cover NAND logic, SRAM storage and write drive.
+References use the nominal predictive BSIM4 models and candidate-derived Magic
+RC under the conditions declared by each case. The
+[process manifest](pdk.toml) owns pinned resources and profiles.
+
+Each problem is self-contained. Its configuration owns the exact devices, loads,
+stimuli, observation times, bounds, dimensions and area anchors. Source simulation defines the electrical scoring baseline. Standard-cell area
+uses the reference layout; other areas use the frozen compact estimate. Witnesses
+are excluded from standard solver inputs.
+
+## Physical and extraction scope
+
+The KLayout profile enables all implemented DRC, manufacturing-grid and antenna
+checks without waivers. The community deck's POLY.3 spacing is 50 nm, as documented
+upstream for Nangate compatibility. The source deck explicitly lacks its different-potential
+well-spacing check, so a pass is not complete manufacturing signoff. Strict LVS
+flattens an isolated candidate copy with its labels, removes library-specific
+`cheat` blocks and implicit/global rail joins, and compares models, W/L, named
+ports and real well/tap connectivity. The upstream audit profile is separate and
+retains the original library assumptions; it is not the task judge.
+
+The functional footprint includes drawing layers 1/0 through 29/0, including all
+ten routing metals and nine vias. The same layer set supplies the hard 100 by
+100 um envelope and scored bounding-box area. Annotation and pin-purpose shapes
+are excluded; the contract requires functional routing on drawing layers.
+
+Magic imports the candidate on its exact DBU grid, filters electrical text to
+poly/metal drawing layers and aliases case-insensitive SPICE port names. It
+extracts resistances and capacitances from the GDS, with no schematic replacement.
+Independent LVS selects the applicable VTG or VTL model class first. The native
+RC topology is checked during qualification against the source after removing
+capacitors and collapsing parasitic resistors. Simulation always uses the full,
+unchanged extracted RC network.
+
+The predictive extraction uses the community Magic technology's estimated
+resistance/capacitance coefficients and its native placement of coupling and
+ground capacitance, with nominal VTG/VTL ngspice models at 27 C. Wells and substrate
+are lumped connections. This is not calibrated field-solver extraction or a
+foundry signoff claim; process variation, substrate noise and RF/EM are outside scope.
+
+Use `/resources/support/magic-vtg/freepdk45.tech` or the `magic-vtl` counterpart
+for evaluation-equivalent extraction, as specified by the case problem. The unified
+PDK directory retains the upstream views; reviewed profiles include the adaptations.
+
+The explicit manifest adaptations map MOS extraction to the LVS-selected model
+class, import threshold/annotation markers as non-electrical comments, and correct
+`lambda` from 0.025 to **2.5**. Magic expresses this length in centimicrons, so 2.5
+represents the technology's 25 nm internal grid; the upstream value otherwise
+extracts a 50 nm gate as 0.5 nm. Upstream coefficients are retained. Qualification
+checks the selected published layouts through the complete extraction and simulation
+path. This does not establish stream-out equivalence between Magic and KLayout;
+the community repository documents known via/metal stream-out differences.

tasks/freepdk45/nangate45-pdk/LICENSE

@@ -0,0 +1,177 @@
+
+                                 Apache License
+                           Version 2.0, January 2004
+                        http://www.apache.org/licenses/
+
+   TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
+
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+
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+      any Contribution intentionally submitted for inclusion in the Work
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+      the terms of any separate license agreement you may have executed
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+      PARTICULAR PURPOSE. You are solely responsible for determining the
+      appropriateness of using or redistributing the Work and assume any
+      risks associated with Your exercise of permissions under this License.
+
+   8. Limitation of Liability. In no event and under no legal theory,
+      whether in tort (including negligence), contract, or otherwise,
+      unless required by applicable law (such as deliberate and grossly
+      negligent acts) or agreed to in writing, shall any Contributor be
+      liable to You for damages, including any direct, indirect, special,
+      incidental, or consequential damages of any character arising as a
+      result of this License or out of the use or inability to use the
+      Work (including but not limited to damages for loss of goodwill,
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+      other commercial damages or losses), even if such Contributor
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+
+   END OF TERMS AND CONDITIONS

tasks/freepdk45/nangate45-pdk/NOTICE

@@ -0,0 +1,39 @@
+Copyright 2008-2021 Silvaco, Inc. 
+
+
+Contributed Materials
+
+Silvaco Inc. has submitted to Si2 the following materials (“Contribution”):
+
+	45nm Open-Source Digital Cell Library (“Library”)
+
+This submission hereunder constitutes a “Contribution” under the Si2 Project and OpenStandards IP. For avoidance of doubt, any portions of the Contribution consisting of source code or software are contributed pursuant to the Apache 2.0 license accompanying such material. 
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+
+Documentation is contributed pursuant to the Creative Commons License, Version 4.0 (CCL-4.0).
+
+This work is licensed under the Creative Common Attribution 4.0 International License. 
+To view a copy of this license visit: https://creativecommons.org/licenses/by/4.0/
+or send a letter to Creative Commons PO Box 1866, Mountainview CA 94042, USA.
+
+
+Under the terms of this Contribution, the materials are to be posted to Si2’s website (www.si2.org) and made available to members and Universities for download and use at no charge. Non-members may visit https://silvaco.com/services/library-design/ for further information on obtaining the Library.
+
+Retained source declarations
+----------------------------
+This collection retains generated upstream copyright headers, including legacy
+proprietary wording, alongside the Apache license and Silvaco/Si2 notice from the
+pinned upstream publication. Preserve these declarations together; source URLs
+are recorded in the case manifests.

tasks/freepdk45/nangate45-pdk/cases/AOI21_X1/case.toml

@@ -0,0 +1,1073 @@
+in_core = false
+kind = "layout_case"
+id = "freepdk45.nangate45-pdk.AOI21_X1"
+title = "AND-OR-Invert Gate"
+status = "qualified"
+
+[[assets]]
+path = "reference/AOI21_X1.gds"
+role = "reference"
+visibility = "maintainer"
+format = "gds"
+sha256 = "1ebcc6f4d7a8f5c50846b5cdfd60f3039fb96caf455b89f2d7f30568c5a2af94"
+
+[[assets]]
+path = "materials/schematic.svg"
+role = "schematic"
+visibility = "maintainer"
+format = "svg"
+sha256 = "bd3f9998b37ef9ed17592ce028beb4b0dd2de95e3f8118eddb4133d66141c3a7"
+
+[task]
+hours = 3
+kind = "netlist_to_gds"
+family = "freepdk45_aoi21_x1"
+coefficient = 2
+environment = "freepdk45-nominal-predictive-rc"
+
+[task.inputs.description]
+path = "problem.md"
+sha256 = "4ace260ca69cbe7c09224a583aaffcde13d68ad6fd81ad5bcb2ee9554fe19311"
+format = "text"
+
+[task.inputs.netlist]
+path = "materials/circuit.spice"
+sha256 = "07d8b2857f5ecd7bde8d5b3e231b16b6819272db2d19c1ee4882094e04bc909e"
+format = "spice"
+subcircuit = "AOI21_X1"
+
+[task.inputs.performance]
+path = "materials/testbench.spice"
+sha256 = "f8401ddcc740853f48b867b25e5bbf895409a9d1df90dfd5b013f31d236aa6b8"
+format = "spice"
+
+[task.constraints]
+quality = [
+    { id = "area", type = "functional_bbox_area", layers_from = "outline" },
+]
+
+[[task.constraints.hard]]
+id = "outline"
+type = "bbox_max"
+functional_layers = [
+    [
+        1,
+        0,
+    ],
+    [
+        2,
+        0,
+    ],
+    [
+        3,
+        0,
+    ],
+    [
+        4,
+        0,
+    ],
+    [
+        5,
+        0,
+    ],
+    [
+        6,
+        0,
+    ],
+    [
+        7,
+        0,
+    ],
+    [
+        8,
+        0,
+    ],
+    [
+        9,
+        0,
+    ],
+    [
+        10,
+        0,
+    ],
+    [
+        11,
+        0,
+    ],
+    [
+        12,
+        0,
+    ],
+    [
+        13,
+        0,
+    ],
+    [
+        14,
+        0,
+    ],
+    [
+        15,
+        0,
+    ],
+    [
+        16,
+        0,
+    ],
+    [
+        17,
+        0,
+    ],
+    [
+        18,
+        0,
+    ],
+    [
+        19,
+        0,
+    ],
+    [
+        20,
+        0,
+    ],
+    [
+        21,
+        0,
+    ],
+    [
+        22,
+        0,
+    ],
+    [
+        23,
+        0,
+    ],
+    [
+        24,
+        0,
+    ],
+    [
+        25,
+        0,
+    ],
+    [
+        26,
+        0,
+    ],
+    [
+        27,
+        0,
+    ],
+    [
+        28,
+        0,
+    ],
+    [
+        29,
+        0,
+    ],
+]
+max_width_um = 100
+max_height_um = 100
+
+[[task.constraints.hard]]
+id = "cell_frame"
+type = "cell_frame"
+functional_layers = [
+    [
+        1,
+        0,
+    ],
+    [
+        2,
+        0,
+    ],
+    [
+        3,
+        0,
+    ],
+    [
+        4,
+        0,
+    ],
+    [
+        5,
+        0,
+    ],
+    [
+        6,
+        0,
+    ],
+    [
+        7,
+        0,
+    ],
+    [
+        8,
+        0,
+    ],
+    [
+        9,
+        0,
+    ],
+    [
+        10,
+        0,
+    ],
+    [
+        11,
+        0,
+    ],
+    [
+        12,
+        0,
+    ],
+    [
+        13,
+        0,
+    ],
+    [
+        14,
+        0,
+    ],
+    [
+        15,
+        0,
+    ],
+    [
+        16,
+        0,
+    ],
+    [
+        17,
+        0,
+    ],
+    [
+        18,
+        0,
+    ],
+    [
+        19,
+        0,
+    ],
+    [
+        20,
+        0,
+    ],
+    [
+        21,
+        0,
+    ],
+    [
+        22,
+        0,
+    ],
+    [
+        23,
+        0,
+    ],
+    [
+        24,
+        0,
+    ],
+    [
+        25,
+        0,
+    ],
+    [
+        26,
+        0,
+    ],
+    [
+        27,
+        0,
+    ],
+    [
+        28,
+        0,
+    ],
+    [
+        29,
+        0,
+    ],
+]
+height_um = 1.6300000000000001
+width_grid_um = 0.01
+
+[[task.constraints.hard.rails]]
+name = "VDD"
+layer = [
+    11,
+    0,
+]
+connectivity_layer = "metal1"
+y_um = 1.5150000000000001
+thickness_um = 0.07
+left_um = 0.115
+right_um = 0.030000000000000002
+
+[[task.constraints.hard.rails]]
+name = "VSS"
+layer = [
+    11,
+    0,
+]
+connectivity_layer = "metal1"
+y_um = 0.115
+thickness_um = 0.07
+left_um = 0.115
+right_um = 0.030000000000000002
+
+[task.output]
+path = "output/final.gds"
+format = "gds"
+top_cell = "AOI21_X1"
+max_bytes = 10485760
+
+[task.evaluation]
+mode = "post_layout"
+
+[[task.evaluation.jobs]]
+id = "artifact"
+stage = "check"
+operation = "layout.artifact"
+gate = "artifact"
+
+[task.evaluation.jobs.inputs]
+layout = "candidate"
+task = "task"
+
+[[task.evaluation.jobs]]
+id = "drc"
+stage = "check"
+operation = "layout.drc"
+gate = "drc"
+
+[task.evaluation.jobs.inputs]
+layout = "candidate"
+task = "task"
+
+[[task.evaluation.jobs]]
+id = "lvs"
+stage = "check"
+operation = "layout.lvs"
+gate = "lvs"
+
+[task.evaluation.jobs.inputs]
+layout = "candidate"
+task = "task"
+netlist = "input:netlist"
+
+[task.evaluation.jobs.outputs]
+database = "klayout-lvs"
+binding = "json"
+
+[[task.evaluation.jobs]]
+id = "geometry"
+stage = "check"
+operation = "layout.geometry"
+gate = "constraint"
+requires = [
+    "artifact",
+    "drc",
+    "lvs",
+]
+
+[task.evaluation.jobs.inputs]
+layout = "candidate"
+task = "task"
+constraints = "input:constraints"
+database = "job:lvs:database"
+binding = "job:lvs:binding"
+
+[[task.evaluation.jobs]]
+id = "parasitics"
+stage = "extract"
+operation = "layout.extract_rc"
+requires = [
+    "artifact",
+    "drc",
+    "lvs",
+    "geometry",
+]
+
+[task.evaluation.jobs.inputs]
+layout = "candidate"
+task = "task"
+
+[task.evaluation.jobs.outputs]
+netlist = "spice"
+
+[task.evaluation.jobs.parameters]
+ports = [
+    "A",
+    "B1",
+    "B2",
+    "ZN",
+    "VDD",
+    "VSS",
+]
+
+[[task.evaluation.jobs]]
+id = "nominal"
+stage = "simulate"
+operation = "circuit.simulate"
+
+[task.evaluation.jobs.inputs]
+deck = "input:performance"
+dut = "job:parasitics:netlist"
+
+[task.evaluation.jobs.outputs]
+waveform = "ngspice-raw"
+
+[task.evaluation.jobs.parameters.exports]
+waveform = "waveform.raw"
+
+[task.evaluation.jobs.parameters.measurements]
+state_0 = "V"
+state_1 = "V"
+state_2 = "V"
+state_3 = "V"
+state_4 = "V"
+state_5 = "V"
+state_6 = "V"
+state_7 = "V"
+state_8 = "V"
+state_9 = "V"
+state_10 = "V"
+state_11 = "V"
+state_12 = "V"
+state_13 = "V"
+state_14 = "V"
+state_15 = "V"
+state_16 = "V"
+supply = "W"
+delay_b1_fall_2 = "s"
+transition_b1_fall_2 = "s"
+delay_b2_rise_3 = "s"
+transition_b2_rise_3 = "s"
+delay_a_fall_4 = "s"
+transition_a_fall_4 = "s"
+delay_a_rise_8 = "s"
+transition_a_rise_8 = "s"
+delay_a_fall_9 = "s"
+transition_a_fall_9 = "s"
+delay_a_rise_13 = "s"
+transition_a_rise_13 = "s"
+delay_b2_fall_14 = "s"
+transition_b2_fall_14 = "s"
+delay_b1_rise_15 = "s"
+transition_b1_rise_15 = "s"
+
+[[task.evaluation.metrics]]
+id = "functional_area"
+category = "physical"
+observations = [
+    "geometry:area",
+]
+unit = "um2"
+direction = "minimize"
+aggregation = "max"
+
+[[task.evaluation.metrics]]
+id = "state_0"
+category = "performance"
+observations = [
+    "nominal:state_0",
+]
+unit = "V"
+direction = "maximize"
+aggregation = "min"
+lower = 0.9
+
+[[task.evaluation.metrics]]
+id = "state_1"
+category = "performance"
+observations = [
+    "nominal:state_1",
+]
+unit = "V"
+direction = "maximize"
+aggregation = "min"
+lower = 0.9
+
+[[task.evaluation.metrics]]
+id = "state_2"
+category = "performance"
+observations = [
+    "nominal:state_2",
+]
+unit = "V"
+direction = "minimize"
+aggregation = "max"
+upper = 0.1
+
+[[task.evaluation.metrics]]
+id = "state_3"
+category = "performance"
+observations = [
+    "nominal:state_3",
+]
+unit = "V"
+direction = "maximize"
+aggregation = "min"
+lower = 0.9
+
+[[task.evaluation.metrics]]
+id = "state_4"
+category = "performance"
+observations = [
+    "nominal:state_4",
+]
+unit = "V"
+direction = "minimize"
+aggregation = "max"
+upper = 0.1
+
+[[task.evaluation.metrics]]
+id = "state_5"
+category = "performance"
+observations = [
+    "nominal:state_5",
+]
+unit = "V"
+direction = "minimize"
+aggregation = "max"
+upper = 0.1
+
+[[task.evaluation.metrics]]
+id = "state_6"
+category = "performance"
+observations = [
+    "nominal:state_6",
+]
+unit = "V"
+direction = "minimize"
+aggregation = "max"
+upper = 0.1
+
+[[task.evaluation.metrics]]
+id = "state_7"
+category = "performance"
+observations = [
+    "nominal:state_7",
+]
+unit = "V"
+direction = "minimize"
+aggregation = "max"
+upper = 0.1
+
+[[task.evaluation.metrics]]
+id = "state_8"
+category = "performance"
+observations = [
+    "nominal:state_8",
+]
+unit = "V"
+direction = "maximize"
+aggregation = "min"
+lower = 0.9
+
+[[task.evaluation.metrics]]
+id = "state_9"
+category = "performance"
+observations = [
+    "nominal:state_9",
+]
+unit = "V"
+direction = "minimize"
+aggregation = "max"
+upper = 0.1
+
+[[task.evaluation.metrics]]
+id = "state_10"
+category = "performance"
+observations = [
+    "nominal:state_10",
+]
+unit = "V"
+direction = "minimize"
+aggregation = "max"
+upper = 0.1
+
+[[task.evaluation.metrics]]
+id = "state_11"
+category = "performance"
+observations = [
+    "nominal:state_11",
+]
+unit = "V"
+direction = "minimize"
+aggregation = "max"
+upper = 0.1
+
+[[task.evaluation.metrics]]
+id = "state_12"
+category = "performance"
+observations = [
+    "nominal:state_12",
+]
+unit = "V"
+direction = "minimize"
+aggregation = "max"
+upper = 0.1
+
+[[task.evaluation.metrics]]
+id = "state_13"
+category = "performance"
+observations = [
+    "nominal:state_13",
+]
+unit = "V"
+direction = "maximize"
+aggregation = "min"
+lower = 0.9
+
+[[task.evaluation.metrics]]
+id = "state_14"
+category = "performance"
+observations = [
+    "nominal:state_14",
+]
+unit = "V"
+direction = "minimize"
+aggregation = "max"
+upper = 0.1
+
+[[task.evaluation.metrics]]
+id = "state_15"
+category = "performance"
+observations = [
+    "nominal:state_15",
+]
+unit = "V"
+direction = "maximize"
+aggregation = "min"
+lower = 0.9
+
+[[task.evaluation.metrics]]
+id = "state_16"
+category = "performance"
+observations = [
+    "nominal:state_16",
+]
+unit = "V"
+direction = "maximize"
+aggregation = "min"
+lower = 0.9
+
+[[task.evaluation.metrics]]
+id = "supply"
+category = "performance"
+observations = [
+    "nominal:supply",
+]
+unit = "W"
+direction = "minimize"
+aggregation = "max"
+dimension = "supply"
+baseline = [
+    "source_nominal:supply",
+]
+normalization = "ratio"
+lower = 0
+scale = 1e-12
+
+[[task.evaluation.metrics]]
+id = "propagation_delay"
+category = "performance"
+observations = [
+    "nominal:delay_b1_fall_2",
+    "nominal:delay_b2_rise_3",
+    "nominal:delay_a_fall_4",
+    "nominal:delay_a_rise_8",
+    "nominal:delay_a_fall_9",
+    "nominal:delay_a_rise_13",
+    "nominal:delay_b2_fall_14",
+    "nominal:delay_b1_rise_15",
+]
+unit = "s"
+direction = "minimize"
+aggregation = "max"
+dimension = "response"
+baseline = [
+    "source_nominal:delay_b1_fall_2",
+    "source_nominal:delay_b2_rise_3",
+    "source_nominal:delay_a_fall_4",
+    "source_nominal:delay_a_rise_8",
+    "source_nominal:delay_a_fall_9",
+    "source_nominal:delay_a_rise_13",
+    "source_nominal:delay_b2_fall_14",
+    "source_nominal:delay_b1_rise_15",
+]
+normalization = "ratio"
+lower = 0
+
+[[task.evaluation.metrics]]
+id = "output_transition"
+category = "performance"
+observations = [
+    "nominal:transition_b1_fall_2",
+    "nominal:transition_b2_rise_3",
+    "nominal:transition_a_fall_4",
+    "nominal:transition_a_rise_8",
+    "nominal:transition_a_fall_9",
+    "nominal:transition_a_rise_13",
+    "nominal:transition_b2_fall_14",
+    "nominal:transition_b1_rise_15",
+]
+unit = "s"
+direction = "minimize"
+aggregation = "max"
+dimension = "response"
+baseline = [
+    "source_nominal:transition_b1_fall_2",
+    "source_nominal:transition_b2_rise_3",
+    "source_nominal:transition_a_fall_4",
+    "source_nominal:transition_a_rise_8",
+    "source_nominal:transition_a_fall_9",
+    "source_nominal:transition_a_rise_13",
+    "source_nominal:transition_b2_fall_14",
+    "source_nominal:transition_b1_rise_15",
+]
+normalization = "ratio"
+lower = 0
+
+[task.evaluation.scoring]
+method = "layout"
+area_metric = "functional_area"
+area_target = 2.0049
+rationale = "Standard-cell logic: propagation delay 48%; output transition 16%; supply power 16%; area 20%. Each objective's weight is divided equally among its metrics."
+
+[task.evaluation.scoring.weights]
+functional_area = 0.2
+propagation_delay = 0.48
+output_transition = 0.16
+supply = 0.16
+
+[task.evaluation.pre_layout]
+source_report_sha256 = "2a3f55d7521f2e9338277bf7bd78bf43b1d66c5c9262d5c5afc06f73e69257db"
+
+[task.evaluation.pre_layout.backends]
+"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"ef9cb87fa27b849376472663b7362673979b89e012f161ba47bb5f6af6ede8eb\", \"compatibility\": null, \"execution_sha256\": \"5424b579002782bfddf0a729715b8fbf2a5f7f2b4cf14982d7616e352d5de9be\", \"image_id\": \"sha256:6562558774d43c085a289bbba696c55959eb8051a0996f96633451fbeb9c652d\", \"limits\": {\"cpus\": 4, \"memory_mb\": 4096, \"pids\": 256}, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"7fc8a0cde0f7d722e87c34a1115c13986b3db8fecba4b7dadb0a1edf171df62b\", \"timeout_seconds\": 120.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}"
+
+[task.evaluation.pre_layout.jobs.source_nominal]
+operation = "circuit.simulate"
+
+[task.evaluation.pre_layout.jobs.source_nominal.inputs]
+deck = "input:performance"
+dut = "input:netlist"
+
+[task.evaluation.pre_layout.jobs.source_nominal.outputs]
+waveform = "ngspice-raw"
+
+[task.evaluation.pre_layout.jobs.source_nominal.parameters.exports]
+waveform = "waveform.raw"
+
+[task.evaluation.pre_layout.jobs.source_nominal.parameters.measurements]
+state_0 = "V"
+state_1 = "V"
+state_2 = "V"
+state_3 = "V"
+state_4 = "V"
+state_5 = "V"
+state_6 = "V"
+state_7 = "V"
+state_8 = "V"
+state_9 = "V"
+state_10 = "V"
+state_11 = "V"
+state_12 = "V"
+state_13 = "V"
+state_14 = "V"
+state_15 = "V"
+state_16 = "V"
+supply = "W"
+delay_b1_fall_2 = "s"
+transition_b1_fall_2 = "s"
+delay_b2_rise_3 = "s"
+transition_b2_rise_3 = "s"
+delay_a_fall_4 = "s"
+transition_a_fall_4 = "s"
+delay_a_rise_8 = "s"
+transition_a_rise_8 = "s"
+delay_a_fall_9 = "s"
+transition_a_fall_9 = "s"
+delay_a_rise_13 = "s"
+transition_a_rise_13 = "s"
+delay_b2_fall_14 = "s"
+transition_b2_fall_14 = "s"
+delay_b1_rise_15 = "s"
+transition_b1_rise_15 = "s"
+
+[task.evaluation.pre_layout.jobs.source_nominal.input_sha256]
+deck = "f8401ddcc740853f48b867b25e5bbf895409a9d1df90dfd5b013f31d236aa6b8"
+dut = "07d8b2857f5ecd7bde8d5b3e231b16b6819272db2d19c1ee4882094e04bc909e"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.delay_a_fall_4]
+value = 1.163873e-11
+unit = "s"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.delay_a_fall_9]
+value = 1.228236e-11
+unit = "s"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.delay_a_rise_13]
+value = 1.992426e-11
+unit = "s"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.delay_a_rise_8]
+value = 1.523821e-11
+unit = "s"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.delay_b1_fall_2]
+value = 1.536536e-11
+unit = "s"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.delay_b1_rise_15]
+value = 1.536857e-11
+unit = "s"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.delay_b2_fall_14]
+value = 1.620396e-11
+unit = "s"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.delay_b2_rise_3]
+value = 1.698568e-11
+unit = "s"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.state_0]
+value = 0.999952
+unit = "V"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.state_1]
+value = 0.9998967
+unit = "V"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.state_10]
+value = 0.0003069374
+unit = "V"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.state_11]
+value = 1.216504e-06
+unit = "V"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.state_12]
+value = 7.794863e-05
+unit = "V"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.state_13]
+value = 0.99935
+unit = "V"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.state_14]
+value = 0.0001950317
+unit = "V"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.state_15]
+value = 0.9998362
+unit = "V"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.state_16]
+value = 0.9997699
+unit = "V"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.state_2]
+value = 0.0001918556
+unit = "V"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.state_3]
+value = 0.9994024
+unit = "V"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.state_4]
+value = 0.0004865273
+unit = "V"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.state_5]
+value = 1.239731e-06
+unit = "V"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.state_6]
+value = 8.142936e-05
+unit = "V"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.state_7]
+value = -3.673975e-05
+unit = "V"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.state_8]
+value = 0.9998379
+unit = "V"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.state_9]
+value = 0.0004804343
+unit = "V"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.supply]
+value = 4.305193e-06
+unit = "W"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.transition_a_fall_4]
+value = 1.3624e-11
+unit = "s"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.transition_a_fall_9]
+value = 1.274633e-11
+unit = "s"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.transition_a_rise_13]
+value = 2.079778e-11
+unit = "s"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.transition_a_rise_8]
+value = 1.548592e-11
+unit = "s"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.transition_b1_fall_2]
+value = 1.762384e-11
+unit = "s"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.transition_b1_rise_15]
+value = 1.878498e-11
+unit = "s"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.transition_b2_fall_14]
+value = 1.762316e-11
+unit = "s"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.transition_b2_rise_3]
+value = 2.078537e-11
+unit = "s"
+
+[toolchain.backends.artifact]
+type = "klayout-docker"
+
+[toolchain.backends.artifact.settings]
+image = "iclayout-bench-tools:local"
+check = "artifact"
+timeout_seconds = 120
+
+[toolchain.backends.drc]
+type = "klayout-docker"
+
+[toolchain.backends.drc.settings]
+image = "iclayout-bench-tools:local"
+check = "drc"
+timeout_seconds = 120
+support = "build/support/freepdk45-klayout"
+profile = "drc.json"
+
+[toolchain.backends.drc.support_profiles]
+support = "klayout"
+
+[toolchain.backends.lvs]
+type = "klayout-docker"
+
+[toolchain.backends.lvs.settings]
+image = "iclayout-bench-tools:local"
+check = "lvs"
+timeout_seconds = 120
+support = "build/support/freepdk45-klayout"
+profile = "strict-lvs.json"
+
+[toolchain.backends.lvs.support_profiles]
+support = "klayout"
+
+[toolchain.backends.geometry]
+type = "klayout-geometry-docker"
+
+[toolchain.backends.geometry.settings]
+image = "iclayout-bench-tools:local"
+timeout_seconds = 60
+
+[toolchain.backends.rc]
+type = "magic-rc-docker"
+
+[toolchain.backends.rc.settings]
+image = "iclayout-bench-tools:local"
+support = "build/support/freepdk45-magic-vtl"
+technology = "freepdk45.tech"
+tech_name = "freepdk45"
+style = "spice3(sim)"
+gds_readonly = false
+case_insensitive_ports = true
+label_layers = [
+    [
+        9,
+        0,
+    ],
+    [
+        11,
+        0,
+    ],
+    [
+        13,
+        0,
+    ],
+    [
+        15,
+        0,
+    ],
+    [
+        17,
+        0,
+    ],
+    [
+        19,
+        0,
+    ],
+    [
+        21,
+        0,
+    ],
+    [
+        23,
+        0,
+    ],
+    [
+        25,
+        0,
+    ],
+    [
+        27,
+        0,
+    ],
+    [
+        29,
+        0,
+    ],
+]
+timeout_seconds = 120
+
+[toolchain.backends.rc.support_profiles]
+support = "magic-vtl"
+
+[toolchain.backends.ngspice]
+type = "ngspice-docker"
+
+[toolchain.backends.ngspice.settings]
+image = "iclayout-bench-tools:local"
+support = "build/support/freepdk45-models"
+timeout_seconds = 120
+
+[toolchain.backends.ngspice.support_profiles]
+support = "models"
+
+[toolchain.bindings]
+"layout.artifact" = "artifact"
+"layout.drc" = "drc"
+"layout.lvs" = "lvs"
+"layout.geometry" = "geometry"
+"layout.extract_rc" = "rc"
+"circuit.simulate" = "ngspice"
+
+[qualification]
+reference = "reference/AOI21_X1.gds"
+
+[origin]
+url = "https://foss-eda-tools.googlesource.com/third_party/freepdk45/+/356e90646f5ef26ea09b1ed8ce4796871403a0c7/Back_End/spice/AOI21_X1.spi"
+
+[presentation]
+category = "Logic & memory"
+summary = "Implements AND-OR-invert logic in a fixed-height standard cell."

tasks/freepdk45/nangate45-pdk/cases/AOI21_X1/materials/circuit.spice

@@ -0,0 +1,58 @@
+* 
+* ******************************************************************************
+* *                                                                            *
+* *                   Copyright (C) 2004-2010, Nangate Inc.                    *
+* *                           All rights reserved.                             *
+* *                                                                            *
+* * Nangate and the Nangate logo are trademarks of Nangate Inc.                *
+* *                                                                            *
+* * All trademarks, logos, software marks, and trade names (collectively the   *
+* * "Marks") in this program are proprietary to Nangate or other respective    *
+* * owners that have granted Nangate the right and license to use such Marks.  *
+* * You are not permitted to use the Marks without the prior written consent   *
+* * of Nangate or such third party that may own the Marks.                     *
+* *                                                                            *
+* * This file has been provided pursuant to a License Agreement containing     *
+* * restrictions on its use. This file contains valuable trade secrets and     *
+* * proprietary information of Nangate Inc., and is protected by U.S. and      *
+* * international laws and/or treaties.                                        *
+* *                                                                            *
+* * The copyright notice(s) in this file does not indicate actual or intended  *
+* * publication of this file.                                                  *
+* *                                                                            *
+* *         buildcell, v2010.08-HR32-SP3-2010-08-05 - build 1009061800         *
+* *                                                                            *
+* ******************************************************************************
+* 
+* 
+* Running on brazil06.nangate.com.br for user Giancarlo Franciscatto (gfr).
+* Local time is now Fri, 3 Dec 2010, 19:18:00.
+* Main process id is 28034.
+*
+********************************************************************************
+*                                                                              *
+* Cellname:   AOI21_X1.                                                        *
+*                                                                              *
+* Technology: NCSU FreePDK 45nm.                                               *
+* Format:     Cdl.                                                             *
+*                                                                              *
+* Written on brazil06.nangate.com.br for user Giancarlo Franciscatto (gfr)     *
+* at 19:18:00 on Fri, 3 Dec 2010.                                              *
+*                                                                              *
+********************************************************************************
+.SUBCKT AOI21_X1 A B1 B2 ZN VDD VSS 
+*.PININFO A:I B1:I B2:I ZN:O VDD:P VSS:G 
+*.EQN ZN=!(A + (B1 * B2))
+M_i_1 net_0 B2 VSS VSS NMOS_VTL W=0.415000U L=0.050000U
+M_i_0 ZN B1 net_0 VSS NMOS_VTL W=0.415000U L=0.050000U
+M_i_2 VSS A ZN VSS NMOS_VTL W=0.415000U L=0.050000U
+M_i_4 ZN B2 net_1 VDD PMOS_VTL W=0.630000U L=0.050000U
+M_i_3 net_1 B1 ZN VDD PMOS_VTL W=0.630000U L=0.050000U
+M_i_5 VDD A net_1 VDD PMOS_VTL W=0.630000U L=0.050000U
+.ENDS 
+
+********************************************************************************
+*
+* END
+*
+********************************************************************************

tasks/freepdk45/nangate45-pdk/cases/AOI21_X1/materials/testbench.spice

@@ -0,0 +1,52 @@
+* AOI21_X1: exhaustive Gray sequence and reversed sequence
+.include /workspace/support/models.spice
+.include dut.spice
+.temp 27
+Vdd vdd 0 1
+Vss vss 0 0
+Xdut A B1 B2 ZN VDD VSS AOI21_X1
+Cl ZN 0 5f
+VA A 0 PWL(0 0 0.500n 0 0.510n 0 1.000n 0 1.010n 0 1.500n 0 1.510n 0 2.000n 0 2.010n 1 2.500n 1 2.510n 1 3.000n 1 3.010n 1 3.500n 1 3.510n 1 4.000n 1 4.010n 0 4.500n 0 4.510n 1 5.000n 1 5.010n 1 5.500n 1 5.510n 1 6.000n 1 6.010n 1 6.500n 1 6.510n 0 7.000n 0 7.010n 0 7.500n 0 7.510n 0 8.000n 0 8.010n 0)
+VB1 B1 0 PWL(0 0 0.500n 0 0.510n 0 1.000n 0 1.010n 1 1.500n 1 1.510n 1 2.000n 1 2.010n 1 2.500n 1 2.510n 1 3.000n 1 3.010n 0 3.500n 0 3.510n 0 4.000n 0 4.010n 0 4.500n 0 4.510n 0 5.000n 0 5.010n 0 5.500n 0 5.510n 1 6.000n 1 6.010n 1 6.500n 1 6.510n 1 7.000n 1 7.010n 1 7.500n 1 7.510n 0 8.000n 0 8.010n 0)
+VB2 B2 0 PWL(0 0 0.500n 0 0.510n 1 1.000n 1 1.010n 1 1.500n 1 1.510n 0 2.000n 0 2.010n 0 2.500n 0 2.510n 1 3.000n 1 3.010n 1 3.500n 1 3.510n 0 4.000n 0 4.010n 0 4.500n 0 4.510n 0 5.000n 0 5.010n 1 5.500n 1 5.510n 1 6.000n 1 6.010n 0 6.500n 0 6.510n 0 7.000n 0 7.010n 1 7.500n 1 7.510n 1 8.000n 1 8.010n 0)
+.tran 0.5p 8.500n
+.meas tran state_0 find v(ZN) at=0.110n
+.meas tran state_1 find v(ZN) at=0.610n
+.meas tran state_2 find v(ZN) at=1.110n
+.meas tran state_3 find v(ZN) at=1.610n
+.meas tran state_4 find v(ZN) at=2.110n
+.meas tran state_5 find v(ZN) at=2.610n
+.meas tran state_6 find v(ZN) at=3.110n
+.meas tran state_7 find v(ZN) at=3.610n
+.meas tran state_8 find v(ZN) at=4.110n
+.meas tran state_9 find v(ZN) at=4.610n
+.meas tran state_10 find v(ZN) at=5.110n
+.meas tran state_11 find v(ZN) at=5.610n
+.meas tran state_12 find v(ZN) at=6.110n
+.meas tran state_13 find v(ZN) at=6.610n
+.meas tran state_14 find v(ZN) at=7.110n
+.meas tran state_15 find v(ZN) at=7.610n
+.meas tran state_16 find v(ZN) at=8.110n
+.meas tran supply avg par('-v(vdd)*i(Vdd)') from=0 to=8.400n
+.meas tran delay_b1_fall_2 trig v(B1) val=0.5 rise=1 td=1n targ v(ZN) val=0.5 fall=1 td=1n
+.meas tran transition_b1_fall_2 trig v(ZN) val=0.8 fall=1 td=1n targ v(ZN) val=0.2 fall=1 td=1n
+.meas tran delay_b2_rise_3 trig v(B2) val=0.5 fall=1 td=1.5n targ v(ZN) val=0.5 rise=1 td=1.5n
+.meas tran transition_b2_rise_3 trig v(ZN) val=0.2 rise=1 td=1.5n targ v(ZN) val=0.8 rise=1 td=1.5n
+.meas tran delay_a_fall_4 trig v(A) val=0.5 rise=1 td=2n targ v(ZN) val=0.5 fall=1 td=2n
+.meas tran transition_a_fall_4 trig v(ZN) val=0.8 fall=1 td=2n targ v(ZN) val=0.2 fall=1 td=2n
+.meas tran delay_a_rise_8 trig v(A) val=0.5 fall=1 td=4n targ v(ZN) val=0.5 rise=1 td=4n
+.meas tran transition_a_rise_8 trig v(ZN) val=0.2 rise=1 td=4n targ v(ZN) val=0.8 rise=1 td=4n
+.meas tran delay_a_fall_9 trig v(A) val=0.5 rise=1 td=4.5n targ v(ZN) val=0.5 fall=1 td=4.5n
+.meas tran transition_a_fall_9 trig v(ZN) val=0.8 fall=1 td=4.5n targ v(ZN) val=0.2 fall=1 td=4.5n
+.meas tran delay_a_rise_13 trig v(A) val=0.5 fall=1 td=6.5n targ v(ZN) val=0.5 rise=1 td=6.5n
+.meas tran transition_a_rise_13 trig v(ZN) val=0.2 rise=1 td=6.5n targ v(ZN) val=0.8 rise=1 td=6.5n
+.meas tran delay_b2_fall_14 trig v(B2) val=0.5 rise=1 td=7n targ v(ZN) val=0.5 fall=1 td=7n
+.meas tran transition_b2_fall_14 trig v(ZN) val=0.8 fall=1 td=7n targ v(ZN) val=0.2 fall=1 td=7n
+.meas tran delay_b1_rise_15 trig v(B1) val=0.5 fall=1 td=7.5n targ v(ZN) val=0.5 rise=1 td=7.5n
+.meas tran transition_b1_rise_15 trig v(ZN) val=0.2 rise=1 td=7.5n targ v(ZN) val=0.8 rise=1 td=7.5n
+.control
+run
+write waveform.raw v(A) v(B1) v(B2) v(ZN) v(VDD) i(Vdd)
+quit
+.endc
+.end

tasks/freepdk45/nangate45-pdk/cases/AOI21_X1/problem.md

@@ -0,0 +1,126 @@
+# AND-OR-Invert Gate Layout Task
+
+## Objective
+
+Implement ZN = NOT (A OR (B1 AND B2)) using the supplied VTL transistors. Preserve the authoritative netlist's model classes, W/L, interface and connectivity. Submit top cell `AOI21_X1`.
+
+## Inputs and Interface
+
+Ordered SPICE ports: `A B1 B2 ZN VDD VSS`. Names are case-insensitive; different names are not interchangeable. The delivered inputs are this problem, `materials/circuit.spice`, and `materials/testbench.spice`. The model and extraction resources are supplied as reviewed support bundles. Reference geometry and qualification evidence are maintainer materials, excluded from solver inputs.
+
+## Operating Conditions
+
+Use the nominal FreePDK45 BSIM4 models at **1.0 V and 27 C**, with ground at 0 V. All transistor lengths are 50 nm; widths and model classes come from the netlist.
+
+ZN drives 5 fF. Apply the three-bit Gray cycle 000, 001, 011, 010, 110, 111, 101, 100, 000 and then its reverse to A/B1/B2 in 500 ps slots, with 10 ps edges. Sample ZN at slot start + 110 ps. This covers the truth table and both directions of every transition in that cycle. Average DUT supply power over 0–8.4 ns.
+
+The deck defines stimuli and observation times exactly. Tests use only external ports. Qualification covers these nominal conditions, not PVT, mismatch, array abutment, substrate noise or manufacturing signoff.
+
+## Physical Requirements
+
+Submit a nonempty GDSII of at most 10 MiB. Enable all checks present in the supplied KLayout DRC deck, including grid and antenna checks, with no waivers. Strict LVS checks named ports, models, W/L and actual well/tap connectivity; library-specific implicit or global rail connections are disabled. The upstream deck does not implement its documented different-potential well-spacing rule; it is not a complete foundry signoff deck.
+
+The hard functional envelope is 100 um by 100 um. Its bounding rectangle includes every drawing layer 1/0 through 29/0: active, wells, implants, threshold markers, poly, contacts, all ten metals and all nine vias. It supplies the scored footprint in um2. Put functional geometry on these layers; pin-purpose and annotation geometry is excluded. Electrical labels use poly or metal drawing layers (9/0 and 11/0, 13/0, ..., 29/0). Non-electrical annotation text is ignored by extraction.
+
+Translation, equivalent hierarchy and internal instance renaming are allowed. LVS permits source/drain exchange and equivalent parallel devices; any such layout must also pass the same RC-based electrical requirements. Preserve top-level port identities and explicit body connections.
+
+
+The standard-cell functional frame has fixed height 1.63 um and width on a 0.01 um grid. Coordinates below are relative to its lower-left functional bound; global translation remains allowed. Supply rails must be continuous on metal1 and bound by LVS to the named supply.
+
+- `VDD`: centre y = 1.515 um, thickness at least 0.07 um, from left + 0.115 um to right − 0.03 um.
+- `VSS`: centre y = 0.115 um, thickness at least 0.07 um, from left + 0.115 um to right − 0.03 um.
+
+## Electrical Requirements and Scoring
+
+Artifact, DRC, LVS and geometry gates precede candidate GDS extraction. Simulation consumes the candidate's Magic RC netlist unchanged; source simulation supplies the independent scoring baseline. VTG/VTL device classes are checked by independent LVS before the matching extraction profile is used. Extraction includes poly/metal sheet resistance, contacts/vias, geometry-dependent coupling and ground capacitance, and device junction area/perimeter. Wells are lumped connections; BSIM4 supplies device/junction behavior. Interconnect resistance and capacitance use the pinned community FreePDK45 Magic technology's estimated coefficients and native capacitance placement. The extraction adapter binds VTG/VTL models, preserves annotation layers and corrects the technology's dimensional unit conversion. This is a predictive approximation without field-solver signoff accuracy.
+
+Physical checks and declared functional bounds remain mandatory. Quality has no
+fixed allowed-degradation threshold. Each `source_*` job simulates the declared
+source circuit with exactly the same testbench, model resources, parameters,
+load and measurement window as its paired extracted-candidate job. A source
+observation is the 100-point electrical baseline; it is independent of the
+submitted GDS. All individual pairs are retained in the evaluation report.
+
+For a post-layout observation x and its source observation b:
+
+- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,
+  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;
+  s is a normalization floor, not an allowed degradation or pass threshold.
+- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.
+- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and
+  zero-valued operating points are never divided directly.
+
+Scoring uses `layout`. A metric uses its worst paired quality q. The score is
+S = 100 * product(q_i ** w_i), including area quality
+q_area = area_reference / candidate_functional_area. The weights below sum to
+one. Dimensions describe measurements but do not determine their weights.
+Physical or functional rejection scores zero; missing or invalid measurements
+produce an unknown score, including measurements with zero weight.
+Source-equivalent performance at the area reference scores 100; improvements
+can exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.
+
+| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale |
+| --- | --- | --- | --- | --- | --- |
+| `state_0` | `find v(ZN) at=0.110n` | V | functional check | 0.9 … +∞ | — |
+| `state_1` | `find v(ZN) at=0.610n` | V | functional check | 0.9 … +∞ | — |
+| `state_2` | `find v(ZN) at=1.110n` | V | functional check | −∞ … 0.1 | — |
+| `state_3` | `find v(ZN) at=1.610n` | V | functional check | 0.9 … +∞ | — |
+| `state_4` | `find v(ZN) at=2.110n` | V | functional check | −∞ … 0.1 | — |
+| `state_5` | `find v(ZN) at=2.610n` | V | functional check | −∞ … 0.1 | — |
+| `state_6` | `find v(ZN) at=3.110n` | V | functional check | −∞ … 0.1 | — |
+| `state_7` | `find v(ZN) at=3.610n` | V | functional check | −∞ … 0.1 | — |
+| `state_8` | `find v(ZN) at=4.110n` | V | functional check | 0.9 … +∞ | — |
+| `state_9` | `find v(ZN) at=4.610n` | V | functional check | −∞ … 0.1 | — |
+| `state_10` | `find v(ZN) at=5.110n` | V | functional check | −∞ … 0.1 | — |
+| `state_11` | `find v(ZN) at=5.610n` | V | functional check | −∞ … 0.1 | — |
+| `state_12` | `find v(ZN) at=6.110n` | V | functional check | −∞ … 0.1 | — |
+| `state_13` | `find v(ZN) at=6.610n` | V | functional check | 0.9 … +∞ | — |
+| `state_14` | `find v(ZN) at=7.110n` | V | functional check | −∞ … 0.1 | — |
+| `state_15` | `find v(ZN) at=7.610n` | V | functional check | 0.9 … +∞ | — |
+| `state_16` | `find v(ZN) at=8.110n` | V | functional check | 0.9 … +∞ | — |
+| `supply` | `avg par('-v(vdd)*i(Vdd)') from=0 to=8.400n` | W | minimize / ratio | 0 … +∞ | 1e-12 |
+| `propagation_delay` | Worst paired quality over: delay_b1_fall_2, delay_b2_rise_3, delay_a_fall_4, delay_a_rise_8, delay_a_fall_9, delay_a_rise_13, delay_b2_fall_14, delay_b1_rise_15. | s | minimize / ratio | 0 … +∞ | — |
+| `output_transition` | Worst paired quality over: transition_b1_fall_2, transition_b2_rise_3, transition_a_fall_4, transition_a_rise_8, transition_a_fall_9, transition_a_rise_13, transition_b2_fall_14, transition_b1_rise_15. | s | minimize / ratio | 0 … +∞ | — |
+
+Area reference: **2.0049 um2**. Complete functional bounding rectangle of the declared standard-cell reference GDS: 1.23 by 1.63 um = 2.0049 um2. Reference SHA-256: 1ebcc6f4d7a8f5c50846b5cdfd60f3039fb96caf455b89f2d7f30568c5a2af94. This footprint includes the maintained explicit taps and routing.
+
+The capability coefficient remains **2**; it is independent of
+the reference-relative task score.
+
+### Standard-cell design guidance
+
+Plan the device rows, power rails and signal access before routing. Represent
+pull-up and pull-down connectivity as transistor-edge graphs; explore compatible
+Euler trails and alternative orderings to share diffusion and reduce breaks.
+Choose among legal orderings using routing length, parasitic loading and signal
+access, rather than diffusion sharing alone. Preserve the fixed netlist sizes,
+models and connectivity; size optimization is outside this task.
+
+Use the task's declared row height, grid and rail geometry. Keep local routes
+compact, leave signal pins accessible, and avoid consuming extra routing layers
+without benefit. Check DRC and named-port LVS, then extract the candidate and
+compare both transition directions and power with the source simulation. Iterate
+on measured parasitic effects rather than visual compactness alone. These are
+optional techniques, not a mandated algorithm or reference placement.
+
+Adapted from Xu et al., *Standard Cell Library Design and Optimization Methodology
+for ASAP7 PDK*, Sections 2–3 (https://arxiv.org/abs/1807.11396). Its FinFET sizing,
+track counts and process-specific dimensions do not apply to this task.
+
+
+### Score weights
+
+Standard-cell logic: propagation delay 48%; output transition 16%; supply power 16%; area 20%. Each objective's weight is divided equally among its metrics.
+
+| Metric | Weight |
+| --- | ---: |
+| `functional_area` | 0.2 |
+| `propagation_delay` | 0.480000000000 |
+| `output_transition` | 0.160000000000 |
+| `supply` | 0.160000000000 |
+
+## Tools and Submission
+
+Solve budget: **3 hours**.
+
+Use the reviewed FreePDK45 KLayout, Magic and ngspice resources from `/protocol/resources.json`. For Magic RC extraction, use `/resources/support/magic-vtl/freepdk45.tech`, which includes the required model and unit adaptations. Runtime `/protocol/task.json` publishes the same constraints, measurements and scoring. Only declared inputs appear under `/task`. Write `/workspace/output/final.gds`, then explicitly submit with `python -I /protocol/submit.py`. A harness that declares `process-feedback` uses the same frozen plan and backend identities for process checks; those snapshots do not count as final submissions.

tasks/freepdk45/nangate45-pdk/cases/NAND2_X1/case.toml

@@ -0,0 +1,872 @@
+in_core = true
+kind = "layout_case"
+id = "freepdk45.nangate45-pdk.NAND2_X1"
+title = "Two-Input NAND"
+status = "qualified"
+
+[[assets]]
+path = "reference/NAND2_X1.gds"
+role = "reference"
+visibility = "maintainer"
+format = "gds"
+sha256 = "d077499ea242e1c8506c7a992ce713d46ea513c52b80073a2b7ae6d6515f2d3f"
+
+[[assets]]
+path = "materials/schematic.svg"
+role = "schematic"
+visibility = "maintainer"
+format = "svg"
+sha256 = "b01b8aa3a1ff8bbe322d92979d9d59e897d655c9e002c7f50b83916ae96b19da"
+
+[task]
+hours = 3
+kind = "netlist_to_gds"
+family = "freepdk45_nand2_x1"
+coefficient = 1
+environment = "freepdk45-nominal-predictive-rc"
+
+[task.inputs.description]
+path = "problem.md"
+sha256 = "26feeab7c4edda1754cfed7055c6507b8a04b5383401b55b1761c1dc8f76d454"
+format = "text"
+
+[task.inputs.netlist]
+path = "materials/circuit.spice"
+sha256 = "1decfdcffa5a7f962e26c0831e9a219521670f282df72e465fd61ebccdba12b0"
+format = "spice"
+subcircuit = "NAND2_X1"
+
+[task.inputs.performance]
+path = "materials/testbench.spice"
+sha256 = "389d2d09f05913f740d0b776e0fe2d4382057b2bc8a23564f4150adae920e4c9"
+format = "spice"
+
+[task.constraints]
+quality = [
+    { id = "area", type = "functional_bbox_area", layers_from = "outline" },
+]
+
+[[task.constraints.hard]]
+id = "outline"
+type = "bbox_max"
+functional_layers = [
+    [
+        1,
+        0,
+    ],
+    [
+        2,
+        0,
+    ],
+    [
+        3,
+        0,
+    ],
+    [
+        4,
+        0,
+    ],
+    [
+        5,
+        0,
+    ],
+    [
+        6,
+        0,
+    ],
+    [
+        7,
+        0,
+    ],
+    [
+        8,
+        0,
+    ],
+    [
+        9,
+        0,
+    ],
+    [
+        10,
+        0,
+    ],
+    [
+        11,
+        0,
+    ],
+    [
+        12,
+        0,
+    ],
+    [
+        13,
+        0,
+    ],
+    [
+        14,
+        0,
+    ],
+    [
+        15,
+        0,
+    ],
+    [
+        16,
+        0,
+    ],
+    [
+        17,
+        0,
+    ],
+    [
+        18,
+        0,
+    ],
+    [
+        19,
+        0,
+    ],
+    [
+        20,
+        0,
+    ],
+    [
+        21,
+        0,
+    ],
+    [
+        22,
+        0,
+    ],
+    [
+        23,
+        0,
+    ],
+    [
+        24,
+        0,
+    ],
+    [
+        25,
+        0,
+    ],
+    [
+        26,
+        0,
+    ],
+    [
+        27,
+        0,
+    ],
+    [
+        28,
+        0,
+    ],
+    [
+        29,
+        0,
+    ],
+]
+max_width_um = 100
+max_height_um = 100
+
+[[task.constraints.hard]]
+id = "cell_frame"
+type = "cell_frame"
+functional_layers = [
+    [
+        1,
+        0,
+    ],
+    [
+        2,
+        0,
+    ],
+    [
+        3,
+        0,
+    ],
+    [
+        4,
+        0,
+    ],
+    [
+        5,
+        0,
+    ],
+    [
+        6,
+        0,
+    ],
+    [
+        7,
+        0,
+    ],
+    [
+        8,
+        0,
+    ],
+    [
+        9,
+        0,
+    ],
+    [
+        10,
+        0,
+    ],
+    [
+        11,
+        0,
+    ],
+    [
+        12,
+        0,
+    ],
+    [
+        13,
+        0,
+    ],
+    [
+        14,
+        0,
+    ],
+    [
+        15,
+        0,
+    ],
+    [
+        16,
+        0,
+    ],
+    [
+        17,
+        0,
+    ],
+    [
+        18,
+        0,
+    ],
+    [
+        19,
+        0,
+    ],
+    [
+        20,
+        0,
+    ],
+    [
+        21,
+        0,
+    ],
+    [
+        22,
+        0,
+    ],
+    [
+        23,
+        0,
+    ],
+    [
+        24,
+        0,
+    ],
+    [
+        25,
+        0,
+    ],
+    [
+        26,
+        0,
+    ],
+    [
+        27,
+        0,
+    ],
+    [
+        28,
+        0,
+    ],
+    [
+        29,
+        0,
+    ],
+]
+height_um = 1.6300000000000001
+width_grid_um = 0.01
+
+[[task.constraints.hard.rails]]
+name = "VDD"
+layer = [
+    11,
+    0,
+]
+connectivity_layer = "metal1"
+y_um = 1.5150000000000001
+thickness_um = 0.07
+left_um = 0.115
+right_um = 0.030000000000000002
+
+[[task.constraints.hard.rails]]
+name = "VSS"
+layer = [
+    11,
+    0,
+]
+connectivity_layer = "metal1"
+y_um = 0.115
+thickness_um = 0.07
+left_um = 0.115
+right_um = 0.030000000000000002
+
+[task.output]
+path = "output/final.gds"
+format = "gds"
+top_cell = "NAND2_X1"
+max_bytes = 10485760
+
+[task.evaluation]
+mode = "post_layout"
+
+[[task.evaluation.jobs]]
+id = "artifact"
+stage = "check"
+operation = "layout.artifact"
+gate = "artifact"
+
+[task.evaluation.jobs.inputs]
+layout = "candidate"
+task = "task"
+
+[[task.evaluation.jobs]]
+id = "drc"
+stage = "check"
+operation = "layout.drc"
+gate = "drc"
+
+[task.evaluation.jobs.inputs]
+layout = "candidate"
+task = "task"
+
+[[task.evaluation.jobs]]
+id = "lvs"
+stage = "check"
+operation = "layout.lvs"
+gate = "lvs"
+
+[task.evaluation.jobs.inputs]
+layout = "candidate"
+task = "task"
+netlist = "input:netlist"
+
+[task.evaluation.jobs.outputs]
+database = "klayout-lvs"
+binding = "json"
+
+[[task.evaluation.jobs]]
+id = "geometry"
+stage = "check"
+operation = "layout.geometry"
+gate = "constraint"
+requires = [
+    "artifact",
+    "drc",
+    "lvs",
+]
+
+[task.evaluation.jobs.inputs]
+layout = "candidate"
+task = "task"
+constraints = "input:constraints"
+database = "job:lvs:database"
+binding = "job:lvs:binding"
+
+[[task.evaluation.jobs]]
+id = "parasitics"
+stage = "extract"
+operation = "layout.extract_rc"
+requires = [
+    "artifact",
+    "drc",
+    "lvs",
+    "geometry",
+]
+
+[task.evaluation.jobs.inputs]
+layout = "candidate"
+task = "task"
+
+[task.evaluation.jobs.outputs]
+netlist = "spice"
+
+[task.evaluation.jobs.parameters]
+ports = [
+    "A1",
+    "A2",
+    "ZN",
+    "VDD",
+    "VSS",
+]
+
+[[task.evaluation.jobs]]
+id = "nominal"
+stage = "simulate"
+operation = "circuit.simulate"
+
+[task.evaluation.jobs.inputs]
+deck = "input:performance"
+dut = "job:parasitics:netlist"
+
+[task.evaluation.jobs.outputs]
+waveform = "ngspice-raw"
+
+[task.evaluation.jobs.parameters.exports]
+waveform = "waveform.raw"
+
+[task.evaluation.jobs.parameters.measurements]
+state_0 = "V"
+state_1 = "V"
+state_2 = "V"
+state_3 = "V"
+state_4 = "V"
+state_5 = "V"
+state_6 = "V"
+state_7 = "V"
+state_8 = "V"
+supply = "W"
+delay_a1_fall_2 = "s"
+transition_a1_fall_2 = "s"
+delay_a2_rise_3 = "s"
+transition_a2_rise_3 = "s"
+delay_a2_fall_6 = "s"
+transition_a2_fall_6 = "s"
+delay_a1_rise_7 = "s"
+transition_a1_rise_7 = "s"
+
+[[task.evaluation.metrics]]
+id = "functional_area"
+category = "physical"
+observations = [
+    "geometry:area",
+]
+unit = "um2"
+direction = "minimize"
+aggregation = "max"
+
+[[task.evaluation.metrics]]
+id = "state_0"
+category = "performance"
+observations = [
+    "nominal:state_0",
+]
+unit = "V"
+direction = "maximize"
+aggregation = "min"
+lower = 0.9
+
+[[task.evaluation.metrics]]
+id = "state_1"
+category = "performance"
+observations = [
+    "nominal:state_1",
+]
+unit = "V"
+direction = "maximize"
+aggregation = "min"
+lower = 0.9
+
+[[task.evaluation.metrics]]
+id = "state_2"
+category = "performance"
+observations = [
+    "nominal:state_2",
+]
+unit = "V"
+direction = "minimize"
+aggregation = "max"
+upper = 0.1
+
+[[task.evaluation.metrics]]
+id = "state_3"
+category = "performance"
+observations = [
+    "nominal:state_3",
+]
+unit = "V"
+direction = "maximize"
+aggregation = "min"
+lower = 0.9
+
+[[task.evaluation.metrics]]
+id = "state_4"
+category = "performance"
+observations = [
+    "nominal:state_4",
+]
+unit = "V"
+direction = "maximize"
+aggregation = "min"
+lower = 0.9
+
+[[task.evaluation.metrics]]
+id = "state_5"
+category = "performance"
+observations = [
+    "nominal:state_5",
+]
+unit = "V"
+direction = "maximize"
+aggregation = "min"
+lower = 0.9
+
+[[task.evaluation.metrics]]
+id = "state_6"
+category = "performance"
+observations = [
+    "nominal:state_6",
+]
+unit = "V"
+direction = "minimize"
+aggregation = "max"
+upper = 0.1
+
+[[task.evaluation.metrics]]
+id = "state_7"
+category = "performance"
+observations = [
+    "nominal:state_7",
+]
+unit = "V"
+direction = "maximize"
+aggregation = "min"
+lower = 0.9
+
+[[task.evaluation.metrics]]
+id = "state_8"
+category = "performance"
+observations = [
+    "nominal:state_8",
+]
+unit = "V"
+direction = "maximize"
+aggregation = "min"
+lower = 0.9
+
+[[task.evaluation.metrics]]
+id = "supply"
+category = "performance"
+observations = [
+    "nominal:supply",
+]
+unit = "W"
+direction = "minimize"
+aggregation = "max"
+dimension = "supply"
+baseline = [
+    "source_nominal:supply",
+]
+normalization = "ratio"
+lower = 0
+scale = 1e-12
+
+[[task.evaluation.metrics]]
+id = "propagation_delay"
+category = "performance"
+observations = [
+    "nominal:delay_a1_fall_2",
+    "nominal:delay_a2_rise_3",
+    "nominal:delay_a2_fall_6",
+    "nominal:delay_a1_rise_7",
+]
+unit = "s"
+direction = "minimize"
+aggregation = "max"
+dimension = "response"
+baseline = [
+    "source_nominal:delay_a1_fall_2",
+    "source_nominal:delay_a2_rise_3",
+    "source_nominal:delay_a2_fall_6",
+    "source_nominal:delay_a1_rise_7",
+]
+normalization = "ratio"
+lower = 0
+
+[[task.evaluation.metrics]]
+id = "output_transition"
+category = "performance"
+observations = [
+    "nominal:transition_a1_fall_2",
+    "nominal:transition_a2_rise_3",
+    "nominal:transition_a2_fall_6",
+    "nominal:transition_a1_rise_7",
+]
+unit = "s"
+direction = "minimize"
+aggregation = "max"
+dimension = "response"
+baseline = [
+    "source_nominal:transition_a1_fall_2",
+    "source_nominal:transition_a2_rise_3",
+    "source_nominal:transition_a2_fall_6",
+    "source_nominal:transition_a1_rise_7",
+]
+normalization = "ratio"
+lower = 0
+
+[task.evaluation.scoring]
+method = "layout"
+area_metric = "functional_area"
+area_target = 1.6789
+rationale = "Standard-cell logic: propagation delay 48%; output transition 16%; supply power 16%; area 20%. Each objective's weight is divided equally among its metrics."
+
+[task.evaluation.scoring.weights]
+functional_area = 0.2
+propagation_delay = 0.48
+output_transition = 0.16
+supply = 0.16
+
+[task.evaluation.pre_layout]
+source_report_sha256 = "76a86a4f03264579807d0206b09e5d64b666842b96240cc4a582b1fc7bf5bf5a"
+
+[task.evaluation.pre_layout.backends]
+"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"ef9cb87fa27b849376472663b7362673979b89e012f161ba47bb5f6af6ede8eb\", \"compatibility\": null, \"execution_sha256\": \"5424b579002782bfddf0a729715b8fbf2a5f7f2b4cf14982d7616e352d5de9be\", \"image_id\": \"sha256:6562558774d43c085a289bbba696c55959eb8051a0996f96633451fbeb9c652d\", \"limits\": {\"cpus\": 4, \"memory_mb\": 4096, \"pids\": 256}, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"7fc8a0cde0f7d722e87c34a1115c13986b3db8fecba4b7dadb0a1edf171df62b\", \"timeout_seconds\": 120.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}"
+
+[task.evaluation.pre_layout.jobs.source_nominal]
+operation = "circuit.simulate"
+
+[task.evaluation.pre_layout.jobs.source_nominal.inputs]
+deck = "input:performance"
+dut = "input:netlist"
+
+[task.evaluation.pre_layout.jobs.source_nominal.outputs]
+waveform = "ngspice-raw"
+
+[task.evaluation.pre_layout.jobs.source_nominal.parameters.exports]
+waveform = "waveform.raw"
+
+[task.evaluation.pre_layout.jobs.source_nominal.parameters.measurements]
+state_0 = "V"
+state_1 = "V"
+state_2 = "V"
+state_3 = "V"
+state_4 = "V"
+state_5 = "V"
+state_6 = "V"
+state_7 = "V"
+state_8 = "V"
+supply = "W"
+delay_a1_fall_2 = "s"
+transition_a1_fall_2 = "s"
+delay_a2_rise_3 = "s"
+transition_a2_rise_3 = "s"
+delay_a2_fall_6 = "s"
+transition_a2_fall_6 = "s"
+delay_a1_rise_7 = "s"
+transition_a1_rise_7 = "s"
+
+[task.evaluation.pre_layout.jobs.source_nominal.input_sha256]
+deck = "389d2d09f05913f740d0b776e0fe2d4382057b2bc8a23564f4150adae920e4c9"
+dut = "1decfdcffa5a7f962e26c0831e9a219521670f282df72e465fd61ebccdba12b0"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.delay_a1_fall_2]
+value = 1.430693e-11
+unit = "s"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.delay_a1_rise_7]
+value = 9.335134e-12
+unit = "s"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.delay_a2_fall_6]
+value = 1.515943e-11
+unit = "s"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.delay_a2_rise_3]
+value = 1.022087e-11
+unit = "s"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.state_0]
+value = 0.9999975
+unit = "V"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.state_1]
+value = 0.9999739
+unit = "V"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.state_2]
+value = 0.0001741408
+unit = "V"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.state_3]
+value = 0.9998214
+unit = "V"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.state_4]
+value = 0.999999
+unit = "V"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.state_5]
+value = 0.9999582
+unit = "V"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.state_6]
+value = 0.0001756712
+unit = "V"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.state_7]
+value = 0.9999739
+unit = "V"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.state_8]
+value = 0.9999406
+unit = "V"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.supply]
+value = 3.425277e-06
+unit = "W"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.transition_a1_fall_2]
+value = 1.658675e-11
+unit = "s"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.transition_a1_rise_7]
+value = 9.668356e-12
+unit = "s"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.transition_a2_fall_6]
+value = 1.658596e-11
+unit = "s"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.transition_a2_rise_3]
+value = 1.080812e-11
+unit = "s"
+
+[toolchain.backends.artifact]
+type = "klayout-docker"
+
+[toolchain.backends.artifact.settings]
+image = "iclayout-bench-tools:local"
+check = "artifact"
+timeout_seconds = 120
+
+[toolchain.backends.drc]
+type = "klayout-docker"
+
+[toolchain.backends.drc.settings]
+image = "iclayout-bench-tools:local"
+check = "drc"
+timeout_seconds = 120
+support = "build/support/freepdk45-klayout"
+profile = "drc.json"
+
+[toolchain.backends.drc.support_profiles]
+support = "klayout"
+
+[toolchain.backends.lvs]
+type = "klayout-docker"
+
+[toolchain.backends.lvs.settings]
+image = "iclayout-bench-tools:local"
+check = "lvs"
+timeout_seconds = 120
+support = "build/support/freepdk45-klayout"
+profile = "strict-lvs.json"
+
+[toolchain.backends.lvs.support_profiles]
+support = "klayout"
+
+[toolchain.backends.geometry]
+type = "klayout-geometry-docker"
+
+[toolchain.backends.geometry.settings]
+image = "iclayout-bench-tools:local"
+timeout_seconds = 60
+
+[toolchain.backends.rc]
+type = "magic-rc-docker"
+
+[toolchain.backends.rc.settings]
+image = "iclayout-bench-tools:local"
+support = "build/support/freepdk45-magic-vtl"
+technology = "freepdk45.tech"
+tech_name = "freepdk45"
+style = "spice3(sim)"
+gds_readonly = false
+case_insensitive_ports = true
+label_layers = [
+    [
+        9,
+        0,
+    ],
+    [
+        11,
+        0,
+    ],
+    [
+        13,
+        0,
+    ],
+    [
+        15,
+        0,
+    ],
+    [
+        17,
+        0,
+    ],
+    [
+        19,
+        0,
+    ],
+    [
+        21,
+        0,
+    ],
+    [
+        23,
+        0,
+    ],
+    [
+        25,
+        0,
+    ],
+    [
+        27,
+        0,
+    ],
+    [
+        29,
+        0,
+    ],
+]
+timeout_seconds = 120
+
+[toolchain.backends.rc.support_profiles]
+support = "magic-vtl"
+
+[toolchain.backends.ngspice]
+type = "ngspice-docker"
+
+[toolchain.backends.ngspice.settings]
+image = "iclayout-bench-tools:local"
+support = "build/support/freepdk45-models"
+timeout_seconds = 120
+
+[toolchain.backends.ngspice.support_profiles]
+support = "models"
+
+[toolchain.bindings]
+"layout.artifact" = "artifact"
+"layout.drc" = "drc"
+"layout.lvs" = "lvs"
+"layout.geometry" = "geometry"
+"layout.extract_rc" = "rc"
+"circuit.simulate" = "ngspice"
+
+[qualification]
+reference = "reference/NAND2_X1.gds"
+
+[origin]
+url = "https://foss-eda-tools.googlesource.com/third_party/freepdk45/+/356e90646f5ef26ea09b1ed8ce4796871403a0c7/Back_End/spice/NAND2_X1.spi"
+
+[presentation]
+category = "Logic & memory"
+summary = "Implements two-input NAND logic in a fixed-height standard cell."

tasks/freepdk45/nangate45-pdk/cases/NAND2_X1/materials/circuit.spice

@@ -0,0 +1,56 @@
+* 
+* ******************************************************************************
+* *                                                                            *
+* *                   Copyright (C) 2004-2010, Nangate Inc.                    *
+* *                           All rights reserved.                             *
+* *                                                                            *
+* * Nangate and the Nangate logo are trademarks of Nangate Inc.                *
+* *                                                                            *
+* * All trademarks, logos, software marks, and trade names (collectively the   *
+* * "Marks") in this program are proprietary to Nangate or other respective    *
+* * owners that have granted Nangate the right and license to use such Marks.  *
+* * You are not permitted to use the Marks without the prior written consent   *
+* * of Nangate or such third party that may own the Marks.                     *
+* *                                                                            *
+* * This file has been provided pursuant to a License Agreement containing     *
+* * restrictions on its use. This file contains valuable trade secrets and     *
+* * proprietary information of Nangate Inc., and is protected by U.S. and      *
+* * international laws and/or treaties.                                        *
+* *                                                                            *
+* * The copyright notice(s) in this file does not indicate actual or intended  *
+* * publication of this file.                                                  *
+* *                                                                            *
+* *         buildcell, v2010.08-HR32-SP3-2010-08-05 - build 1009061800         *
+* *                                                                            *
+* ******************************************************************************
+* 
+* 
+* Running on brazil06.nangate.com.br for user Giancarlo Franciscatto (gfr).
+* Local time is now Fri, 3 Dec 2010, 19:22:54.
+* Main process id is 28034.
+*
+********************************************************************************
+*                                                                              *
+* Cellname:   NAND2_X1.                                                        *
+*                                                                              *
+* Technology: NCSU FreePDK 45nm.                                               *
+* Format:     Cdl.                                                             *
+*                                                                              *
+* Written on brazil06.nangate.com.br for user Giancarlo Franciscatto (gfr)     *
+* at 19:22:54 on Fri, 3 Dec 2010.                                              *
+*                                                                              *
+********************************************************************************
+.SUBCKT NAND2_X1 A1 A2 ZN VDD VSS 
+*.PININFO A1:I A2:I ZN:O VDD:P VSS:G 
+*.EQN ZN=!(A1 * A2)
+M_i_1 net_0 A2 VSS VSS NMOS_VTL W=0.415000U L=0.050000U
+M_i_0 ZN A1 net_0 VSS NMOS_VTL W=0.415000U L=0.050000U
+M_i_3 ZN A2 VDD VDD PMOS_VTL W=0.630000U L=0.050000U
+M_i_2 VDD A1 ZN VDD PMOS_VTL W=0.630000U L=0.050000U
+.ENDS 
+
+********************************************************************************
+*
+* END
+*
+********************************************************************************

tasks/freepdk45/nangate45-pdk/cases/NAND2_X1/materials/testbench.spice

@@ -0,0 +1,35 @@
+* NAND2_X1: exhaustive Gray sequence and reversed sequence
+.include /workspace/support/models.spice
+.include dut.spice
+.temp 27
+Vdd vdd 0 1
+Vss vss 0 0
+Xdut A1 A2 ZN VDD VSS NAND2_X1
+Cl ZN 0 5f
+VA1 A1 0 PWL(0 0 0.500n 0 0.510n 0 1.000n 0 1.010n 1 1.500n 1 1.510n 1 2.000n 1 2.010n 0 2.500n 0 2.510n 1 3.000n 1 3.010n 1 3.500n 1 3.510n 0 4.000n 0 4.010n 0)
+VA2 A2 0 PWL(0 0 0.500n 0 0.510n 1 1.000n 1 1.010n 1 1.500n 1 1.510n 0 2.000n 0 2.010n 0 2.500n 0 2.510n 0 3.000n 0 3.010n 1 3.500n 1 3.510n 1 4.000n 1 4.010n 0)
+.tran 0.5p 4.500n
+.meas tran state_0 find v(ZN) at=0.110n
+.meas tran state_1 find v(ZN) at=0.610n
+.meas tran state_2 find v(ZN) at=1.110n
+.meas tran state_3 find v(ZN) at=1.610n
+.meas tran state_4 find v(ZN) at=2.110n
+.meas tran state_5 find v(ZN) at=2.610n
+.meas tran state_6 find v(ZN) at=3.110n
+.meas tran state_7 find v(ZN) at=3.610n
+.meas tran state_8 find v(ZN) at=4.110n
+.meas tran supply avg par('-v(vdd)*i(Vdd)') from=0 to=4.400n
+.meas tran delay_a1_fall_2 trig v(A1) val=0.5 rise=1 td=1n targ v(ZN) val=0.5 fall=1 td=1n
+.meas tran transition_a1_fall_2 trig v(ZN) val=0.8 fall=1 td=1n targ v(ZN) val=0.2 fall=1 td=1n
+.meas tran delay_a2_rise_3 trig v(A2) val=0.5 fall=1 td=1.5n targ v(ZN) val=0.5 rise=1 td=1.5n
+.meas tran transition_a2_rise_3 trig v(ZN) val=0.2 rise=1 td=1.5n targ v(ZN) val=0.8 rise=1 td=1.5n
+.meas tran delay_a2_fall_6 trig v(A2) val=0.5 rise=1 td=3n targ v(ZN) val=0.5 fall=1 td=3n
+.meas tran transition_a2_fall_6 trig v(ZN) val=0.8 fall=1 td=3n targ v(ZN) val=0.2 fall=1 td=3n
+.meas tran delay_a1_rise_7 trig v(A1) val=0.5 fall=1 td=3.5n targ v(ZN) val=0.5 rise=1 td=3.5n
+.meas tran transition_a1_rise_7 trig v(ZN) val=0.2 rise=1 td=3.5n targ v(ZN) val=0.8 rise=1 td=3.5n
+.control
+run
+write waveform.raw v(A1) v(A2) v(ZN) v(VDD) i(Vdd)
+quit
+.endc
+.end

tasks/freepdk45/nangate45-pdk/cases/NAND2_X1/problem.md

@@ -0,0 +1,118 @@
+# Two-Input NAND Layout Task
+
+## Objective
+
+Implement ZN = NOT (A1 AND A2) using the supplied VTL transistors. Preserve the authoritative netlist's model classes, W/L, interface and connectivity. Submit top cell `NAND2_X1`.
+
+## Inputs and Interface
+
+Ordered SPICE ports: `A1 A2 ZN VDD VSS`. Names are case-insensitive; different names are not interchangeable. The delivered inputs are this problem, `materials/circuit.spice`, and `materials/testbench.spice`. The model and extraction resources are supplied as reviewed support bundles. Reference geometry and qualification evidence are maintainer materials, excluded from solver inputs.
+
+## Operating Conditions
+
+Use the nominal FreePDK45 BSIM4 models at **1.0 V and 27 C**, with ground at 0 V. All transistor lengths are 50 nm; widths and model classes come from the netlist.
+
+ZN drives 5 fF. Apply 00, 01, 11, 10, 00, 10, 11, 01, 00 to A1/A2 in 500 ps slots, with 10 ps edges. Sample ZN at slot start + 110 ps. This visits the full truth table and both directions of each single-input transition. Average DUT supply power over 0–4.4 ns.
+
+The deck defines stimuli and observation times exactly. Tests use only external ports. Qualification covers these nominal conditions, not PVT, mismatch, array abutment, substrate noise or manufacturing signoff.
+
+## Physical Requirements
+
+Submit a nonempty GDSII of at most 10 MiB. Enable all checks present in the supplied KLayout DRC deck, including grid and antenna checks, with no waivers. Strict LVS checks named ports, models, W/L and actual well/tap connectivity; library-specific implicit or global rail connections are disabled. The upstream deck does not implement its documented different-potential well-spacing rule; it is not a complete foundry signoff deck.
+
+The hard functional envelope is 100 um by 100 um. Its bounding rectangle includes every drawing layer 1/0 through 29/0: active, wells, implants, threshold markers, poly, contacts, all ten metals and all nine vias. It supplies the scored footprint in um2. Put functional geometry on these layers; pin-purpose and annotation geometry is excluded. Electrical labels use poly or metal drawing layers (9/0 and 11/0, 13/0, ..., 29/0). Non-electrical annotation text is ignored by extraction.
+
+Translation, equivalent hierarchy and internal instance renaming are allowed. LVS permits source/drain exchange and equivalent parallel devices; any such layout must also pass the same RC-based electrical requirements. Preserve top-level port identities and explicit body connections.
+
+
+The standard-cell functional frame has fixed height 1.63 um and width on a 0.01 um grid. Coordinates below are relative to its lower-left functional bound; global translation remains allowed. Supply rails must be continuous on metal1 and bound by LVS to the named supply.
+
+- `VDD`: centre y = 1.515 um, thickness at least 0.07 um, from left + 0.115 um to right − 0.03 um.
+- `VSS`: centre y = 0.115 um, thickness at least 0.07 um, from left + 0.115 um to right − 0.03 um.
+
+## Electrical Requirements and Scoring
+
+Artifact, DRC, LVS and geometry gates precede candidate GDS extraction. Simulation consumes the candidate's Magic RC netlist unchanged; source simulation supplies the independent scoring baseline. VTG/VTL device classes are checked by independent LVS before the matching extraction profile is used. Extraction includes poly/metal sheet resistance, contacts/vias, geometry-dependent coupling and ground capacitance, and device junction area/perimeter. Wells are lumped connections; BSIM4 supplies device/junction behavior. Interconnect resistance and capacitance use the pinned community FreePDK45 Magic technology's estimated coefficients and native capacitance placement. The extraction adapter binds VTG/VTL models, preserves annotation layers and corrects the technology's dimensional unit conversion. This is a predictive approximation without field-solver signoff accuracy.
+
+Physical checks and declared functional bounds remain mandatory. Quality has no
+fixed allowed-degradation threshold. Each `source_*` job simulates the declared
+source circuit with exactly the same testbench, model resources, parameters,
+load and measurement window as its paired extracted-candidate job. A source
+observation is the 100-point electrical baseline; it is independent of the
+submitted GDS. All individual pairs are retained in the evaluation report.
+
+For a post-layout observation x and its source observation b:
+
+- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,
+  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;
+  s is a normalization floor, not an allowed degradation or pass threshold.
+- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.
+- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and
+  zero-valued operating points are never divided directly.
+
+Scoring uses `layout`. A metric uses its worst paired quality q. The score is
+S = 100 * product(q_i ** w_i), including area quality
+q_area = area_reference / candidate_functional_area. The weights below sum to
+one. Dimensions describe measurements but do not determine their weights.
+Physical or functional rejection scores zero; missing or invalid measurements
+produce an unknown score, including measurements with zero weight.
+Source-equivalent performance at the area reference scores 100; improvements
+can exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.
+
+| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale |
+| --- | --- | --- | --- | --- | --- |
+| `state_0` | `find v(ZN) at=0.110n` | V | functional check | 0.9 … +∞ | — |
+| `state_1` | `find v(ZN) at=0.610n` | V | functional check | 0.9 … +∞ | — |
+| `state_2` | `find v(ZN) at=1.110n` | V | functional check | −∞ … 0.1 | — |
+| `state_3` | `find v(ZN) at=1.610n` | V | functional check | 0.9 … +∞ | — |
+| `state_4` | `find v(ZN) at=2.110n` | V | functional check | 0.9 … +∞ | — |
+| `state_5` | `find v(ZN) at=2.610n` | V | functional check | 0.9 … +∞ | — |
+| `state_6` | `find v(ZN) at=3.110n` | V | functional check | −∞ … 0.1 | — |
+| `state_7` | `find v(ZN) at=3.610n` | V | functional check | 0.9 … +∞ | — |
+| `state_8` | `find v(ZN) at=4.110n` | V | functional check | 0.9 … +∞ | — |
+| `supply` | `avg par('-v(vdd)*i(Vdd)') from=0 to=4.400n` | W | minimize / ratio | 0 … +∞ | 1e-12 |
+| `propagation_delay` | Worst paired quality over: delay_a1_fall_2, delay_a2_rise_3, delay_a2_fall_6, delay_a1_rise_7. | s | minimize / ratio | 0 … +∞ | — |
+| `output_transition` | Worst paired quality over: transition_a1_fall_2, transition_a2_rise_3, transition_a2_fall_6, transition_a1_rise_7. | s | minimize / ratio | 0 … +∞ | — |
+
+Area reference: **1.6789 um2**. Complete functional bounding rectangle of the declared standard-cell reference GDS: 1.03 by 1.63 um = 1.6789 um2. Reference SHA-256: d077499ea242e1c8506c7a992ce713d46ea513c52b80073a2b7ae6d6515f2d3f. This footprint includes the maintained explicit taps and routing.
+
+The capability coefficient remains **1**; it is independent of
+the reference-relative task score.
+
+### Standard-cell design guidance
+
+Plan the device rows, power rails and signal access before routing. Represent
+pull-up and pull-down connectivity as transistor-edge graphs; explore compatible
+Euler trails and alternative orderings to share diffusion and reduce breaks.
+Choose among legal orderings using routing length, parasitic loading and signal
+access, rather than diffusion sharing alone. Preserve the fixed netlist sizes,
+models and connectivity; size optimization is outside this task.
+
+Use the task's declared row height, grid and rail geometry. Keep local routes
+compact, leave signal pins accessible, and avoid consuming extra routing layers
+without benefit. Check DRC and named-port LVS, then extract the candidate and
+compare both transition directions and power with the source simulation. Iterate
+on measured parasitic effects rather than visual compactness alone. These are
+optional techniques, not a mandated algorithm or reference placement.
+
+Adapted from Xu et al., *Standard Cell Library Design and Optimization Methodology
+for ASAP7 PDK*, Sections 2–3 (https://arxiv.org/abs/1807.11396). Its FinFET sizing,
+track counts and process-specific dimensions do not apply to this task.
+
+
+### Score weights
+
+Standard-cell logic: propagation delay 48%; output transition 16%; supply power 16%; area 20%. Each objective's weight is divided equally among its metrics.
+
+| Metric | Weight |
+| --- | ---: |
+| `functional_area` | 0.2 |
+| `propagation_delay` | 0.480000000000 |
+| `output_transition` | 0.160000000000 |
+| `supply` | 0.160000000000 |
+
+## Tools and Submission
+
+Solve budget: **3 hours**.
+
+Use the reviewed FreePDK45 KLayout, Magic and ngspice resources from `/protocol/resources.json`. For Magic RC extraction, use `/resources/support/magic-vtl/freepdk45.tech`, which includes the required model and unit adaptations. Runtime `/protocol/task.json` publishes the same constraints, measurements and scoring. Only declared inputs appear under `/task`. Write `/workspace/output/final.gds`, then explicitly submit with `python -I /protocol/submit.py`. A harness that declares `process-feedback` uses the same frozen plan and backend identities for process checks; those snapshots do not count as final submissions.

tasks/freepdk45/pdk.toml

@@ -0,0 +1,353 @@
+[agent]
+id = "freepdk45"
+support_profiles = [
+    "models",
+    "klayout",
+    "magic-vtg",
+    "magic-vtl",
+]
+checks = [
+    [
+        "python",
+        "-c",
+        "import pya; t=pya.Technology(); t.load('/resources/pdks/freepdk45/libs.tech/klayout/tech/freepdk45/freepdk45.lyt'); assert t.name; print('FreePDK45 technology loaded:', t.name)",
+    ],
+]
+
+[agent.sources.freepdk45]
+installation = true
+path = "freepdk45"
+
+[agent.environment]
+ICLAYOUT_BENCH_PDK = "freepdk45"
+PDK_ROOT = "/resources/pdks"
+PDK_PATH = "/resources/pdks/freepdk45"
+KLAYOUT_PATH = "/resources/pdks/freepdk45/libs.tech/klayout"
+
+[source]
+repository = "https://github.com/rjordans/freepdk45-open-pdks.git"
+commit = "ab8b395503e5b6149f76549abfd375e7cbb156cc"
+license = "Component licenses in libs.tech/klayout/LICENSE and libs.tech/ngspice/APACHE-LICENSE-2.0.txt"
+
+[profiles.klayout.files."upstream/drc.lydrc"]
+path = "freepdk45/libs.tech/klayout/tech/freepdk45/drc/drc_freepdk45.lydrc"
+format = "text"
+
+[profiles.klayout.files."upstream/lvs.lylvs"]
+path = "freepdk45/libs.tech/klayout/tech/freepdk45/lvs/lvs_freepdk45.lylvs"
+format = "text"
+
+[profiles.klayout.generated."freepdk45.drc"]
+content = """
+# ICLayout-Bench CLI adapter; original rules and switches are unchanged.
+$output = $report
+eval(RBA::Macro.new(\"/workspace/support/upstream/drc.lydrc\").text, binding)
+"""
+format = "text"
+
+[profiles.klayout.generated."strict.lvs"]
+content = """
+# ICLayout-Bench strict candidate LVS; modified from the pinned BSD-3-Clause macro.
+# Preserve device extraction and physical connectivity. Require real body taps,
+# exact model/width/length and named ports; no cell-name shortcuts or pin swaps.
+code = RBA::Macro.new(\"/workspace/support/upstream/lvs.lylvs\").text
+# Promote geometry AND text labels through wrappers before reading DSL layers.
+# The immutable original candidate remains available to all other gates.
+flat_layout = RBA::Layout.new
+flat_layout.read($input)
+flat_layout.cell($topcell).flatten(true)
+flat_layout.write(\"/workspace/flat-candidate.gds\")
+code = code.sub(\"source($input)\", 'source(\"/workspace/flat-candidate.gds\", $topcell)')
+code = code.sub(\"report($report)\", \"report_lvs($report)\")
+# Flatten for candidate checks so an electrically empty wrapper cannot hide its child.
+code = code.sub(\"\\ndeep\\n\", \"\\n\")
+code = code.sub(/cheat\\([^
+]+\\) \\{\\s*
+/, \"\")
+code = code.sub(\"\\n}\\n\\n# Define connectivity\", \"\\n# Define connectivity\")
+code = code.sub(/# Global.*?# Actually performs the extraction/m, \"schematic.simplify\\n# Actually performs the extraction\")
+code = code.sub(/# Tolerances for.*?max_branch_complexity/m, \"max_branch_complexity\")
+raise \"Unexpected upstream shortcut remains\" if code.match?(/connect_global|connect_explicit|connect_implicit|equivalent_pins|cheat\\(/)
+metal1 = nil
+eval(code, binding)
+"""
+format = "text"
+
+[profiles.klayout.generated."drc.json"]
+content = """
+{
+  \"deck\": \"freepdk45.drc\",
+  \"variables\": {},
+  \"scope\": \"All upstream DRC, antenna and off-grid checks; no waivers.\",
+  \"required_categories\": [
+    \"'WELL.1'\",
+    \"'WELL.3'\",
+    \"'WELL.4'\",
+    \"'VT.1'\",
+    \"'POLY.1'\",
+    \"'POLY.3'\",
+    \"'POLY.4'\",
+    \"'POLY.5'\",
+    \"'POLY.6'\",
+    \"'ACTIVE.1'\",
+    \"'ACTIVE.2'\",
+    \"'ACTIVE.3'\",
+    \"'ACTIVE.4'\",
+    \"'IMPLANT.1'\",
+    \"'IMPLANT.2'\",
+    \"'IMPLANT.3'\",
+    \"'IMPLANT.4'\",
+    \"'IMPLANT.5'\",
+    \"'CONTACT.1'\",
+    \"'CONTACT.2'\",
+    \"'CONTACT.3'\",
+    \"'CONTACT.4'\",
+    \"'CONTACT.5'\",
+    \"'CONTACT.6'\",
+    \"'METAL1.1'\",
+    \"'METAL1.2'\",
+    \"'METAL1.3'\",
+    \"'METAL1.4'\",
+    \"'METAL1.5'\",
+    \"'METAL1.6'\",
+    \"'METAL1.7'\",
+    \"'METAL1.8'\",
+    \"'METAL1.9'\",
+    \"'VIA1.1'\",
+    \"'VIA1.2'\",
+    \"'VIA1.3'\",
+    \"'VIA1.4'\",
+    \"'METAL2.1'\",
+    \"'METAL2.2'\",
+    \"'METAL2.3'\",
+    \"'METAL2.4'\",
+    \"'METAL2.5'\",
+    \"'METAL2.6'\",
+    \"'METAL2.7'\",
+    \"'METAL2.8'\",
+    \"'METAL2.9'\",
+    \"'VIA2.1'\",
+    \"'VIA2.2'\",
+    \"'VIA2.3'\",
+    \"'VIA2.4'\",
+    \"'METAL3.1'\",
+    \"'METAL3.2'\",
+    \"'METAL3.3'\",
+    \"'METAL3.4'\",
+    \"'METAL3.5'\",
+    \"'METAL3.6'\",
+    \"'METAL3.7'\",
+    \"'METAL3.8'\",
+    \"'METAL3.9'\",
+    \"'VIA3.1'\",
+    \"'VIA3.2'\",
+    \"'VIA3.3'\",
+    \"'VIA3.4'\",
+    \"'METAL4.1'\",
+    \"'METAL4.2'\",
+    \"'METAL4.6'\",
+    \"'METAL4.7'\",
+    \"'METAL4.8'\",
+    \"'VIA4.1'\",
+    \"'VIA4.2'\",
+    \"'VIA4.3'\",
+    \"'VIA4.4'\",
+    \"'METAL5.1'\",
+    \"'METAL5.2'\",
+    \"'METAL5.6'\",
+    \"'METAL5.7'\",
+    \"'METAL5.8'\",
+    \"'VIA5.1'\",
+    \"'VIA5.2'\",
+    \"'VIA5.3'\",
+    \"'VIA5.4'\",
+    \"'METAL6.1'\",
+    \"'METAL6.2'\",
+    \"'METAL6.6'\",
+    \"'METAL6.7'\",
+    \"'METAL6.8'\",
+    \"'VIA6.1'\",
+    \"'VIA6.2'\",
+    \"'VIA6.3'\",
+    \"'VIA6.4'\",
+    \"'METAL7.1'\",
+    \"'METAL7.2'\",
+    \"'METAL7.7'\",
+    \"'METAL7.8'\",
+    \"'METAL7.9'\",
+    \"'VIA7.3'\",
+    \"'VIA7.4'\",
+    \"'METAL8.1'\",
+    \"'METAL8.2'\",
+    \"'METAL8.7'\",
+    \"'METAL8.8'\",
+    \"'METAL8.9'\",
+    \"'VIA8.1'\",
+    \"'VIA8.2'\",
+    \"'VIA8.3'\",
+    \"'VIA8.4'\",
+    \"'METAL9.1'\",
+    \"'METAL9.2'\",
+    \"'METAL9.7'\",
+    \"'METAL9.8'\",
+    \"'METAL9.9'\",
+    \"'VIA9.1'\",
+    \"'VIA9.2'\",
+    \"'VIA9.3'\",
+    \"'VIA9.4'\",
+    \"'METAL10.1'\",
+    \"'METAL10.2'\",
+    \"'METAL10.7'\",
+    \"'METAL10.8'\",
+    \"'METAL10.9'\",
+    \"'GRID: vertexes on layer well not on grid of 0.0025'\",
+    \"'GRID: vertexes on layer active not on grid of 0.0025'\",
+    \"'GRID: vertexes on layer vtg not on grid of 0.0025'\",
+    \"'GRID: vertexes on layer vth not on grid of 0.0025'\",
+    \"'GRID: vertexes on layer pplus not on grid of 0.0025'\",
+    \"'GRID: vertexes on layer nplus not on grid of 0.0025'\",
+    \"'GRID: vertexes on layer poly not on grid of 0.0025'\",
+    \"'GRID: vertexes on layer thkox not on grid of 0.0025'\",
+    \"'GRID: vertexes on layer cont not on grid of 0.0025'\",
+    \"'GRID: vertexes on layer metal1 not on grid of 0.0025'\",
+    \"'GRID: vertexes on layer via1 not on grid of 0.0025'\",
+    \"'GRID: vertexes on layer metal2 not on grid of 0.0025'\",
+    \"'GRID: vertexes on layer via2 not on grid of 0.0025'\",
+    \"'GRID: vertexes on layer metal3 not on grid of 0.0025'\",
+    \"'GRID: vertexes on layer via3 not on grid of 0.0025'\",
+    \"'GRID: vertexes on layer metal4 not on grid of 0.0025'\",
+    \"'GRID: vertexes on layer via4 not on grid of 0.0025'\",
+    \"'GRID: vertexes on layer metal5 not on grid of 0.0025'\",
+    \"'GRID: vertexes on layer via5 not on grid of 0.0025'\",
+    \"'GRID: vertexes on layer metal6 not on grid of 0.0025'\",
+    \"'GRID: vertexes on layer via6 not on grid of 0.0025'\",
+    \"'GRID: vertexes on layer metal7 not on grid of 0.0025'\",
+    \"'GRID: vertexes on layer via7 not on grid of 0.0025'\",
+    \"'GRID: vertexes on layer metal8 not on grid of 0.0025'\",
+    \"'GRID: vertexes on layer via8 not on grid of 0.0025'\",
+    \"'GRID: vertexes on layer metal9 not on grid of 0.0025'\",
+    \"'GRID: vertexes on layer via9 not on grid of 0.0025'\",
+    \"'GRID: vertexes on layer metal10 not on grid of 0.0025'\",
+    \"METAL1_ANTENNA\",
+    \"METAL2_ANTENNA\",
+    \"METAL3_ANTENNA\",
+    \"METAL4_ANTENNA\",
+    \"METAL5_ANTENNA\",
+    \"METAL6_ANTENNA\",
+    \"METAL7_ANTENNA\",
+    \"METAL8_ANTENNA\",
+    \"METAL9_ANTENNA\",
+    \"METAL10_ANTENNA\"
+  ]
+}
+"""
+format = "json"
+
+[profiles.klayout.generated."strict-lvs.json"]
+content = """
+{
+  \"deck\": \"strict.lvs\",
+  \"layer_names\": {\"metal1\": \"metal1\"},
+  \"variables\": {},
+  \"scope\": \"Physical well/tap connectivity, no global or implicit connections, no cell-name cheat blocks, exact MOS W/L, named ports.\"
+}
+"""
+format = "json"
+
+[profiles.models]
+check = [
+    "python",
+    "/resources/pdk-check.py",
+    "models",
+    "NMOS_VTL",
+    "models.spice",
+    "--length",
+    "50n",
+    "--width",
+    "200n",
+]
+
+[profiles.models.files."NMOS_VTG.inc"]
+path = "freepdk45/libs.tech/ngspice/tran_models/models_nom/NMOS_VTG.inc"
+format = "text"
+
+[profiles.models.files."PMOS_VTG.inc"]
+path = "freepdk45/libs.tech/ngspice/tran_models/models_nom/PMOS_VTG.inc"
+format = "text"
+
+[profiles.models.files."NMOS_VTL.inc"]
+path = "freepdk45/libs.tech/ngspice/tran_models/models_nom/NMOS_VTL.inc"
+format = "text"
+
+[profiles.models.files."PMOS_VTL.inc"]
+path = "freepdk45/libs.tech/ngspice/tran_models/models_nom/PMOS_VTL.inc"
+format = "text"
+
+[profiles.models.generated."models.spice"]
+format = "spice"
+content = """
+.include /workspace/support/NMOS_VTG.inc
+.include /workspace/support/PMOS_VTG.inc
+.include /workspace/support/NMOS_VTL.inc
+.include /workspace/support/PMOS_VTL.inc
+"""
+
+[profiles.magic-vtg.files."freepdk45.tech"]
+path = "freepdk45/libs.tech/magic/freepdk45.tech"
+format = "text"
+
+[[profiles.magic-vtg.files."freepdk45.tech".replace]]
+old = "device msubcircuit pmos pfet *pdiff *pdiff nwell error l=l w=w"
+new = "device mosfet PMOS_VTG pfet pdiff,pdc nwell"
+
+[[profiles.magic-vtg.files."freepdk45.tech".replace]]
+old = "device msubcircuit nmos nfet *ndiff *ndiff psub,space/w error l=l w=w"
+new = "device mosfet NMOS_VTG nfet ndiff,ndc psub,space/w"
+
+[[profiles.magic-vtg.files."freepdk45.tech".replace]]
+old = "  calma TEXT 63 63"
+new = """
+  calma TEXT 63 63
+  calma VTG 6 0
+  calma VTH 7 0
+  calma THKOX 8 0
+  calma ANNOTATION 239 0
+  calma BOUNDARY230 230 0"""
+
+[[profiles.magic-vtg.files."freepdk45.tech".replace]]
+old = "  layer comment TEXT"
+new = "  layer comment TEXT,VTG,VTH,THKOX,ANNOTATION,BOUNDARY230"
+
+[[profiles.magic-vtg.files."freepdk45.tech".replace]]
+old = " lambda  0.025"
+new = " lambda  2.5"
+
+[profiles.magic-vtl.files."freepdk45.tech"]
+path = "freepdk45/libs.tech/magic/freepdk45.tech"
+format = "text"
+
+[[profiles.magic-vtl.files."freepdk45.tech".replace]]
+old = "device msubcircuit pmos pfet *pdiff *pdiff nwell error l=l w=w"
+new = "device mosfet PMOS_VTL pfet pdiff,pdc nwell"
+
+[[profiles.magic-vtl.files."freepdk45.tech".replace]]
+old = "device msubcircuit nmos nfet *ndiff *ndiff psub,space/w error l=l w=w"
+new = "device mosfet NMOS_VTL nfet ndiff,ndc psub,space/w"
+
+[[profiles.magic-vtl.files."freepdk45.tech".replace]]
+old = "  calma TEXT 63 63"
+new = """
+  calma TEXT 63 63
+  calma VTG 6 0
+  calma VTH 7 0
+  calma THKOX 8 0
+  calma ANNOTATION 239 0
+  calma BOUNDARY230 230 0"""
+
+[[profiles.magic-vtl.files."freepdk45.tech".replace]]
+old = "  layer comment TEXT"
+new = "  layer comment TEXT,VTG,VTH,THKOX,ANNOTATION,BOUNDARY230"
+
+[[profiles.magic-vtl.files."freepdk45.tech".replace]]
+old = " lambda  0.025"
+new = " lambda  2.5"

tasks/gf180mcuD/2AMLogic-sar-adc/LICENSE

@@ -0,0 +1,202 @@
+                                 Apache License
+                           Version 2.0, January 2004
+                        http://www.apache.org/licenses/
+
+   TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
+
+   1. Definitions.
+
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+      and distribution as defined by Sections 1 through 9 of this document.
+
+      "Licensor" shall mean the copyright owner or entity authorized by
+      the copyright owner that is granting the License.
+
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+      direction or management of such entity, whether by contract or
+      otherwise, or (ii) ownership of fifty percent (50%) or more of the
+      outstanding shares, or (iii) beneficial ownership of such entity.
+
+      "You" (or "Your") shall mean an individual or Legal Entity
+      exercising permissions granted by this License.
+
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+
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+   5. Submission of Contributions. Unless You explicitly state otherwise,
+      any Contribution intentionally submitted for inclusion in the Work
+      by You to the Licensor shall be under the terms and conditions of
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+      the terms of any separate license agreement you may have executed
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+   6. Trademarks. This License does not grant permission to use the trade
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+      defend, and hold each Contributor harmless for any liability
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+      of your accepting any such warranty or additional liability.
+
+   END OF TERMS AND CONDITIONS
+
+   APPENDIX: How to apply the Apache License to your work.
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+      To apply the Apache License to your work, attach the following
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+   Copyright 2026 2AM Logic
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+   Licensed under the Apache License, Version 2.0 (the "License");
+   you may not use this file except in compliance with the License.
+   You may obtain a copy of the License at
+
+       http://www.apache.org/licenses/LICENSE-2.0
+
+   Unless required by applicable law or agreed to in writing, software
+   distributed under the License is distributed on an "AS IS" BASIS,
+   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+   See the License for the specific language governing permissions and
+   limitations under the License.
+

tasks/gf180mcuD/2AMLogic-sar-adc/cases/track_switch/case.toml

@@ -0,0 +1,775 @@
+in_core = false
+kind = "layout_case"
+id = "gf180mcuD.2AMLogic-sar-adc.track_switch"
+title = "Dummy-Compensated Track Switch"
+status = "qualified"
+
+[[assets]]
+path = "materials/schematic.svg"
+role = "schematic"
+visibility = "maintainer"
+format = "svg"
+sha256 = "e5f06c8b3160abc3605f55603d74694c7f96faf76ec2eab893cfcbb0eafc2a07"
+
+[[assets]]
+path = "reference/adc_tgate_dum.gds"
+role = "reference"
+visibility = "maintainer"
+format = "gds"
+sha256 = "ac42852033a1e1372d70dbd6fab92e35c668fda8c2ede932e71ef47511cc9db2"
+
+[task]
+hours = 3
+kind = "netlist_to_gds"
+family = "gf180_track_switch"
+coefficient = 4
+environment = "gf180mcuD-typical-rc"
+
+[task.inputs.description]
+path = "problem.md"
+format = "text"
+sha256 = "61dad99299cb63987ff9252905cf3c0b7db5b8d24d74c07b27a2b0f962346c87"
+
+[task.inputs.netlist]
+path = "materials/circuit.spice"
+format = "spice"
+sha256 = "24b64a7a410681352d4ec80b0fead64d6c1987ebd375acde58af33e7832f30dd"
+subcircuit = "adc_tgate_dum"
+
+[task.inputs.performance]
+path = "materials/testbench.spice"
+format = "spice"
+sha256 = "35039b03b178d1954f4a5caf712b05ecf0780f12128b6d0028db9ea9ead924c5"
+
+[task.output]
+path = "output/final.gds"
+format = "gds"
+top_cell = "adc_tgate_dum"
+max_bytes = 10485760
+
+[task.constraints]
+quality = [
+    { id = "area", type = "functional_bbox_area", layers_from = "outline" },
+]
+
+[[task.constraints.hard]]
+id = "outline"
+type = "bbox_max"
+functional_layers = [
+    [
+        5,
+        0,
+    ],
+    [
+        11,
+        17,
+    ],
+    [
+        11,
+        39,
+    ],
+    [
+        12,
+        0,
+    ],
+    [
+        13,
+        17,
+    ],
+    [
+        21,
+        0,
+    ],
+    [
+        22,
+        0,
+    ],
+    [
+        22,
+        4,
+    ],
+    [
+        24,
+        0,
+    ],
+    [
+        24,
+        5,
+    ],
+    [
+        30,
+        0,
+    ],
+    [
+        30,
+        4,
+    ],
+    [
+        31,
+        0,
+    ],
+    [
+        32,
+        0,
+    ],
+    [
+        33,
+        0,
+    ],
+    [
+        34,
+        0,
+    ],
+    [
+        34,
+        3,
+    ],
+    [
+        34,
+        4,
+    ],
+    [
+        34,
+        5,
+    ],
+    [
+        35,
+        0,
+    ],
+    [
+        36,
+        0,
+    ],
+    [
+        36,
+        3,
+    ],
+    [
+        36,
+        4,
+    ],
+    [
+        36,
+        5,
+    ],
+    [
+        37,
+        0,
+    ],
+    [
+        38,
+        0,
+    ],
+    [
+        40,
+        0,
+    ],
+    [
+        41,
+        0,
+    ],
+    [
+        42,
+        0,
+    ],
+    [
+        42,
+        3,
+    ],
+    [
+        42,
+        4,
+    ],
+    [
+        42,
+        5,
+    ],
+    [
+        46,
+        0,
+    ],
+    [
+        46,
+        3,
+    ],
+    [
+        46,
+        4,
+    ],
+    [
+        46,
+        5,
+    ],
+    [
+        49,
+        0,
+    ],
+    [
+        53,
+        0,
+    ],
+    [
+        53,
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+        53,
+        4,
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+    [
+        53,
+        5,
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+    [
+        55,
+        0,
+    ],
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+        62,
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+        100,
+        5,
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+    [
+        100,
+        7,
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+        8,
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+        108,
+        5,
+    ],
+    [
+        110,
+        5,
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+    [
+        110,
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+        110,
+        12,
+    ],
+    [
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+    ],
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+    [
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+    [
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+        0,
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+    [
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+    [
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+        0,
+    ],
+    [
+        227,
+        0,
+    ],
+    [
+        241,
+        0,
+    ],
+]
+max_width_um = 160
+max_height_um = 160
+
+[task.evaluation]
+mode = "post_layout"
+
+[[task.evaluation.jobs]]
+id = "artifact"
+stage = "check"
+operation = "layout.artifact"
+gate = "artifact"
+
+[task.evaluation.jobs.inputs]
+layout = "candidate"
+task = "task"
+
+[[task.evaluation.jobs]]
+id = "drc"
+stage = "check"
+operation = "layout.drc"
+gate = "drc"
+requires = [
+    "artifact",
+]
+
+[task.evaluation.jobs.inputs]
+layout = "candidate"
+task = "task"
+
+[[task.evaluation.jobs]]
+id = "lvs"
+stage = "check"
+operation = "layout.lvs"
+gate = "lvs"
+requires = [
+    "artifact",
+]
+
+[task.evaluation.jobs.inputs]
+layout = "candidate"
+task = "task"
+netlist = "input:netlist"
+
+[task.evaluation.jobs.outputs]
+database = "klayout-lvs"
+binding = "json"
+
+[[task.evaluation.jobs]]
+id = "geometry"
+stage = "check"
+operation = "layout.geometry"
+gate = "constraint"
+requires = [
+    "artifact",
+    "drc",
+    "lvs",
+]
+
+[task.evaluation.jobs.inputs]
+layout = "candidate"
+task = "task"
+constraints = "input:constraints"
+database = "job:lvs:database"
+binding = "job:lvs:binding"
+
+[[task.evaluation.jobs]]
+id = "parasitics"
+stage = "extract"
+operation = "layout.extract_rc"
+requires = [
+    "artifact",
+    "drc",
+    "lvs",
+    "geometry",
+]
+
+[task.evaluation.jobs.inputs]
+layout = "candidate"
+task = "task"
+
+[task.evaluation.jobs.outputs]
+netlist = "spice"
+
+[task.evaluation.jobs.parameters]
+ports = [
+    "vin",
+    "vout",
+    "clk",
+    "clkb",
+    "vdd",
+    "vss",
+]
+
+[[task.evaluation.jobs]]
+id = "nominal"
+stage = "simulate"
+operation = "circuit.simulate"
+
+[task.evaluation.jobs.inputs]
+deck = "input:performance"
+dut = "job:parasitics:netlist"
+
+[task.evaluation.jobs.outputs]
+waveform = "ngspice-raw"
+
+[task.evaluation.jobs.parameters.measurements]
+track_high = "V"
+track_again = "V"
+track_low = "V"
+hold_error_v = "V"
+settle_s = "s"
+
+[task.evaluation.jobs.parameters.values]
+
+[task.evaluation.jobs.parameters.exports]
+waveform = "waveform.raw"
+
+[[task.evaluation.metrics]]
+id = "functional_area"
+category = "physical"
+observations = [
+    "geometry:area",
+]
+unit = "um2"
+direction = "minimize"
+aggregation = "max"
+
+[[task.evaluation.metrics]]
+id = "high"
+category = "performance"
+observations = [
+    "nominal:track_high",
+    "nominal:track_again",
+]
+unit = "V"
+direction = "maximize"
+aggregation = "min"
+lower = 2.48
+upper = 2.52
+
+[[task.evaluation.metrics]]
+id = "low"
+category = "performance"
+observations = [
+    "nominal:track_low",
+]
+unit = "V"
+direction = "maximize"
+aggregation = "min"
+lower = 0.48
+upper = 0.52
+
+[[task.evaluation.metrics]]
+id = "hold"
+category = "performance"
+observations = [
+    "nominal:hold_error_v",
+]
+unit = "V"
+direction = "minimize"
+aggregation = "max"
+dimension = "response"
+baseline = [
+    "source_nominal:hold_error_v",
+]
+normalization = "ratio"
+scale = 0.02
+lower = 0
+upper = 3.3
+
+[[task.evaluation.metrics]]
+id = "settling"
+category = "performance"
+observations = [
+    "nominal:settle_s",
+]
+unit = "s"
+direction = "minimize"
+aggregation = "min"
+dimension = "response"
+baseline = [
+    "source_nominal:settle_s",
+]
+normalization = "ratio"
+lower = 0
+scale = 1e-15
+
+[task.evaluation.scoring]
+method = "layout"
+area_metric = "functional_area"
+area_target = 702.46
+rationale = "Track/hold switches: acquisition 39.4%; hold fidelity 50.6%; area 10%. Each objective's weight is divided equally among its metrics."
+
+[task.evaluation.scoring.weights]
+functional_area = 0.1
+settling = 0.39375
+hold = 0.50625
+
+[task.evaluation.pre_layout]
+source_report_sha256 = "226b4e1cf76a5bf2e7fd15531853087715beec009c901ae6d2fd68c87c68f287"
+
+[task.evaluation.pre_layout.backends]
+"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"ef9cb87fa27b849376472663b7362673979b89e012f161ba47bb5f6af6ede8eb\", \"compatibility\": null, \"execution_sha256\": \"5424b579002782bfddf0a729715b8fbf2a5f7f2b4cf14982d7616e352d5de9be\", \"image_id\": \"sha256:6562558774d43c085a289bbba696c55959eb8051a0996f96633451fbeb9c652d\", \"limits\": {\"cpus\": 4, \"memory_mb\": 4096, \"pids\": 256}, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"a340269fb13edfad479628bd59a0b72b878e648c0740e89671cd95b64adc03ef\", \"timeout_seconds\": 240.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}"
+
+[task.evaluation.pre_layout.jobs.source_nominal]
+operation = "circuit.simulate"
+
+[task.evaluation.pre_layout.jobs.source_nominal.inputs]
+deck = "input:performance"
+dut = "input:netlist"
+
+[task.evaluation.pre_layout.jobs.source_nominal.outputs]
+waveform = "ngspice-raw"
+
+[task.evaluation.pre_layout.jobs.source_nominal.parameters.measurements]
+track_high = "V"
+track_again = "V"
+track_low = "V"
+hold_error_v = "V"
+settle_s = "s"
+
+[task.evaluation.pre_layout.jobs.source_nominal.parameters.values]
+
+[task.evaluation.pre_layout.jobs.source_nominal.parameters.exports]
+waveform = "waveform.raw"
+
+[task.evaluation.pre_layout.jobs.source_nominal.input_sha256]
+deck = "35039b03b178d1954f4a5caf712b05ecf0780f12128b6d0028db9ea9ead924c5"
+dut = "24b64a7a410681352d4ec80b0fead64d6c1987ebd375acde58af33e7832f30dd"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.hold_error_v]
+value = 0.003106877
+unit = "V"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.settle_s]
+value = 4.361648e-10
+unit = "s"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.track_again]
+value = 2.5
+unit = "V"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.track_high]
+value = 2.5
+unit = "V"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.track_low]
+value = 0.5
+unit = "V"
+
+[toolchain.backends.artifact]
+type = "klayout-docker"
+
+[toolchain.backends.artifact.settings]
+image = "iclayout-bench-tools:local"
+check = "artifact"
+timeout_seconds = 180
+
+[toolchain.backends.drc]
+type = "klayout-docker"
+
+[toolchain.backends.drc.settings]
+image = "iclayout-bench-tools:local"
+check = "drc"
+timeout_seconds = 180
+support = "build/support/gf180-physical"
+profile = "drc.json"
+
+[toolchain.backends.drc.support_profiles]
+support = "physical"
+
+[toolchain.backends.lvs]
+type = "klayout-docker"
+
+[toolchain.backends.lvs.settings]
+image = "iclayout-bench-tools:local"
+check = "lvs"
+timeout_seconds = 180
+support = "build/support/gf180-physical"
+profile = "lvs.json"
+
+[toolchain.backends.lvs.support_profiles]
+support = "physical"
+
+[toolchain.backends.geometry]
+type = "klayout-geometry-docker"
+
+[toolchain.backends.geometry.settings]
+image = "iclayout-bench-tools:local"
+timeout_seconds = 180
+
+[toolchain.backends.rc]
+type = "magic-rc-docker"
+
+[toolchain.backends.rc.settings]
+image = "iclayout-bench-tools:local"
+support = "build/support/gf180-magic"
+technology = "gf180mcuD.tech"
+tech_name = "gf180mcuD"
+style = "ngspice()"
+gds_readonly = false
+grid_subdivision = 10
+case_insensitive_ports = true
+timeout_seconds = 240
+
+[toolchain.backends.rc.support_profiles]
+support = "magic"
+
+[toolchain.backends.ngspice]
+type = "ngspice-docker"
+
+[toolchain.backends.ngspice.settings]
+image = "iclayout-bench-tools:local"
+support = "build/support/gf180-models"
+timeout_seconds = 240
+
+[toolchain.backends.ngspice.support_profiles]
+support = "models"
+
+[toolchain.bindings]
+"layout.artifact" = "artifact"
+"layout.drc" = "drc"
+"layout.lvs" = "lvs"
+"layout.geometry" = "geometry"
+"layout.extract_rc" = "rc"
+"circuit.simulate" = "ngspice"
+
+[origin]
+url = "https://github.com/2AMLogic/gf180-sar-adc/tree/c32c8da53e52fbb7d75f6f628b8cc9f6f45a13fc/design/adc-top/adc_top.spice"
+
+[qualification]
+reference = "reference/adc_tgate_dum.gds"
+
+[presentation]
+category = "Mixed-signal"
+summary = "Tracks an analog input through a transmission gate with dummy compensation."

tasks/gf180mcuD/2AMLogic-sar-adc/cases/track_switch/materials/circuit.spice

@@ -0,0 +1,7 @@
+* Layout-Bench source-library derivative: Xschem wrapper enabled, terminal .end and local path comments removed.
+.subckt adc_tgate_dum vin vout clk clkb vdd vss
+XN  vin  clk  vout vss   nfet_03v3 w=40u l=0.28u
+XP  vin  clkb vout vdd pfet_03v3 w=80u l=0.28u
+XDN vout clkb vout vss   nfet_03v3 w=17.5u l=0.28u
+XDP vout clk  vout vdd pfet_03v3 w=35u l=0.28u
+.ends adc_tgate_dum

tasks/gf180mcuD/2AMLogic-sar-adc/cases/track_switch/materials/testbench.spice

@@ -0,0 +1,24 @@
+* GF180MCU nominal characterization: 3.3 V, 27 C, typical models.
+.include "support/models.spice"
+.include "dut.spice"
+.include "parameters.spice"
+.temp 27
+VDD vdd 0 3.3
+VIN vin 0 PWL(0 .5 5n .5 5.1n 2.5 30n 2.5 30.1n .5 55n .5 55.1n 2.5)
+VCLK clk 0 PWL(0 3.3 20n 3.3 20.1n 0 45n 0 45.1n 3.3)
+VCLKB clkb 0 PWL(0 0 20n 0 20.1n 3.3 45n 3.3 45.1n 0)
+CLOAD out 0 1p
+XDUT vin out clk clkb vdd 0 adc_tgate_dum
+.control
+tran .01n 70n
+meas tran track_high find v(out) at=19n
+meas tran hold_high find v(out) at=44n
+meas tran track_low find v(out) at=54n
+meas tran track_again find v(out) at=69n
+meas tran settle_s trig v(vin) val=1.5 rise=1 targ v(out) val=2.48 rise=1
+let hold_error=abs(v(out)-2.5)
+meas tran hold_error_v max hold_error from=21n to=44n
+write waveform.raw
+quit
+.endc
+.end

tasks/gf180mcuD/2AMLogic-sar-adc/cases/track_switch/problem.md

@@ -0,0 +1,97 @@
+# Dummy-Compensated Track Switch Layout Task
+
+## Objective
+
+Implement `adc_tgate_dum` in GF180MCU variant D while preserving the supplied circuit, device dimensions and ordered interface. Complementary-clock tracking, settling and hold feedthrough for 0.5 V / 2.5 V steps and a 1 pF output capacitor.
+
+## Inputs and Interface
+
+The delivered files are `materials/circuit.spice` (authoritative circuit), `materials/testbench.spice` (stimuli and measurements), and this problem. Runtime task metadata supplies the same frozen constraints, evaluation conditions and output declaration.
+
+Ordered subcircuit and GDS interface: `vin, vout, clk, clkb, vdd, vss`.
+vin: signal input; vout: sampled output; clk/clkb: complementary track control; vdd/vss: supply and device body connections.
+
+Preserve topology and total device width, channel length, multiplicity, resistor dimensions and body connections. Equivalent hierarchy, diffusion sharing and parallel-finger implementations are allowed when they pass connectivity and electrical checks. No source-model replacement, idealized internal device or changed device sizing is permitted. A dummy device remains part of the circuit even when its terminals are tied together.
+
+## Operating Conditions
+
+Use 3.3 V and 27 C with a 1 pF capacitor from vout to vss. Vin begins at 0.5 V, rises to 2.5 V at 5.1 ns, falls to 0.5 V at 30.1 ns and rises to 2.5 V at 55.1 ns. Track initially (clk=3.3 V, clkb=0 V), hold from 20.1 to 45 ns and resume tracking at 45.1 ns. All transitions take 0.1 ns. Simulate to 70 ns with a 0.01 ns requested step. The four MOS widths are fixed to the upstream default values: 40, 80, 17.5 and 35 um; every channel length is 0.28 um. vss is the explicit form of the original global ground connection.
+
+Use the reviewed typical primitive models with statistical variation disabled. Numerical parameters in the runtime simulation jobs supply the testbench's `parameters.spice`. Follow the delivered testbench for interpolation and detailed PWL definitions. This is a nominal compact-model task; temperature/process corners, mismatch yield, noise, RF/EM and full-chip density closure are outside its qualification scope.
+
+## Physical Requirements
+
+Submit a nonempty GDS with top cell `adc_tgate_dum` and at most 10485760 bytes. Its functional bounding box must not exceed 160 by 160 um. All relevant device and routing polygons contribute, including implant/well, passive markers, contacts, vias and dummy routing. The complete layer/datatype set is:
+
+`[[5,0],[11,17],[11,39],[12,0],[13,17],[21,0],[22,0],[22,4],[24,0],[24,5],[30,0],[30,4],[31,0],[32,0],[33,0],[34,0],[34,3],[34,4],[34,5],[35,0],[36,0],[36,3],[36,4],[36,5],[37,0],[38,0],[40,0],[41,0],[42,0],[42,3],[42,4],[42,5],[46,0],[46,3],[46,4],[46,5],[49,0],[53,0],[53,3],[53,4],[53,5],[55,0],[62,0],[75,0],[80,5],[81,0],[81,3],[81,4],[81,5],[82,0],[86,17],[88,17],[96,1],[100,5],[100,7],[100,8],[108,5],[110,5],[110,11],[110,12],[110,13],[110,14],[110,15],[110,16],[111,5],[112,1],[115,5],[116,5],[117,5],[117,10],[118,5],[119,5],[122,5],[123,5],[124,5],[125,5],[127,5],[128,17],[137,5],[151,5],[152,5],[153,51],[166,5],[167,5],[173,5],[178,0],[183,0],[184,0],[185,0],[204,0],[210,0],[220,0],[226,0],[227,0],[241,0]]`.
+
+Text and nonfunctional boundary layers 0/0 and 63/0 are excluded from area. Functional geometry may not be hidden on annotation layers. Pass the pinned GF180 D FEOL, BEOL, connectivity, off-grid and antenna checks without marker waivers. The stack is five metals with 1.1 um top metal and the 1 kOhm/square high-resistance poly option. Chip-level density and seal-ring closure are integration responsibilities outside this standalone block.
+
+LVS checks device topology, dimensions, body connections and every named top-level pin (case insensitive). Supply and substrate/well contacts must be physical. Distinct electrical nets must not be joined by touching silicided diffusion. After validity and geometry gates, extract the submitted candidate's devices and distributed interconnect resistance and capacitance. Simulations use that extracted circuit. The substrate compact-model boundary is one equipotential bulk domain with explicit well/body contacts; this does not model a distributed silicon substrate network. Unreliable extraction, absent named ports or incomplete measurements cannot establish success.
+
+## Electrical Requirements and Scoring
+
+Physical checks and declared functional bounds remain mandatory. Quality has no
+fixed allowed-degradation threshold. Each `source_*` job simulates the declared
+source circuit with exactly the same testbench, model resources, parameters,
+load and measurement window as its paired extracted-candidate job. A source
+observation is the 100-point electrical baseline; it is independent of the
+submitted GDS. All individual pairs are retained in the evaluation report.
+
+For a post-layout observation x and its source observation b:
+
+- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,
+  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;
+  s is a normalization floor, not an allowed degradation or pass threshold.
+- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.
+- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and
+  zero-valued operating points are never divided directly.
+
+Scoring uses `layout`. A metric uses its worst paired quality q. The score is
+S = 100 * product(q_i ** w_i), including area quality
+q_area = area_reference / candidate_functional_area. The weights below sum to
+one. Dimensions describe measurements but do not determine their weights.
+Physical or functional rejection scores zero; missing or invalid measurements
+produce an unknown score, including measurements with zero weight.
+Source-equivalent performance at the area reference scores 100; improvements
+can exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.
+
+| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale |
+| --- | --- | --- | --- | --- | --- |
+| `high` | vout at 19 and 69 ns. | V | functional check | 2.48 … 2.52 | — |
+| `low` | vout at 54 ns, after tracking resumes with vin=0.5 V. | V | functional check | 0.48 … 0.52 | — |
+| `hold` | Maximum absolute vout-2.5 V over 21–44 ns, including the vin transition while the switch is open. | V | minimize / ratio | 0 … 3.3 | 0.02 |
+| `settling` | First vin rising 1.5 V crossing to vout reaching 2.48 V. | s | minimize / ratio | 0 … +∞ | 1e-15 |
+
+The tracking checks define a 1% settling-accuracy task: 20 mV is 1% of
+the declared 2 V input step. Both sampled tracking levels must meet that
+accuracy; the settling measurement uses the same high-level boundary.
+This is an explicit sampled acquisition requirement, not a tolerance fitted
+to the reference layout. Hold error remains continuous quality, with q=(source_error+0.02 V)/
+(candidate_error+0.02 V), so reducing absolute error always improves quality.
+The 20 mV floor uses the declared acquisition-accuracy scale and keeps
+near-zero source error well-conditioned; it is not a hold-error pass threshold.
+
+Area reference: **702.46 um2**. 4 expanded device instances; sum of device/contact envelopes 411.5400 um2, per-side envelope allowance 1 um, 50% routing allowance and total outer width/height allowance 2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.
+
+The capability coefficient remains **4**; it is independent of
+the reference-relative task score.
+
+
+### Score weights
+
+Track/hold switches: acquisition 39.4%; hold fidelity 50.6%; area 10%. Each objective's weight is divided equally among its metrics.
+
+| Metric | Weight |
+| --- | ---: |
+| `functional_area` | 0.1 |
+| `settling` | 0.393750000000 |
+| `hold` | 0.506250000000 |
+
+## Tools and Submission
+
+Solve budget: **3 hours**.
+
+Use runtime task, resource and harness discovery to locate the delivered inputs and reviewed GF180 resources. Trusted feedback runs the declared physical and post-layout evaluation; source-only simulation is useful for design but is not acceptance. Write the final GDS to `/workspace/output/final.gds` and explicitly submit it using the harness submission interface. A generated file or successful standalone simulation alone does not complete the task.
+
+Use a GDS database unit of 0.001 um, as required by the GF180MCU DRC deck.

tasks/gf180mcuD/Chipathon2023_ADC/LICENSE

@@ -0,0 +1,231 @@
+                                 Apache License
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+
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+      the terms of any separate license agreement you may have executed
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+   6. Trademarks. This License does not grant permission to use the trade
+      names, trademarks, service marks, or product names of the Licensor,
+      except as required for reasonable and customary use in describing the
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+   7. Disclaimer of Warranty. Unless required by applicable law or
+      agreed to in writing, Licensor provides the Work (and each
+      Contributor provides its Contributions) on an "AS IS" BASIS,
+      WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+      implied, including, without limitation, any warranties or conditions
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+      PARTICULAR PURPOSE. You are solely responsible for determining the
+      appropriateness of using or redistributing the Work and assume any
+      risks associated with Your exercise of permissions under this License.
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+   8. Limitation of Liability. In no event and under no legal theory,
+      whether in tort (including negligence), contract, or otherwise,
+      unless required by applicable law (such as deliberate and grossly
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+      on Your own behalf and on Your sole responsibility, not on behalf
+      of any other Contributor, and only if You agree to indemnify,
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+   END OF TERMS AND CONDITIONS
+
+   APPENDIX: How to apply the Apache License to your work.
+
+      To apply the Apache License to your work, attach the following
+      boilerplate notice, with the fields enclosed by brackets "[]"
+      replaced with your own identifying information. (Don't include
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+      comment syntax for the file format. We also recommend that a
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+   Copyright [yyyy] [name of copyright owner]
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+   Licensed under the Apache License, Version 2.0 (the "License");
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+
+GF180 primitive symbol export expressions in materials/circuit.spice
+==================================================================
+Copyright 2022 GlobalFoundries PDK Authors. Licensed under Apache-2.0.
+Source: gf180mcu_fd_pr/cells/xschem/symbols; exported MOS geometry expressions.
+# This is the list of GlobalFoundries PDK's significant contributors.
+#
+# This does not necessarily list everyone who has contributed code,
+# especially since many employees of one corporation may be contributing.
+# To see the full list of contributors, see the revision history in
+# source control.
+
+# Companies
+Google LLC
+GlobalFoundries
+Efabless Corporation
+Mabrains LLC
+
+# Individuals
+tansell@google.com, me@mith.ro (Tim 'mithro' Ansell)
+proppy@google.com (Johan 'proppy' Euphrosine)
+tim@efabless.com (Tim Edwards)
+mkk@efabless.com (Mohamed Kassem)
+stefan.schippers@gmail.com (Stefan Schippers)
+amro_tork@mabrains.com (Amro Tork)
+farag_agoor@mabrains.com (Farag Agoor)
+mohanad_mohamed@mabrains.com (Mohanad Mohammed)
+
+The Apache-2.0 license text above also applies to these expressions.

tasks/gf180mcuD/Chipathon2023_ADC/cases/comparator/case.toml

@@ -0,0 +1,815 @@
+in_core = false
+kind = "layout_case"
+id = "gf180mcuD.Chipathon2023_ADC.comparator"
+title = "Dynamic Comparator"
+status = "qualified"
+
+[[assets]]
+path = "materials/schematic.svg"
+role = "schematic"
+visibility = "maintainer"
+format = "svg"
+sha256 = "220dfa102f1425882ab0057dc450b308072c80b1e2336f0f0ba620de2c092b26"
+
+[[assets]]
+path = "reference/comp_20240331.gds"
+role = "reference"
+visibility = "maintainer"
+format = "gds"
+sha256 = "6f48088208f611c25dcb6874006b1ac07903745b48689f025cd6765afd09123e"
+
+[task]
+hours = 3
+kind = "netlist_to_gds"
+family = "gf180_comparator"
+coefficient = 6
+environment = "gf180mcuD-typical-rc"
+
+[task.inputs.description]
+path = "problem.md"
+format = "text"
+sha256 = "c8272d354198b139b8a76da6e44cd5ef93d95ce452ef413ddfe437e9e7d61d36"
+
+[task.inputs.netlist]
+path = "materials/circuit.spice"
+format = "spice"
+sha256 = "0f529f8162a367b1408730f5dee3b06847de139a770fc41be1bd38e92c056e3d"
+subcircuit = "comp_20240331"
+
+[task.inputs.performance]
+path = "materials/testbench.spice"
+format = "spice"
+sha256 = "f291cfa28ac8a9c0d85d36712ffbee761dab2793167b829908212de24738b809"
+
+[task.output]
+path = "output/final.gds"
+format = "gds"
+top_cell = "comp_20240331"
+max_bytes = 10485760
+
+[task.constraints]
+quality = [
+    { id = "area", type = "functional_bbox_area", layers_from = "outline" },
+]
+
+[[task.constraints.hard]]
+id = "outline"
+type = "bbox_max"
+functional_layers = [
+    [
+        5,
+        0,
+    ],
+    [
+        11,
+        17,
+    ],
+    [
+        11,
+        39,
+    ],
+    [
+        12,
+        0,
+    ],
+    [
+        13,
+        17,
+    ],
+    [
+        21,
+        0,
+    ],
+    [
+        22,
+        0,
+    ],
+    [
+        22,
+        4,
+    ],
+    [
+        24,
+        0,
+    ],
+    [
+        24,
+        5,
+    ],
+    [
+        30,
+        0,
+    ],
+    [
+        30,
+        4,
+    ],
+    [
+        31,
+        0,
+    ],
+    [
+        32,
+        0,
+    ],
+    [
+        33,
+        0,
+    ],
+    [
+        34,
+        0,
+    ],
+    [
+        34,
+        3,
+    ],
+    [
+        34,
+        4,
+    ],
+    [
+        34,
+        5,
+    ],
+    [
+        35,
+        0,
+    ],
+    [
+        36,
+        0,
+    ],
+    [
+        36,
+        3,
+    ],
+    [
+        36,
+        4,
+    ],
+    [
+        36,
+        5,
+    ],
+    [
+        37,
+        0,
+    ],
+    [
+        38,
+        0,
+    ],
+    [
+        40,
+        0,
+    ],
+    [
+        41,
+        0,
+    ],
+    [
+        42,
+        0,
+    ],
+    [
+        42,
+        3,
+    ],
+    [
+        42,
+        4,
+    ],
+    [
+        42,
+        5,
+    ],
+    [
+        46,
+        0,
+    ],
+    [
+        46,
+        3,
+    ],
+    [
+        46,
+        4,
+    ],
+    [
+        46,
+        5,
+    ],
+    [
+        49,
+        0,
+    ],
+    [
+        53,
+        0,
+    ],
+    [
+        53,
+        3,
+    ],
+    [
+        53,
+        4,
+    ],
+    [
+        53,
+        5,
+    ],
+    [
+        55,
+        0,
+    ],
+    [
+        62,
+        0,
+    ],
+    [
+        75,
+        0,
+    ],
+    [
+        80,
+        5,
+    ],
+    [
+        81,
+        0,
+    ],
+    [
+        81,
+        3,
+    ],
+    [
+        81,
+        4,
+    ],
+    [
+        81,
+        5,
+    ],
+    [
+        82,
+        0,
+    ],
+    [
+        86,
+        17,
+    ],
+    [
+        88,
+        17,
+    ],
+    [
+        96,
+        1,
+    ],
+    [
+        100,
+        5,
+    ],
+    [
+        100,
+        7,
+    ],
+    [
+        100,
+        8,
+    ],
+    [
+        108,
+        5,
+    ],
+    [
+        110,
+        5,
+    ],
+    [
+        110,
+        11,
+    ],
+    [
+        110,
+        12,
+    ],
+    [
+        110,
+        13,
+    ],
+    [
+        110,
+        14,
+    ],
+    [
+        110,
+        15,
+    ],
+    [
+        110,
+        16,
+    ],
+    [
+        111,
+        5,
+    ],
+    [
+        112,
+        1,
+    ],
+    [
+        115,
+        5,
+    ],
+    [
+        116,
+        5,
+    ],
+    [
+        117,
+        5,
+    ],
+    [
+        117,
+        10,
+    ],
+    [
+        118,
+        5,
+    ],
+    [
+        119,
+        5,
+    ],
+    [
+        122,
+        5,
+    ],
+    [
+        123,
+        5,
+    ],
+    [
+        124,
+        5,
+    ],
+    [
+        125,
+        5,
+    ],
+    [
+        127,
+        5,
+    ],
+    [
+        128,
+        17,
+    ],
+    [
+        137,
+        5,
+    ],
+    [
+        151,
+        5,
+    ],
+    [
+        152,
+        5,
+    ],
+    [
+        153,
+        51,
+    ],
+    [
+        166,
+        5,
+    ],
+    [
+        167,
+        5,
+    ],
+    [
+        173,
+        5,
+    ],
+    [
+        178,
+        0,
+    ],
+    [
+        183,
+        0,
+    ],
+    [
+        184,
+        0,
+    ],
+    [
+        185,
+        0,
+    ],
+    [
+        204,
+        0,
+    ],
+    [
+        210,
+        0,
+    ],
+    [
+        220,
+        0,
+    ],
+    [
+        226,
+        0,
+    ],
+    [
+        227,
+        0,
+    ],
+    [
+        241,
+        0,
+    ],
+]
+max_width_um = 200
+max_height_um = 100
+
+[task.evaluation]
+mode = "post_layout"
+
+[[task.evaluation.jobs]]
+id = "artifact"
+stage = "check"
+operation = "layout.artifact"
+gate = "artifact"
+
+[task.evaluation.jobs.inputs]
+layout = "candidate"
+task = "task"
+
+[[task.evaluation.jobs]]
+id = "drc"
+stage = "check"
+operation = "layout.drc"
+gate = "drc"
+requires = [
+    "artifact",
+]
+
+[task.evaluation.jobs.inputs]
+layout = "candidate"
+task = "task"
+
+[[task.evaluation.jobs]]
+id = "lvs"
+stage = "check"
+operation = "layout.lvs"
+gate = "lvs"
+requires = [
+    "artifact",
+]
+
+[task.evaluation.jobs.inputs]
+layout = "candidate"
+task = "task"
+netlist = "input:netlist"
+
+[task.evaluation.jobs.outputs]
+database = "klayout-lvs"
+binding = "json"
+
+[[task.evaluation.jobs]]
+id = "geometry"
+stage = "check"
+operation = "layout.geometry"
+gate = "constraint"
+requires = [
+    "artifact",
+    "drc",
+    "lvs",
+]
+
+[task.evaluation.jobs.inputs]
+layout = "candidate"
+task = "task"
+constraints = "input:constraints"
+database = "job:lvs:database"
+binding = "job:lvs:binding"
+
+[[task.evaluation.jobs]]
+id = "parasitics"
+stage = "extract"
+operation = "layout.extract_rc"
+requires = [
+    "artifact",
+    "drc",
+    "lvs",
+    "geometry",
+]
+
+[task.evaluation.jobs.inputs]
+layout = "candidate"
+task = "task"
+
+[task.evaluation.jobs.outputs]
+netlist = "spice"
+
+[task.evaluation.jobs.parameters]
+ports = [
+    "VDD",
+    "CLK",
+    "VOUTP",
+    "VOUTN",
+    "VINP",
+    "VINN",
+    "VSS",
+]
+
+[[task.evaluation.jobs]]
+id = "negative"
+stage = "simulate"
+operation = "circuit.simulate"
+
+[task.evaluation.jobs.inputs]
+deck = "input:performance"
+dut = "job:parasitics:netlist"
+
+[task.evaluation.jobs.outputs]
+waveform = "ngspice-raw"
+
+[task.evaluation.jobs.parameters.measurements]
+decision_v = "V"
+delay_s = "s"
+power_w = "W"
+
+[task.evaluation.jobs.parameters.values]
+polarity = -1
+
+[task.evaluation.jobs.parameters.exports]
+waveform = "waveform.raw"
+
+[[task.evaluation.jobs]]
+id = "positive"
+stage = "simulate"
+operation = "circuit.simulate"
+
+[task.evaluation.jobs.inputs]
+deck = "input:performance"
+dut = "job:parasitics:netlist"
+
+[task.evaluation.jobs.outputs]
+waveform = "ngspice-raw"
+
+[task.evaluation.jobs.parameters.measurements]
+decision_v = "V"
+delay_s = "s"
+power_w = "W"
+
+[task.evaluation.jobs.parameters.values]
+polarity = 1
+
+[task.evaluation.jobs.parameters.exports]
+waveform = "waveform.raw"
+
+[[task.evaluation.metrics]]
+id = "functional_area"
+category = "physical"
+observations = [
+    "geometry:area",
+]
+unit = "um2"
+direction = "minimize"
+aggregation = "max"
+
+[[task.evaluation.metrics]]
+id = "decision"
+category = "performance"
+observations = [
+    "negative:decision_v",
+    "positive:decision_v",
+]
+unit = "V"
+direction = "maximize"
+aggregation = "min"
+lower = 2.97
+
+[[task.evaluation.metrics]]
+id = "delay"
+category = "performance"
+observations = [
+    "negative:delay_s",
+    "positive:delay_s",
+]
+unit = "s"
+direction = "minimize"
+aggregation = "min"
+dimension = "response"
+baseline = [
+    "source_negative:delay_s",
+    "source_positive:delay_s",
+]
+normalization = "ratio"
+lower = 0
+
+[[task.evaluation.metrics]]
+id = "supply"
+category = "performance"
+observations = [
+    "negative:power_w",
+    "positive:power_w",
+]
+unit = "W"
+direction = "minimize"
+aggregation = "min"
+dimension = "supply"
+baseline = [
+    "source_negative:power_w",
+    "source_positive:power_w",
+]
+normalization = "ratio"
+lower = 0
+scale = 1e-12
+
+[task.evaluation.scoring]
+method = "layout"
+area_metric = "functional_area"
+area_target = 301.49
+rationale = "Clocked comparators: decision delay 71.1%; supply power 18.9%; area 10%. Each objective's weight is divided equally among its metrics."
+
+[task.evaluation.scoring.weights]
+functional_area = 0.1
+delay = 0.710526315789
+supply = 0.189473684211
+
+[task.evaluation.pre_layout]
+source_report_sha256 = "45bf5e421a40402e85ad6b594cd1a464d5076efb92c85930110d97c8259bd132"
+
+[task.evaluation.pre_layout.backends]
+"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"ef9cb87fa27b849376472663b7362673979b89e012f161ba47bb5f6af6ede8eb\", \"compatibility\": null, \"execution_sha256\": \"5424b579002782bfddf0a729715b8fbf2a5f7f2b4cf14982d7616e352d5de9be\", \"image_id\": \"sha256:6562558774d43c085a289bbba696c55959eb8051a0996f96633451fbeb9c652d\", \"limits\": {\"cpus\": 4, \"memory_mb\": 4096, \"pids\": 256}, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"a340269fb13edfad479628bd59a0b72b878e648c0740e89671cd95b64adc03ef\", \"timeout_seconds\": 240.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}"
+
+[task.evaluation.pre_layout.jobs.source_negative]
+operation = "circuit.simulate"
+
+[task.evaluation.pre_layout.jobs.source_negative.inputs]
+deck = "input:performance"
+dut = "input:netlist"
+
+[task.evaluation.pre_layout.jobs.source_negative.outputs]
+waveform = "ngspice-raw"
+
+[task.evaluation.pre_layout.jobs.source_negative.parameters.measurements]
+decision_v = "V"
+delay_s = "s"
+power_w = "W"
+
+[task.evaluation.pre_layout.jobs.source_negative.parameters.values]
+polarity = -1
+
+[task.evaluation.pre_layout.jobs.source_negative.parameters.exports]
+waveform = "waveform.raw"
+
+[task.evaluation.pre_layout.jobs.source_negative.input_sha256]
+deck = "f291cfa28ac8a9c0d85d36712ffbee761dab2793167b829908212de24738b809"
+dut = "0f529f8162a367b1408730f5dee3b06847de139a770fc41be1bd38e92c056e3d"
+
+[task.evaluation.pre_layout.jobs.source_negative.measurements.decision_v]
+value = 3.299999
+unit = "V"
+
+[task.evaluation.pre_layout.jobs.source_negative.measurements.delay_s]
+value = 1.228056e-09
+unit = "s"
+
+[task.evaluation.pre_layout.jobs.source_negative.measurements.power_w]
+value = 9.475911e-05
+unit = "W"
+
+[task.evaluation.pre_layout.jobs.source_positive]
+operation = "circuit.simulate"
+
+[task.evaluation.pre_layout.jobs.source_positive.inputs]
+deck = "input:performance"
+dut = "input:netlist"
+
+[task.evaluation.pre_layout.jobs.source_positive.outputs]
+waveform = "ngspice-raw"
+
+[task.evaluation.pre_layout.jobs.source_positive.parameters.measurements]
+decision_v = "V"
+delay_s = "s"
+power_w = "W"
+
+[task.evaluation.pre_layout.jobs.source_positive.parameters.values]
+polarity = 1
+
+[task.evaluation.pre_layout.jobs.source_positive.parameters.exports]
+waveform = "waveform.raw"
+
+[task.evaluation.pre_layout.jobs.source_positive.input_sha256]
+deck = "f291cfa28ac8a9c0d85d36712ffbee761dab2793167b829908212de24738b809"
+dut = "0f529f8162a367b1408730f5dee3b06847de139a770fc41be1bd38e92c056e3d"
+
+[task.evaluation.pre_layout.jobs.source_positive.measurements.decision_v]
+value = 3.299999
+unit = "V"
+
+[task.evaluation.pre_layout.jobs.source_positive.measurements.delay_s]
+value = 1.228056e-09
+unit = "s"
+
+[task.evaluation.pre_layout.jobs.source_positive.measurements.power_w]
+value = 9.475911e-05
+unit = "W"
+
+[toolchain.backends.artifact]
+type = "klayout-docker"
+
+[toolchain.backends.artifact.settings]
+image = "iclayout-bench-tools:local"
+check = "artifact"
+timeout_seconds = 180
+
+[toolchain.backends.drc]
+type = "klayout-docker"
+
+[toolchain.backends.drc.settings]
+image = "iclayout-bench-tools:local"
+check = "drc"
+timeout_seconds = 180
+support = "build/support/gf180-physical"
+profile = "drc.json"
+
+[toolchain.backends.drc.support_profiles]
+support = "physical"
+
+[toolchain.backends.lvs]
+type = "klayout-docker"
+
+[toolchain.backends.lvs.settings]
+image = "iclayout-bench-tools:local"
+check = "lvs"
+timeout_seconds = 180
+support = "build/support/gf180-physical"
+profile = "lvs.json"
+
+[toolchain.backends.lvs.support_profiles]
+support = "physical"
+
+[toolchain.backends.geometry]
+type = "klayout-geometry-docker"
+
+[toolchain.backends.geometry.settings]
+image = "iclayout-bench-tools:local"
+timeout_seconds = 180
+
+[toolchain.backends.rc]
+type = "magic-rc-docker"
+
+[toolchain.backends.rc.settings]
+image = "iclayout-bench-tools:local"
+support = "build/support/gf180-magic"
+technology = "gf180mcuD.tech"
+tech_name = "gf180mcuD"
+style = "ngspice()"
+gds_readonly = false
+grid_subdivision = 10
+case_insensitive_ports = true
+timeout_seconds = 240
+
+[toolchain.backends.rc.support_profiles]
+support = "magic"
+
+[toolchain.backends.ngspice]
+type = "ngspice-docker"
+
+[toolchain.backends.ngspice.settings]
+image = "iclayout-bench-tools:local"
+support = "build/support/gf180-models"
+timeout_seconds = 240
+
+[toolchain.backends.ngspice.support_profiles]
+support = "models"
+
+[toolchain.bindings]
+"layout.artifact" = "artifact"
+"layout.drc" = "drc"
+"layout.lvs" = "lvs"
+"layout.geometry" = "geometry"
+"layout.extract_rc" = "rc"
+"circuit.simulate" = "ngspice"
+
+[origin]
+url = "https://github.com/ishi-kai/Chipathon2023_ADC/tree/3dce439b2125a9d628e43be40c65cf8fce5d795c/gitefu/comp_20240331/comp_20240331.sch"
+
+[qualification]
+reference = "reference/comp_20240331.gds"
+
+[presentation]
+category = "Mixed-signal"
+summary = "Compares two input voltages using a clocked regenerative decision."

tasks/gf180mcuD/Chipathon2023_ADC/cases/comparator/materials/circuit.spice

@@ -0,0 +1,41 @@
+* Layout-Bench source-library derivative: Xschem wrapper enabled, terminal .end and local path comments removed.
+.subckt comp_20240331 VDD CLK VOUTP VOUTN VINP VINN VSS
+
+*.ipin VDD
+*.ipin CLK
+*.ipin VINP
+*.ipin VINN
+*.ipin VSS
+*.opin VOUTP
+*.opin VOUTN
+XM1 net3 CLK VSS VSS nfet_03v3 L=0.28u W=2.80u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)'
++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1
+XM2 net1 VINP net3 VSS nfet_03v3 L=0.28u W=2.80u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)'
++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1
+XM4 net1 CLK VDD VDD pfet_03v3 L=0.28u W=2.80u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)'
++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1
+XM6 net4 net1 VDD VDD pfet_03v3 L=0.28u W=2.80u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)'
++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1
+XM7 VOUTP VOUTN net4 VDD pfet_03v3 L=0.28u W=2.80u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)'
++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1
+XM8 net4 net1 VSS VSS nfet_03v3 L=0.28u W=2.80u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)'
++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1
+XM9 VOUTP net1 VSS VSS nfet_03v3 L=0.28u W=2.80u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)'
++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1
+XM10 VOUTP VOUTN VSS VSS nfet_03v3 L=0.28u W=2.80u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)'
++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1
+XM3 net2 VINN net3 VSS nfet_03v3 L=0.28u W=2.80u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)'
++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1
+XM5 net2 CLK VDD VDD pfet_03v3 L=0.28u W=2.80u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)'
++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1
+XM11 net5 net2 VDD VDD pfet_03v3 L=0.28u W=2.80u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)'
++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1
+XM12 VOUTN VOUTP net5 VDD pfet_03v3 L=0.28u W=2.80u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)'
++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1
+XM13 net5 net2 VSS VSS nfet_03v3 L=0.28u W=2.80u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)'
++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1
+XM14 VOUTN net2 VSS VSS nfet_03v3 L=0.28u W=2.80u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)'
++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1
+XM15 VOUTN VOUTP VSS VSS nfet_03v3 L=0.28u W=2.80u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)'
++ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1
+.ends