Publish native Parquet task index (part 2)

Native typed, Zstd-compressed Parquet index for 92 public tasks (21 core). Static release matches Dataset commit 73f421307434e0953bb9fd5b5d54e0150dffd875.

tasks/gf180mcuD/voidwalkers-scandff/cases/scan_dff/case.toml

@@ -1,15 +1,15 @@
-in_core = true
 kind = "layout_case"
 id = "gf180mcuD.voidwalkers-scandff.scan_dff"
 title = "Scan D Flip-Flop with Active-Low Reset"
 status = "qualified"
+in_core = true
 
 [[assets]]
 path = "materials/schematic.svg"
 role = "schematic"
 visibility = "maintainer"
 format = "svg"
-sha256 = "99ace8db2b9b5611c896d24f0fb95767f76f6568867a21be756c596f11345166"
+sha256 = "cc82ad15dde6c3790aa2277e0b0c16487a74bfc864a207fa605cb022e15c4964"
 
 [[assets]]
 path = "reference/gf180mcu_voidwalkers_sc_sdffrnq_4.gds"
@@ -28,18 +28,18 @@ environment = "gf180mcuD-typical-rc"
 [task.inputs.description]
 path = "problem.md"
 format = "text"
-sha256 = "4dd3b36c545bf772efe7d79ce147682f337e9e9c38f353ba0ae8a129d452865b"
+sha256 = "17629e273b63c5c18ed8c034c06a317115bb626e51dc82f7a5f55c70f4bafde0"
 
 [task.inputs.netlist]
 path = "materials/circuit.spice"
 format = "spice"
-sha256 = "659e961943b07c6a7665d4e640a037508fc255ce66752c02ca5de94ae1d07e58"
 subcircuit = "gf180mcu_voidwalkers_sc_sdffrnq_4"
+sha256 = "659e961943b07c6a7665d4e640a037508fc255ce66752c02ca5de94ae1d07e58"
 
 [task.inputs.performance]
 path = "materials/testbench.spice"
 format = "spice"
-sha256 = "43d1b9312f6024b9fe2f2c55e841d741e915254ffa5d9a1e476ab406323c46dc"
+sha256 = "85002e6ae68a6b3b94f271f3231beab8f86542a4543d047fe1e0c5f62997949f"
 
 [task.output]
 path = "output/final.gds"
@@ -962,9 +962,11 @@ low59 = "V"
 reset89 = "V"
 reset99 = "V"
 low139 = "V"
+setup_rise_q = "V"
 high39 = "V"
 high79 = "V"
 high119 = "V"
+setup_fall_q = "V"
 power_w = "W"
 delay_data_rise = "s"
 slew_data_rise = "s"
@@ -976,6 +978,10 @@ delay_scan_fall = "s"
 slew_scan_fall = "s"
 delay_reset_fall = "s"
 slew_reset_fall = "s"
+delay_setup_a_rise = "s"
+slew_setup_a_rise = "s"
+delay_setup_a_fall = "s"
+slew_setup_a_fall = "s"
 
 [task.evaluation.jobs.parameters.values]
 
@@ -1001,11 +1007,15 @@ observations = [
     "nominal:reset89",
     "nominal:reset99",
     "nominal:low139",
+    "nominal:setup_fall_q",
 ]
 unit = "V"
 direction = "minimize"
 aggregation = "max"
+
+[task.evaluation.metrics.requirement]
 upper = 0.33
+rationale = "The declared truth-table, SRAM sense or polarity-correct comparator output must reach its stated CMOS logic level at every functional sample under the fixed supply and load."
 
 [[task.evaluation.metrics]]
 id = "high"
@@ -1014,11 +1024,15 @@ observations = [
     "nominal:high39",
     "nominal:high79",
     "nominal:high119",
+    "nominal:setup_rise_q",
 ]
 unit = "V"
 direction = "maximize"
 aggregation = "min"
+
+[task.evaluation.metrics.requirement]
 lower = 2.97
+rationale = "The declared truth-table, SRAM sense or polarity-correct comparator output must reach its stated CMOS logic level at every functional sample under the fixed supply and load."
 
 [[task.evaluation.metrics]]
 id = "supply"
@@ -1034,9 +1048,12 @@ baseline = [
     "source_nominal:power_w",
 ]
 normalization = "ratio"
-lower = 0
 scale = 1e-12
 
+[task.evaluation.metrics.requirement]
+lower = 0
+rationale = "The declared powered circuit must consume nonnegative net energy from its supplies and driven references over the stated observation; power magnitude remains a quality objective."
+
 [[task.evaluation.metrics]]
 id = "propagation_delay"
 category = "performance"
@@ -1046,6 +1063,8 @@ observations = [
     "nominal:delay_scan_rise",
     "nominal:delay_scan_fall",
     "nominal:delay_reset_fall",
+    "nominal:delay_setup_a_rise",
+    "nominal:delay_setup_a_fall",
 ]
 baseline = [
     "source_nominal:delay_data_rise",
@@ -1053,13 +1072,22 @@ baseline = [
     "source_nominal:delay_scan_rise",
     "source_nominal:delay_scan_fall",
     "source_nominal:delay_reset_fall",
+    "source_nominal:delay_setup_a_rise",
+    "source_nominal:delay_setup_a_fall",
 ]
 unit = "s"
 direction = "minimize"
 aggregation = "max"
 dimension = "response"
 normalization = "ratio"
+
+[task.evaluation.metrics.requirement]
 lower = 0.0
+rationale = "The declared ordered-event interval or crossing frequency has a nonnegative measurement domain, and its crossing must exist for a usable observation."
+
+[task.evaluation.metrics.quality_target]
+value = 5.5e-10
+rationale = "Keep all declared clock/data/reset-to-Q timing observations within 550 ps at 50 fF, including the late-cycle capture exercises."
 
 [[task.evaluation.metrics]]
 id = "output_transition"
@@ -1070,6 +1098,8 @@ observations = [
     "nominal:slew_scan_rise",
     "nominal:slew_scan_fall",
     "nominal:slew_reset_fall",
+    "nominal:slew_setup_a_rise",
+    "nominal:slew_setup_a_fall",
 ]
 baseline = [
     "source_nominal:slew_data_rise",
@@ -1077,31 +1107,36 @@ baseline = [
     "source_nominal:slew_scan_rise",
     "source_nominal:slew_scan_fall",
     "source_nominal:slew_reset_fall",
+    "source_nominal:slew_setup_a_rise",
+    "source_nominal:slew_setup_a_fall",
 ]
 unit = "s"
 direction = "minimize"
 aggregation = "max"
 dimension = "response"
 normalization = "ratio"
+
+[task.evaluation.metrics.requirement]
 lower = 0.0
+rationale = "The declared ordered-event interval or crossing frequency has a nonnegative measurement domain, and its crossing must exist for a usable observation."
 
 [task.evaluation.scoring]
 method = "layout"
 area_metric = "functional_area"
-area_target = 175.5775
-rationale = "Scan flip-flop: clock-to-output delay 51%; output transition 17%; supply power 17%; area 15%. Each objective's weight is divided equally among its metrics."
+area_target = 100.0
+rationale = "The 100 um2 area goal rewards compact latch, clock and scan-multiplexer placement. Timing 45% and area 40% expose clock/internal-node routing cost, with 10% slew and 5% power. The 550 ps target is close to the slowest source path. Fixed setup/hold exercises establish correct capture, not a characterized minimum setup or hold time."
 
 [task.evaluation.scoring.weights]
-functional_area = 0.15
-propagation_delay = 0.51
-output_transition = 0.17
-supply = 0.17
+functional_area = 0.4
+propagation_delay = 0.45
+output_transition = 0.1
+supply = 0.05
 
 [task.evaluation.pre_layout]
-source_report_sha256 = "7c186efc01707e6576d7e22647bdb61c6ed569f153d08f49cbfed8c6f659cdfb"
+source_report_sha256 = "134505ad949e6884fc916494c291d60ef09ed321c20a6c91aa17279ec71fff54"
 
 [task.evaluation.pre_layout.backends]
-"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"ef9cb87fa27b849376472663b7362673979b89e012f161ba47bb5f6af6ede8eb\", \"compatibility\": null, \"execution_sha256\": \"5424b579002782bfddf0a729715b8fbf2a5f7f2b4cf14982d7616e352d5de9be\", \"image_id\": \"sha256:6562558774d43c085a289bbba696c55959eb8051a0996f96633451fbeb9c652d\", \"limits\": {\"cpus\": 4, \"memory_mb\": 4096, \"pids\": 256}, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"a340269fb13edfad479628bd59a0b72b878e648c0740e89671cd95b64adc03ef\", \"timeout_seconds\": 240.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}"
+"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"dfbdf2f93297bbe7d8b576fb988504bd0ecf85b93ef47c314a0f2c9c8830c3e7\", \"compatibility\": null, \"cpu_budget\": 8, \"execution_sha256\": \"495aa9623759f70228a236eb4825c2ae443ef6a741816d8cfc17d1830841dcef\", \"image_id\": \"sha256:060fee64f9f6e71a647e5e958b788d723c9d51d2928ff93e6a295db1959bc37f\", \"limits\": {\"cpus\": 8, \"memory_mb\": 4096, \"pids\": 256}, \"max_parallel_jobs\": 8, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"4c7a26df97245613922e47bdae060a40d6cb59f9c243e22d8964f97209f47011\", \"thread_environment\": {\"OMP_NUM_THREADS\": \"1\", \"OMP_THREAD_LIMIT\": \"1\"}, \"threads\": 1, \"timeout_seconds\": 240.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}"
 
 [task.evaluation.pre_layout.jobs.source_nominal]
 operation = "circuit.simulate"
@@ -1113,34 +1148,40 @@ dut = "input:netlist"
 [task.evaluation.pre_layout.jobs.source_nominal.outputs]
 waveform = "ngspice-raw"
 
+[task.evaluation.pre_layout.jobs.source_nominal.parameters.exports]
+waveform = "waveform.raw"
+
 [task.evaluation.pre_layout.jobs.source_nominal.parameters.measurements]
+delay_data_fall = "s"
+delay_data_rise = "s"
+delay_reset_fall = "s"
+delay_scan_fall = "s"
+delay_scan_rise = "s"
+delay_setup_a_fall = "s"
+delay_setup_a_rise = "s"
+high119 = "V"
+high39 = "V"
+high79 = "V"
+low139 = "V"
 low19 = "V"
 low59 = "V"
+power_w = "W"
 reset89 = "V"
 reset99 = "V"
-low139 = "V"
-high39 = "V"
-high79 = "V"
-high119 = "V"
-power_w = "W"
-delay_data_rise = "s"
-slew_data_rise = "s"
-delay_data_fall = "s"
+setup_fall_q = "V"
+setup_rise_q = "V"
 slew_data_fall = "s"
-delay_scan_rise = "s"
-slew_scan_rise = "s"
-delay_scan_fall = "s"
-slew_scan_fall = "s"
-delay_reset_fall = "s"
+slew_data_rise = "s"
 slew_reset_fall = "s"
+slew_scan_fall = "s"
+slew_scan_rise = "s"
+slew_setup_a_fall = "s"
+slew_setup_a_rise = "s"
 
 [task.evaluation.pre_layout.jobs.source_nominal.parameters.values]
 
-[task.evaluation.pre_layout.jobs.source_nominal.parameters.exports]
-waveform = "waveform.raw"
-
 [task.evaluation.pre_layout.jobs.source_nominal.input_sha256]
-deck = "43d1b9312f6024b9fe2f2c55e841d741e915254ffa5d9a1e476ab406323c46dc"
+deck = "85002e6ae68a6b3b94f271f3231beab8f86542a4543d047fe1e0c5f62997949f"
 dut = "659e961943b07c6a7665d4e640a037508fc255ce66752c02ca5de94ae1d07e58"
 
 [task.evaluation.pre_layout.jobs.source_nominal.measurements.delay_data_fall]
@@ -1163,6 +1204,14 @@ unit = "s"
 value = 5.49924e-10
 unit = "s"
 
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.delay_setup_a_fall]
+value = 5.492423e-10
+unit = "s"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.delay_setup_a_rise]
+value = 5.499524e-10
+unit = "s"
+
 [task.evaluation.pre_layout.jobs.source_nominal.measurements.high119]
 value = 3.3
 unit = "V"
@@ -1188,7 +1237,7 @@ value = 3.66929e-08
 unit = "V"
 
 [task.evaluation.pre_layout.jobs.source_nominal.measurements.power_w]
-value = 4.187209e-05
+value = 3.956966e-05
 unit = "W"
 
 [task.evaluation.pre_layout.jobs.source_nominal.measurements.reset89]
@@ -1199,6 +1248,14 @@ unit = "V"
 value = 7.300858e-09
 unit = "V"
 
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.setup_fall_q]
+value = 0.0005908675
+unit = "V"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.setup_rise_q]
+value = 3.292228
+unit = "V"
+
 [task.evaluation.pre_layout.jobs.source_nominal.measurements.slew_data_fall]
 value = 2.787912e-10
 unit = "s"
@@ -1219,11 +1276,22 @@ unit = "s"
 value = 3.358867e-10
 unit = "s"
 
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.slew_setup_a_fall]
+value = 2.787912e-10
+unit = "s"
+
+[task.evaluation.pre_layout.jobs.source_nominal.measurements.slew_setup_a_rise]
+value = 3.358857e-10
+unit = "s"
+
+[task.evaluation.pre_layout.jobs.source_nominal.output_sha256]
+waveform = "86580f93eed2615372bb626bef61c7e4a88d5c355086b0579f97326387c8e71b"
+
 [toolchain.backends.artifact]
 type = "klayout-docker"
 
 [toolchain.backends.artifact.settings]
-image = "iclayout-bench-tools:local"
+image = "iclayout-eda-open:local"
 check = "artifact"
 timeout_seconds = 180
 
@@ -1231,7 +1299,7 @@ timeout_seconds = 180
 type = "klayout-docker"
 
 [toolchain.backends.drc.settings]
-image = "iclayout-bench-tools:local"
+image = "iclayout-eda-open:local"
 check = "drc"
 timeout_seconds = 180
 support = "build/support/gf180-physical"
@@ -1244,7 +1312,7 @@ support = "physical"
 type = "klayout-docker"
 
 [toolchain.backends.lvs.settings]
-image = "iclayout-bench-tools:local"
+image = "iclayout-eda-open:local"
 check = "lvs"
 timeout_seconds = 180
 support = "build/support/gf180-physical"
@@ -1257,14 +1325,14 @@ support = "physical"
 type = "klayout-geometry-docker"
 
 [toolchain.backends.geometry.settings]
-image = "iclayout-bench-tools:local"
+image = "iclayout-eda-open:local"
 timeout_seconds = 180
 
 [toolchain.backends.rc]
 type = "magic-rc-docker"
 
 [toolchain.backends.rc.settings]
-image = "iclayout-bench-tools:local"
+image = "iclayout-eda-open:local"
 support = "build/support/gf180-magic"
 technology = "gf180mcuD.tech"
 tech_name = "gf180mcuD"
@@ -1281,7 +1349,10 @@ support = "magic"
 type = "ngspice-docker"
 
 [toolchain.backends.ngspice.settings]
-image = "iclayout-bench-tools:local"
+max_parallel_jobs = 8
+threads = 1
+cpu_budget = 8
+image = "iclayout-eda-open:local"
 support = "build/support/gf180-models"
 timeout_seconds = 240
 

tasks/gf180mcuD/voidwalkers-scandff/cases/scan_dff/materials/testbench.spice

@@ -7,12 +7,13 @@ VDD vdd 0 3.3
 VCLK clk 0 PULSE(0 3.3 10n .1n .1n 10n 20n)
 VRN rn 0 PWL(0 0 5n 0 5.1n 3.3 85n 3.3 85.1n 0 95n 0 95.1n 3.3)
 VS s 0 PWL(0 0 40n 0 40.1n 3.3 80n 3.3 80.1n 0)
-VA a 0 PWL(0 0 20n 0 20.1n 3.3 60n 3.3 60.1n 0 100n 0 100.1n 3.3 120n 3.3 120.1n 0)
+VA a 0 PWL(0 0 20n 0 20.1n 3.3 60n 3.3 60.1n 0 100n 0 100.1n 3.3 120n 3.3 120.1n 0 149.2n 0 149.3n 3.3 150.2n 3.3 150.3n 0 169.1n 0 169.2n 3.3 170.1n 3.3 170.2n 0 180.1n 0 180.2n 3.3 189.2n 3.3 189.3n 0 190.2n 0 190.3n 3.3 200n 3.3)
 VB b 0 PWL(0 0 60n 0 60.1n 3.3)
 CLOAD q 0 50f
 XDUT s vdd q b clk a rn 0 gf180mcu_voidwalkers_sc_sdffrnq_4
 .control
-tran .01n 140n
+save i(vdd) v(clk) v(q) v(rn)
+tran .01n 200n
 meas tran low19 find v(q) at=19n
 meas tran high39 find v(q) at=39n
 meas tran low59 find v(q) at=59n
@@ -21,6 +22,8 @@ meas tran reset89 find v(q) at=89n
 meas tran reset99 find v(q) at=99n
 meas tran high119 find v(q) at=119n
 meas tran low139 find v(q) at=139n
+meas tran setup_rise_q find v(q) at=151.5n
+meas tran setup_fall_q find v(q) at=191.5n
 * Measure effective CLK->Q arcs for functional and scan data, plus asynchronous reset.
 meas tran delay_data_rise trig v(clk) val=1.65 rise=1 td=100n targ v(q) val=1.65 rise=1 td=100n
 meas tran slew_data_rise trig v(q) val=0.66 rise=1 td=100n targ v(q) val=2.64 rise=1 td=100n
@@ -32,8 +35,13 @@ meas tran delay_scan_fall trig v(clk) val=1.65 rise=1 td=40n targ v(q) val=1.65
 meas tran slew_scan_fall trig v(q) val=2.64 fall=1 td=40n targ v(q) val=0.66 fall=1 td=40n
 meas tran delay_reset_fall trig v(rn) val=1.65 fall=1 td=80n targ v(q) val=1.65 fall=1 td=80n
 meas tran slew_reset_fall trig v(q) val=2.64 fall=1 td=80n targ v(q) val=0.66 fall=1 td=80n
+* Exercise 0.8 ns A setup and 0.2 ns post-edge A hold around rising clock edges.
+meas tran delay_setup_a_rise trig v(clk) val=1.65 rise=1 td=150n targ v(q) val=1.65 rise=1 td=150n
+meas tran slew_setup_a_rise trig v(q) val=0.66 rise=1 td=150n targ v(q) val=2.64 rise=1 td=150n
+meas tran delay_setup_a_fall trig v(clk) val=1.65 rise=1 td=190n targ v(q) val=1.65 fall=1 td=190n
+meas tran slew_setup_a_fall trig v(q) val=2.64 fall=1 td=190n targ v(q) val=0.66 fall=1 td=190n
 let pwr=-3.3*i(vdd)
-meas tran power_w avg pwr from=20n to=140n
+meas tran power_w avg pwr from=20n to=200n
 write waveform.raw
 quit
 .endc

tasks/gf180mcuD/voidwalkers-scandff/cases/scan_dff/problem.md

@@ -6,29 +6,30 @@ Implement `gf180mcu_voidwalkers_sc_sdffrnq_4` in GF180MCU variant D while preser
 
 ## Inputs and Interface
 
-The delivered files are `materials/circuit.spice` (authoritative circuit), `materials/testbench.spice` (stimuli and measurements), and this problem. Runtime task metadata supplies the same frozen constraints, evaluation conditions and output declaration.
+Inputs are this description, `materials/circuit.spice` (the authoritative circuit) and `materials/testbench.spice` (stimuli and measurements). Runtime task metadata supplies consistent frozen constraints, evaluation conditions and output declarations.
 
 Ordered subcircuit and GDS interface: `S, VDD, Q, B, CLK, A, RN, VSS`.
 VDD/VSS: supply/return; A: functional data; B: scan data; S: select (0=A, 1=B); CLK: rising-edge clock; RN: active-low asynchronous reset; Q: stored output.
 
-Preserve topology and total device width, channel length, multiplicity, resistor dimensions and body connections. Equivalent hierarchy, diffusion sharing and parallel-finger implementations are allowed when they pass connectivity and electrical checks. No source-model replacement, idealized internal device or changed device sizing is permitted. A dummy device remains part of the circuit even when its terminals are tied together.
+Preserve topology, total device widths, channel lengths, multiplicities, resistor dimensions and body connections. Equivalent hierarchy, diffusion sharing and parallel fingers are allowed when connectivity and electrical checks pass; preserve source models and dimensions without idealizing internal devices. Retain dummy devices even when all their terminals are shorted.
 
 ## Operating Conditions
 
-Use 3.3 V and 27 C, a 50 fF Q load and the same 50 MHz clock throughout (first rise 10 ns, rise/fall 0.1 ns, high time 10 ns). Select A initially; select B at 40.1 ns; return to A at 80.1 ns. A rises at 20.1 ns, falls at 60.1 ns, rises at 100.1 ns and falls at 120.1 ns. B rises at 60.1 ns. RN starts low, releases at 5.1 ns, asserts at 85.1 ns and releases at 95.1 ns. All data/reset transitions take 0.1 ns, as specified in the testbench. Simulate through 140 ns.
+Use 3.3 V and 27 C, a 50 fF Q load and the same 50 MHz clock throughout (first rise 10 ns, rise/fall 0.1 ns, high time 10 ns). Select A initially; select B at 40.1 ns; return to A at 80.1 ns. A rises at 20.1 ns, falls at 60.1 ns, rises at 100.1 ns and falls at 120.1 ns. B rises at 60.1 ns. RN starts low, releases at 5.1 ns, asserts at 85.1 ns and releases at 95.1 ns. All data/reset transitions take 0.1 ns, as specified in the testbench.
 
-Use the reviewed typical primitive models with statistical variation disabled. Numerical parameters in the runtime simulation jobs supply the testbench's `parameters.spice`. Follow the delivered testbench for interpolation and detailed PWL definitions. This is a nominal compact-model task; temperature/process corners, mismatch yield, noise, RF/EM and full-chip density closure are outside its qualification scope.
+The testbench also checks two late-cycle A-to-Q cases at the nominal 50 MHz clock and 50 fF load. At each measured rising edge, A crosses 1.65 V 0.8 ns before the edge and makes the opposite transition 0.2 ns after it, exercising setup and hold behavior. It checks Q after the capture edge and source-pairs the corresponding clock-to-Q delay and output slew. These fixed setup/hold exercises do not measure minimum setup/hold time or establish timing signoff across corners. Simulate through 200 ns.
+
+Use reviewed typical primitive models with statistical variation disabled. Numerical parameters from runtime simulation jobs generate the testbench's `parameters.spice`; interpolation and detailed PWL follow the delivered deck. Scope is limited to nominal compact-model conditions, excluding temperature/process corners, mismatch yield, noise, RF/EM and full-chip density closure.
 
 ## Physical Requirements
 
-Submit a nonempty GDS with top cell `gf180mcu_voidwalkers_sc_sdffrnq_4` and at most 10485760 bytes. Its functional bounding box must not exceed 80 by 80 um. All relevant device and routing polygons contribute, including implant/well, passive markers, contacts, vias and dummy routing. The complete layer/datatype set is:
+Submit a nonempty GDS with top cell `gf180mcu_voidwalkers_sc_sdffrnq_4`, no larger than 10485760 bytes. The functional bounding box must fit within 80 × 80 um and includes relevant device and routing polygons, implants/wells, passive markers, contacts, vias and dummy routing. The complete layer/datatype set is:
 
 `[[5,0],[11,17],[11,39],[12,0],[13,17],[21,0],[22,0],[22,4],[24,0],[24,5],[30,0],[30,4],[31,0],[32,0],[33,0],[34,0],[34,3],[34,4],[34,5],[35,0],[36,0],[36,3],[36,4],[36,5],[37,0],[38,0],[40,0],[41,0],[42,0],[42,3],[42,4],[42,5],[46,0],[46,3],[46,4],[46,5],[49,0],[53,0],[53,3],[53,4],[53,5],[55,0],[62,0],[75,0],[80,5],[81,0],[81,3],[81,4],[81,5],[82,0],[86,17],[88,17],[96,1],[100,5],[100,7],[100,8],[108,5],[110,5],[110,11],[110,12],[110,13],[110,14],[110,15],[110,16],[111,5],[112,1],[115,5],[116,5],[117,5],[117,10],[118,5],[119,5],[122,5],[123,5],[124,5],[125,5],[127,5],[128,17],[137,5],[151,5],[152,5],[153,51],[166,5],[167,5],[173,5],[178,0],[183,0],[184,0],[185,0],[204,0],[210,0],[220,0],[226,0],[227,0],[241,0]]`.
 
-Text and nonfunctional boundary layers 0/0 and 63/0 are excluded from area. Functional geometry may not be hidden on annotation layers. Pass the pinned GF180 D FEOL, BEOL, connectivity, off-grid and antenna checks without marker waivers. The stack is five metals with 1.1 um top metal and the 1 kOhm/square high-resistance poly option. Chip-level density and seal-ring closure are integration responsibilities outside this standalone block.
-
-LVS checks device topology, dimensions, body connections and every named top-level pin (case insensitive). Supply and substrate/well contacts must be physical. Distinct electrical nets must not be joined by touching silicided diffusion. After validity and geometry gates, extract the submitted candidate's devices and distributed interconnect resistance and capacitance. Simulations use that extracted circuit. The substrate compact-model boundary is one equipotential bulk domain with explicit well/body contacts; this does not model a distributed silicon substrate network. Unreliable extraction, absent named ports or incomplete measurements cannot establish success.
+Area excludes text and nonfunctional boundary layers 0/0 and 63/0; functional geometry must remain on functional layers. Pass the fixed GF180 D FEOL, BEOL, connectivity, grid and antenna checks without waivers. Use five metal layers, the 1.1 um top-metal option and the 1 kOhm/square high-resistance poly option. Chip density and seal-ring closure belong to higher-level integration.
 
+LVS checks topology, dimensions, body terminals and all named top-level ports, case-insensitively. Physically implement supply and substrate/well contacts; do not short different nets through adjoining silicided diffusion. After validity and geometric checks pass, extract candidate devices and distributed interconnect RC, then simulate the extracted circuit. The substrate model is one equipotential body region with explicit well/body contacts, rather than a distributed silicon-substrate network. Unreliable extraction, missing ports or incomplete measurements cannot establish success.
 
 The standard-cell functional frame has fixed height 6.35 um and width on a 0.005 um grid. Coordinates below are relative to its lower-left functional bound; global translation remains allowed. Supply rails must be continuous on metal1 and bound by LVS to the named supply.
 
@@ -37,80 +38,55 @@ The standard-cell functional frame has fixed height 6.35 um and width on a 0.005
 
 ## Electrical Requirements and Scoring
 
-Physical checks and declared functional bounds remain mandatory. Quality has no
-fixed allowed-degradation threshold. Each `source_*` job simulates the declared
-source circuit with exactly the same testbench, model resources, parameters,
-load and measurement window as its paired extracted-candidate job. A source
-observation is the 100-point electrical baseline; it is independent of the
-submitted GDS. All individual pairs are retained in the evaluation report.
-
-For a post-layout observation x and its source observation b:
-
-- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,
-  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;
-  s is a normalization floor, not an allowed degradation or pass threshold.
-- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.
-- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and
-  zero-valued operating points are never divided directly.
-
-Scoring uses `layout`. A metric uses its worst paired quality q. The score is
-S = 100 * product(q_i ** w_i), including area quality
-q_area = area_reference / candidate_functional_area. The weights below sum to
-one. Dimensions describe measurements but do not determine their weights.
-Physical or functional rejection scores zero; missing or invalid measurements
-produce an unknown score, including measurements with zero weight.
-Source-equivalent performance at the area reference scores 100; improvements
-can exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.
-
-| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale |
+Physical checks and the declared functional bounds must pass. Quality scoring imposes no fixed degradation allowance. Each `source_*` job and its corresponding candidate extracted circuit use exactly the same testbench, model resources, parameters, loads and measurement windows. Independent source observations remain required evidence; the quality targets below set the scoring anchors without depending on the submitted GDS. Reports retain every source/candidate pair.
+
+Let x be the post-layout measurement and b the declared quality target, or the same-condition source measurement when no target is declared:
+
+- Ratio normalization: maximize with q = x/b and minimize with q = b/x. When a numerical scale s is declared, use (x+s)/(b+s) and its reciprocal, respectively. The scale handles zero values as a normalization floor; it is neither an allowed degradation nor an acceptance bound.
+- Amplitude in dB: maximize with q = 10^((x-b)/20) and minimize with its reciprocal.
+- Target normalization: q = 1/(1+abs(x-b)/s), where s is the declared physical scale. Signed or zero-valued operating points are not divided directly.
+
+Use `layout` scoring. Each metric takes its worst paired quality q, and the total score is S = 100 * product(q_i ** w_i), with area quality q_area = area_target / candidate_functional_area. The weights below sum to 1; metric dimensions describe measurements and do not determine weights. Physical or functional rejection scores zero; missing or invalid measurements leave the score unknown, and zero-weight observations must also be valid. Joint attainment of the electrical and area targets scores 100 points; better valid solutions may exceed 100. A feasible reference is allowed to score far below 100. Weights express quality tradeoffs rather than hard bounds.
+
+| Metric | Definition / observation | Unit | Quality normalization | Functional range | Scale |
 | --- | --- | --- | --- | --- | --- |
-| `low` | Q at 19, 59, 89, 99 and 139 ns; the 89 ns sample checks asynchronous reset before the next rising clock. | V | functional check | −∞ … 0.33 | — |
-| `high` | Q at 39, 79 and 119 ns, exercising functional and scan data. | V | functional check | 2.97 … +∞ | — |
-| `propagation_delay` | Worst paired quality over: delay_data_rise, delay_data_fall, delay_scan_rise, delay_scan_fall, delay_reset_fall. | s | minimize / ratio | 0 … +∞ | — |
-| `output_transition` | Worst paired quality over: slew_data_rise, slew_data_fall, slew_scan_rise, slew_scan_fall, slew_reset_fall. | s | minimize / ratio | 0 … +∞ | — |
-| `supply` | Average VDD power over 20–140 ns. | W | minimize / ratio | 0 … +∞ | 1e-12 |
+| `low` | Q at 19, 59, 89, 99 and 139 ns plus the 191.5 ns near-edge capture/hold check; the 89 ns sample checks asynchronous reset before the next rising clock. | V | functional check | −∞ … 0.33 | — |
+| `high` | Q at 39, 79 and 119 ns plus the 151.5 ns near-edge capture/hold check, exercising functional and scan data. | V | functional check | 2.97 … +∞ | — |
+| `propagation_delay` | Worst paired quality over the five existing data/scan/reset arcs and two additional A-data clock-to-Q arcs with 0.8 ns setup. | s | minimize / ratio | 0 … +∞ | — |
+| `output_transition` | Worst paired quality over the five existing data/scan/reset arcs and the two additional A-data output-slew arcs with 0.8 ns setup. | s | minimize / ratio | 0 … +∞ | — |
+| `supply` | Average VDD power over 20–200 ns, including the late-cycle timing stimuli. | W | minimize / ratio | 0 … +∞ | 1e-12 |
 
-Area reference: **175.5775 um2**. Complete functional bounding rectangle of the declared standard-cell reference GDS: 27.65 by 6.35 um = 175.577 um2. Reference SHA-256: ffd6654d5505bf6340acbb3061ad81fab36951badda45b3bd3a8448be0fa00ab. This footprint includes the maintained explicit taps and routing.
+The area scoring target is **100 um2**. It is a continuous quality goal, not a hard limit, process minimum or a percentage of the current feasibility witness.
 
-The capability coefficient remains **5**; it is independent of
-the reference-relative task score.
+- `propagation_delay`: **5.5e-10 s**. Keep all declared clock/data/reset-to-Q timing observations within 550 ps at 50 fF, including the late-cycle capture exercises.
 
-### Standard-cell design guidance
+The 100 um2 area goal rewards compact latch, clock and scan-multiplexer placement. Timing 45% and area 40% expose clock/internal-node routing cost, with 10% slew and 5% power. The 550 ps target is close to the slowest source path. Fixed setup/hold exercises establish correct capture, not a characterized minimum setup or hold time.
 
-Plan the device rows, power rails and signal access before routing. Represent
-pull-up and pull-down connectivity as transistor-edge graphs; explore compatible
-Euler trails and alternative orderings to share diffusion and reduce breaks.
-Choose among legal orderings using routing length, parasitic loading and signal
-access, rather than diffusion sharing alone. Preserve the fixed netlist sizes,
-models and connectivity; size optimization is outside this task.
+Quality targets do not impose additional functional cutoffs. Metrics without an explicit target retain their same-condition source anchors.
 
-Use the task's declared row height, grid and rail geometry. Keep local routes
-compact, leave signal pins accessible, and avoid consuming extra routing layers
-without benefit. Check DRC and named-port LVS, then extract the candidate and
-compare both transition directions and power with the source simulation. Iterate
-on measured parasitic effects rather than visual compactness alone. These are
-optional techniques, not a mandated algorithm or reference placement.
+The capability coefficient is **5**, independent of this task's reference-normalized score.
 
-Adapted from Xu et al., *Standard Cell Library Design and Optimization Methodology
-for ASAP7 PDK*, Sections 2–3 (https://arxiv.org/abs/1807.11396). Its FinFET sizing,
-track counts and process-specific dimensions do not apply to this task.
+### Standard-cell design guidance
 
+You may plan device rows, supply rails and signal access before routing. Represent pull-up/pull-down connections as transistor-edge graphs and explore compatible Euler paths and alternative orders to share diffusion and reduce breaks. Choose a legal arrangement considering routing length, parasitics and signal access. Keep fixed netlist sizes, models and connections; do not optimize sizing.
 
-### Score weights
+Use the declared row height, grid and supply-rail geometry. Keep local routing compact and signal pins accessible, avoiding routing layers with no benefit. Check DRC and named-port LVS, then extract the candidate and compare transitions in both directions and power against source simulation; iterate using parasitic measurements. These methods are optional and do not prescribe an algorithm or reference layout.
 
-Scan flip-flop: clock-to-output delay 51%; output transition 17%; supply power 17%; area 15%. Each objective's weight is divided equally among its metrics.
+These methods refer to Sections 2–3 of Xu et al., *Standard Cell Library Design and Optimization Methodology for ASAP7 PDK* (https://arxiv.org/abs/1807.11396). Its FinFET sizing, track count and process-specific dimensions do not apply to this task.
+
+### Score weights
 
 | Metric | Weight |
 | --- | ---: |
-| `functional_area` | 0.15 |
-| `propagation_delay` | 0.510000000000 |
-| `output_transition` | 0.170000000000 |
-| `supply` | 0.170000000000 |
+| `functional_area` | 0.4 |
+| `propagation_delay` | 0.45 |
+| `output_transition` | 0.1 |
+| `supply` | 0.05 |
 
 ## Tools and Submission
 
 Solve budget: **3 hours**.
 
-Use runtime task, resource and harness discovery to locate the delivered inputs and reviewed GF180 resources. Trusted feedback runs the declared physical and post-layout evaluation; source-only simulation is useful for design but is not acceptance. Write the final GDS to `/workspace/output/final.gds` and explicitly submit it using the harness submission interface. A generated file or successful standalone simulation alone does not complete the task.
+Discover inputs and reviewed GF180 resources through the runtime task, resource and submission protocols. Trusted feedback executes the declared physical and post-layout evaluation; source simulation only assists design. Write the final GDS to `/workspace/output/final.gds` and explicitly submit through the runtime protocol. File generation or a successful standalone simulation alone does not complete the task.
 
-Use a GDS database unit of 0.001 um, as required by the GF180MCU DRC deck.
+Use a GDS database unit of 0.001 um as required by GF180MCU DRC rules.

tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/comparator/case.toml

@@ -1,15 +1,15 @@
-in_core = false
 kind = "layout_case"
 id = "module_3_8_bit_SAR_ADC.part_5_analog_layout.comparator"
 title = "IHP AnalogAcademy comparator"
 status = "qualified"
+in_core = false
 
 [[assets]]
 path = "materials/schematic.svg"
 role = "schematic"
 visibility = "maintainer"
 format = "svg"
-sha256 = "6555f7c6a8b7a3330ccb93621458f99753c3ceadd7acab40fb9610bd64edf3c1"
+sha256 = "cfc9095bb59e3408eab339880f64e488005f2861c257ea6ee942ef46a0aa85de"
 
 [[assets]]
 path = "reference/DIFF_COMPARATOR.gds"
@@ -27,24 +27,24 @@ environment = "ihp-sg13g2-comparator-rc-tt"
 
 [task.inputs.description]
 path = "problem.md"
-sha256 = "c15d95f6e71753ce74b456e4f0b8ff70ab3ebd15fb6b15f7bfe261f8358f653a"
 format = "text"
+sha256 = "2a80ec3a49eab643333d8121018e7228a1ba1dd2464a1370d8837611c7e88f3e"
 
 [task.inputs.netlist]
 path = "materials/circuit.cdl"
-sha256 = "0fe0279db5d2975dec32196670118a05d0dd9a240e7f70b642c94e0a7ec80a4c"
 format = "spice"
 subcircuit = "DIFF_COMPARATOR"
+sha256 = "0fe0279db5d2975dec32196670118a05d0dd9a240e7f70b642c94e0a7ec80a4c"
 
 [task.inputs.simulation]
 path = "materials/circuit.spice"
-sha256 = "daffa3508cb005a2a96651e48ec56909c94596208d48cbc099e24702f8f72221"
 format = "spice"
+sha256 = "daffa3508cb005a2a96651e48ec56909c94596208d48cbc099e24702f8f72221"
 
 [task.inputs.performance]
 path = "materials/testbench.spice"
-sha256 = "61d8165d7b359539cebe3a94815dcbd22cede35ca87c393e345832523f3c4c8e"
 format = "spice"
+sha256 = "61d8165d7b359539cebe3a94815dcbd22cede35ca87c393e345832523f3c4c8e"
 
 [task.constraints]
 quality = [
@@ -576,7 +576,10 @@ baseline = [
     "source_positive_5mv:delay_c09",
 ]
 normalization = "ratio"
+
+[task.evaluation.metrics.requirement]
 lower = 0
+rationale = "The observed frequency or ordered-event interval has a nonnegative measurement domain, and its required crossing must exist for a usable observation."
 
 [[task.evaluation.metrics]]
 id = "decision_margin"
@@ -618,7 +621,10 @@ observations = [
 unit = "V"
 direction = "maximize"
 aggregation = "min"
+
+[task.evaluation.metrics.requirement]
 lower = 1.0
+rationale = "The clocked comparator must hold the polarity-correct 1 V differential logic decision throughout every declared decision window, matching the decision threshold used for timing."
 
 [[task.evaluation.metrics]]
 id = "supply_power"
@@ -640,14 +646,17 @@ baseline = [
     "source_positive_5mv:supply_power",
 ]
 normalization = "ratio"
-lower = 0
 scale = 1e-12
 
+[task.evaluation.metrics.requirement]
+lower = 0
+rationale = "The declared powered circuit or driven switching network must consume nonnegative net supply/driver energy or quiescent current under the complete stated observation."
+
 [task.evaluation.pre_layout]
-source_report_sha256 = "3a8ba863ecaddad4b7a01a0ac94e32a8770b03b0d7aeda98f3fcf1f88c2e56f5"
+source_report_sha256 = "a394889677327cea33683d1a1d7656cb18c7cabc8363cc74d777e22d3f6f9afd"
 
 [task.evaluation.pre_layout.backends]
-"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"ef9cb87fa27b849376472663b7362673979b89e012f161ba47bb5f6af6ede8eb\", \"compatibility\": null, \"execution_sha256\": \"5424b579002782bfddf0a729715b8fbf2a5f7f2b4cf14982d7616e352d5de9be\", \"image_id\": \"sha256:6562558774d43c085a289bbba696c55959eb8051a0996f96633451fbeb9c652d\", \"limits\": {\"cpus\": 4, \"memory_mb\": 4096, \"pids\": 256}, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"30c5b5b710850a636e75d962f27982d72b8b68307dd77a34df044e2a3b07d34b\", \"timeout_seconds\": 600.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}"
+"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"dfbdf2f93297bbe7d8b576fb988504bd0ecf85b93ef47c314a0f2c9c8830c3e7\", \"compatibility\": null, \"cpu_budget\": 8, \"execution_sha256\": \"495aa9623759f70228a236eb4825c2ae443ef6a741816d8cfc17d1830841dcef\", \"image_id\": \"sha256:060fee64f9f6e71a647e5e958b788d723c9d51d2928ff93e6a295db1959bc37f\", \"limits\": {\"cpus\": 8, \"memory_mb\": 4096, \"pids\": 256}, \"max_parallel_jobs\": 8, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"dce84f0cb44c7192511c807348bb3852682b1b4ec71ee94055876cb79ccbbdb1\", \"thread_environment\": {\"OMP_NUM_THREADS\": \"1\", \"OMP_THREAD_LIMIT\": \"1\"}, \"threads\": 1, \"timeout_seconds\": 600.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}"
 
 [task.evaluation.pre_layout.jobs.source_negative_5mv]
 operation = "circuit.simulate"
@@ -757,6 +766,9 @@ unit = "V"
 value = 5.722953e-05
 unit = "W"
 
+[task.evaluation.pre_layout.jobs.source_negative_5mv.output_sha256]
+waveform = "2e45ec295299cba6a91602496fcf77c74a8f04ee22222d58138d5d8d6c1198b5"
+
 [task.evaluation.pre_layout.jobs.source_negative_3mv]
 operation = "circuit.simulate"
 
@@ -865,6 +877,9 @@ unit = "V"
 value = 5.815247e-05
 unit = "W"
 
+[task.evaluation.pre_layout.jobs.source_negative_3mv.output_sha256]
+waveform = "e5129f1f45095560be335028e88030799611d03e1be05e2264b6a4972b92b76b"
+
 [task.evaluation.pre_layout.jobs.source_positive_3mv]
 operation = "circuit.simulate"
 
@@ -973,6 +988,9 @@ unit = "V"
 value = 5.782437e-05
 unit = "W"
 
+[task.evaluation.pre_layout.jobs.source_positive_3mv.output_sha256]
+waveform = "a73ee16b6882e0ee905cd0fe3e2cb743b88f70a944da2030e20d47b3c5cd2a01"
+
 [task.evaluation.pre_layout.jobs.source_positive_5mv]
 operation = "circuit.simulate"
 
@@ -1081,11 +1099,14 @@ unit = "V"
 value = 5.667991e-05
 unit = "W"
 
+[task.evaluation.pre_layout.jobs.source_positive_5mv.output_sha256]
+waveform = "96f7d3ea97f82f75fc54b1bf367873f9f7fce58dab855672c5b5a5c60db8836f"
+
 [toolchain.backends.artifact]
 type = "klayout-docker"
 
 [toolchain.backends.artifact.settings]
-image = "iclayout-bench-tools:local"
+image = "iclayout-eda-open:local"
 check = "artifact"
 
 [toolchain.backends.drc]
@@ -1095,7 +1116,7 @@ type = "klayout-docker"
 support = "klayout"
 
 [toolchain.backends.drc.settings]
-image = "iclayout-bench-tools:local"
+image = "iclayout-eda-open:local"
 check = "drc"
 support = "build/support/comparator-klayout"
 profile = "drc-upstream.json"
@@ -1108,7 +1129,7 @@ type = "klayout-docker"
 support = "klayout"
 
 [toolchain.backends.lvs.settings]
-image = "iclayout-bench-tools:local"
+image = "iclayout-eda-open:local"
 check = "lvs"
 support = "build/support/comparator-klayout"
 profile = "lvs-upstream.json"
@@ -1118,7 +1139,7 @@ timeout_seconds = 600
 type = "klayout-geometry-docker"
 
 [toolchain.backends.geometry.settings]
-image = "iclayout-bench-tools:local"
+image = "iclayout-eda-open:local"
 timeout_seconds = 120
 
 [toolchain.backends.rc]
@@ -1128,7 +1149,7 @@ type = "magic-rc-docker"
 support = "magic"
 
 [toolchain.backends.rc.settings]
-image = "iclayout-bench-tools:local"
+image = "iclayout-eda-open:local"
 support = "build/support/comparator-magic"
 technology = "magic/ihp-sg13g2.tech"
 tech_name = "ihp-sg13g2"
@@ -1143,7 +1164,10 @@ type = "ngspice-docker"
 support = "analog-models"
 
 [toolchain.backends.simulation.settings]
-image = "iclayout-bench-tools:local"
+max_parallel_jobs = 8
+threads = 1
+cpu_budget = 8
+image = "iclayout-eda-open:local"
 support = "build/support/comparator-analog-models"
 timeout_seconds = 600
 

tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/comparator/problem.md

@@ -10,9 +10,7 @@ meet the clocked decision requirements after candidate-derived RC extraction.
 
 ## Inputs and Interface
 
-In addition to this problem, the solver receives the following declared
-materials. The structured constraints
-and evaluation plan are also available at runtime through `/protocol/task.json`.
+In addition to this description, the solver receives the following declared materials. The runtime `/protocol/task.json` also supplies structured constraints and the evaluation plan.
 
 | Input | Purpose |
 |---|---|
@@ -66,8 +64,7 @@ current `lvs-upstream.json` profile and strict named-port matching against
 `materials/circuit.cdl`; port names are matched case-insensitively, while every
 declared port must remain on its own conductor with the declared connectivity.
 
-The functional outline is the recursive bounding box of polygons on these
-SG13G2 datatype-0 layers, including child cells and the complete routing stack:
+The functional outline is the recursive bounding box of polygons on the following SG13G2 datatype-0 layers, including child cells and every routing layer:
 
 `1, 3, 5, 6, 7, 8, 10, 11, 13, 14, 19, 24, 26, 28, 29, 30, 31, 32, 33, 35, 36, 40, 44, 46, 49, 50, 51, 52, 53, 55, 58, 66, 67, 90, 101, 111, 125, 126, 128, 129, 133, 134, 139, 152`.
 
@@ -88,57 +85,31 @@ extraction choice.
 
 ## Electrical Requirements and Scoring
 
-Physical checks and declared functional bounds remain mandatory. Quality has no
-fixed allowed-degradation threshold. Each `source_*` job simulates the declared
-source circuit with exactly the same testbench, model resources, parameters,
-load and measurement window as its paired extracted-candidate job. A source
-observation is the 100-point electrical baseline; it is independent of the
-submitted GDS. All individual pairs are retained in the evaluation report.
-
-For a post-layout observation x and its source observation b:
-
-- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,
-  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;
-  s is a normalization floor, not an allowed degradation or pass threshold.
-- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.
-- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and
-  zero-valued operating points are never divided directly.
-
-Scoring uses `layout`. A metric uses its worst paired quality q. The score is
-S = 100 * product(q_i ** w_i), including area quality
-q_area = area_reference / candidate_functional_area. The weights below sum to
-one. Dimensions describe measurements but do not determine their weights.
-Physical or functional rejection scores zero; missing or invalid measurements
-produce an unknown score, including measurements with zero weight.
-Source-equivalent performance at the area reference scores 100; improvements
-can exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.
-
-Measurement definitions below use the supplied SPICE node/source names.
-`v(n)` is node voltage and `i(V)` is current into a voltage source; delivered
-power therefore uses a minus sign. `db(z)=20*log10(abs(z))`, `mag/abs`
-denote magnitude, and `cph` is continuous phase in radians. `find`, `when`,
-`from/to`, and `rise/fall` retain the deck's interpolation, window and
-crossing conventions; SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/
-milli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv`
-mean the stated window average, extrema and sampled derivative. All
-declared conditions are measured separately and paired with the same
-source condition; a group uses its worst paired quality.
-
-| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | Dimension |
+Physical checks and the declared functional bounds must pass. Quality scoring imposes no fixed degradation allowance. Each `source_*` job and its corresponding candidate extracted circuit use exactly the same testbench, model resources, parameters, loads and measurement windows. Independent source observations define the 100-point electrical baseline without depending on the submitted GDS; reports retain every paired result.
+
+Let x be the post-layout measurement and b the source-circuit measurement under the same conditions:
+
+- Ratio normalization: maximize with q = x/b and minimize with q = b/x. When a numerical scale s is declared, use (x+s)/(b+s) and its reciprocal, respectively. The scale handles zero values as a normalization floor; it is neither an allowed degradation nor an acceptance bound.
+- Amplitude in dB: maximize with q = 10^((x-b)/20) and minimize with its reciprocal.
+- Target normalization: q = 1/(1+abs(x-b)/s), where s is the declared physical scale. Signed or zero-valued operating points are not divided directly.
+
+Use `layout` scoring. Each metric takes its worst paired quality q, and the total score is S = 100 * product(q_i ** w_i), with area quality q_area = area_reference / candidate_functional_area. The weights below sum to 1; metric dimensions describe measurements and do not determine weights. Physical or functional rejection scores zero; missing or invalid measurements leave the score unknown, and zero-weight observations must also be valid. Matching source-circuit performance at the reference area scores 100 points; better valid solutions may exceed 100. Weights express quality tradeoffs rather than hard bounds.
+
+The measurements below use the supplied SPICE node and source names. `v(n)` is a node voltage; `i(V)` is current flowing into a voltage source, so delivered power uses a negative sign. `db(z)=20*log10(abs(z))`; `mag/abs` denote magnitude, and `cph` denotes continuous phase in radians. `find`, `when`, `from/to` and `rise/fall` follow the deck's interpolation, window and crossing conventions. SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/milli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv` represent window averages, extrema and sampled derivatives. Measure each operating condition independently, pair it with the source result under that condition, and take the worst paired quality within each metric group.
+
+| Metric | Definition / observation | Unit | Quality normalization | Functional range | Scale | Dimension |
 | --- | --- | --- | --- | --- | --- | --- |
 | `worst_delay` | Clock falling through 0.6 V to polarity-correct output difference reaching 1 V in cycles 2–9 (trigger delays 20–90 ns; target search starts 5.75 ns later). Every cycle and input condition is paired; the worst quality is scored. | s | minimize / ratio | 0 … +∞ | — | response |
 | `decision_margin` | Minimum polarity*(V(OUTP)-V(OUTM)) in each 1 ns decision window, 28.75–29.75 ns through 98.75–99.75 ns; all eight cycles and four signed input conditions must pass. | V | functional check | 1.0 … +∞ | — | functional check |
 | `supply_power` | Mean delivered VDD power, -V(VDD)*I(VDD), over 20–100 ns, independently for each signed input condition. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |
 
-Area reference: **502.96 um2**. 24 expanded device instances; sum of device/contact envelopes 306.3377 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.
-
-The capability coefficient remains **6**; it is independent of
-the reference-relative task score.
+Area reference: **502.96 um2**. The expanded circuit has 24 device instances, a sum of device/contact envelopes 306.3377 um2, a one-sided envelope margin of 0.6 um, a routing allowance of 50%, and a total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across both sides, and the envelope sum is displayed to four decimal places. MOS/passive envelopes use W/L (or resistor dimensions) and multiplicity, including explicit contacts and HBT emitter/contact envelopes. This is a frozen engineering estimate, not a process minimum or a proven achievable area.
 
+The capability coefficient is **6**, independent of this task's reference-normalized score.
 
 ### Score weights
 
-Clocked comparators: decision delay 71.1%; supply power 18.9%; area 10%. Each objective's weight is divided equally among its metrics.
+Clocked comparator: decision delay 71.1%, supply power 18.9%, area 10%; each objective weight is divided equally among its metrics.
 
 | Metric | Weight |
 | --- | ---: |
@@ -164,7 +135,4 @@ netlist produced by candidate-derived RC extraction. If the harness declares
 `process-feedback`, the optional command is
 `python -I /protocol/process_check.py`; the final evaluation remains independent.
 
-Write the result to `/workspace/output/final.gds`, then run
-`python -I /protocol/submit.py` and wait for the submission receipt. Solver
-netlists, waveforms, and measurements are not accepted as substitutes for the
-independent evaluator inputs.
+Write the result to `/workspace/output/final.gds`, run `python -I /protocol/submit.py` and wait for a submission receipt. Solver netlists, waveforms and measurements cannot replace independent evaluator inputs.

tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/full_OTA/case.toml

@@ -1,15 +1,15 @@
-in_core = false
 kind = "layout_case"
 id = "module_1_bandgap_reference.part_3_layout.OTA_layout.full_OTA"
 title = "IHP AnalogAcademy full_OTA"
 status = "qualified"
+in_core = false
 
 [[assets]]
 path = "materials/schematic.svg"
 role = "schematic"
 visibility = "maintainer"
 format = "svg"
-sha256 = "d02c9549e1d7ef313f774236268cc2f80b6efb6d7c764002fe118bd0a651f70f"
+sha256 = "d0ffea6b17b397105057f93491c5f44dce93f8e3f7723c7202cd403569a5fd05"
 
 [[assets]]
 path = "reference/two_stage_OTA_layout.gds"
@@ -27,24 +27,24 @@ environment = "ihp-sg13g2-full-ota-rc-tt"
 
 [task.inputs.description]
 path = "problem.md"
-sha256 = "ab78fb43d86ffe211d3ae76848a0459a591d1631e1c8d287659b8518a530f1a8"
 format = "text"
+sha256 = "0c9b66663404284688d7bfd47bb08eb5a5e38cf252f336e3759e37bfe14b9cc6"
 
 [task.inputs.netlist]
 path = "materials/circuit.cdl"
-sha256 = "b26120b95af66cc4075ac9d12a25444b6badbe7e2c96b50d7a1bd7a15b0cf409"
 format = "spice"
 subcircuit = "two_stage_OTA_layout"
+sha256 = "b26120b95af66cc4075ac9d12a25444b6badbe7e2c96b50d7a1bd7a15b0cf409"
 
 [task.inputs.simulation]
 path = "materials/circuit.spice"
-sha256 = "2c82bb396be0377ae24ee933e5402f87edf9e5da5f2c509774e6ff5c50705a20"
 format = "spice"
+sha256 = "2c82bb396be0377ae24ee933e5402f87edf9e5da5f2c509774e6ff5c50705a20"
 
 [task.inputs.performance]
 path = "materials/testbench.spice"
-sha256 = "62851f9d9bf6754a4d9b70ca2d9d63a0fd6241ae5e65b289fc5e2e8882469bea"
 format = "spice"
+sha256 = "52b7c144f113f3fd175235e912d8ee6212d541f81492122181f9aca045e48c20"
 
 [task.constraints]
 quality = [
@@ -402,7 +402,10 @@ baseline = [
     "source_nominal:unity_gain_bandwidth",
 ]
 normalization = "ratio"
+
+[task.evaluation.metrics.requirement]
 lower = 0
+rationale = "The observed frequency or ordered-event interval has a nonnegative measurement domain, and its required crossing must exist for a usable observation."
 
 [[task.evaluation.metrics]]
 id = "phase_margin"
@@ -419,8 +422,11 @@ baseline = [
 ]
 normalization = "target"
 scale = 180
+
+[task.evaluation.metrics.requirement]
 lower = 0
 upper = 180
+rationale = "The declared negative-feedback loop must stay on the measured 0 to 180 degree stable-feedback branch at the required unity crossing; the amount of positive phase margin remains a scored objective."
 
 [[task.evaluation.metrics]]
 id = "supply_power"
@@ -436,9 +442,12 @@ baseline = [
     "source_nominal:supply_power",
 ]
 normalization = "ratio"
-lower = 0
 scale = 1e-12
 
+[task.evaluation.metrics.requirement]
+lower = 0
+rationale = "The declared powered circuit or driven switching network must consume nonnegative net supply/driver energy or quiescent current under the complete stated observation."
+
 [[task.evaluation.metrics]]
 id = "output_bias"
 category = "performance"
@@ -454,14 +463,17 @@ baseline = [
 ]
 normalization = "target"
 scale = 1.2
+
+[task.evaluation.metrics.requirement]
 lower = 0
 upper = 1.2
+rationale = "The declared node voltage or voltage span must remain within its ground-to-supply operating envelope; precision relative to the source remains a scored objective."
 
 [task.evaluation.pre_layout]
-source_report_sha256 = "3f51127da701e18e468482e3f12272f1923ec7764474fe59fa890f3ef0ed8e69"
+source_report_sha256 = "f4047bdf4424327e402d0ed2d7e04501c8f1b9a1476c1ea678628845e113e903"
 
 [task.evaluation.pre_layout.backends]
-"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"ef9cb87fa27b849376472663b7362673979b89e012f161ba47bb5f6af6ede8eb\", \"compatibility\": null, \"execution_sha256\": \"5424b579002782bfddf0a729715b8fbf2a5f7f2b4cf14982d7616e352d5de9be\", \"image_id\": \"sha256:6562558774d43c085a289bbba696c55959eb8051a0996f96633451fbeb9c652d\", \"limits\": {\"cpus\": 4, \"memory_mb\": 4096, \"pids\": 256}, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"46a60326db6f55e6517e1b351825550ad9e1a19b30e7ba8579189923428f2c9c\", \"timeout_seconds\": 600.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}"
+"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"dfbdf2f93297bbe7d8b576fb988504bd0ecf85b93ef47c314a0f2c9c8830c3e7\", \"compatibility\": null, \"cpu_budget\": 8, \"execution_sha256\": \"495aa9623759f70228a236eb4825c2ae443ef6a741816d8cfc17d1830841dcef\", \"image_id\": \"sha256:060fee64f9f6e71a647e5e958b788d723c9d51d2928ff93e6a295db1959bc37f\", \"limits\": {\"cpus\": 8, \"memory_mb\": 4096, \"pids\": 256}, \"max_parallel_jobs\": 8, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"dce84f0cb44c7192511c807348bb3852682b1b4ec71ee94055876cb79ccbbdb1\", \"thread_environment\": {\"OMP_NUM_THREADS\": \"1\", \"OMP_THREAD_LIMIT\": \"1\"}, \"threads\": 1, \"timeout_seconds\": 600.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}"
 
 [task.evaluation.pre_layout.jobs.source_nominal]
 operation = "circuit.simulate"
@@ -486,7 +498,7 @@ supply_power = "W"
 output_bias = "V"
 
 [task.evaluation.pre_layout.jobs.source_nominal.input_sha256]
-deck = "62851f9d9bf6754a4d9b70ca2d9d63a0fd6241ae5e65b289fc5e2e8882469bea"
+deck = "52b7c144f113f3fd175235e912d8ee6212d541f81492122181f9aca045e48c20"
 dut = "2c82bb396be0377ae24ee933e5402f87edf9e5da5f2c509774e6ff5c50705a20"
 
 [task.evaluation.pre_layout.jobs.source_nominal.measurements.low_frequency_gain]
@@ -509,11 +521,15 @@ unit = "W"
 value = 4148602.0
 unit = "Hz"
 
+[task.evaluation.pre_layout.jobs.source_nominal.output_sha256]
+ac = "021787e583eef86c3e0ba57af79027a5c41acc6b2f68801af952e1db0692932f"
+op = "05ea8768699ad8c4caae223037737554cb017bc21946db3300f98f65731a0996"
+
 [toolchain.backends.artifact]
 type = "klayout-docker"
 
 [toolchain.backends.artifact.settings]
-image = "iclayout-bench-tools:local"
+image = "iclayout-eda-open:local"
 check = "artifact"
 
 [toolchain.backends.drc]
@@ -523,7 +539,7 @@ type = "klayout-docker"
 support = "klayout"
 
 [toolchain.backends.drc.settings]
-image = "iclayout-bench-tools:local"
+image = "iclayout-eda-open:local"
 check = "drc"
 support = "build/support/full-ota-klayout-spice"
 profile = "drc-upstream.json"
@@ -536,7 +552,7 @@ type = "klayout-docker"
 support = "klayout"
 
 [toolchain.backends.lvs.settings]
-image = "iclayout-bench-tools:local"
+image = "iclayout-eda-open:local"
 check = "lvs"
 support = "build/support/full-ota-klayout-spice"
 profile = "lvs-upstream.json"
@@ -549,7 +565,7 @@ type = "magic-rc-docker"
 support = "magic"
 
 [toolchain.backends.rc.settings]
-image = "iclayout-bench-tools:local"
+image = "iclayout-eda-open:local"
 support = "build/support/full-ota-magic"
 technology = "magic/ihp-sg13g2.tech"
 tech_name = "ihp-sg13g2"
@@ -561,7 +577,7 @@ timeout_seconds = 600
 type = "klayout-geometry-docker"
 
 [toolchain.backends.geometry.settings]
-image = "iclayout-bench-tools:local"
+image = "iclayout-eda-open:local"
 timeout_seconds = 120
 
 [toolchain.backends.simulation]
@@ -571,7 +587,10 @@ type = "ngspice-docker"
 support = "analog-models"
 
 [toolchain.backends.simulation.settings]
-image = "iclayout-bench-tools:local"
+max_parallel_jobs = 8
+threads = 1
+cpu_budget = 8
+image = "iclayout-eda-open:local"
 support = "build/support/full-ota-models"
 timeout_seconds = 600
 

tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/full_OTA/materials/testbench.spice

@@ -23,6 +23,7 @@ let supply_power = -v(vdd)*i(VDD)
 let output_bias = v(vout)
 print supply_power output_bias
 write ota-op.raw all
+save i(vdd) v(vdd) v(vm) v(vout) v(vp)
 ac dec 100 1 10meg
 let differential = v(vp)-v(vm)
 let transfer = v(vout)/differential

tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/full_OTA/problem.md

@@ -11,9 +11,7 @@ AC-response limits after candidate-derived RC extraction.
 
 ## Inputs and Interface
 
-In addition to this problem, the solver receives the following declared
-materials. The structured constraints
-and evaluation plan are also available at runtime through `/protocol/task.json`.
+In addition to this description, the solver receives the following declared materials. The runtime `/protocol/task.json` also supplies structured constraints and the evaluation plan.
 
 | Input | Purpose |
 |---|---|
@@ -21,8 +19,7 @@ and evaluation plan are also available at runtime through `/protocol/task.json`.
 | [materials/circuit.spice](materials/circuit.spice) | Pre-layout simulator netlist |
 | [materials/testbench.spice](materials/testbench.spice) | Nominal bias, feedback fixture, AC sweep, and measurements |
 
-Use one external label on each distinct conductor. Internal nodes must not be
-declared as external ports.
+Use one external label per independent conductor; internal nodes must not be declared as external ports.
 
 | Port | Function | Nominal connection |
 |---|---|---|
@@ -61,15 +58,9 @@ Submit a readable GDSII file with a nonempty `two_stage_OTA_layout` top cell. Th
 file must be at most 10 MiB (10,485,760 bytes) and must contain the complete
 hierarchy needed by the target cell.
 
-The evaluator runs the pinned SG13G2 main and additional maximal DRC rules in
-deep mode, with density and antenna checks disabled and no waivers. LVS uses the
-current `lvs-upstream.json` profile and strict named-port matching against
-`materials/circuit.cdl`; every declared port must stay on its own conductor with
-the declared connectivity and device parameters. Port names are matched
-case-insensitively.
+Use the pinned SG13G2 main rules and additional maximal DRC rules in deep mode, with density and antenna checks disabled and no waivers. LVS uses the current `lvs-upstream.json` configuration and strictly matches named ports against `materials/circuit.cdl`, preserving each port's independent conductor, connections and device parameters; port names are case insensitive.
 
-The functional outline is the recursive bounding box of polygons on these
-SG13G2 datatype-0 layers, including child cells and the complete routing stack:
+The functional outline is the recursive bounding box of polygons on the following SG13G2 datatype-0 layers, including child cells and every routing layer:
 
 `1, 3, 5, 6, 7, 8, 10, 11, 13, 14, 19, 24, 26, 28, 29, 30, 31, 32, 33, 35, 36, 40, 44, 46, 49, 50, 51, 52, 53, 55, 58, 66, 67, 90, 101, 111, 125, 126, 128, 129, 133, 134, 139, 152`.
 
@@ -90,43 +81,19 @@ requirements.
 
 ## Electrical Requirements and Scoring
 
-Physical checks and declared functional bounds remain mandatory. Quality has no
-fixed allowed-degradation threshold. Each `source_*` job simulates the declared
-source circuit with exactly the same testbench, model resources, parameters,
-load and measurement window as its paired extracted-candidate job. A source
-observation is the 100-point electrical baseline; it is independent of the
-submitted GDS. All individual pairs are retained in the evaluation report.
-
-For a post-layout observation x and its source observation b:
-
-- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,
-  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;
-  s is a normalization floor, not an allowed degradation or pass threshold.
-- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.
-- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and
-  zero-valued operating points are never divided directly.
-
-Scoring uses `layout`. A metric uses its worst paired quality q. The score is
-S = 100 * product(q_i ** w_i), including area quality
-q_area = area_reference / candidate_functional_area. The weights below sum to
-one. Dimensions describe measurements but do not determine their weights.
-Physical or functional rejection scores zero; missing or invalid measurements
-produce an unknown score, including measurements with zero weight.
-Source-equivalent performance at the area reference scores 100; improvements
-can exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.
-
-Measurement definitions below use the supplied SPICE node/source names.
-`v(n)` is node voltage and `i(V)` is current into a voltage source; delivered
-power therefore uses a minus sign. `db(z)=20*log10(abs(z))`, `mag/abs`
-denote magnitude, and `cph` is continuous phase in radians. `find`, `when`,
-`from/to`, and `rise/fall` retain the deck's interpolation, window and
-crossing conventions; SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/
-milli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv`
-mean the stated window average, extrema and sampled derivative. All
-declared conditions are measured separately and paired with the same
-source condition; a group uses its worst paired quality.
-
-| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | Dimension |
+Physical checks and the declared functional bounds must pass. Quality scoring imposes no fixed degradation allowance. Each `source_*` job and its corresponding candidate extracted circuit use exactly the same testbench, model resources, parameters, loads and measurement windows. Independent source observations define the 100-point electrical baseline without depending on the submitted GDS; reports retain every paired result.
+
+Let x be the post-layout measurement and b the source-circuit measurement under the same conditions:
+
+- Ratio normalization: maximize with q = x/b and minimize with q = b/x. When a numerical scale s is declared, use (x+s)/(b+s) and its reciprocal, respectively. The scale handles zero values as a normalization floor; it is neither an allowed degradation nor an acceptance bound.
+- Amplitude in dB: maximize with q = 10^((x-b)/20) and minimize with its reciprocal.
+- Target normalization: q = 1/(1+abs(x-b)/s), where s is the declared physical scale. Signed or zero-valued operating points are not divided directly.
+
+Use `layout` scoring. Each metric takes its worst paired quality q, and the total score is S = 100 * product(q_i ** w_i), with area quality q_area = area_reference / candidate_functional_area. The weights below sum to 1; metric dimensions describe measurements and do not determine weights. Physical or functional rejection scores zero; missing or invalid measurements leave the score unknown, and zero-weight observations must also be valid. Matching source-circuit performance at the reference area scores 100 points; better valid solutions may exceed 100. Weights express quality tradeoffs rather than hard bounds.
+
+The measurements below use the supplied SPICE node and source names. `v(n)` is a node voltage; `i(V)` is current flowing into a voltage source, so delivered power uses a negative sign. `db(z)=20*log10(abs(z))`; `mag/abs` denote magnitude, and `cph` denotes continuous phase in radians. `find`, `when`, `from/to` and `rise/fall` follow the deck's interpolation, window and crossing conventions. SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/milli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv` represent window averages, extrema and sampled derivatives. Measure each operating condition independently, pair it with the source result under that condition, and take the worst paired quality within each metric group.
+
+| Metric | Definition / observation | Unit | Quality normalization | Functional range | Scale | Dimension |
 | --- | --- | --- | --- | --- | --- | --- |
 | `low_frequency_gain` | AC: Value of `(db((v(vout)/(v(vp)-v(vm))))) at=1`. | dB | maximize / db20 | −∞ … +∞ | — | response |
 | `unity_gain_bandwidth` | AC: Crossing coordinate where `(db((v(vout)/(v(vp)-v(vm)))))=0 fall=1`. | Hz | maximize / ratio | 0 … +∞ | — | response |
@@ -134,15 +101,13 @@ source condition; a group uses its worst paired quality.
 | `supply_power` | DC operating point: `-v(vdd)*i(VDD)`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |
 | `output_bias` | DC operating point: `v(vout)`. | V | target / target | 0 … 1.2 | 1.2 | bias |
 
-Area reference: **2936.48 um2**. 24 expanded device instances; sum of device/contact envelopes 1887.1830 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.
-
-The capability coefficient remains **6**; it is independent of
-the reference-relative task score.
+Area reference: **2936.48 um2**. The expanded circuit has 24 device instances, a sum of device/contact envelopes 1887.1830 um2, a one-sided envelope margin of 0.6 um, a routing allowance of 50%, and a total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across both sides, and the envelope sum is displayed to four decimal places. MOS/passive envelopes use W/L (or resistor dimensions) and multiplicity, including explicit contacts and HBT emitter/contact envelopes. This is a frozen engineering estimate, not a process minimum or a proven achievable area.
 
+The capability coefficient is **6**, independent of this task's reference-normalized score.
 
 ### Score weights
 
-Small-signal OTAs: gain 27%; bandwidth 22.5%; phase margin 22.5%; operating points 4.5%; power 13.5%; area 10%. Each objective's weight is divided equally among its metrics.
+Small-signal OTAs: gain 27%, bandwidth 22.5%, phase margin 22.5%, operating points 4.5%, power 13.5%, area 10%. Each objective's weight is divided equally among its metrics.
 
 | Metric | Weight |
 | --- | ---: |
@@ -157,12 +122,7 @@ Small-signal OTAs: gain 27%; bandwidth 22.5%; phase margin 22.5%; operating poin
 
 Solve budget: **3 hours**.
 
-Runtime environment and support resources are declared in
-`/protocol/resources.json` and `/protocol/harness.json`; the working directory is
-`/workspace`. KLayout performs artifact, DRC, LVS, and geometry checks; Magic
-performs RC extraction; ngspice runs the supplied deck with the reviewed SG13G2
-models. The evaluator provides the tool and PDK resources named by the case
-toolchain.
+See `/protocol/resources.json` and `/protocol/harness.json` for runtime and supporting resources; the working directory is `/workspace`. KLayout checks files, DRC, LVS and geometry, Magic extracts RC, and ngspice runs decks with reviewed SG13G2 models. The evaluator supplies tools and PDK specified by the contract toolchain.
 
 For pre-layout simulation, use `materials/circuit.spice` as `dut.spice` beside
 the supplied testbench, with the model paths and settings exposed by the runtime
@@ -171,7 +131,4 @@ candidate-derived extracted netlist. If the harness declares
 `process-feedback`, the optional command is
 `python -I /protocol/process_check.py`; the final evaluation remains independent.
 
-Write the result to `/workspace/output/final.gds`, then run
-`python -I /protocol/submit.py` and wait for the submission receipt. Solver
-netlists, waveforms, and measurements are not accepted as substitutes for the
-independent evaluator inputs.
+Write the result to `/workspace/output/final.gds`, run `python -I /protocol/submit.py` and wait for a submission receipt. Solver netlists, waveforms and measurements cannot replace independent evaluator inputs.

tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/input_pair/case.toml

@@ -1,15 +1,15 @@
-in_core = false
 kind = "layout_case"
 id = "module_1_bandgap_reference.part_3_layout.OTA_layout.input_pair"
 title = "IHP AnalogAcademy input_pair"
 status = "qualified"
+in_core = false
 
 [[assets]]
 path = "materials/schematic.svg"
 role = "schematic"
 visibility = "maintainer"
 format = "svg"
-sha256 = "be0b3098da9309ede946b43b9bda1188c5f8a717d0d558693d32b98ae726e0f2"
+sha256 = "1d79d6b9e0810b86b030f483c69745ef084caf776a9fc1670b627162b8022b53"
 
 [[assets]]
 path = "reference/input_common_centroid.gds"
@@ -27,24 +27,24 @@ environment = "ihp-sg13g2-input-pair-rc-tt"
 
 [task.inputs.description]
 path = "problem.md"
-sha256 = "b91a95f0f2879d8d309b2b9a6a9b918bf174b21a49a70f096d8843ffb8351d77"
 format = "text"
+sha256 = "919e94d5dd3388d5d8517fe86cc3ccefe065f4a413559c1882acd8f80b550057"
 
 [task.inputs.netlist]
 path = "materials/circuit.cdl"
-sha256 = "25456f0316c22ee5586ad3e306f0d513fd35e48f32ee67ce9cb0dc373d306f3d"
 format = "spice"
 subcircuit = "input_common_centroid"
+sha256 = "25456f0316c22ee5586ad3e306f0d513fd35e48f32ee67ce9cb0dc373d306f3d"
 
 [task.inputs.simulation]
 path = "materials/circuit.spice"
-sha256 = "cde9a2075fbac6afcf32fd02baf847398de1e9d179b3d3a87762534adfd8bd2b"
 format = "spice"
+sha256 = "cde9a2075fbac6afcf32fd02baf847398de1e9d179b3d3a87762534adfd8bd2b"
 
 [task.inputs.performance]
 path = "materials/testbench.spice"
-sha256 = "0ce316136b95395971965c7760a711d8431e8c1d4294a074b658520442e11dde"
 format = "spice"
+sha256 = "72c2f7c4f272b1797d936a09ff51ce7d2715f0569d4bd11f6d31d23e9f64b4b0"
 
 [task.constraints]
 quality = [
@@ -397,7 +397,10 @@ baseline = [
     "source_nominal:differential_gain",
 ]
 normalization = "ratio"
+
+[task.evaluation.metrics.requirement]
 lower = 0
+rationale = "The declared response magnitude, impedance, capacitance, amplitude or absolute return-ratio diagnostic has a nonnegative measurement domain; its value remains a quality or diagnostic observation."
 
 [[task.evaluation.metrics]]
 id = "differential_gain_high"
@@ -413,7 +416,10 @@ baseline = [
     "source_nominal:differential_gain_high",
 ]
 normalization = "ratio"
+
+[task.evaluation.metrics.requirement]
 lower = 0
+rationale = "The declared response magnitude, impedance, capacitance, amplitude or absolute return-ratio diagnostic has a nonnegative measurement domain; its value remains a quality or diagnostic observation."
 
 [[task.evaluation.metrics]]
 id = "tail_voltage"
@@ -446,8 +452,11 @@ baseline = [
 ]
 normalization = "target"
 scale = 1.2
+
+[task.evaluation.metrics.requirement]
 lower = 0
 upper = 1.2
+rationale = "The declared node voltage or voltage span must remain within its ground-to-supply operating envelope; precision relative to the source remains a scored objective."
 
 [[task.evaluation.metrics]]
 id = "drain_balance"
@@ -479,14 +488,17 @@ baseline = [
     "source_nominal:supply_power",
 ]
 normalization = "ratio"
-lower = 0
 scale = 1e-12
 
+[task.evaluation.metrics.requirement]
+lower = 0
+rationale = "The declared powered circuit or driven switching network must consume nonnegative net supply/driver energy or quiescent current under the complete stated observation."
+
 [task.evaluation.pre_layout]
-source_report_sha256 = "f82335367c588d196a9e3634129a29b2b3e98a9f67b5fa984c53f940f2253886"
+source_report_sha256 = "50fc5cbecb2735b61f960996a3f839f1d5a8e3519184a6ed6cf48f4bea467f3c"
 
 [task.evaluation.pre_layout.backends]
-"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"ef9cb87fa27b849376472663b7362673979b89e012f161ba47bb5f6af6ede8eb\", \"compatibility\": null, \"execution_sha256\": \"5424b579002782bfddf0a729715b8fbf2a5f7f2b4cf14982d7616e352d5de9be\", \"image_id\": \"sha256:6562558774d43c085a289bbba696c55959eb8051a0996f96633451fbeb9c652d\", \"limits\": {\"cpus\": 4, \"memory_mb\": 4096, \"pids\": 256}, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"868b87913ea2ceaa4e2650d73a934158d54aae1ad194f3713dc37b8c89b75884\", \"timeout_seconds\": 600.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}"
+"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"dfbdf2f93297bbe7d8b576fb988504bd0ecf85b93ef47c314a0f2c9c8830c3e7\", \"compatibility\": null, \"cpu_budget\": 8, \"execution_sha256\": \"495aa9623759f70228a236eb4825c2ae443ef6a741816d8cfc17d1830841dcef\", \"image_id\": \"sha256:060fee64f9f6e71a647e5e958b788d723c9d51d2928ff93e6a295db1959bc37f\", \"limits\": {\"cpus\": 8, \"memory_mb\": 4096, \"pids\": 256}, \"max_parallel_jobs\": 8, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"dce84f0cb44c7192511c807348bb3852682b1b4ec71ee94055876cb79ccbbdb1\", \"thread_environment\": {\"OMP_NUM_THREADS\": \"1\", \"OMP_THREAD_LIMIT\": \"1\"}, \"threads\": 1, \"timeout_seconds\": 600.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}"
 
 [task.evaluation.pre_layout.jobs.source_nominal]
 operation = "circuit.simulate"
@@ -517,7 +529,7 @@ differential_gain = "V/V"
 differential_gain_high = "V/V"
 
 [task.evaluation.pre_layout.jobs.source_nominal.input_sha256]
-deck = "0ce316136b95395971965c7760a711d8431e8c1d4294a074b658520442e11dde"
+deck = "72c2f7c4f272b1797d936a09ff51ce7d2715f0569d4bd11f6d31d23e9f64b4b0"
 dut = "cde9a2075fbac6afcf32fd02baf847398de1e9d179b3d3a87762534adfd8bd2b"
 
 [task.evaluation.pre_layout.jobs.source_nominal.measurements.common_drain]
@@ -544,6 +556,10 @@ unit = "W"
 value = 1.192980871489
 unit = "V"
 
+[task.evaluation.pre_layout.jobs.source_nominal.output_sha256]
+ac = "0360aae789606dbd608b542c97e489bea026c36d2f0dc5727c579843eb85e2fd"
+op = "af65808f45ca9d302127bba58fdc0289a4b74f113b7d1a3c5b729bf713988aae"
+
 [toolchain.bindings]
 "layout.artifact" = "artifact"
 "layout.drc" = "drc"
@@ -556,7 +572,7 @@ unit = "V"
 type = "klayout-docker"
 
 [toolchain.backends.artifact.settings]
-image = "iclayout-bench-tools:local"
+image = "iclayout-eda-open:local"
 check = "artifact"
 timeout_seconds = 600
 
@@ -567,7 +583,7 @@ type = "klayout-docker"
 support = "klayout"
 
 [toolchain.backends.drc.settings]
-image = "iclayout-bench-tools:local"
+image = "iclayout-eda-open:local"
 check = "drc"
 support = "build/support/input-pair-klayout"
 profile = "drc-upstream.json"
@@ -580,7 +596,7 @@ type = "klayout-docker"
 support = "klayout"
 
 [toolchain.backends.lvs.settings]
-image = "iclayout-bench-tools:local"
+image = "iclayout-eda-open:local"
 check = "lvs"
 support = "build/support/input-pair-klayout"
 profile = "lvs-upstream.json"
@@ -593,7 +609,7 @@ type = "magic-rc-docker"
 support = "magic"
 
 [toolchain.backends.rc.settings]
-image = "iclayout-bench-tools:local"
+image = "iclayout-eda-open:local"
 support = "build/support/input-pair-magic"
 technology = "magic/ihp-sg13g2.tech"
 tech_name = "ihp-sg13g2"
@@ -605,7 +621,7 @@ timeout_seconds = 600
 type = "klayout-geometry-docker"
 
 [toolchain.backends.geometry.settings]
-image = "iclayout-bench-tools:local"
+image = "iclayout-eda-open:local"
 timeout_seconds = 120
 
 [toolchain.backends.simulation]
@@ -615,7 +631,10 @@ type = "ngspice-docker"
 support = "analog-models"
 
 [toolchain.backends.simulation.settings]
-image = "iclayout-bench-tools:local"
+max_parallel_jobs = 8
+threads = 1
+cpu_budget = 8
+image = "iclayout-eda-open:local"
 support = "build/support/input-pair-models"
 timeout_seconds = 600
 

tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/input_pair/materials/testbench.spice

@@ -25,6 +25,7 @@ let common_drain = (v(dn3)+v(dn4))/2
 let supply_power = -v(vdd)*i(VDD)
 print tail_voltage drain_balance common_drain supply_power
 write input-op.raw all
+save i(vdd) v(dn3) v(dn4) v(tail) v(vdd) v(vm) v(vp)
 ac dec 40 1 1g
 let differential_gain = (v(dn3)-v(dn4))/(v(vp)-v(vm))
 let differential_gain_abs = abs(differential_gain)

tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/input_pair/problem.md

@@ -11,9 +11,7 @@ candidate-derived RC extraction.
 
 ## Inputs and Interface
 
-In addition to this problem, the solver receives the following declared
-materials. The structured constraints
-and evaluation plan are also available at runtime through `/protocol/task.json`.
+In addition to this description, the solver receives the following declared materials. The runtime `/protocol/task.json` also supplies structured constraints and the evaluation plan.
 
 | Input | Purpose |
 |---|---|
@@ -21,8 +19,7 @@ and evaluation plan are also available at runtime through `/protocol/task.json`.
 | [materials/circuit.spice](materials/circuit.spice) | Pre-layout simulator netlist |
 | [materials/testbench.spice](materials/testbench.spice) | Bias, load, AC sweep, and public measurement expressions |
 
-Use one external label on each distinct conductor. Internal nodes must not be
-declared as external ports.
+Use one external label per independent conductor; internal nodes must not be declared as external ports.
 
 | Port | Function | Nominal connection |
 |---|---|---|
@@ -36,8 +33,7 @@ The extraction port order is `v- v+ vdd dn3 dn4 tail`.
 
 ## Operating Conditions
 
-The pre-layout and candidate-derived simulations use the supplied deck and the
-same nominal model and parameter values.
+Source and candidate extracted circuits use the supplied decks with identical nominal models and parameters.
 
 | Parameter | Setting |
 |---|---|
@@ -60,15 +56,9 @@ Submit a readable GDSII file with a nonempty `input_common_centroid` top cell.
 The file must be at most 10 MiB (10,485,760 bytes) and must contain the complete
 hierarchy needed by the target cell.
 
-The evaluator runs the pinned SG13G2 main and additional maximal DRC rules in
-deep mode, with density and antenna checks disabled and no waivers. LVS uses the
-current `lvs-upstream.json` profile and strict named-port matching against
-`materials/circuit.cdl`; every declared port must stay on its own conductor
-with the declared connectivity and device parameters. Port names are matched
-case-insensitively.
+Use the pinned SG13G2 main rules and additional maximal DRC rules in deep mode, with density and antenna checks disabled and no waivers. LVS uses the current `lvs-upstream.json` configuration and strictly matches named ports against `materials/circuit.cdl`, preserving each port's independent conductor, connections and device parameters; port names are case insensitive.
 
-The functional outline is the recursive bounding box of polygons on these
-SG13G2 datatype-0 layers, including child cells and the complete routing stack:
+The functional outline is the recursive bounding box of polygons on the following SG13G2 datatype-0 layers, including child cells and every routing layer:
 
 `1, 3, 5, 6, 7, 8, 10, 11, 13, 14, 19, 24, 26, 28, 29, 30, 31, 32, 33, 35, 36, 40, 44, 46, 49, 50, 51, 52, 53, 55, 58, 66, 67, 90, 101, 111, 125, 126, 128, 129, 133, 134, 139, 152`.
 
@@ -87,43 +77,19 @@ noise are outside the declared scope. The finite source tap is used only in sour
 
 ## Electrical Requirements and Scoring
 
-Physical checks and declared functional bounds remain mandatory. Quality has no
-fixed allowed-degradation threshold. Each `source_*` job simulates the declared
-source circuit with exactly the same testbench, model resources, parameters,
-load and measurement window as its paired extracted-candidate job. A source
-observation is the 100-point electrical baseline; it is independent of the
-submitted GDS. All individual pairs are retained in the evaluation report.
-
-For a post-layout observation x and its source observation b:
-
-- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,
-  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;
-  s is a normalization floor, not an allowed degradation or pass threshold.
-- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.
-- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and
-  zero-valued operating points are never divided directly.
-
-Scoring uses `layout`. A metric uses its worst paired quality q. The score is
-S = 100 * product(q_i ** w_i), including area quality
-q_area = area_reference / candidate_functional_area. The weights below sum to
-one. Dimensions describe measurements but do not determine their weights.
-Physical or functional rejection scores zero; missing or invalid measurements
-produce an unknown score, including measurements with zero weight.
-Source-equivalent performance at the area reference scores 100; improvements
-can exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.
-
-Measurement definitions below use the supplied SPICE node/source names.
-`v(n)` is node voltage and `i(V)` is current into a voltage source; delivered
-power therefore uses a minus sign. `db(z)=20*log10(abs(z))`, `mag/abs`
-denote magnitude, and `cph` is continuous phase in radians. `find`, `when`,
-`from/to`, and `rise/fall` retain the deck's interpolation, window and
-crossing conventions; SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/
-milli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv`
-mean the stated window average, extrema and sampled derivative. All
-declared conditions are measured separately and paired with the same
-source condition; a group uses its worst paired quality.
-
-| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | Dimension |
+Physical checks and the declared functional bounds must pass. Quality scoring imposes no fixed degradation allowance. Each `source_*` job and its corresponding candidate extracted circuit use exactly the same testbench, model resources, parameters, loads and measurement windows. Independent source observations define the 100-point electrical baseline without depending on the submitted GDS; reports retain every paired result.
+
+Let x be the post-layout measurement and b the source-circuit measurement under the same conditions:
+
+- Ratio normalization: maximize with q = x/b and minimize with q = b/x. When a numerical scale s is declared, use (x+s)/(b+s) and its reciprocal, respectively. The scale handles zero values as a normalization floor; it is neither an allowed degradation nor an acceptance bound.
+- Amplitude in dB: maximize with q = 10^((x-b)/20) and minimize with its reciprocal.
+- Target normalization: q = 1/(1+abs(x-b)/s), where s is the declared physical scale. Signed or zero-valued operating points are not divided directly.
+
+Use `layout` scoring. Each metric takes its worst paired quality q, and the total score is S = 100 * product(q_i ** w_i), with area quality q_area = area_reference / candidate_functional_area. The weights below sum to 1; metric dimensions describe measurements and do not determine weights. Physical or functional rejection scores zero; missing or invalid measurements leave the score unknown, and zero-weight observations must also be valid. Matching source-circuit performance at the reference area scores 100 points; better valid solutions may exceed 100. Weights express quality tradeoffs rather than hard bounds.
+
+The measurements below use the supplied SPICE node and source names. `v(n)` is a node voltage; `i(V)` is current flowing into a voltage source, so delivered power uses a negative sign. `db(z)=20*log10(abs(z))`; `mag/abs` denote magnitude, and `cph` denotes continuous phase in radians. `find`, `when`, `from/to` and `rise/fall` follow the deck's interpolation, window and crossing conventions. SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/milli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv` represent window averages, extrema and sampled derivatives. Measure each operating condition independently, pair it with the source result under that condition, and take the worst paired quality within each metric group.
+
+| Metric | Definition / observation | Unit | Quality normalization | Functional range | Scale | Dimension |
 | --- | --- | --- | --- | --- | --- | --- |
 | `differential_gain` | AC: Value of `(abs(((v(dn3)-v(dn4))/(v(vp)-v(vm))))) at=1meg`. | V/V | maximize / ratio | 0 … +∞ | — | response |
 | `differential_gain_high` | AC: Value of `(abs(((v(dn3)-v(dn4))/(v(vp)-v(vm))))) at=100meg`. | V/V | maximize / ratio | 0 … +∞ | — | response |
@@ -132,11 +98,9 @@ source condition; a group uses its worst paired quality.
 | `drain_balance` | DC operating point: `v(dn3)-v(dn4)`. | V | target / target | −∞ … +∞ | 1.2 | bias |
 | `supply_power` | DC operating point: `-v(vdd)*i(VDD)`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |
 
-Area reference: **1236.14 um2**. 13 expanded device instances; sum of device/contact envelopes 778.4891 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.
-
-The capability coefficient remains **3**; it is independent of
-the reference-relative task score.
+Area reference: **1236.14 um2**. The expanded circuit has 13 device instances, a sum of device/contact envelopes 778.4891 um2, a one-sided envelope margin of 0.6 um, a routing allowance of 50%, and a total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across both sides, and the envelope sum is displayed to four decimal places. MOS/passive envelopes use W/L (or resistor dimensions) and multiplicity, including explicit contacts and HBT emitter/contact envelopes. This is a frozen engineering estimate, not a process minimum or a proven achievable area.
 
+The capability coefficient is **3**, independent of this task's reference-normalized score.
 
 ### Score weights
 
@@ -156,22 +120,8 @@ Local gain stages: signal transfer 44.7%; balance and linearity 22.4%; operating
 
 Solve budget: **3 hours**.
 
-Runtime environment and support resources are declared in
-`/protocol/resources.json` and `/protocol/harness.json`; the working directory is
-`/workspace`. KLayout performs artifact, DRC, LVS, and geometry checks; Magic
-performs RC extraction; ngspice runs the supplied deck with the reviewed SG13G2
-models. The evaluator provides the tool and PDK resources named by the case
-toolchain.
-
-For pre-layout simulation, use `materials/circuit.spice` as `dut.spice` beside
-the supplied testbench. The evaluator generates `parameters.spice` from the
-per-job values in `/protocol/task.json` and supplies the model paths and settings
-through the runtime resource bundle. For the submitted layout, the evaluator
-supplies the candidate-derived extracted netlist. If the harness declares
-`process-feedback`, the optional command is
-`python -I /protocol/process_check.py`; the final evaluation remains independent.
-
-Write the result to `/workspace/output/final.gds`, then run
-`python -I /protocol/submit.py` and wait for the submission receipt. Solver
-netlists, waveforms, and measurements are not accepted as substitutes for the
-independent evaluator inputs.
+See `/protocol/resources.json` and `/protocol/harness.json` for runtime and supporting resources; the working directory is `/workspace`. KLayout checks files, DRC, LVS and geometry, Magic extracts RC, and ngspice runs decks with reviewed SG13G2 models. The evaluator supplies tools and PDK specified by the contract toolchain.
+
+For source simulation, place `materials/circuit.spice` as `dut.spice` beside the testbench. The evaluator generates `parameters.spice` from per-job parameters in `/protocol/task.json`, supplying model paths and settings through the resource bundle; candidate evaluation uses its extracted netlist. If `process-feedback` is declared, run `python -I /protocol/process_check.py`; final evaluation is independent.
+
+Write the result to `/workspace/output/final.gds`, run `python -I /protocol/submit.py` and wait for a submission receipt. Solver netlists, waveforms and measurements cannot replace independent evaluator inputs.

tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/output_stage/case.toml

@@ -1,15 +1,15 @@
-in_core = false
 kind = "layout_case"
 id = "module_1_bandgap_reference.part_3_layout.OTA_layout.output_stage"
 title = "IHP AnalogAcademy output_stage"
 status = "qualified"
+in_core = false
 
 [[assets]]
 path = "materials/schematic.svg"
 role = "schematic"
 visibility = "maintainer"
 format = "svg"
-sha256 = "dac4dbead6434a4bb345826211848b873d70a2725654491aadd7a64609c69684"
+sha256 = "a222ca439e61eb4ffe4f5f25b56e7f0d2d68236645ecc284c85941c824b0af50"
 
 [[assets]]
 path = "reference/output_stage.gds"
@@ -27,24 +27,24 @@ environment = "ihp-sg13g2-output-stage-rc-tt"
 
 [task.inputs.description]
 path = "problem.md"
-sha256 = "129a8b29c8a92c2d912e0d6ffb5c09efc3d2c10b286e45c3bd53b0376f2c9b1a"
 format = "text"
+sha256 = "066f5d5d0f2de3d2df97eff3f68bf5a9c76d47e980e1747ebe3c15a88a022af7"
 
 [task.inputs.netlist]
 path = "materials/circuit.cdl"
-sha256 = "81620ebba529edccd1beddbcb1349c0e3e7ee58b9e3749d8235433610bd98ad5"
 format = "spice"
 subcircuit = "output_stage"
+sha256 = "81620ebba529edccd1beddbcb1349c0e3e7ee58b9e3749d8235433610bd98ad5"
 
 [task.inputs.simulation]
 path = "materials/circuit.spice"
-sha256 = "d5c4009de00efbc07ad6c612fb371ef8cd7a837a49bec1a27f1d1729a2d8440d"
 format = "spice"
+sha256 = "d5c4009de00efbc07ad6c612fb371ef8cd7a837a49bec1a27f1d1729a2d8440d"
 
 [task.inputs.performance]
 path = "materials/testbench.spice"
-sha256 = "b857814e44bf0b95d14cd69944cbbdbc5da3b756290f76d824b26b7f73990678"
 format = "spice"
+sha256 = "93b5c000491d8575e5b3b545fe48405e685d1412efa48b9a0551637877d1320b"
 
 [task.constraints]
 quality = [
@@ -393,7 +393,10 @@ baseline = [
     "source_nominal:output_gain",
 ]
 normalization = "ratio"
+
+[task.evaluation.metrics.requirement]
 lower = 0
+rationale = "The declared response magnitude, impedance, capacitance, amplitude or absolute return-ratio diagnostic has a nonnegative measurement domain; its value remains a quality or diagnostic observation."
 
 [[task.evaluation.metrics]]
 id = "output_gain_high"
@@ -409,7 +412,10 @@ baseline = [
     "source_nominal:output_gain_high",
 ]
 normalization = "ratio"
+
+[task.evaluation.metrics.requirement]
 lower = 0
+rationale = "The declared response magnitude, impedance, capacitance, amplitude or absolute return-ratio diagnostic has a nonnegative measurement domain; its value remains a quality or diagnostic observation."
 
 [[task.evaluation.metrics]]
 id = "output_bias"
@@ -426,8 +432,11 @@ baseline = [
 ]
 normalization = "target"
 scale = 1.2
+
+[task.evaluation.metrics.requirement]
 lower = 0
 upper = 1.2
+rationale = "The declared node voltage or voltage span must remain within its ground-to-supply operating envelope; precision relative to the source remains a scored objective."
 
 [[task.evaluation.metrics]]
 id = "supply_power"
@@ -443,14 +452,17 @@ baseline = [
     "source_nominal:supply_power",
 ]
 normalization = "ratio"
-lower = 0
 scale = 1e-12
 
+[task.evaluation.metrics.requirement]
+lower = 0
+rationale = "The declared powered circuit or driven switching network must consume nonnegative net supply/driver energy or quiescent current under the complete stated observation."
+
 [task.evaluation.pre_layout]
-source_report_sha256 = "a81b188b06daaafc0a2dc0ec69b3a9ffe9c07c41d587b1a9f0824df25ff7ab4b"
+source_report_sha256 = "97d06fbb60ba8b20fd4d39cef6b75104b7d85b375d768f21ff2c08a1a824a3f5"
 
 [task.evaluation.pre_layout.backends]
-"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"ef9cb87fa27b849376472663b7362673979b89e012f161ba47bb5f6af6ede8eb\", \"compatibility\": null, \"execution_sha256\": \"5424b579002782bfddf0a729715b8fbf2a5f7f2b4cf14982d7616e352d5de9be\", \"image_id\": \"sha256:6562558774d43c085a289bbba696c55959eb8051a0996f96633451fbeb9c652d\", \"limits\": {\"cpus\": 4, \"memory_mb\": 4096, \"pids\": 256}, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"9f4c9b1c265d2a44e4af063f0645ed195f02c242644afa80a28d17583b5aaae8\", \"timeout_seconds\": 600.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}"
+"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"dfbdf2f93297bbe7d8b576fb988504bd0ecf85b93ef47c314a0f2c9c8830c3e7\", \"compatibility\": null, \"cpu_budget\": 8, \"execution_sha256\": \"495aa9623759f70228a236eb4825c2ae443ef6a741816d8cfc17d1830841dcef\", \"image_id\": \"sha256:060fee64f9f6e71a647e5e958b788d723c9d51d2928ff93e6a295db1959bc37f\", \"limits\": {\"cpus\": 8, \"memory_mb\": 4096, \"pids\": 256}, \"max_parallel_jobs\": 8, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"dce84f0cb44c7192511c807348bb3852682b1b4ec71ee94055876cb79ccbbdb1\", \"thread_environment\": {\"OMP_NUM_THREADS\": \"1\", \"OMP_THREAD_LIMIT\": \"1\"}, \"threads\": 1, \"timeout_seconds\": 600.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}"
 
 [task.evaluation.pre_layout.jobs.source_nominal]
 operation = "circuit.simulate"
@@ -480,7 +492,7 @@ output_gain = "V/V"
 output_gain_high = "V/V"
 
 [task.evaluation.pre_layout.jobs.source_nominal.input_sha256]
-deck = "b857814e44bf0b95d14cd69944cbbdbc5da3b756290f76d824b26b7f73990678"
+deck = "93b5c000491d8575e5b3b545fe48405e685d1412efa48b9a0551637877d1320b"
 dut = "d5c4009de00efbc07ad6c612fb371ef8cd7a837a49bec1a27f1d1729a2d8440d"
 
 [task.evaluation.pre_layout.jobs.source_nominal.measurements.output_bias]
@@ -499,6 +511,10 @@ unit = "V/V"
 value = 4.814877853977e-05
 unit = "W"
 
+[task.evaluation.pre_layout.jobs.source_nominal.output_sha256]
+ac = "7f3d1b944988ff00b215d75dc34da587af36b5c3c4a32f1b60fb38048a111f8e"
+op = "e134a725d52c23c467cafd58e24cde7c4bd256a09b151d7bf174430d29776fdd"
+
 [toolchain.bindings]
 "layout.artifact" = "artifact"
 "layout.drc" = "drc"
@@ -511,7 +527,7 @@ unit = "W"
 type = "klayout-docker"
 
 [toolchain.backends.artifact.settings]
-image = "iclayout-bench-tools:local"
+image = "iclayout-eda-open:local"
 check = "artifact"
 timeout_seconds = 600
 
@@ -522,7 +538,7 @@ type = "klayout-docker"
 support = "klayout"
 
 [toolchain.backends.drc.settings]
-image = "iclayout-bench-tools:local"
+image = "iclayout-eda-open:local"
 check = "drc"
 support = "build/support/output-stage-klayout"
 profile = "drc-upstream.json"
@@ -535,7 +551,7 @@ type = "klayout-docker"
 support = "klayout"
 
 [toolchain.backends.lvs.settings]
-image = "iclayout-bench-tools:local"
+image = "iclayout-eda-open:local"
 check = "lvs"
 support = "build/support/output-stage-klayout"
 profile = "lvs-upstream.json"
@@ -548,7 +564,7 @@ type = "magic-rc-docker"
 support = "magic"
 
 [toolchain.backends.rc.settings]
-image = "iclayout-bench-tools:local"
+image = "iclayout-eda-open:local"
 support = "build/support/output-stage-magic"
 technology = "magic/ihp-sg13g2.tech"
 tech_name = "ihp-sg13g2"
@@ -560,7 +576,7 @@ timeout_seconds = 600
 type = "klayout-geometry-docker"
 
 [toolchain.backends.geometry.settings]
-image = "iclayout-bench-tools:local"
+image = "iclayout-eda-open:local"
 timeout_seconds = 120
 
 [toolchain.backends.simulation]
@@ -570,7 +586,10 @@ type = "ngspice-docker"
 support = "analog-models"
 
 [toolchain.backends.simulation.settings]
-image = "iclayout-bench-tools:local"
+max_parallel_jobs = 8
+threads = 1
+cpu_budget = 8
+image = "iclayout-eda-open:local"
 support = "build/support/output-stage-models"
 timeout_seconds = 600
 

tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/output_stage/materials/testbench.spice

@@ -23,6 +23,7 @@ let output_bias = v(vout)
 let supply_power = -v(vdd)*i(VDD)
 print output_bias supply_power
 write output-op.raw all
+save i(vdd) v(dn4) v(vdd) v(vout)
 ac dec 40 1 1g
 let output_gain_signed = -v(vout)/v(dn4)
 let gain_magnitude = abs(output_gain_signed)

tasks/ihp-sg13g2/IHP-AnalogAcademy/cases/output_stage/problem.md

@@ -11,9 +11,7 @@ output-response limits after candidate-derived RC extraction.
 
 ## Inputs and Interface
 
-In addition to this problem, the solver receives the following declared
-materials. The structured constraints
-and evaluation plan are also available at runtime through `/protocol/task.json`.
+In addition to this description, the solver receives the following declared materials. The runtime `/protocol/task.json` also supplies structured constraints and the evaluation plan.
 
 | Input | Purpose |
 |---|---|
@@ -21,8 +19,7 @@ and evaluation plan are also available at runtime through `/protocol/task.json`.
 | [materials/circuit.spice](materials/circuit.spice) | Pre-layout simulator netlist |
 | [materials/testbench.spice](materials/testbench.spice) | Bias, load, AC sweep, and public measurement expressions |
 
-Use one external label on each distinct conductor. Internal nodes must not be
-declared as external ports.
+Use one external label per independent conductor; internal nodes must not be declared as external ports.
 
 | Port | Function | Nominal connection |
 |---|---|---|
@@ -40,8 +37,7 @@ replica `MM9`, long-channel NMOS pull-down `MM6`, MIM compensation capacitor
 
 ## Operating Conditions
 
-The pre-layout and candidate-derived simulations use the supplied deck and the
-same nominal model and parameter values.
+Source and candidate extracted circuits use the supplied decks with identical nominal models and parameters.
 
 | Parameter | Setting |
 |---|---|
@@ -62,15 +58,9 @@ Submit a readable GDSII file with a nonempty `output_stage` top cell. The file
 must be at most 10 MiB (10,485,760 bytes) and must contain the complete
 hierarchy needed by the target cell.
 
-The evaluator runs the pinned SG13G2 main and additional maximal DRC rules in
-deep mode, with density and antenna checks disabled and no waivers. LVS uses the
-current `lvs-upstream.json` profile and strict named-port matching against
-`materials/circuit.cdl`; every declared port must stay on its own conductor
-with the declared connectivity and device parameters. Port names are matched
-case-insensitively.
+Use the pinned SG13G2 main rules and additional maximal DRC rules in deep mode, with density and antenna checks disabled and no waivers. LVS uses the current `lvs-upstream.json` configuration and strictly matches named ports against `materials/circuit.cdl`, preserving each port's independent conductor, connections and device parameters; port names are case insensitive.
 
-The functional outline is the recursive bounding box of polygons on these
-SG13G2 datatype-0 layers, including child cells and the complete routing stack:
+The functional outline is the recursive bounding box of polygons on the following SG13G2 datatype-0 layers, including child cells and every routing layer:
 
 `1, 3, 5, 6, 7, 8, 10, 11, 13, 14, 19, 24, 26, 28, 29, 30, 31, 32, 33, 35, 36, 40, 44, 46, 49, 50, 51, 52, 53, 55, 58, 66, 67, 90, 101, 111, 125, 126, 128, 129, 133, 134, 139, 152`.
 
@@ -89,54 +79,28 @@ outside the declared scope. The finite source taps are used only in source calib
 
 ## Electrical Requirements and Scoring
 
-Physical checks and declared functional bounds remain mandatory. Quality has no
-fixed allowed-degradation threshold. Each `source_*` job simulates the declared
-source circuit with exactly the same testbench, model resources, parameters,
-load and measurement window as its paired extracted-candidate job. A source
-observation is the 100-point electrical baseline; it is independent of the
-submitted GDS. All individual pairs are retained in the evaluation report.
-
-For a post-layout observation x and its source observation b:
-
-- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,
-  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;
-  s is a normalization floor, not an allowed degradation or pass threshold.
-- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.
-- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and
-  zero-valued operating points are never divided directly.
-
-Scoring uses `layout`. A metric uses its worst paired quality q. The score is
-S = 100 * product(q_i ** w_i), including area quality
-q_area = area_reference / candidate_functional_area. The weights below sum to
-one. Dimensions describe measurements but do not determine their weights.
-Physical or functional rejection scores zero; missing or invalid measurements
-produce an unknown score, including measurements with zero weight.
-Source-equivalent performance at the area reference scores 100; improvements
-can exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.
-
-Measurement definitions below use the supplied SPICE node/source names.
-`v(n)` is node voltage and `i(V)` is current into a voltage source; delivered
-power therefore uses a minus sign. `db(z)=20*log10(abs(z))`, `mag/abs`
-denote magnitude, and `cph` is continuous phase in radians. `find`, `when`,
-`from/to`, and `rise/fall` retain the deck's interpolation, window and
-crossing conventions; SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/
-milli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv`
-mean the stated window average, extrema and sampled derivative. All
-declared conditions are measured separately and paired with the same
-source condition; a group uses its worst paired quality.
-
-| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | Dimension |
+Physical checks and the declared functional bounds must pass. Quality scoring imposes no fixed degradation allowance. Each `source_*` job and its corresponding candidate extracted circuit use exactly the same testbench, model resources, parameters, loads and measurement windows. Independent source observations define the 100-point electrical baseline without depending on the submitted GDS; reports retain every paired result.
+
+Let x be the post-layout measurement and b the source-circuit measurement under the same conditions:
+
+- Ratio normalization: maximize with q = x/b and minimize with q = b/x. When a numerical scale s is declared, use (x+s)/(b+s) and its reciprocal, respectively. The scale handles zero values as a normalization floor; it is neither an allowed degradation nor an acceptance bound.
+- Amplitude in dB: maximize with q = 10^((x-b)/20) and minimize with its reciprocal.
+- Target normalization: q = 1/(1+abs(x-b)/s), where s is the declared physical scale. Signed or zero-valued operating points are not divided directly.
+
+Use `layout` scoring. Each metric takes its worst paired quality q, and the total score is S = 100 * product(q_i ** w_i), with area quality q_area = area_reference / candidate_functional_area. The weights below sum to 1; metric dimensions describe measurements and do not determine weights. Physical or functional rejection scores zero; missing or invalid measurements leave the score unknown, and zero-weight observations must also be valid. Matching source-circuit performance at the reference area scores 100 points; better valid solutions may exceed 100. Weights express quality tradeoffs rather than hard bounds.
+
+The measurements below use the supplied SPICE node and source names. `v(n)` is a node voltage; `i(V)` is current flowing into a voltage source, so delivered power uses a negative sign. `db(z)=20*log10(abs(z))`; `mag/abs` denote magnitude, and `cph` denotes continuous phase in radians. `find`, `when`, `from/to` and `rise/fall` follow the deck's interpolation, window and crossing conventions. SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/milli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv` represent window averages, extrema and sampled derivatives. Measure each operating condition independently, pair it with the source result under that condition, and take the worst paired quality within each metric group.
+
+| Metric | Definition / observation | Unit | Quality normalization | Functional range | Scale | Dimension |
 | --- | --- | --- | --- | --- | --- | --- |
 | `output_gain` | AC: Value of `(abs((-v(vout)/v(dn4)))) at=1meg`. | V/V | maximize / ratio | 0 … +∞ | — | response |
 | `output_gain_high` | AC: Value of `(abs((-v(vout)/v(dn4)))) at=100meg`. | V/V | maximize / ratio | 0 … +∞ | — | response |
 | `output_bias` | DC operating point: `v(vout)`. | V | target / target | 0 … 1.2 | 1.2 | bias |
 | `supply_power` | DC operating point: `-v(vdd)*i(VDD)`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |
 
-Area reference: **2292.35 um2**. 6 expanded device instances; sum of device/contact envelopes 1466.0063 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.
-
-The capability coefficient remains **4**; it is independent of
-the reference-relative task score.
+Area reference: **2292.35 um2**. The expanded circuit has 6 device instances, a sum of device/contact envelopes 1466.0063 um2, a one-sided envelope margin of 0.6 um, a routing allowance of 50%, and a total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across both sides, and the envelope sum is displayed to four decimal places. MOS/passive envelopes use W/L (or resistor dimensions) and multiplicity, including explicit contacts and HBT emitter/contact envelopes. This is a frozen engineering estimate, not a process minimum or a proven achievable area.
 
+The capability coefficient is **4**, independent of this task's reference-normalized score.
 
 ### Score weights
 
@@ -154,22 +118,8 @@ Local gain stages: signal transfer 60.7%; operating points 6.07%; power 18.2%; a
 
 Solve budget: **3 hours**.
 
-Runtime environment and support resources are declared in
-`/protocol/resources.json` and `/protocol/harness.json`; the working directory is
-`/workspace`. KLayout performs artifact, DRC, LVS, and geometry checks; Magic
-performs RC extraction; ngspice runs the supplied deck with the reviewed SG13G2
-models. The evaluator provides the tool and PDK resources named by the case
-toolchain.
-
-For pre-layout simulation, use `materials/circuit.spice` as `dut.spice` beside
-the supplied testbench. The evaluator generates `parameters.spice` from the
-per-job values in `/protocol/task.json` and supplies the model paths and settings
-through the runtime resource bundle. For the submitted layout, the evaluator
-supplies the candidate-derived extracted netlist. If the harness declares
-`process-feedback`, the optional command is
-`python -I /protocol/process_check.py`; the final evaluation remains independent.
-
-Write the result to `/workspace/output/final.gds`, then run
-`python -I /protocol/submit.py` and wait for the submission receipt. Solver
-netlists, waveforms, and measurements are not accepted as substitutes for the
-independent evaluator inputs.
+See `/protocol/resources.json` and `/protocol/harness.json` for runtime and supporting resources; the working directory is `/workspace`. KLayout checks files, DRC, LVS and geometry, Magic extracts RC, and ngspice runs decks with reviewed SG13G2 models. The evaluator supplies tools and PDK specified by the contract toolchain.
+
+For source simulation, place `materials/circuit.spice` as `dut.spice` beside the testbench. The evaluator generates `parameters.spice` from per-job parameters in `/protocol/task.json`, supplying model paths and settings through the resource bundle; candidate evaluation uses its extracted netlist. If `process-feedback` is declared, run `python -I /protocol/process_check.py`; final evaluation is independent.
+
+Write the result to `/workspace/output/final.gds`, run `python -I /protocol/submit.py` and wait for a submission receipt. Solver netlists, waveforms and measurements cannot replace independent evaluator inputs.

tasks/ihp-sg13g2/TO_Apr2025/cases/160GHz_LNA/case.toml

@@ -1,15 +1,15 @@
-in_core = false
 kind = "layout_case"
 id = "TO_Apr2025.160GHz_LNA"
 title = "TO_Apr2025 160-derived four-stage LNA at 100 MHz"
 status = "qualified"
+in_core = false
 
 [[assets]]
 path = "materials/schematic.svg"
 role = "schematic"
 visibility = "maintainer"
 format = "svg"
-sha256 = "e8fd0801394151ea393920be920c74307331b14c1f69fce20b9ec4b98132eb34"
+sha256 = "3efe6d2ab9b53c7ed1d5c9647466b0447e0c2c3e41a6c864e00b3d8c686b7c5d"
 
 [[assets]]
 path = "reference/LNA160_FOUR_STAGE.gds"
@@ -27,24 +27,24 @@ environment = "ihp-sg13g2-lna160-derived-functional"
 
 [task.inputs.description]
 path = "problem.md"
-sha256 = "5e5a0af0922c789a4839a8864678558907f3d5061195d75c24a648250014a300"
 format = "text"
+sha256 = "0af53557020e96c00a175ed22da089ac02e8398e21ead951e4f7b7b0be3e295a"
 
 [task.inputs.netlist]
 path = "materials/circuit.cdl"
-sha256 = "26b815aa103d0d81b54e21c661b28860304a5d23be900d17192cbb92100be3c6"
 format = "spice"
 subcircuit = "LNA160_FOUR_STAGE"
+sha256 = "26b815aa103d0d81b54e21c661b28860304a5d23be900d17192cbb92100be3c6"
 
 [task.inputs.simulation]
 path = "materials/circuit.spice"
-sha256 = "ab1256da874a66cd7e70117d2e9758747cd99ba37c5fd0209180bcb558b1c379"
 format = "spice"
+sha256 = "ab1256da874a66cd7e70117d2e9758747cd99ba37c5fd0209180bcb558b1c379"
 
 [task.inputs.performance]
 path = "materials/testbench.spice"
-sha256 = "73cd2486a28743b5e6f7b28533c3f4f8a30dc2794e732b30791612ecebed9dc8"
 format = "spice"
+sha256 = "9dec3c3cdfe1917a14bfad09e13d88d043b331b061fa57515a22c4cb570fe1de"
 
 [task.constraints]
 quality = [
@@ -405,8 +405,11 @@ baseline = [
 ]
 normalization = "target"
 scale = 1.2
+
+[task.evaluation.metrics.requirement]
 lower = 0
 upper = 1.2
+rationale = "The declared node voltage or voltage span must remain within its ground-to-supply operating envelope; precision relative to the source remains a scored objective."
 
 [[task.evaluation.metrics]]
 id = "supply_current"
@@ -423,13 +426,16 @@ baseline = [
 ]
 normalization = "ratio"
 scale = 1e-12
+
+[task.evaluation.metrics.requirement]
 lower = 0
+rationale = "The declared powered circuit or driven switching network must consume nonnegative net supply/driver energy or quiescent current under the complete stated observation."
 
 [task.evaluation.pre_layout]
-source_report_sha256 = "0b95e12c8ba9c8144ab776bd212e0b732ddd10d86f9cd2c9afaf53f40b85a29e"
+source_report_sha256 = "246755dfc52757d48dbd754d54bbc32b55daf6d2848910528af13374ba769b62"
 
 [task.evaluation.pre_layout.backends]
-"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"ef9cb87fa27b849376472663b7362673979b89e012f161ba47bb5f6af6ede8eb\", \"compatibility\": null, \"execution_sha256\": \"5424b579002782bfddf0a729715b8fbf2a5f7f2b4cf14982d7616e352d5de9be\", \"image_id\": \"sha256:6562558774d43c085a289bbba696c55959eb8051a0996f96633451fbeb9c652d\", \"limits\": {\"cpus\": 4, \"memory_mb\": 4096, \"pids\": 256}, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"9bd461e0d9b1be65a6cd4e1c2352feb4a9aedfbc1fb32828bccfdba2f208dba2\", \"timeout_seconds\": 600.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}"
+"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"dfbdf2f93297bbe7d8b576fb988504bd0ecf85b93ef47c314a0f2c9c8830c3e7\", \"compatibility\": null, \"cpu_budget\": 8, \"execution_sha256\": \"495aa9623759f70228a236eb4825c2ae443ef6a741816d8cfc17d1830841dcef\", \"image_id\": \"sha256:060fee64f9f6e71a647e5e958b788d723c9d51d2928ff93e6a295db1959bc37f\", \"limits\": {\"cpus\": 8, \"memory_mb\": 4096, \"pids\": 256}, \"max_parallel_jobs\": 8, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"7b432fb4cf7911c02eacee3ceaad658c961f16f22bc890ee7ad89b3e44108141\", \"thread_environment\": {\"OMP_NUM_THREADS\": \"1\", \"OMP_THREAD_LIMIT\": \"1\"}, \"threads\": 1, \"timeout_seconds\": 600.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}"
 
 [task.evaluation.pre_layout.jobs.source_nominal]
 operation = "circuit.simulate"
@@ -459,7 +465,7 @@ ac = "frequency_response.raw"
 
 [task.evaluation.pre_layout.jobs.source_nominal.input_sha256]
 circuit = "ab1256da874a66cd7e70117d2e9758747cd99ba37c5fd0209180bcb558b1c379"
-deck = "73cd2486a28743b5e6f7b28533c3f4f8a30dc2794e732b30791612ecebed9dc8"
+deck = "9dec3c3cdfe1917a14bfad09e13d88d043b331b061fa57515a22c4cb570fe1de"
 
 [task.evaluation.pre_layout.jobs.source_nominal.measurements.gain_db]
 value = 40.84071
@@ -481,6 +487,10 @@ unit = "V"
 value = 0.8
 unit = "V"
 
+[task.evaluation.pre_layout.jobs.source_nominal.output_sha256]
+op = "8d3601a640cbbdffb5c01f968995ccc258e5bf8ea99f3b3fdcd6ac12583781e3"
+ac = "7c534f3430aabd2e9dc6fdb583dc8552ce6d8cafd1cd75ef135af645a9cdd650"
+
 [toolchain.bindings]
 "layout.artifact" = "artifact"
 "layout.drc" = "drc"
@@ -493,7 +503,7 @@ unit = "V"
 type = "klayout-docker"
 
 [toolchain.backends.artifact.settings]
-image = "iclayout-bench-tools:local"
+image = "iclayout-eda-open:local"
 check = "artifact"
 timeout_seconds = 600
 
@@ -504,7 +514,7 @@ type = "klayout-docker"
 support = "klayout"
 
 [toolchain.backends.drc.settings]
-image = "iclayout-bench-tools:local"
+image = "iclayout-eda-open:local"
 check = "drc"
 support = "build/support/lna160-klayout"
 profile = "drc-upstream.json"
@@ -517,7 +527,7 @@ type = "klayout-docker"
 support = "klayout"
 
 [toolchain.backends.lvs.settings]
-image = "iclayout-bench-tools:local"
+image = "iclayout-eda-open:local"
 check = "lvs"
 support = "build/support/lna160-klayout"
 profile = "lvs-upstream.json"
@@ -527,7 +537,7 @@ timeout_seconds = 600
 type = "klayout-geometry-docker"
 
 [toolchain.backends.geometry.settings]
-image = "iclayout-bench-tools:local"
+image = "iclayout-eda-open:local"
 timeout_seconds = 600
 
 [toolchain.backends.parasitics]
@@ -538,7 +548,7 @@ klayout_support = "klayout"
 magic_support = "magic"
 
 [toolchain.backends.parasitics.settings]
-image = "iclayout-bench-tools:local"
+image = "iclayout-eda-open:local"
 klayout_support = "build/support/lna160-klayout"
 klayout_profile = "lvs-upstream.json"
 magic_support = "build/support/lna160-magic"
@@ -555,7 +565,10 @@ type = "ngspice-docker"
 support = "hbt-models"
 
 [toolchain.backends.simulation.settings]
-image = "iclayout-bench-tools:local"
+max_parallel_jobs = 8
+threads = 1
+cpu_budget = 8
+image = "iclayout-eda-open:local"
 support = "build/support/lna160-hbt-models"
 timeout_seconds = 600
 

tasks/ihp-sg13g2/TO_Apr2025/cases/160GHz_LNA/materials/testbench.spice

@@ -27,6 +27,7 @@ echo out_bias = $&out_bias
 echo i_vdd = $&i_vdd
 echo i_vbias = $&i_vbias
 write operating_point.raw all
+save i(vbias) i(vdd) v(in) v(out)
 ac dec 40 1meg 1gig
 let gain_db=db(v(out)/v(in))
 meas ac gain_db find gain_db at=100meg

tasks/ihp-sg13g2/TO_Apr2025/cases/160GHz_LNA/problem.md

@@ -10,8 +10,7 @@ checks and nominal post-layout measurements below.
 
 ## Inputs and Interface
 
-In addition to this problem, the runtime task supplies the following declared
-inputs:
+In addition to this description, the runtime task supplies the following declared inputs:
 
 | Input | Purpose |
 |---|---|
@@ -67,12 +66,9 @@ also pass strict named-port LVS against `materials/circuit.cdl`, including
 the five ports, HBT multiplicities, passive geometry and explicit substrate
 tap. Artifact, DRC, LVS and geometry gates all precede candidate extraction.
 
-The GDS must include the complete target hierarchy. Port names are matched
-case-insensitively; each declared port must remain on its own conductor with
-the declared connectivity.
+The GDS must contain the complete target hierarchy. Port names are case insensitive; each declared port must retain its conductor and declared connections.
 
-The functional outline is the recursive bounding box of polygons on these
-SG13G2 datatype-0 layers, including child cells and the complete routing stack:
+The functional outline is the recursive bounding box of polygons on the following SG13G2 datatype-0 layers, including child cells and every routing layer:
 
 `1, 3, 5, 6, 7, 8, 10, 11, 13, 14, 19, 24, 26, 28, 29, 30, 31, 32, 33, 35, 36, 40, 44, 46, 49, 50, 51, 52, 53, 55, 58, 66, 67, 90, 101, 111, 125, 126, 128, 129, 133, 134, 139, 152`.
 
@@ -95,57 +91,31 @@ internal-node aliases or simulator global-ground substitutions are permitted.
 
 ## Electrical Requirements and Scoring
 
-Physical checks and declared functional bounds remain mandatory. Quality has no
-fixed allowed-degradation threshold. Each `source_*` job simulates the declared
-source circuit with exactly the same testbench, model resources, parameters,
-load and measurement window as its paired extracted-candidate job. A source
-observation is the 100-point electrical baseline; it is independent of the
-submitted GDS. All individual pairs are retained in the evaluation report.
-
-For a post-layout observation x and its source observation b:
-
-- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,
-  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;
-  s is a normalization floor, not an allowed degradation or pass threshold.
-- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.
-- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and
-  zero-valued operating points are never divided directly.
-
-Scoring uses `layout`. A metric uses its worst paired quality q. The score is
-S = 100 * product(q_i ** w_i), including area quality
-q_area = area_reference / candidate_functional_area. The weights below sum to
-one. Dimensions describe measurements but do not determine their weights.
-Physical or functional rejection scores zero; missing or invalid measurements
-produce an unknown score, including measurements with zero weight.
-Source-equivalent performance at the area reference scores 100; improvements
-can exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.
-
-Measurement definitions below use the supplied SPICE node/source names.
-`v(n)` is node voltage and `i(V)` is current into a voltage source; delivered
-power therefore uses a minus sign. `db(z)=20*log10(abs(z))`, `mag/abs`
-denote magnitude, and `cph` is continuous phase in radians. `find`, `when`,
-`from/to`, and `rise/fall` retain the deck's interpolation, window and
-crossing conventions; SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/
-milli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv`
-mean the stated window average, extrema and sampled derivative. All
-declared conditions are measured separately and paired with the same
-source condition; a group uses its worst paired quality.
-
-| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | Dimension |
+Physical checks and the declared functional bounds must pass. Quality scoring imposes no fixed degradation allowance. Each `source_*` job and its corresponding candidate extracted circuit use exactly the same testbench, model resources, parameters, loads and measurement windows. Independent source observations define the 100-point electrical baseline without depending on the submitted GDS; reports retain every paired result.
+
+Let x be the post-layout measurement and b the source-circuit measurement under the same conditions:
+
+- Ratio normalization: maximize with q = x/b and minimize with q = b/x. When a numerical scale s is declared, use (x+s)/(b+s) and its reciprocal, respectively. The scale handles zero values as a normalization floor; it is neither an allowed degradation nor an acceptance bound.
+- Amplitude in dB: maximize with q = 10^((x-b)/20) and minimize with its reciprocal.
+- Target normalization: q = 1/(1+abs(x-b)/s), where s is the declared physical scale. Signed or zero-valued operating points are not divided directly.
+
+Use `layout` scoring. Each metric takes its worst paired quality q, and the total score is S = 100 * product(q_i ** w_i), with area quality q_area = area_reference / candidate_functional_area. The weights below sum to 1; metric dimensions describe measurements and do not determine weights. Physical or functional rejection scores zero; missing or invalid measurements leave the score unknown, and zero-weight observations must also be valid. Matching source-circuit performance at the reference area scores 100 points; better valid solutions may exceed 100. Weights express quality tradeoffs rather than hard bounds.
+
+The measurements below use the supplied SPICE node and source names. `v(n)` is a node voltage; `i(V)` is current flowing into a voltage source, so delivered power uses a negative sign. `db(z)=20*log10(abs(z))`; `mag/abs` denote magnitude, and `cph` denotes continuous phase in radians. `find`, `when`, `from/to` and `rise/fall` follow the deck's interpolation, window and crossing conventions. SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/milli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv` represent window averages, extrema and sampled derivatives. Measure each operating condition independently, pair it with the source result under that condition, and take the worst paired quality within each metric group.
+
+| Metric | Definition / observation | Unit | Quality normalization | Functional range | Scale | Dimension |
 | --- | --- | --- | --- | --- | --- | --- |
 | `gain_db` | AC: Value of `(db(v(out)/v(in))) at=100meg`. | dB | maximize / db20 | −∞ … +∞ | — | response |
 | `output_bias` | DC operating point: `v(out)`. | V | target / target | 0 … 1.2 | 1.2 | bias |
 | `supply_current` | DC operating point: `-i(vdd)`. | A | minimize / ratio | 0 … +∞ | 1e-12 | supply |
 
-Area reference: **1326.32 um2**. 16 expanded device instances; sum of device/contact envelopes 836.9640 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.
-
-The capability coefficient remains **5**; it is independent of
-the reference-relative task score.
+Area reference: **1326.32 um2**. The expanded circuit has 16 device instances, a sum of device/contact envelopes 836.9640 um2, a one-sided envelope margin of 0.6 um, a routing allowance of 50%, and a total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across both sides, and the envelope sum is displayed to four decimal places. MOS/passive envelopes use W/L (or resistor dimensions) and multiplicity, including explicit contacts and HBT emitter/contact envelopes. This is a frozen engineering estimate, not a process minimum or a proven achievable area.
 
+The capability coefficient is **5**, independent of this task's reference-normalized score.
 
 ### Score weights
 
-SiGe low-frequency transfer tasks: signal transfer 68.8%; bias 5.29%; supply cost 15.9%; area 10%. Each objective's weight is divided equally among its metrics.
+SiGe low-frequency transfer: signal transfer 68.8%, bias 5.29%, supply cost 15.9%, area 10%; each objective weight is divided equally among its metrics.
 
 | Metric | Weight |
 | --- | ---: |
@@ -158,12 +128,7 @@ SiGe low-frequency transfer tasks: signal transfer 68.8%; bias 5.29%; supply cos
 
 Solve budget: **3 hours**.
 
-Discover the supplied task, resources, harness and constraints from
-`/protocol/task.json`, `/protocol/resources.json` and
-`/protocol/harness.json`. Use the tool and PDK resources selected by the
-runtime environment. If the harness declares `process-feedback`, request
-an optional frozen process check with `python -I /protocol/process_check.py`;
-the final evaluation remains independent.
+Discover the task, resources, protocol and constraints through `/protocol/task.json`, `/protocol/resources.json`, `/protocol/harness.json`, and use the tools and PDK specified by the runtime environment. If the protocol declares `process-feedback`, run `python -I /protocol/process_check.py` to request an intermediate check using the frozen flow; final evaluation runs independently.
 
 Write the answer to `/workspace/output/final.gds` as a GDS file with top cell
 `LNA160_FOUR_STAGE` and wait for the submission receipt:
@@ -172,5 +137,4 @@ Write the answer to `/workspace/output/final.gds` as a GDS file with top cell
 python -I /protocol/submit.py
 ```
 
-The evaluator uses the submitted snapshot for all physical checks, extraction
-and simulations.
+All physical checks, extraction and simulation use the submitted snapshot.

tasks/ihp-sg13g2/TO_Apr2025/cases/40_GHZ_LOW_NOISE_TIA/case.toml

@@ -1,15 +1,15 @@
-in_core = false
 kind = "layout_case"
 id = "TO_Apr2025.40_GHZ_LOW_NOISE_TIA"
 title = "TO_Apr2025 40 GHz low-noise single-ended TIA"
 status = "qualified"
+in_core = false
 
 [[assets]]
 path = "materials/schematic.svg"
 role = "schematic"
 visibility = "maintainer"
 format = "svg"
-sha256 = "de9db61acedff476ca6403a72f828a9b43e95a296ea7f9220562876179cded52"
+sha256 = "9d8bc219eccf04d45f518366d400222c9c33b1b78663e09c1aa846c60f9e688f"
 
 [[assets]]
 path = "reference/FDM_QNC_00_LN_TIA.gds"
@@ -27,24 +27,24 @@ environment = "ihp-sg13g2-to-40ghz-lvs"
 
 [task.inputs.description]
 path = "problem.md"
-sha256 = "4e1bf1e9856e4ca70e160b47ab5585fe97b6da4e48c97cc3287c62ff3fada74a"
 format = "text"
+sha256 = "dcc2226fca41d92bedd955c19f360f9bd49d364512e11461c499510dbfc831f0"
 
 [task.inputs.netlist]
 path = "materials/circuit.cdl"
-sha256 = "17a094c09698acfbe6a25a50d3a0292ebb82fd82b7e21269442bcdd4fa3c0d45"
 format = "spice"
 subcircuit = "FDM_QNC_00_LN_TIA"
+sha256 = "17a094c09698acfbe6a25a50d3a0292ebb82fd82b7e21269442bcdd4fa3c0d45"
 
 [task.inputs.simulation]
 path = "materials/circuit.spice"
-sha256 = "62f7df0322744074c141d2bbbd3d5e9537fb06ee02729758e5f787a6de56c515"
 format = "spice"
+sha256 = "62f7df0322744074c141d2bbbd3d5e9537fb06ee02729758e5f787a6de56c515"
 
 [task.inputs.performance]
 path = "materials/testbench.spice"
-sha256 = "4973b1a2b9d7ca896646e106df79170391670961e01377f4d4dd2c2109a9dae4"
 format = "spice"
+sha256 = "2aee1a67cca0ecbdb43a34da2f0891063e81857771f4380abed0538d548f9040"
 
 [task.constraints]
 quality = [
@@ -457,7 +457,10 @@ baseline = [
     "source_positive:transimpedance_low",
 ]
 normalization = "ratio"
+
+[task.evaluation.metrics.requirement]
 lower = 0
+rationale = "The declared response magnitude, impedance, capacitance, amplitude or absolute return-ratio diagnostic has a nonnegative measurement domain; its value remains a quality or diagnostic observation."
 
 [[task.evaluation.metrics]]
 id = "transimpedance_high"
@@ -477,7 +480,10 @@ baseline = [
     "source_positive:transimpedance_high",
 ]
 normalization = "ratio"
+
+[task.evaluation.metrics.requirement]
 lower = 0
+rationale = "The declared response magnitude, impedance, capacitance, amplitude or absolute return-ratio diagnostic has a nonnegative measurement domain; its value remains a quality or diagnostic observation."
 
 [[task.evaluation.metrics]]
 id = "input_bias"
@@ -498,8 +504,11 @@ baseline = [
 ]
 normalization = "target"
 scale = 2.1
+
+[task.evaluation.metrics.requirement]
 lower = 0
 upper = 2.1
+rationale = "The declared node voltage or voltage span must remain within its ground-to-supply operating envelope; precision relative to the source remains a scored objective."
 
 [[task.evaluation.metrics]]
 id = "output_bias"
@@ -520,8 +529,11 @@ baseline = [
 ]
 normalization = "target"
 scale = 2.1
+
+[task.evaluation.metrics.requirement]
 lower = 0
 upper = 2.1
+rationale = "The declared node voltage or voltage span must remain within its ground-to-supply operating envelope; precision relative to the source remains a scored objective."
 
 [[task.evaluation.metrics]]
 id = "supply_power"
@@ -541,14 +553,17 @@ baseline = [
     "source_positive:supply_power",
 ]
 normalization = "ratio"
-lower = 0
 scale = 1e-12
 
+[task.evaluation.metrics.requirement]
+lower = 0
+rationale = "The declared powered circuit or driven switching network must consume nonnegative net supply/driver energy or quiescent current under the complete stated observation."
+
 [task.evaluation.pre_layout]
-source_report_sha256 = "1ffd46800506bade3d1b06c7a06ba55a3ae9860cfdb7fae985ea26b8e36d2dfc"
+source_report_sha256 = "68069e1e105c99222fcb6f755fad21514d774d3c5e6704f5f81b2c3f04227499"
 
 [task.evaluation.pre_layout.backends]
-"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"ef9cb87fa27b849376472663b7362673979b89e012f161ba47bb5f6af6ede8eb\", \"compatibility\": null, \"execution_sha256\": \"5424b579002782bfddf0a729715b8fbf2a5f7f2b4cf14982d7616e352d5de9be\", \"image_id\": \"sha256:6562558774d43c085a289bbba696c55959eb8051a0996f96633451fbeb9c652d\", \"limits\": {\"cpus\": 4, \"memory_mb\": 4096, \"pids\": 256}, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"cb523c6d8d1360cb230ef661aff6bf7e231b68cb3b2effe84934228456a0d7d1\", \"timeout_seconds\": 120.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}"
+"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"dfbdf2f93297bbe7d8b576fb988504bd0ecf85b93ef47c314a0f2c9c8830c3e7\", \"compatibility\": null, \"cpu_budget\": 8, \"execution_sha256\": \"495aa9623759f70228a236eb4825c2ae443ef6a741816d8cfc17d1830841dcef\", \"image_id\": \"sha256:060fee64f9f6e71a647e5e958b788d723c9d51d2928ff93e6a295db1959bc37f\", \"limits\": {\"cpus\": 8, \"memory_mb\": 4096, \"pids\": 256}, \"max_parallel_jobs\": 8, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"7b432fb4cf7911c02eacee3ceaad658c961f16f22bc890ee7ad89b3e44108141\", \"thread_environment\": {\"OMP_NUM_THREADS\": \"1\", \"OMP_THREAD_LIMIT\": \"1\"}, \"threads\": 1, \"timeout_seconds\": 120.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}"
 
 [task.evaluation.pre_layout.jobs.source_negative]
 operation = "circuit.simulate"
@@ -580,7 +595,7 @@ ac = "frequency_response.raw"
 
 [task.evaluation.pre_layout.jobs.source_negative.input_sha256]
 circuit = "62f7df0322744074c141d2bbbd3d5e9537fb06ee02729758e5f787a6de56c515"
-deck = "4973b1a2b9d7ca896646e106df79170391670961e01377f4d4dd2c2109a9dae4"
+deck = "2aee1a67cca0ecbdb43a34da2f0891063e81857771f4380abed0538d548f9040"
 
 [task.evaluation.pre_layout.jobs.source_negative.measurements.input_bias]
 value = 0.7692856317372
@@ -614,6 +629,10 @@ unit = "ohm"
 value = 635.1806
 unit = "ohm"
 
+[task.evaluation.pre_layout.jobs.source_negative.output_sha256]
+op = "2b9e71b969b0c266076638e209a551c2050c3b2ef62939e435ebf0edf1d538a3"
+ac = "a29c0604888c2afeac5f69ea478f9b1edc766df3c99dc4dfbe9636f983822615"
+
 [task.evaluation.pre_layout.jobs.source_zero]
 operation = "circuit.simulate"
 
@@ -644,7 +663,7 @@ ac = "frequency_response.raw"
 
 [task.evaluation.pre_layout.jobs.source_zero.input_sha256]
 circuit = "62f7df0322744074c141d2bbbd3d5e9537fb06ee02729758e5f787a6de56c515"
-deck = "4973b1a2b9d7ca896646e106df79170391670961e01377f4d4dd2c2109a9dae4"
+deck = "2aee1a67cca0ecbdb43a34da2f0891063e81857771f4380abed0538d548f9040"
 
 [task.evaluation.pre_layout.jobs.source_zero.measurements.input_bias]
 value = 0.7969694832621
@@ -678,6 +697,10 @@ unit = "ohm"
 value = 447.0679
 unit = "ohm"
 
+[task.evaluation.pre_layout.jobs.source_zero.output_sha256]
+op = "cd8f3569e233aa6858b3f418ade3b3524211f8257e3a239f74fbaf4df222cd33"
+ac = "98e56751f590f9b2fc74dbd82c3ca1f08dae9f58f7262044935b2fbfdee2e789"
+
 [task.evaluation.pre_layout.jobs.source_positive]
 operation = "circuit.simulate"
 
@@ -708,7 +731,7 @@ ac = "frequency_response.raw"
 
 [task.evaluation.pre_layout.jobs.source_positive.input_sha256]
 circuit = "62f7df0322744074c141d2bbbd3d5e9537fb06ee02729758e5f787a6de56c515"
-deck = "4973b1a2b9d7ca896646e106df79170391670961e01377f4d4dd2c2109a9dae4"
+deck = "2aee1a67cca0ecbdb43a34da2f0891063e81857771f4380abed0538d548f9040"
 
 [task.evaluation.pre_layout.jobs.source_positive.measurements.input_bias]
 value = 0.8137989315389
@@ -742,6 +765,10 @@ unit = "ohm"
 value = 69.38208
 unit = "ohm"
 
+[task.evaluation.pre_layout.jobs.source_positive.output_sha256]
+op = "31740e38ef2a8f5fcfaa48247ff5a3077d3b013dcc554cefb513296dbe48ac78"
+ac = "c9c42b8c3926055f1cf898675a4e2bfb8c42ee6c14d584842b776a40771cdf55"
+
 [qualification]
 reference = "reference/FDM_QNC_00_LN_TIA.gds"
 
@@ -757,7 +784,7 @@ reference = "reference/FDM_QNC_00_LN_TIA.gds"
 type = "klayout-geometry-docker"
 
 [toolchain.backends.geometry.settings]
-image = "iclayout-bench-tools:local"
+image = "iclayout-eda-open:local"
 timeout_seconds = 120
 
 [toolchain.backends.drc]
@@ -767,7 +794,7 @@ type = "klayout-docker"
 support = "klayout"
 
 [toolchain.backends.drc.settings]
-image = "iclayout-bench-tools:local"
+image = "iclayout-eda-open:local"
 check = "drc"
 support = "build/support/to-40ghz-klayout"
 profile = "drc-upstream.json"
@@ -780,7 +807,7 @@ type = "klayout-docker"
 support = "klayout"
 
 [toolchain.backends.lvs.settings]
-image = "iclayout-bench-tools:local"
+image = "iclayout-eda-open:local"
 check = "lvs"
 support = "build/support/to-40ghz-klayout"
 profile = "lvs-upstream.json"
@@ -790,7 +817,7 @@ timeout_seconds = 600
 type = "klayout-docker"
 
 [toolchain.backends.artifact.settings]
-image = "iclayout-bench-tools:local"
+image = "iclayout-eda-open:local"
 check = "artifact"
 timeout_seconds = 60
 
@@ -801,7 +828,10 @@ type = "ngspice-docker"
 support = "hbt-models"
 
 [toolchain.backends.simulation.settings]
-image = "iclayout-bench-tools:local"
+max_parallel_jobs = 8
+threads = 1
+cpu_budget = 8
+image = "iclayout-eda-open:local"
 support = "build/support/to-40ghz-hbt-models"
 timeout_seconds = 120
 
@@ -813,7 +843,7 @@ klayout_support = "klayout"
 magic_support = "magic"
 
 [toolchain.backends.parasitics.settings]
-image = "iclayout-bench-tools:local"
+image = "iclayout-eda-open:local"
 klayout_support = "build/support/to-40ghz-klayout"
 klayout_profile = "lvs-upstream.json"
 magic_support = "build/support/to-40ghz-magic"

tasks/ihp-sg13g2/TO_Apr2025/cases/40_GHZ_LOW_NOISE_TIA/materials/testbench.spice

@@ -32,6 +32,7 @@ let supply3_current = -i(VCC3)
 let supply_power = -v(vcc1)*i(VCC1)-v(vcc2)*i(VCC2)-v(vcc3)*i(VCC3)
 print input_bias output_bias supply1_current supply2_current supply3_current supply_power
 write operating_point.raw all
+save i(vcc1) i(vcc2) i(vcc3) i(vsense) v(rfin) v(rfout) v(vcc1) v(vcc2) v(vcc3)
 ac dec 40 1meg 100meg
 let signed_transimpedance = real(v(RFout)/i(VSENSE))
 let magnitude_transimpedance = mag(v(RFout)/i(VSENSE))

tasks/ihp-sg13g2/TO_Apr2025/cases/40_GHZ_LOW_NOISE_TIA/problem.md

@@ -10,8 +10,7 @@ physical checks and nominal post-layout measurements below.
 
 ## Inputs and Interface
 
-In addition to this problem, the runtime task supplies the following declared
-inputs:
+In addition to this description, the runtime task supplies the following declared inputs:
 
 | Input | Purpose |
 |---|---|
@@ -60,20 +59,11 @@ calculated from the three independent supply sources.
 
 ## Physical Requirements
 
-The candidate GDS must be readable, non-empty and no larger than 32 MiB. It
-must pass the pinned SG13G2 main and additional maximal DRC scopes in deep
-mode without waivers; density and antenna checks are outside this declared scope. It must
-also pass strict named-port LVS against `materials/circuit.cdl`, including
-the six ports, device multiplicities, passive geometry and explicit substrate
-tap. Artifact, DRC, strict LVS and geometry gates all precede candidate
-extraction.
+Candidate GDS must be readable, nonempty and at most 32 MiB. Use pinned SG13G2 main and additional maximal DRC rules in deep mode without waivers; density and antenna are outside the declared scope. Strict named-port LVS compares against `materials/circuit.cdl`, checking six ports, device multiplicities, passive geometry and explicit substrate contacts. File, DRC, strict LVS and geometry checks all precede candidate extraction.
 
-The GDS must include the complete target hierarchy. Port names are matched
-case-insensitively; each declared port must remain on its own conductor with
-the declared connectivity.
+The GDS must contain the complete target hierarchy. Port names are case insensitive; each declared port must retain its conductor and declared connections.
 
-The functional outline is the recursive bounding box of polygons on these
-SG13G2 datatype-0 layers, including child cells and the complete routing stack:
+The functional outline is the recursive bounding box of polygons on the following SG13G2 datatype-0 layers, including child cells and every routing layer:
 
 `1, 3, 5, 6, 7, 8, 10, 11, 13, 14, 19, 24, 26, 28, 29, 30, 31, 32, 33, 35, 36, 40, 44, 46, 49, 50, 51, 52, 53, 55, 58, 66, 67, 90, 101, 111, 125, 126, 128, 129, 133, 134, 139, 152`.
 
@@ -97,43 +87,19 @@ alias must not replace the explicit source substrate connection.
 
 ## Electrical Requirements and Scoring
 
-Physical checks and declared functional bounds remain mandatory. Quality has no
-fixed allowed-degradation threshold. Each `source_*` job simulates the declared
-source circuit with exactly the same testbench, model resources, parameters,
-load and measurement window as its paired extracted-candidate job. A source
-observation is the 100-point electrical baseline; it is independent of the
-submitted GDS. All individual pairs are retained in the evaluation report.
-
-For a post-layout observation x and its source observation b:
-
-- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,
-  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;
-  s is a normalization floor, not an allowed degradation or pass threshold.
-- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.
-- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and
-  zero-valued operating points are never divided directly.
-
-Scoring uses `layout`. A metric uses its worst paired quality q. The score is
-S = 100 * product(q_i ** w_i), including area quality
-q_area = area_reference / candidate_functional_area. The weights below sum to
-one. Dimensions describe measurements but do not determine their weights.
-Physical or functional rejection scores zero; missing or invalid measurements
-produce an unknown score, including measurements with zero weight.
-Source-equivalent performance at the area reference scores 100; improvements
-can exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.
-
-Measurement definitions below use the supplied SPICE node/source names.
-`v(n)` is node voltage and `i(V)` is current into a voltage source; delivered
-power therefore uses a minus sign. `db(z)=20*log10(abs(z))`, `mag/abs`
-denote magnitude, and `cph` is continuous phase in radians. `find`, `when`,
-`from/to`, and `rise/fall` retain the deck's interpolation, window and
-crossing conventions; SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/
-milli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv`
-mean the stated window average, extrema and sampled derivative. All
-declared conditions are measured separately and paired with the same
-source condition; a group uses its worst paired quality.
-
-| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | Dimension |
+Physical checks and the declared functional bounds must pass. Quality scoring imposes no fixed degradation allowance. Each `source_*` job and its corresponding candidate extracted circuit use exactly the same testbench, model resources, parameters, loads and measurement windows. Independent source observations define the 100-point electrical baseline without depending on the submitted GDS; reports retain every paired result.
+
+Let x be the post-layout measurement and b the source-circuit measurement under the same conditions:
+
+- Ratio normalization: maximize with q = x/b and minimize with q = b/x. When a numerical scale s is declared, use (x+s)/(b+s) and its reciprocal, respectively. The scale handles zero values as a normalization floor; it is neither an allowed degradation nor an acceptance bound.
+- Amplitude in dB: maximize with q = 10^((x-b)/20) and minimize with its reciprocal.
+- Target normalization: q = 1/(1+abs(x-b)/s), where s is the declared physical scale. Signed or zero-valued operating points are not divided directly.
+
+Use `layout` scoring. Each metric takes its worst paired quality q, and the total score is S = 100 * product(q_i ** w_i), with area quality q_area = area_reference / candidate_functional_area. The weights below sum to 1; metric dimensions describe measurements and do not determine weights. Physical or functional rejection scores zero; missing or invalid measurements leave the score unknown, and zero-weight observations must also be valid. Matching source-circuit performance at the reference area scores 100 points; better valid solutions may exceed 100. Weights express quality tradeoffs rather than hard bounds.
+
+The measurements below use the supplied SPICE node and source names. `v(n)` is a node voltage; `i(V)` is current flowing into a voltage source, so delivered power uses a negative sign. `db(z)=20*log10(abs(z))`; `mag/abs` denote magnitude, and `cph` denotes continuous phase in radians. `find`, `when`, `from/to` and `rise/fall` follow the deck's interpolation, window and crossing conventions. SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/milli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv` represent window averages, extrema and sampled derivatives. Measure each operating condition independently, pair it with the source result under that condition, and take the worst paired quality within each metric group.
+
+| Metric | Definition / observation | Unit | Quality normalization | Functional range | Scale | Dimension |
 | --- | --- | --- | --- | --- | --- | --- |
 | `transimpedance_low` | AC: Value of `(real(v(RFout)/i(VSENSE))) at=1meg`. | ohm | maximize / ratio | 0 … +∞ | — | response |
 | `transimpedance_high` | AC: Value of `(mag(v(RFout)/i(VSENSE))) at=100meg`. | ohm | maximize / ratio | 0 … +∞ | — | response |
@@ -141,15 +107,13 @@ source condition; a group uses its worst paired quality.
 | `output_bias` | DC operating point: `v(RFout)`. | V | target / target | 0 … 2.1 | 2.1 | bias |
 | `supply_power` | DC operating point: `-v(vcc1)*i(VCC1)-v(vcc2)*i(VCC2)-v(vcc3)*i(VCC3)`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |
 
-Area reference: **18573.26 um2**. 15 expanded device instances; sum of device/contact envelopes 12204.4550 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.
-
-The capability coefficient remains **5**; it is independent of
-the reference-relative task score.
+Area reference: **18573.26 um2**. The expanded circuit has 15 device instances, a sum of device/contact envelopes 12204.4550 um2, a one-sided envelope margin of 0.6 um, a routing allowance of 50%, and a total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across both sides, and the envelope sum is displayed to four decimal places. MOS/passive envelopes use W/L (or resistor dimensions) and multiplicity, including explicit contacts and HBT emitter/contact envelopes. This is a frozen engineering estimate, not a process minimum or a proven achievable area.
 
+The capability coefficient is **5**, independent of this task's reference-normalized score.
 
 ### Score weights
 
-SiGe low-frequency transfer tasks: signal transfer 68.8%; bias 5.29%; supply cost 15.9%; area 10%. Each objective's weight is divided equally among its metrics.
+SiGe low-frequency transfer: signal transfer 68.8%, bias 5.29%, supply cost 15.9%, area 10%; each objective weight is divided equally among its metrics.
 
 | Metric | Weight |
 | --- | ---: |
@@ -164,12 +128,7 @@ SiGe low-frequency transfer tasks: signal transfer 68.8%; bias 5.29%; supply cos
 
 Solve budget: **3 hours**.
 
-Discover the supplied task, resources, harness and constraints from
-`/protocol/task.json`, `/protocol/resources.json` and
-`/protocol/harness.json`. Use the tool and PDK resources selected by the
-runtime environment. If the harness declares `process-feedback`, request
-an optional frozen process check with `python -I /protocol/process_check.py`;
-the final evaluation remains independent.
+Discover the task, resources, protocol and constraints through `/protocol/task.json`, `/protocol/resources.json`, `/protocol/harness.json`, and use the tools and PDK specified by the runtime environment. If the protocol declares `process-feedback`, run `python -I /protocol/process_check.py` to request an intermediate check using the frozen flow; final evaluation runs independently.
 
 Write the answer to `/workspace/output/final.gds` as a GDS file with top cell
 `FDM_QNC_00_LN_TIA` and wait for the submission receipt:

tasks/ihp-sg13g2/TO_Apr2025/cases/97_GHZ_LINEAR_TIA/case.toml

@@ -1,15 +1,15 @@
-in_core = false
 kind = "layout_case"
 id = "TO_Apr2025.97_GHZ_LINEAR_TIA"
 title = "TO_Apr2025 97-derived multi-stage linear TIA"
 status = "qualified"
+in_core = false
 
 [[assets]]
 path = "materials/schematic.svg"
 role = "schematic"
 visibility = "maintainer"
 format = "svg"
-sha256 = "05dbe3a98796a51d2a409b6bf458430e55db4798d2582ae3b1f5229eb8704ba0"
+sha256 = "f6f8324cd36acaac731164356ef72d80d3159bb1b4b750b14a3b0314229c0d12"
 
 [[assets]]
 path = "reference/FMD_QNC_01_LIN_TIA.gds"
@@ -27,24 +27,24 @@ environment = "ihp-sg13g2-to-97-derived-linear-tia"
 
 [task.inputs.description]
 path = "problem.md"
-sha256 = "10e5739f8f4672e013a37dc5477cc22e853b9b09844cb0d3dee7857d359c46ac"
 format = "text"
+sha256 = "14f3d0ae7285240f63d34fe37ba5979111afcfdc3ef8c7caada576eb0981cb2e"
 
 [task.inputs.netlist]
 path = "materials/circuit.cdl"
-sha256 = "150ab19522eecccf2889ed62c07b14e15e29e97a75ce12563fcd95d846be9112"
 format = "spice"
 subcircuit = "FMD_QNC_01_LIN_TIA"
+sha256 = "150ab19522eecccf2889ed62c07b14e15e29e97a75ce12563fcd95d846be9112"
 
 [task.inputs.simulation]
 path = "materials/circuit.spice"
-sha256 = "fc6c9d1a6ea884f20e7cbddee9c30b4feff18e4a70fbf729789101955a87c334"
 format = "spice"
+sha256 = "fc6c9d1a6ea884f20e7cbddee9c30b4feff18e4a70fbf729789101955a87c334"
 
 [task.inputs.performance]
 path = "materials/testbench.spice"
-sha256 = "759a7548f5ea81399322a73a10b58207d3ff28b2a5ed0ef7d55850b1a6b3959e"
 format = "spice"
+sha256 = "6f076ef2bba62665f975f26f34f645c97ac5d1e023b22dbbe5a88364f8540255"
 
 [task.constraints]
 quality = [
@@ -467,7 +467,10 @@ baseline = [
     "source_positive:transimpedance_low",
 ]
 normalization = "ratio"
+
+[task.evaluation.metrics.requirement]
 lower = 0
+rationale = "The declared response magnitude, impedance, capacitance, amplitude or absolute return-ratio diagnostic has a nonnegative measurement domain; its value remains a quality or diagnostic observation."
 
 [[task.evaluation.metrics]]
 id = "transimpedance_high"
@@ -487,7 +490,10 @@ baseline = [
     "source_positive:transimpedance_high",
 ]
 normalization = "ratio"
+
+[task.evaluation.metrics.requirement]
 lower = 0
+rationale = "The declared response magnitude, impedance, capacitance, amplitude or absolute return-ratio diagnostic has a nonnegative measurement domain; its value remains a quality or diagnostic observation."
 
 [[task.evaluation.metrics]]
 id = "linearity_error_pct"
@@ -506,10 +512,13 @@ baseline = [
     "source_zero:linearity_error_pct",
     "source_positive:linearity_error_pct",
 ]
-normalization = "ratio"
-lower = 0
+normalization = "saturating_ratio"
 scale = 1e-06
 
+[task.evaluation.metrics.requirement]
+lower = 0
+rationale = "The absolute error, voltage span, charge magnitude or recovery deviation has a nonnegative measurement domain; its positive value remains a continuously scored quality observation."
+
 [[task.evaluation.metrics]]
 id = "input_bias"
 category = "performance"
@@ -529,8 +538,11 @@ baseline = [
 ]
 normalization = "target"
 scale = 2.1
+
+[task.evaluation.metrics.requirement]
 lower = 0
 upper = 2.1
+rationale = "The declared node voltage or voltage span must remain within its ground-to-supply operating envelope; precision relative to the source remains a scored objective."
 
 [[task.evaluation.metrics]]
 id = "output_bias"
@@ -551,8 +563,11 @@ baseline = [
 ]
 normalization = "target"
 scale = 2.1
+
+[task.evaluation.metrics.requirement]
 lower = 0
 upper = 2.1
+rationale = "The declared node voltage or voltage span must remain within its ground-to-supply operating envelope; precision relative to the source remains a scored objective."
 
 [[task.evaluation.metrics]]
 id = "supply_power"
@@ -572,14 +587,17 @@ baseline = [
     "source_positive:supply_power",
 ]
 normalization = "ratio"
-lower = 0
 scale = 1e-12
 
+[task.evaluation.metrics.requirement]
+lower = 0
+rationale = "The declared powered circuit or driven switching network must consume nonnegative net supply/driver energy or quiescent current under the complete stated observation."
+
 [task.evaluation.pre_layout]
-source_report_sha256 = "a295d81e4884b121e95ea84f91182d3530050133c06f4365da881249ce63968e"
+source_report_sha256 = "81b4ca0f9f2a34d5d90009e38b56e526d8b228c650ac20b3e64a73f5a67e6099"
 
 [task.evaluation.pre_layout.backends]
-"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"ef9cb87fa27b849376472663b7362673979b89e012f161ba47bb5f6af6ede8eb\", \"compatibility\": null, \"execution_sha256\": \"5424b579002782bfddf0a729715b8fbf2a5f7f2b4cf14982d7616e352d5de9be\", \"image_id\": \"sha256:6562558774d43c085a289bbba696c55959eb8051a0996f96633451fbeb9c652d\", \"limits\": {\"cpus\": 4, \"memory_mb\": 4096, \"pids\": 256}, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"b9527ba49c9eab307a254db28aa45c302eadd71b2563bdec44c610780fa6ed62\", \"timeout_seconds\": 600.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}"
+"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"dfbdf2f93297bbe7d8b576fb988504bd0ecf85b93ef47c314a0f2c9c8830c3e7\", \"compatibility\": null, \"cpu_budget\": 8, \"execution_sha256\": \"495aa9623759f70228a236eb4825c2ae443ef6a741816d8cfc17d1830841dcef\", \"image_id\": \"sha256:060fee64f9f6e71a647e5e958b788d723c9d51d2928ff93e6a295db1959bc37f\", \"limits\": {\"cpus\": 8, \"memory_mb\": 4096, \"pids\": 256}, \"max_parallel_jobs\": 8, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"7b432fb4cf7911c02eacee3ceaad658c961f16f22bc890ee7ad89b3e44108141\", \"thread_environment\": {\"OMP_NUM_THREADS\": \"1\", \"OMP_THREAD_LIMIT\": \"1\"}, \"threads\": 1, \"timeout_seconds\": 600.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}"
 
 [task.evaluation.pre_layout.jobs.source_negative]
 operation = "circuit.simulate"
@@ -614,7 +632,7 @@ dc = "dc_transfer.raw"
 
 [task.evaluation.pre_layout.jobs.source_negative.input_sha256]
 circuit = "fc6c9d1a6ea884f20e7cbddee9c30b4feff18e4a70fbf729789101955a87c334"
-deck = "759a7548f5ea81399322a73a10b58207d3ff28b2a5ed0ef7d55850b1a6b3959e"
+deck = "6f076ef2bba62665f975f26f34f645c97ac5d1e023b22dbbe5a88364f8540255"
 
 [task.evaluation.pre_layout.jobs.source_negative.measurements.input_bias]
 value = 0.798802317629
@@ -652,6 +670,11 @@ unit = "ohm"
 value = 492.1833
 unit = "ohm"
 
+[task.evaluation.pre_layout.jobs.source_negative.output_sha256]
+op = "d963b458199efc9e5b67ca8d7629413cda18e6db73ebbc0466cd8b1ea5fbbb29"
+ac = "859c2e43a924dfcd49d9fa034e6026e65c6ab3bbc7277594279486ff4c52fa78"
+dc = "8466e6ada486f909aa807fe063a991c2b6139ea78a2235378bf1fa6b8929d067"
+
 [task.evaluation.pre_layout.jobs.source_zero]
 operation = "circuit.simulate"
 
@@ -685,7 +708,7 @@ dc = "dc_transfer.raw"
 
 [task.evaluation.pre_layout.jobs.source_zero.input_sha256]
 circuit = "fc6c9d1a6ea884f20e7cbddee9c30b4feff18e4a70fbf729789101955a87c334"
-deck = "759a7548f5ea81399322a73a10b58207d3ff28b2a5ed0ef7d55850b1a6b3959e"
+deck = "6f076ef2bba62665f975f26f34f645c97ac5d1e023b22dbbe5a88364f8540255"
 
 [task.evaluation.pre_layout.jobs.source_zero.measurements.input_bias]
 value = 0.7998357535227
@@ -723,6 +746,11 @@ unit = "ohm"
 value = 468.8727
 unit = "ohm"
 
+[task.evaluation.pre_layout.jobs.source_zero.output_sha256]
+op = "88e54261f79f8a0723dae7ff3aaebec3d7b8ee507935ec9f484a16b15f1372aa"
+ac = "d612bbee2d942605483e8ca9d8dcd593f3a31b735d8fe43709e1256aa00471d2"
+dc = "8466e6ada486f909aa807fe063a991c2b6139ea78a2235378bf1fa6b8929d067"
+
 [task.evaluation.pre_layout.jobs.source_positive]
 operation = "circuit.simulate"
 
@@ -756,7 +784,7 @@ dc = "dc_transfer.raw"
 
 [task.evaluation.pre_layout.jobs.source_positive.input_sha256]
 circuit = "fc6c9d1a6ea884f20e7cbddee9c30b4feff18e4a70fbf729789101955a87c334"
-deck = "759a7548f5ea81399322a73a10b58207d3ff28b2a5ed0ef7d55850b1a6b3959e"
+deck = "6f076ef2bba62665f975f26f34f645c97ac5d1e023b22dbbe5a88364f8540255"
 
 [task.evaluation.pre_layout.jobs.source_positive.measurements.input_bias]
 value = 0.800845761589
@@ -794,6 +822,11 @@ unit = "ohm"
 value = 444.8252
 unit = "ohm"
 
+[task.evaluation.pre_layout.jobs.source_positive.output_sha256]
+op = "8a3a8285aec467b74b0591562e6d2d5dc27b668e8c977484d8fcfba77c2e4a98"
+ac = "2df2e525a29ff61f33a60c2501fc6cb23563ee74cfc031fae0e5cbb4287a39e4"
+dc = "8466e6ada486f909aa807fe063a991c2b6139ea78a2235378bf1fa6b8929d067"
+
 [qualification]
 reference = "reference/FMD_QNC_01_LIN_TIA.gds"
 
@@ -809,7 +842,7 @@ reference = "reference/FMD_QNC_01_LIN_TIA.gds"
 type = "klayout-geometry-docker"
 
 [toolchain.backends.geometry.settings]
-image = "iclayout-bench-tools:local"
+image = "iclayout-eda-open:local"
 timeout_seconds = 120
 
 [toolchain.backends.drc]
@@ -819,7 +852,7 @@ type = "klayout-docker"
 support = "klayout"
 
 [toolchain.backends.drc.settings]
-image = "iclayout-bench-tools:local"
+image = "iclayout-eda-open:local"
 check = "drc"
 support = "build/support/tia97-klayout"
 profile = "drc-upstream.json"
@@ -832,7 +865,7 @@ type = "klayout-docker"
 support = "klayout"
 
 [toolchain.backends.lvs.settings]
-image = "iclayout-bench-tools:local"
+image = "iclayout-eda-open:local"
 check = "lvs"
 support = "build/support/tia97-klayout"
 profile = "lvs-upstream.json"
@@ -842,7 +875,7 @@ timeout_seconds = 600
 type = "klayout-docker"
 
 [toolchain.backends.artifact.settings]
-image = "iclayout-bench-tools:local"
+image = "iclayout-eda-open:local"
 check = "artifact"
 timeout_seconds = 60
 
@@ -853,7 +886,10 @@ type = "ngspice-docker"
 support = "hbt-models"
 
 [toolchain.backends.simulation.settings]
-image = "iclayout-bench-tools:local"
+max_parallel_jobs = 8
+threads = 1
+cpu_budget = 8
+image = "iclayout-eda-open:local"
 support = "build/support/tia97-hbt-models"
 timeout_seconds = 600
 
@@ -865,7 +901,7 @@ klayout_support = "klayout"
 magic_support = "magic"
 
 [toolchain.backends.parasitics.settings]
-image = "iclayout-bench-tools:local"
+image = "iclayout-eda-open:local"
 klayout_support = "build/support/tia97-klayout"
 klayout_profile = "lvs-upstream.json"
 magic_support = "build/support/tia97-magic"

tasks/ihp-sg13g2/TO_Apr2025/cases/97_GHZ_LINEAR_TIA/materials/testbench.spice

@@ -29,6 +29,7 @@ let supply3_current = -i(VCC3)
 let supply_power = -v(VCC1)*i(VCC1)-v(VCC2)*i(VCC2)-v(VCC3)*i(VCC3)
 print input_bias output_bias supply1_current supply2_current supply3_current supply_power
 write operating_point.raw all
+save i(vcc1) i(vcc2) i(vcc3) i(vsense) v(rfin) v(rfout) v(vcc1) v(vcc2) v(vcc3)
 ac dec 40 1meg 100meg
 let signed_transimpedance = real(v(RFOUT)/i(VSENSE))
 let magnitude_transimpedance = mag(v(RFOUT)/i(VSENSE))

tasks/ihp-sg13g2/TO_Apr2025/cases/97_GHZ_LINEAR_TIA/problem.md

@@ -10,8 +10,7 @@ checks and nominal post-layout measurements below.
 
 ## Inputs and Interface
 
-In addition to this problem, the runtime task supplies the following declared
-inputs:
+In addition to this description, the runtime task supplies the following declared inputs:
 
 | Input | Purpose |
 |---|---|
@@ -64,20 +63,11 @@ supply power is calculated from the three independent supply sources.
 
 ## Physical Requirements
 
-The candidate GDS must be readable, non-empty and no larger than 32 MiB. It
-must pass the pinned SG13G2 main and additional maximal DRC scopes in deep
-mode without waivers; density and antenna checks are outside this declared scope. It must
-also pass strict named-port LVS against `materials/circuit.cdl`, including
-the six ports, device multiplicities, passive geometry and explicit substrate
-tap. Artifact, DRC, strict LVS and geometry gates all precede candidate
-extraction.
+Candidate GDS must be readable, nonempty and at most 32 MiB. Use pinned SG13G2 main and additional maximal DRC rules in deep mode without waivers; density and antenna are outside the declared scope. Strict named-port LVS compares against `materials/circuit.cdl`, checking six ports, device multiplicities, passive geometry and explicit substrate contacts. File, DRC, strict LVS and geometry checks all precede candidate extraction.
 
-The GDS must include the complete target hierarchy. Port names are matched
-case-insensitively; each declared port must remain on its own conductor with
-the declared connectivity.
+The GDS must contain the complete target hierarchy. Port names are case insensitive; each declared port must retain its conductor and declared connections.
 
-The functional outline is the recursive bounding box of polygons on these
-SG13G2 datatype-0 layers, including child cells and the complete routing stack:
+The functional outline is the recursive bounding box of polygons on the following SG13G2 datatype-0 layers, including child cells and every routing layer:
 
 `1, 3, 5, 6, 7, 8, 10, 11, 13, 14, 19, 24, 26, 28, 29, 30, 31, 32, 33, 35, 36, 40, 44, 46, 49, 50, 51, 52, 53, 55, 58, 66, 67, 90, 101, 111, 125, 126, 128, 129, 133, 134, 139, 152`.
 
@@ -101,56 +91,32 @@ alias must not replace the explicit source substrate connection.
 
 ## Electrical Requirements and Scoring
 
-Physical checks and declared functional bounds remain mandatory. Quality has no
-fixed allowed-degradation threshold. Each `source_*` job simulates the declared
-source circuit with exactly the same testbench, model resources, parameters,
-load and measurement window as its paired extracted-candidate job. A source
-observation is the 100-point electrical baseline; it is independent of the
-submitted GDS. All individual pairs are retained in the evaluation report.
-
-For a post-layout observation x and its source observation b:
-
-- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,
-  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;
-  s is a normalization floor, not an allowed degradation or pass threshold.
-- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.
-- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and
-  zero-valued operating points are never divided directly.
-
-Scoring uses `layout`. A metric uses its worst paired quality q. The score is
-S = 100 * product(q_i ** w_i), including area quality
-q_area = area_reference / candidate_functional_area. The weights below sum to
-one. Dimensions describe measurements but do not determine their weights.
-Physical or functional rejection scores zero; missing or invalid measurements
-produce an unknown score, including measurements with zero weight.
-Source-equivalent performance at the area reference scores 100; improvements
-can exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.
-
-Measurement definitions below use the supplied SPICE node/source names.
-`v(n)` is node voltage and `i(V)` is current into a voltage source; delivered
-power therefore uses a minus sign. `db(z)=20*log10(abs(z))`, `mag/abs`
-denote magnitude, and `cph` is continuous phase in radians. `find`, `when`,
-`from/to`, and `rise/fall` retain the deck's interpolation, window and
-crossing conventions; SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/
-milli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv`
-mean the stated window average, extrema and sampled derivative. All
-declared conditions are measured separately and paired with the same
-source condition; a group uses its worst paired quality.
-
-| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | Dimension |
+Physical checks and the declared functional bounds must pass. Quality scoring imposes no fixed degradation allowance. Each `source_*` job and its corresponding candidate extracted circuit use exactly the same testbench, model resources, parameters, loads and measurement windows. Independent source observations define the 100-point electrical baseline without depending on the submitted GDS; reports retain every paired result.
+
+Let x be the post-layout measurement and b the source-circuit measurement under the same conditions:
+
+- Ratio normalization: maximize with q = x/b and minimize with q = b/x. When a numerical scale s is declared, use (x+s)/(b+s) and its reciprocal, respectively. The scale handles zero values as a normalization floor; it is neither an allowed degradation nor an acceptance bound.
+- Amplitude in dB: maximize with q = 10^((x-b)/20) and minimize with its reciprocal.
+- Target normalization: q = 1/(1+abs(x-b)/s), where s is the declared physical scale. Signed or zero-valued operating points are not divided directly.
+
+Use `layout` scoring. Each metric takes its worst paired quality q, and the total score is S = 100 * product(q_i ** w_i), with area quality q_area = area_reference / candidate_functional_area. The weights below sum to 1; metric dimensions describe measurements and do not determine weights. Physical or functional rejection scores zero; missing or invalid measurements leave the score unknown, and zero-weight observations must also be valid. Matching source-circuit performance at the reference area scores 100 points; better valid solutions may exceed 100. Weights express quality tradeoffs rather than hard bounds.
+
+The measurements below use the supplied SPICE node and source names. `v(n)` is a node voltage; `i(V)` is current flowing into a voltage source, so delivered power uses a negative sign. `db(z)=20*log10(abs(z))`; `mag/abs` denote magnitude, and `cph` denotes continuous phase in radians. `find`, `when`, `from/to` and `rise/fall` follow the deck's interpolation, window and crossing conventions. SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/milli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv` represent window averages, extrema and sampled derivatives. Measure each operating condition independently, pair it with the source result under that condition, and take the worst paired quality within each metric group.
+
+`linearity_error_pct` uses `saturating_ratio`: q = 2(b+s)/(b+x+2s), where x is candidate error, b is paired source error and s is the positive scale below. Source equivalence gives q=1; improvement approaches the upper limit 2 with diminishing returns. The scale retains its declared unit and numerical-floor meaning. Normalize each condition before taking the worst quality; other rules follow their declarations.
+
+| Metric | Definition / observation | Unit | Quality normalization | Functional range | Scale | Dimension |
 | --- | --- | --- | --- | --- | --- | --- |
 | `transimpedance_low` | AC: Value of `(real(v(RFOUT)/i(VSENSE))) at=1meg`. | ohm | maximize / ratio | 0 … +∞ | — | response |
 | `transimpedance_high` | AC: Value of `(mag(v(RFOUT)/i(VSENSE))) at=100meg`. | ohm | maximize / ratio | 0 … +∞ | — | response |
-| `linearity_error_pct` | Maximum absolute deviation of DC RFOUT from the line through the endpoint samples, divided by absolute output span, times 100; IIN sweeps -5 to +5 uA in 0.5 uA steps. | percent | minimize / ratio | 0 … +∞ | 1e-06 | response |
+| `linearity_error_pct` | Maximum absolute deviation of DC RFOUT from the line through the endpoint samples, divided by absolute output span, times 100; IIN sweeps -5 to +5 uA in 0.5 uA steps. | percent | minimize / saturating_ratio | 0 … +∞ | 1e-06 | response |
 | `input_bias` | DC operating point: `v(RFIN)`. | V | target / target | 0 … 2.1 | 2.1 | bias |
 | `output_bias` | DC operating point: `v(RFOUT)`. | V | target / target | 0 … 2.1 | 2.1 | bias |
 | `supply_power` | DC operating point: `-v(VCC1)*i(VCC1)-v(VCC2)*i(VCC2)-v(VCC3)*i(VCC3)`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |
 
-Area reference: **18718.54 um2**. 17 expanded device instances; sum of device/contact envelopes 12300.6100 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.
-
-The capability coefficient remains **6**; it is independent of
-the reference-relative task score.
+Area reference: **18718.54 um2**. The expanded circuit has 17 device instances, a sum of device/contact envelopes 12300.6100 um2, a one-sided envelope margin of 0.6 um, a routing allowance of 50%, and a total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across both sides, and the envelope sum is displayed to four decimal places. MOS/passive envelopes use W/L (or resistor dimensions) and multiplicity, including explicit contacts and HBT emitter/contact envelopes. This is a frozen engineering estimate, not a process minimum or a proven achievable area.
 
+The capability coefficient is **6**, independent of this task's reference-normalized score.
 
 ### Score weights
 
@@ -170,12 +136,7 @@ SiGe low-frequency transfer tasks: signal transfer 53.2%; linearity 20.5%; bias
 
 Solve budget: **3 hours**.
 
-Discover the supplied task, resources, harness and constraints from
-`/protocol/task.json`, `/protocol/resources.json` and
-`/protocol/harness.json`. Use the tool and PDK resources selected by the
-runtime environment. If the harness declares `process-feedback`, request
-an optional frozen process check with `python -I /protocol/process_check.py`;
-the final evaluation remains independent.
+Discover the task, resources, protocol and constraints through `/protocol/task.json`, `/protocol/resources.json`, `/protocol/harness.json`, and use the tools and PDK specified by the runtime environment. If the protocol declares `process-feedback`, run `python -I /protocol/process_check.py` to request an intermediate check using the frozen flow; final evaluation runs independently.
 
 Write the answer to `/workspace/output/final.gds` as a GDS file with top cell
 `FMD_QNC_01_LIN_TIA` and wait for the submission receipt:
@@ -184,5 +145,4 @@ Write the answer to `/workspace/output/final.gds` as a GDS file with top cell
 python -I /protocol/submit.py
 ```
 
-The evaluator uses the submitted snapshot for all physical checks, extraction
-and simulations.
+All physical checks, extraction and simulation use the submitted snapshot.

tasks/ihp-sg13g2/TO_Apr2025/cases/DC_to_130_GHz_TIA.design_1/case.toml

@@ -1,15 +1,15 @@
-in_core = false
 kind = "layout_case"
 id = "TO_Apr2025.DC_to_130_GHz_TIA.design_1"
 title = "Two-stage SiGe HBT TIA with nominal AC/DC requirements"
 status = "qualified"
+in_core = false
 
 [[assets]]
 path = "materials/schematic.svg"
 role = "schematic"
 visibility = "maintainer"
 format = "svg"
-sha256 = "35c6ad118e5e06bdd1c07e510f66417b2b26454d4db6d3d0ceb10c002028fad6"
+sha256 = "5da14439984543b4e94085678796cca312b870ab4e582e6adb7adc02f4102090"
 
 [[assets]]
 path = "reference/FMD_QNC_03a_TIA_1.gds"
@@ -27,24 +27,24 @@ environment = "ihp-sg13g2-to-design1-functional"
 
 [task.inputs.description]
 path = "problem.md"
-sha256 = "2d77cb2f457a5b7f9188f0ed28eabf7acbbdd8f32b9dcfa75b54b4d34cce0061"
 format = "text"
+sha256 = "aef9abd87f676d07857d0a813253e09b7a95425c3a2f06a8b41245944e7ac3c4"
 
 [task.inputs.netlist]
 path = "materials/circuit.cdl"
-sha256 = "41054606cd4c4845149df6c9a38a7d38d45ae4ba22afb5ff588d33051aaf06f3"
 format = "spice"
 subcircuit = "FMD_QNC_03a_TIA_1"
+sha256 = "41054606cd4c4845149df6c9a38a7d38d45ae4ba22afb5ff588d33051aaf06f3"
 
 [task.inputs.simulation]
 path = "materials/circuit.spice"
-sha256 = "7dc79bb78b7d60f5ff7826fa2aa0cb549e0453a89ed26e2cfd7f64e8ea6bbfbd"
 format = "spice"
+sha256 = "7dc79bb78b7d60f5ff7826fa2aa0cb549e0453a89ed26e2cfd7f64e8ea6bbfbd"
 
 [task.inputs.performance]
 path = "materials/testbench.spice"
-sha256 = "cf9a8f31c266d199966ba4ab102fb9f73b26bc74044d0ed0704fbc1120a01742"
 format = "spice"
+sha256 = "f1144350e7791fcfc8ad81e04a56b6fceca1995600018a70ed301b95c1b42aaf"
 
 [task.constraints]
 quality = [
@@ -453,7 +453,10 @@ baseline = [
     "source_positive:transimpedance_low",
 ]
 normalization = "ratio"
+
+[task.evaluation.metrics.requirement]
 lower = 0
+rationale = "The declared response magnitude, impedance, capacitance, amplitude or absolute return-ratio diagnostic has a nonnegative measurement domain; its value remains a quality or diagnostic observation."
 
 [[task.evaluation.metrics]]
 id = "transimpedance_high"
@@ -473,7 +476,10 @@ baseline = [
     "source_positive:transimpedance_high",
 ]
 normalization = "ratio"
+
+[task.evaluation.metrics.requirement]
 lower = 0
+rationale = "The declared response magnitude, impedance, capacitance, amplitude or absolute return-ratio diagnostic has a nonnegative measurement domain; its value remains a quality or diagnostic observation."
 
 [[task.evaluation.metrics]]
 id = "input_bias"
@@ -494,8 +500,11 @@ baseline = [
 ]
 normalization = "target"
 scale = 2.0
+
+[task.evaluation.metrics.requirement]
 lower = 0
 upper = 2.0
+rationale = "The declared node voltage or voltage span must remain within its ground-to-supply operating envelope; precision relative to the source remains a scored objective."
 
 [[task.evaluation.metrics]]
 id = "output_bias"
@@ -516,8 +525,11 @@ baseline = [
 ]
 normalization = "target"
 scale = 2.0
+
+[task.evaluation.metrics.requirement]
 lower = 0
 upper = 2.0
+rationale = "The declared node voltage or voltage span must remain within its ground-to-supply operating envelope; precision relative to the source remains a scored objective."
 
 [[task.evaluation.metrics]]
 id = "supply_power"
@@ -537,14 +549,17 @@ baseline = [
     "source_positive:supply_power",
 ]
 normalization = "ratio"
-lower = 0
 scale = 1e-12
 
+[task.evaluation.metrics.requirement]
+lower = 0
+rationale = "The declared powered circuit or driven switching network must consume nonnegative net supply/driver energy or quiescent current under the complete stated observation."
+
 [task.evaluation.pre_layout]
-source_report_sha256 = "41bb35cebcae6f4986a76641298df392d8f1164db3e7201143dab10abdbc00b5"
+source_report_sha256 = "0ea4043b7b3d858803a7569266d547a2d98ac1aa57aadeaeb0838bcc6cfd3d90"
 
 [task.evaluation.pre_layout.backends]
-"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"ef9cb87fa27b849376472663b7362673979b89e012f161ba47bb5f6af6ede8eb\", \"compatibility\": null, \"execution_sha256\": \"5424b579002782bfddf0a729715b8fbf2a5f7f2b4cf14982d7616e352d5de9be\", \"image_id\": \"sha256:6562558774d43c085a289bbba696c55959eb8051a0996f96633451fbeb9c652d\", \"limits\": {\"cpus\": 4, \"memory_mb\": 4096, \"pids\": 256}, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"ca37b963bac7a1c8224fec3455a1354dedcf3d1fe3be08114cc9502971070abe\", \"timeout_seconds\": 60.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}"
+"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"dfbdf2f93297bbe7d8b576fb988504bd0ecf85b93ef47c314a0f2c9c8830c3e7\", \"compatibility\": null, \"cpu_budget\": 8, \"execution_sha256\": \"495aa9623759f70228a236eb4825c2ae443ef6a741816d8cfc17d1830841dcef\", \"image_id\": \"sha256:060fee64f9f6e71a647e5e958b788d723c9d51d2928ff93e6a295db1959bc37f\", \"limits\": {\"cpus\": 8, \"memory_mb\": 4096, \"pids\": 256}, \"max_parallel_jobs\": 8, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"7b432fb4cf7911c02eacee3ceaad658c961f16f22bc890ee7ad89b3e44108141\", \"thread_environment\": {\"OMP_NUM_THREADS\": \"1\", \"OMP_THREAD_LIMIT\": \"1\"}, \"threads\": 1, \"timeout_seconds\": 60.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}"
 
 [task.evaluation.pre_layout.jobs.source_negative]
 operation = "circuit.simulate"
@@ -575,7 +590,7 @@ ac = "frequency_response.raw"
 
 [task.evaluation.pre_layout.jobs.source_negative.input_sha256]
 circuit = "7dc79bb78b7d60f5ff7826fa2aa0cb549e0453a89ed26e2cfd7f64e8ea6bbfbd"
-deck = "cf9a8f31c266d199966ba4ab102fb9f73b26bc74044d0ed0704fbc1120a01742"
+deck = "f1144350e7791fcfc8ad81e04a56b6fceca1995600018a70ed301b95c1b42aaf"
 
 [task.evaluation.pre_layout.jobs.source_negative.measurements.input_bias]
 value = 0.9487253947562
@@ -605,6 +620,10 @@ unit = "ohm"
 value = 184.5921
 unit = "ohm"
 
+[task.evaluation.pre_layout.jobs.source_negative.output_sha256]
+op = "44c7d4d7b135a4323961d22dac6fb85a6dd2b6a6dea3ee3e5599838624d15772"
+ac = "fce8396a42751c433fc4d5d5d30a97a38269be9f5a70359e896c0c56337a2942"
+
 [task.evaluation.pre_layout.jobs.source_zero]
 operation = "circuit.simulate"
 
@@ -634,7 +653,7 @@ ac = "frequency_response.raw"
 
 [task.evaluation.pre_layout.jobs.source_zero.input_sha256]
 circuit = "7dc79bb78b7d60f5ff7826fa2aa0cb549e0453a89ed26e2cfd7f64e8ea6bbfbd"
-deck = "cf9a8f31c266d199966ba4ab102fb9f73b26bc74044d0ed0704fbc1120a01742"
+deck = "f1144350e7791fcfc8ad81e04a56b6fceca1995600018a70ed301b95c1b42aaf"
 
 [task.evaluation.pre_layout.jobs.source_zero.measurements.input_bias]
 value = 0.9499771272023
@@ -664,6 +683,10 @@ unit = "ohm"
 value = 181.173
 unit = "ohm"
 
+[task.evaluation.pre_layout.jobs.source_zero.output_sha256]
+op = "8e9f86d1e9cb921a673d4361982249cd3f3230b4346a377c26ef286909c3e69d"
+ac = "f8c932d513055e454f868849f7bfee1770aea87871893ba695cd2b735358fd65"
+
 [task.evaluation.pre_layout.jobs.source_positive]
 operation = "circuit.simulate"
 
@@ -693,7 +716,7 @@ ac = "frequency_response.raw"
 
 [task.evaluation.pre_layout.jobs.source_positive.input_sha256]
 circuit = "7dc79bb78b7d60f5ff7826fa2aa0cb549e0453a89ed26e2cfd7f64e8ea6bbfbd"
-deck = "cf9a8f31c266d199966ba4ab102fb9f73b26bc74044d0ed0704fbc1120a01742"
+deck = "f1144350e7791fcfc8ad81e04a56b6fceca1995600018a70ed301b95c1b42aaf"
 
 [task.evaluation.pre_layout.jobs.source_positive.measurements.input_bias]
 value = 0.9512266397008
@@ -723,6 +746,10 @@ unit = "ohm"
 value = 177.7518
 unit = "ohm"
 
+[task.evaluation.pre_layout.jobs.source_positive.output_sha256]
+op = "5ba7c4132d13b688093d9ba2e043864d53bff8077fd5704d881d6f4ed65dcb22"
+ac = "c3b3ed800ce22cae1099191971e36627abdd3ff7550effc41a9889b8270cd271"
+
 [qualification]
 reference = "reference/FMD_QNC_03a_TIA_1.gds"
 
@@ -738,7 +765,7 @@ reference = "reference/FMD_QNC_03a_TIA_1.gds"
 type = "klayout-geometry-docker"
 
 [toolchain.backends.geometry.settings]
-image = "iclayout-bench-tools:local"
+image = "iclayout-eda-open:local"
 timeout_seconds = 120
 
 [toolchain.backends.lvs]
@@ -748,7 +775,7 @@ type = "klayout-docker"
 support = "klayout"
 
 [toolchain.backends.lvs.settings]
-image = "iclayout-bench-tools:local"
+image = "iclayout-eda-open:local"
 check = "lvs"
 support = "build/support/to-design1-klayout"
 profile = "lvs-upstream.json"
@@ -761,7 +788,10 @@ type = "ngspice-docker"
 support = "hbt-models"
 
 [toolchain.backends.simulation.settings]
-image = "iclayout-bench-tools:local"
+max_parallel_jobs = 8
+threads = 1
+cpu_budget = 8
+image = "iclayout-eda-open:local"
 support = "build/support/to-design1-models"
 timeout_seconds = 60
 
@@ -769,7 +799,7 @@ timeout_seconds = 60
 type = "klayout-docker"
 
 [toolchain.backends.artifact.settings]
-image = "iclayout-bench-tools:local"
+image = "iclayout-eda-open:local"
 check = "artifact"
 timeout_seconds = 60
 
@@ -780,7 +810,7 @@ type = "klayout-docker"
 support = "klayout"
 
 [toolchain.backends.drc.settings]
-image = "iclayout-bench-tools:local"
+image = "iclayout-eda-open:local"
 check = "drc"
 support = "build/support/to-design1-klayout"
 profile = "drc-upstream.json"
@@ -794,7 +824,7 @@ klayout_support = "klayout"
 magic_support = "magic"
 
 [toolchain.backends.parasitics.settings]
-image = "iclayout-bench-tools:local"
+image = "iclayout-eda-open:local"
 klayout_support = "build/support/to-design1-klayout"
 klayout_profile = "lvs-to-apr2025.json"
 magic_support = "build/support/to-design1-magic"

tasks/ihp-sg13g2/TO_Apr2025/cases/DC_to_130_GHz_TIA.design_1/materials/testbench.spice

@@ -29,6 +29,7 @@ let supply2_current = -i(VCC2)
 let supply_power = -v(vcc1)*i(VCC1)-v(vcc2)*i(VCC2)
 print input_bias output_bias supply1_current supply2_current supply_power
 write operating_point.raw all
+save i(vcc1) i(vcc2) i(vsense) v(input) v(output) v(vcc1) v(vcc2)
 ac dec 40 1meg 100meg
 let signed_transimpedance = real(v(output)/i(VSENSE))
 let magnitude_transimpedance = mag(v(output)/i(VSENSE))

tasks/ihp-sg13g2/TO_Apr2025/cases/DC_to_130_GHz_TIA.design_1/problem.md

@@ -10,8 +10,7 @@ post-layout measurements below.
 
 ## Inputs and Interface
 
-In addition to this problem, the runtime task supplies the following declared
-inputs:
+In addition to this description, the runtime task supplies the following declared inputs:
 
 | Input | Purpose |
 |---|---|
@@ -69,12 +68,9 @@ the five ports, device multiplicities, passive geometry and the same-net
 substrate tap. Artifact, DRC, LVS and geometry gates all precede candidate
 extraction.
 
-The GDS must include the complete target hierarchy. Port names are matched
-case-insensitively; each declared port must remain on its own conductor with
-the declared connectivity.
+The GDS must contain the complete target hierarchy. Port names are case insensitive; each declared port must retain its conductor and declared connections.
 
-The functional outline is the recursive bounding box of polygons on these
-SG13G2 datatype-0 layers, including child cells and the complete routing stack:
+The functional outline is the recursive bounding box of polygons on the following SG13G2 datatype-0 layers, including child cells and every routing layer:
 
 `1, 3, 5, 6, 7, 8, 10, 11, 13, 14, 19, 24, 26, 28, 29, 30, 31, 32, 33, 35, 36, 40, 44, 46, 49, 50, 51, 52, 53, 55, 58, 66, 67, 90, 101, 111, 125, 126, 128, 129, 133, 134, 139, 152`.
 
@@ -96,43 +92,19 @@ port or change the maintained circuit.
 
 ## Electrical Requirements and Scoring
 
-Physical checks and declared functional bounds remain mandatory. Quality has no
-fixed allowed-degradation threshold. Each `source_*` job simulates the declared
-source circuit with exactly the same testbench, model resources, parameters,
-load and measurement window as its paired extracted-candidate job. A source
-observation is the 100-point electrical baseline; it is independent of the
-submitted GDS. All individual pairs are retained in the evaluation report.
-
-For a post-layout observation x and its source observation b:
-
-- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,
-  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;
-  s is a normalization floor, not an allowed degradation or pass threshold.
-- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.
-- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and
-  zero-valued operating points are never divided directly.
-
-Scoring uses `layout`. A metric uses its worst paired quality q. The score is
-S = 100 * product(q_i ** w_i), including area quality
-q_area = area_reference / candidate_functional_area. The weights below sum to
-one. Dimensions describe measurements but do not determine their weights.
-Physical or functional rejection scores zero; missing or invalid measurements
-produce an unknown score, including measurements with zero weight.
-Source-equivalent performance at the area reference scores 100; improvements
-can exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.
-
-Measurement definitions below use the supplied SPICE node/source names.
-`v(n)` is node voltage and `i(V)` is current into a voltage source; delivered
-power therefore uses a minus sign. `db(z)=20*log10(abs(z))`, `mag/abs`
-denote magnitude, and `cph` is continuous phase in radians. `find`, `when`,
-`from/to`, and `rise/fall` retain the deck's interpolation, window and
-crossing conventions; SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/
-milli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv`
-mean the stated window average, extrema and sampled derivative. All
-declared conditions are measured separately and paired with the same
-source condition; a group uses its worst paired quality.
-
-| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | Dimension |
+Physical checks and the declared functional bounds must pass. Quality scoring imposes no fixed degradation allowance. Each `source_*` job and its corresponding candidate extracted circuit use exactly the same testbench, model resources, parameters, loads and measurement windows. Independent source observations define the 100-point electrical baseline without depending on the submitted GDS; reports retain every paired result.
+
+Let x be the post-layout measurement and b the source-circuit measurement under the same conditions:
+
+- Ratio normalization: maximize with q = x/b and minimize with q = b/x. When a numerical scale s is declared, use (x+s)/(b+s) and its reciprocal, respectively. The scale handles zero values as a normalization floor; it is neither an allowed degradation nor an acceptance bound.
+- Amplitude in dB: maximize with q = 10^((x-b)/20) and minimize with its reciprocal.
+- Target normalization: q = 1/(1+abs(x-b)/s), where s is the declared physical scale. Signed or zero-valued operating points are not divided directly.
+
+Use `layout` scoring. Each metric takes its worst paired quality q, and the total score is S = 100 * product(q_i ** w_i), with area quality q_area = area_reference / candidate_functional_area. The weights below sum to 1; metric dimensions describe measurements and do not determine weights. Physical or functional rejection scores zero; missing or invalid measurements leave the score unknown, and zero-weight observations must also be valid. Matching source-circuit performance at the reference area scores 100 points; better valid solutions may exceed 100. Weights express quality tradeoffs rather than hard bounds.
+
+The measurements below use the supplied SPICE node and source names. `v(n)` is a node voltage; `i(V)` is current flowing into a voltage source, so delivered power uses a negative sign. `db(z)=20*log10(abs(z))`; `mag/abs` denote magnitude, and `cph` denotes continuous phase in radians. `find`, `when`, `from/to` and `rise/fall` follow the deck's interpolation, window and crossing conventions. SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/milli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv` represent window averages, extrema and sampled derivatives. Measure each operating condition independently, pair it with the source result under that condition, and take the worst paired quality within each metric group.
+
+| Metric | Definition / observation | Unit | Quality normalization | Functional range | Scale | Dimension |
 | --- | --- | --- | --- | --- | --- | --- |
 | `transimpedance_low` | AC: Value of `(real(v(output)/i(VSENSE))) at=1meg`. | ohm | maximize / ratio | 0 … +∞ | — | response |
 | `transimpedance_high` | AC: Value of `(mag(v(output)/i(VSENSE))) at=100meg`. | ohm | maximize / ratio | 0 … +∞ | — | response |
@@ -140,15 +112,13 @@ source condition; a group uses its worst paired quality.
 | `output_bias` | DC operating point: `v(output)`. | V | target / target | 0 … 2.0 | 2.0 | bias |
 | `supply_power` | DC operating point: `-v(vcc1)*i(VCC1)-v(vcc2)*i(VCC2)`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |
 
-Area reference: **3852.28 um2**. 8 expanded device instances; sum of device/contact envelopes 2487.4228 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.
-
-The capability coefficient remains **4**; it is independent of
-the reference-relative task score.
+Area reference: **3852.28 um2**. The expanded circuit has 8 device instances, a sum of device/contact envelopes 2487.4228 um2, a one-sided envelope margin of 0.6 um, a routing allowance of 50%, and a total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across both sides, and the envelope sum is displayed to four decimal places. MOS/passive envelopes use W/L (or resistor dimensions) and multiplicity, including explicit contacts and HBT emitter/contact envelopes. This is a frozen engineering estimate, not a process minimum or a proven achievable area.
 
+The capability coefficient is **4**, independent of this task's reference-normalized score.
 
 ### Score weights
 
-SiGe low-frequency transfer tasks: signal transfer 68.8%; bias 5.29%; supply cost 15.9%; area 10%. Each objective's weight is divided equally among its metrics.
+SiGe low-frequency transfer: signal transfer 68.8%, bias 5.29%, supply cost 15.9%, area 10%; each objective weight is divided equally among its metrics.
 
 | Metric | Weight |
 | --- | ---: |
@@ -163,12 +133,7 @@ SiGe low-frequency transfer tasks: signal transfer 68.8%; bias 5.29%; supply cos
 
 Solve budget: **3 hours**.
 
-Discover the supplied task, resources, harness and constraints from
-`/protocol/task.json`, `/protocol/resources.json` and
-`/protocol/harness.json`. Use the tool and PDK resources selected by the
-runtime environment. If the harness declares `process-feedback`, request
-an optional frozen process check with `python -I /protocol/process_check.py`;
-the final evaluation remains independent.
+Discover the task, resources, protocol and constraints through `/protocol/task.json`, `/protocol/resources.json`, `/protocol/harness.json`, and use the tools and PDK specified by the runtime environment. If the protocol declares `process-feedback`, run `python -I /protocol/process_check.py` to request an intermediate check using the frozen flow; final evaluation runs independently.
 
 Write the answer to `/workspace/output/final.gds` as a GDS file with top cell
 `FMD_QNC_03a_TIA_1` and wait for the submission receipt:
@@ -177,5 +142,4 @@ Write the answer to `/workspace/output/final.gds` as a GDS file with top cell
 python -I /protocol/submit.py
 ```
 
-The evaluator uses the submitted snapshot for all physical checks, extraction
-and simulations.
+All physical checks, extraction and simulation use the submitted snapshot.

tasks/ihp-sg13g2/analog-db/cases/adc_001_inv1b/case.toml

@@ -1,15 +1,15 @@
-in_core = false
 kind = "layout_case"
 id = "ihp-sg13g2.analog-db.adc_001_inv1b"
 title = "CMOS Inverter Threshold Core"
 status = "qualified"
+in_core = false
 
 [[assets]]
 path = "materials/schematic.svg"
 role = "schematic"
 visibility = "maintainer"
 format = "svg"
-sha256 = "a8cccb07772179454cce99b4d0e172c6a622160212c25ddda6f451e08f2350d8"
+sha256 = "94c6b23ff178b3b7e18ecf9a0eed0734f0fbea0f84614a45bc4f57c8acf88643"
 
 [[assets]]
 path = "reference/adc_001_inv1b.gds"
@@ -28,13 +28,13 @@ environment = "ihp-sg13g2-mos-rc-tt"
 [task.inputs.description]
 path = "problem.md"
 format = "text"
-sha256 = "f77341695350c9c22f0f938c9deb1c21d4085419f90b9c92448364039ae9d4e8"
+sha256 = "89ac70eab03942a80bef149eab104bc1c59bf84dde79fd0b873f0974d4505bc3"
 
 [task.inputs.netlist]
 path = "materials/circuit.cdl"
 format = "spice"
-sha256 = "ac17dacdee7c373b47d4038a7318a7b0fedc024031b06f93011f8eaab684caf4"
 subcircuit = "adc_001_inv1b"
+sha256 = "ac17dacdee7c373b47d4038a7318a7b0fedc024031b06f93011f8eaab684caf4"
 
 [task.inputs.simulation]
 path = "materials/circuit.spice"
@@ -44,7 +44,7 @@ sha256 = "5b7039e6399c1336c9ed31405b0176f512f2981b51e1fa8ffae36fa8d51af7aa"
 [task.inputs.performance]
 path = "materials/testbench.spice"
 format = "spice"
-sha256 = "c7fa64149fb838b9ae6b0fbcd173883a86be2db0869ba9f7a3d13e61def94476"
+sha256 = "7305f7b68fdb3c41a8e397a24b229aa79cd228e6d8e261654e9803d208ff84c0"
 
 [task.constraints]
 quality = [
@@ -398,7 +398,6 @@ direction = "minimize"
 dimension = "response"
 normalization = "ratio"
 scale = 1e-12
-lower = 0
 category = "performance"
 observations = [
     "condition_0:delay_s",
@@ -407,6 +406,10 @@ baseline = [
     "source_condition_0:delay_s",
 ]
 
+[task.evaluation.metrics.requirement]
+lower = 0
+rationale = "The observed frequency or ordered-event interval has a nonnegative measurement domain, and its required crossing must exist for a usable observation."
+
 [[task.evaluation.metrics]]
 id = "transition_s"
 unit = "s"
@@ -415,7 +418,6 @@ direction = "minimize"
 dimension = "response"
 normalization = "ratio"
 scale = 1e-12
-lower = 0
 category = "performance"
 observations = [
     "condition_0:transition_s",
@@ -424,6 +426,10 @@ baseline = [
     "source_condition_0:transition_s",
 ]
 
+[task.evaluation.metrics.requirement]
+lower = 0
+rationale = "The observed frequency or ordered-event interval has a nonnegative measurement domain, and its required crossing must exist for a usable observation."
+
 [[task.evaluation.metrics]]
 id = "power_w"
 unit = "W"
@@ -432,7 +438,6 @@ direction = "minimize"
 dimension = "supply"
 normalization = "ratio"
 scale = 1e-12
-lower = 0
 category = "performance"
 observations = [
     "condition_0:power_w",
@@ -441,22 +446,29 @@ baseline = [
     "source_condition_0:power_w",
 ]
 
+[task.evaluation.metrics.requirement]
+lower = 0
+rationale = "The declared powered circuit or driven switching network must consume nonnegative net supply/driver energy or quiescent current under the complete stated observation."
+
 [[task.evaluation.metrics]]
 id = "swing_v"
 unit = "V"
 aggregation = "max"
 direction = "maximize"
-lower = 0.6
 category = "performance"
 observations = [
     "condition_0:swing_v",
 ]
 
+[task.evaluation.metrics.requirement]
+lower = 0.6
+rationale = "The 1.2 V inverter threshold core requires at least the declared 0.6 V DC output swing to establish a meaningful logic transition; unique switching and transient crossings are independently required by the fixture."
+
 [task.evaluation.pre_layout]
-source_report_sha256 = "7a5787418bbed57c79c831f242b405561f2bc6441ec1f54299d52e60df0fe36e"
+source_report_sha256 = "37eef824221b8062d8969766eadf779825de51cd9327d080ebfaf05ccb020c7a"
 
 [task.evaluation.pre_layout.backends]
-"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"ef9cb87fa27b849376472663b7362673979b89e012f161ba47bb5f6af6ede8eb\", \"compatibility\": null, \"execution_sha256\": \"5424b579002782bfddf0a729715b8fbf2a5f7f2b4cf14982d7616e352d5de9be\", \"image_id\": \"sha256:6562558774d43c085a289bbba696c55959eb8051a0996f96633451fbeb9c652d\", \"limits\": {\"cpus\": 4, \"memory_mb\": 4096, \"pids\": 256}, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"d178a2dbf7b8ae93537de0a83c4368f730c62167c354adcc54ce4b03ab9abf29\", \"timeout_seconds\": 600.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}"
+"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"dfbdf2f93297bbe7d8b576fb988504bd0ecf85b93ef47c314a0f2c9c8830c3e7\", \"compatibility\": null, \"cpu_budget\": 8, \"execution_sha256\": \"495aa9623759f70228a236eb4825c2ae443ef6a741816d8cfc17d1830841dcef\", \"image_id\": \"sha256:060fee64f9f6e71a647e5e958b788d723c9d51d2928ff93e6a295db1959bc37f\", \"limits\": {\"cpus\": 8, \"memory_mb\": 4096, \"pids\": 256}, \"max_parallel_jobs\": 8, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"dce84f0cb44c7192511c807348bb3852682b1b4ec71ee94055876cb79ccbbdb1\", \"thread_environment\": {\"OMP_NUM_THREADS\": \"1\", \"OMP_THREAD_LIMIT\": \"1\"}, \"threads\": 1, \"timeout_seconds\": 600.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}"
 
 [task.evaluation.pre_layout.jobs.source_condition_0]
 operation = "circuit.simulate"
@@ -485,7 +497,7 @@ dc = "dc.raw"
 transient = "transient.raw"
 
 [task.evaluation.pre_layout.jobs.source_condition_0.input_sha256]
-deck = "c7fa64149fb838b9ae6b0fbcd173883a86be2db0869ba9f7a3d13e61def94476"
+deck = "7305f7b68fdb3c41a8e397a24b229aa79cd228e6d8e261654e9803d208ff84c0"
 dut = "5b7039e6399c1336c9ed31405b0176f512f2981b51e1fa8ffae36fa8d51af7aa"
 
 [task.evaluation.pre_layout.jobs.source_condition_0.measurements.delay_s]
@@ -508,6 +520,11 @@ unit = "V"
 value = 7.341807e-11
 unit = "s"
 
+[task.evaluation.pre_layout.jobs.source_condition_0.output_sha256]
+op = "974317db1b6ce6abb38ea59ab7f85ae70b26e31d7cde0e156d5f881d5582fd2d"
+dc = "81d88d3270a73f9d61c931227248a726fb3b5ab9b9c239f2f7d1127ba2a8534e"
+transient = "971ff7139ce4033900cb0b29e158a07a65900b3e67c7ee842bf4b1f5b17ebd2a"
+
 [toolchain.bindings]
 "layout.artifact" = "artifact"
 "layout.drc" = "drc"
@@ -520,7 +537,7 @@ unit = "s"
 type = "klayout-docker"
 
 [toolchain.backends.artifact.settings]
-image = "iclayout-bench-tools:local"
+image = "iclayout-eda-open:local"
 check = "artifact"
 timeout_seconds = 600
 
@@ -531,7 +548,7 @@ type = "klayout-docker"
 support = "klayout"
 
 [toolchain.backends.drc.settings]
-image = "iclayout-bench-tools:local"
+image = "iclayout-eda-open:local"
 check = "drc"
 support = "build/support/analog-db-klayout"
 profile = "drc-upstream.json"
@@ -544,7 +561,7 @@ type = "klayout-docker"
 support = "klayout"
 
 [toolchain.backends.lvs.settings]
-image = "iclayout-bench-tools:local"
+image = "iclayout-eda-open:local"
 check = "lvs"
 support = "build/support/analog-db-klayout"
 profile = "lvs-upstream.json"
@@ -557,7 +574,7 @@ type = "magic-rc-docker"
 support = "magic"
 
 [toolchain.backends.rc.settings]
-image = "iclayout-bench-tools:local"
+image = "iclayout-eda-open:local"
 support = "build/support/analog-db-magic"
 technology = "magic/ihp-sg13g2.tech"
 tech_name = "ihp-sg13g2"
@@ -569,7 +586,7 @@ timeout_seconds = 600
 type = "klayout-geometry-docker"
 
 [toolchain.backends.geometry.settings]
-image = "iclayout-bench-tools:local"
+image = "iclayout-eda-open:local"
 timeout_seconds = 120
 
 [toolchain.backends.simulation]
@@ -579,7 +596,10 @@ type = "ngspice-docker"
 support = "analog-models"
 
 [toolchain.backends.simulation.settings]
-image = "iclayout-bench-tools:local"
+max_parallel_jobs = 8
+threads = 1
+cpu_budget = 8
+image = "iclayout-eda-open:local"
 support = "build/support/analog-db-analog-models"
 timeout_seconds = 600
 

tasks/ihp-sg13g2/analog-db/cases/adc_001_inv1b/materials/testbench.spice

@@ -22,6 +22,7 @@ if kcl_residual > 1e-10
 end
 show all
 write op.raw all
+save i(vdd) i(vin) i(vss) v(drive) v(vdd) v(vin) v(vout)
 dc VIN 0 1.2 .001
 let ncross=0
 let idx=0

tasks/ihp-sg13g2/analog-db/cases/adc_001_inv1b/problem.md

@@ -18,30 +18,15 @@ Use IHP native KLayout main and maximum rule decks and named-interface LVS; Magi
 
 ## Electrical Requirements and Scoring
 
-Physical checks and declared functional bounds remain mandatory. Quality has no
-fixed allowed-degradation threshold. Each `source_*` job simulates the declared
-source circuit with exactly the same testbench, model resources, parameters,
-load and measurement window as its paired extracted-candidate job. A source
-observation is the 100-point electrical baseline; it is independent of the
-submitted GDS. All individual pairs are retained in the evaluation report.
-
-For a post-layout observation x and its source observation b:
-
-- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,
-  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;
-  s is a normalization floor, not an allowed degradation or pass threshold.
-- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.
-- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and
-  zero-valued operating points are never divided directly.
-
-Scoring uses `layout`. A metric uses its worst paired quality q. The score is
-S = 100 * product(q_i ** w_i), including area quality
-q_area = area_reference / candidate_functional_area. The weights below sum to
-one. Dimensions describe measurements but do not determine their weights.
-Physical or functional rejection scores zero; missing or invalid measurements
-produce an unknown score, including measurements with zero weight.
-Source-equivalent performance at the area reference scores 100; improvements
-can exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.
+Physical checks and the declared functional bounds must pass. Quality scoring imposes no fixed degradation allowance. Each `source_*` job and its corresponding candidate extracted circuit use exactly the same testbench, model resources, parameters, loads and measurement windows. Independent source observations define the 100-point electrical baseline without depending on the submitted GDS; reports retain every paired result.
+
+Let x be the post-layout measurement and b the source-circuit measurement under the same conditions:
+
+- Ratio normalization: maximize with q = x/b and minimize with q = b/x. When a numerical scale s is declared, use (x+s)/(b+s) and its reciprocal, respectively. The scale handles zero values as a normalization floor; it is neither an allowed degradation nor an acceptance bound.
+- Amplitude in dB: maximize with q = 10^((x-b)/20) and minimize with its reciprocal.
+- Target normalization: q = 1/(1+abs(x-b)/s), where s is the declared physical scale. Signed or zero-valued operating points are not divided directly.
+
+Use `layout` scoring. Each metric takes its worst paired quality q, and the total score is S = 100 * product(q_i ** w_i), with area quality q_area = area_reference / candidate_functional_area. The weights below sum to 1; metric dimensions describe measurements and do not determine weights. Physical or functional rejection scores zero; missing or invalid measurements leave the score unknown, and zero-weight observations must also be valid. Matching source-circuit performance at the reference area scores 100 points; better valid solutions may exceed 100. Weights express quality tradeoffs rather than hard bounds.
 
 | Metric | Unit | Definition | Bound | Quality |
 | --- | --- | --- | --- | --- |
@@ -53,13 +38,12 @@ can exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.
 
 The DC threshold is the unique output=0.6 V crossing, not a scan endpoint. Delay is the worse input 50% to opposite output 50% delay. Transition is the worse output 10–90% rise or 90–10% fall. Guards reject missing or multiple DC/transition crossings; independent audits require the intended 10–15 ns and 20–25 ns windows and correct ordering. DC high/low output uses actual endpoint samples, with a minimum 0.6 V swing establishing a meaningful logic transition. This is nominal loaded characterization, not Liberty/PVT or ADC accuracy.
 
-Static output bounds are physical rail-domain checks, nonnegative power/error bounds establish measurement domains, and KCL guards reject inconsistent DC solutions. All required conditions must be valid. No advertised upstream performance is a hard gate. The metric table specifies each target scale and normalization floor. Floors prevent zero-error ratios; scales and floors are normalization units, not acceptance tolerances.
+Static output bounds check the corresponding supply domain; nonnegative power/error conditions define the measurement domain; KCL checks reject inconsistent DC solutions. Every condition must be valid; upstream advertised performance is not a hard threshold. The metric table declares target scales and normalization floors; floors handle zero-error ratios, and neither scales nor floors are acceptance tolerances.
 
-For each metric take the worst same-condition source-paired quality. Target quality is `1/(1+abs(candidate-source)/scale)`; minimizing ratio quality is `(source+scale)/(candidate+scale)`.  Missing/nonfinite/invalid source or candidate measurements and tool failures yield an unknown score; completed physical/functional rejection yields zero. Bounds apply to every observation.
+Each metric uses the worst source-paired quality over matching conditions. Target quality is `1/(1+abs(candidate-source)/scale)`, and minimizing ratio quality is `(source+scale)/(candidate+scale)`. Missing, nonfinite or invalid source/candidate measurements and tool failures make the score unknown; confirmed physical/functional rejection scores zero. Gates apply separately to every observation.
 
 Compact area anchor: 120 um2 = 20 um2 NMOS contact envelope + 30 um2 PMOS/well envelope + 20 um2 body-contact/isolation allowance + 50 um2 routing. These envelopes follow the fixed widths and contact/isolation needs, not the witness bounding box. Coefficient 1: a single logic stage with loaded transitions and connectivity. The circuit and these anchors are fixed before participant evaluation.
 
-
 ### Score weights
 
 Inverter threshold element: switching threshold 25.5%; delay 34%; transition 12.8%; power 12.8%; area 15%. Each objective's weight is divided equally among its metrics.
@@ -76,4 +60,4 @@ Inverter threshold element: switching threshold 25.5%; delay 34%; transition 12.
 
 Solve budget: **6 hours**.
 
-Use the runtime task/protocol and reviewed resource bundle to discover tools and feedback. Submit `/workspace/output/final.gds` explicitly through the protocol; merely writing it is not a submission. The reference and maintainer source records are excluded from solver inputs.
+Discover tools and feedback through the runtime task, protocol and reviewed resource bundle. Explicitly submit `/workspace/output/final.gds` through the protocol; writing a file alone does not submit it. Reference assets and maintainer source records are not solver inputs.

tasks/ihp-sg13g2/analog-db/cases/amp_001_5t/case.toml

@@ -1,15 +1,15 @@
-in_core = false
 kind = "layout_case"
 id = "ihp-sg13g2.analog-db.amp_001_5t"
 title = "Five-Transistor OTA Core with Bias Mirror"
 status = "qualified"
+in_core = false
 
 [[assets]]
 path = "materials/schematic.svg"
 role = "schematic"
 visibility = "maintainer"
 format = "svg"
-sha256 = "800b203d54fc6c904b885bb5d631d5ec235c17853708d454804c437846318e7d"
+sha256 = "c0bc0afe7c4392b11e3b1836cae47240e81826274c39c7d59ee00f9eb73a87c3"
 
 [[assets]]
 path = "reference/amp_001_5t.gds"
@@ -28,13 +28,13 @@ environment = "ihp-sg13g2-analog-db-ota-rc-tt"
 [task.inputs.description]
 path = "problem.md"
 format = "text"
-sha256 = "7b9c7dd3c5f0ef19f55d3a9a7b9d18042f0ca74940ae76b01ee0c59e348df4ea"
+sha256 = "c2c99ac9c03e4a8d2a7271d9d3b40b607a0c847b8950f7122a684cc1597d3194"
 
 [task.inputs.netlist]
 path = "materials/circuit.cdl"
 format = "spice"
-sha256 = "55016e668fdcbc3087c98af6d92f196225fd586da3a9a8e049200fd0419c119f"
 subcircuit = "amp_001_5t"
+sha256 = "55016e668fdcbc3087c98af6d92f196225fd586da3a9a8e049200fd0419c119f"
 
 [task.inputs.simulation]
 path = "materials/circuit.spice"
@@ -44,7 +44,7 @@ sha256 = "08afdd756d9a1bb7409ddee1ef5a525ec1a0f0261eda6a49db150c1618cb853c"
 [task.inputs.performance]
 path = "materials/testbench.spice"
 format = "spice"
-sha256 = "025c2e754a449b286cdb4b9487ae81c08d0cb2375b0ccb644e522f1720350c5b"
+sha256 = "b661d0d87ce39aac3222d2378bf1e8353f985f6aac729965e318d99882f92a19"
 
 [task.constraints]
 quality = [
@@ -404,7 +404,10 @@ baseline = [
     "source_nominal:unity_gain_bandwidth",
 ]
 normalization = "ratio"
+
+[task.evaluation.metrics.requirement]
 lower = 0
+rationale = "The observed frequency or ordered-event interval has a nonnegative measurement domain, and its required crossing must exist for a usable observation."
 
 [[task.evaluation.metrics]]
 id = "phase_margin"
@@ -421,8 +424,11 @@ baseline = [
 ]
 normalization = "target"
 scale = 180
+
+[task.evaluation.metrics.requirement]
 lower = 0
 upper = 180
+rationale = "The declared negative-feedback loop must stay on the measured 0 to 180 degree stable-feedback branch at the required unity crossing; the amount of positive phase margin remains a scored objective."
 
 [[task.evaluation.metrics]]
 id = "output_bias"
@@ -439,8 +445,11 @@ baseline = [
 ]
 normalization = "target"
 scale = 1.5
+
+[task.evaluation.metrics.requirement]
 lower = 0
 upper = 1.5
+rationale = "The declared node voltage or voltage span must remain within its ground-to-supply operating envelope; precision relative to the source remains a scored objective."
 
 [[task.evaluation.metrics]]
 id = "bias_voltage"
@@ -457,8 +466,11 @@ baseline = [
 ]
 normalization = "target"
 scale = 1.5
+
+[task.evaluation.metrics.requirement]
 lower = 0
 upper = 1.5
+rationale = "The declared node voltage or voltage span must remain within its ground-to-supply operating envelope; precision relative to the source remains a scored objective."
 
 [[task.evaluation.metrics]]
 id = "supply_power"
@@ -474,14 +486,17 @@ baseline = [
     "source_nominal:supply_power",
 ]
 normalization = "ratio"
-lower = 0
 scale = 1e-12
 
+[task.evaluation.metrics.requirement]
+lower = 0
+rationale = "The declared powered circuit or driven switching network must consume nonnegative net supply/driver energy or quiescent current under the complete stated observation."
+
 [task.evaluation.pre_layout]
-source_report_sha256 = "21eaa5a7e7fe46d4c3b669b3bf39685429a713f9d65cab336b463c8acb1077e4"
+source_report_sha256 = "f6c01532c6ccb4619cbbb946b1b3d47c60d10ac5cecdb10269b087d38510cc19"
 
 [task.evaluation.pre_layout.backends]
-"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"ef9cb87fa27b849376472663b7362673979b89e012f161ba47bb5f6af6ede8eb\", \"compatibility\": null, \"execution_sha256\": \"5424b579002782bfddf0a729715b8fbf2a5f7f2b4cf14982d7616e352d5de9be\", \"image_id\": \"sha256:6562558774d43c085a289bbba696c55959eb8051a0996f96633451fbeb9c652d\", \"limits\": {\"cpus\": 4, \"memory_mb\": 4096, \"pids\": 256}, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"5c08f72e97102ca6b0061884b62f431130e119234364146718f1fbb2a5eeaefb\", \"timeout_seconds\": 600.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}"
+"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"dfbdf2f93297bbe7d8b576fb988504bd0ecf85b93ef47c314a0f2c9c8830c3e7\", \"compatibility\": null, \"cpu_budget\": 8, \"execution_sha256\": \"495aa9623759f70228a236eb4825c2ae443ef6a741816d8cfc17d1830841dcef\", \"image_id\": \"sha256:060fee64f9f6e71a647e5e958b788d723c9d51d2928ff93e6a295db1959bc37f\", \"limits\": {\"cpus\": 8, \"memory_mb\": 4096, \"pids\": 256}, \"max_parallel_jobs\": 8, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"dce84f0cb44c7192511c807348bb3852682b1b4ec71ee94055876cb79ccbbdb1\", \"thread_environment\": {\"OMP_NUM_THREADS\": \"1\", \"OMP_THREAD_LIMIT\": \"1\"}, \"threads\": 1, \"timeout_seconds\": 600.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}"
 
 [task.evaluation.pre_layout.jobs.source_nominal]
 operation = "circuit.simulate"
@@ -507,7 +522,7 @@ op = "ota-op.raw"
 ac = "ota-ac.raw"
 
 [task.evaluation.pre_layout.jobs.source_nominal.input_sha256]
-deck = "025c2e754a449b286cdb4b9487ae81c08d0cb2375b0ccb644e522f1720350c5b"
+deck = "b661d0d87ce39aac3222d2378bf1e8353f985f6aac729965e318d99882f92a19"
 dut = "08afdd756d9a1bb7409ddee1ef5a525ec1a0f0261eda6a49db150c1618cb853c"
 
 [task.evaluation.pre_layout.jobs.source_nominal.measurements.bias_voltage]
@@ -534,6 +549,10 @@ unit = "W"
 value = 1211382.0
 unit = "Hz"
 
+[task.evaluation.pre_layout.jobs.source_nominal.output_sha256]
+op = "14d323115c6673ed2d976e5136664f425e3db124dd99d6c50fe7cc0ffe3ec6ef"
+ac = "072fc4ed3bbeccdc8d5ffa92ec56199d5dd6fc1f6270576aa70ca1a7197319b4"
+
 [toolchain.bindings]
 "layout.artifact" = "artifact"
 "layout.drc" = "drc"
@@ -546,7 +565,7 @@ unit = "Hz"
 type = "klayout-docker"
 
 [toolchain.backends.artifact.settings]
-image = "iclayout-bench-tools:local"
+image = "iclayout-eda-open:local"
 check = "artifact"
 timeout_seconds = 600
 
@@ -557,7 +576,7 @@ type = "klayout-docker"
 support = "klayout"
 
 [toolchain.backends.drc.settings]
-image = "iclayout-bench-tools:local"
+image = "iclayout-eda-open:local"
 check = "drc"
 support = "build/support/analog-db-klayout"
 profile = "drc-upstream.json"
@@ -570,7 +589,7 @@ type = "klayout-docker"
 support = "klayout"
 
 [toolchain.backends.lvs.settings]
-image = "iclayout-bench-tools:local"
+image = "iclayout-eda-open:local"
 check = "lvs"
 support = "build/support/analog-db-klayout"
 profile = "lvs-upstream.json"
@@ -583,7 +602,7 @@ type = "magic-rc-docker"
 support = "magic"
 
 [toolchain.backends.rc.settings]
-image = "iclayout-bench-tools:local"
+image = "iclayout-eda-open:local"
 support = "build/support/analog-db-magic"
 technology = "magic/ihp-sg13g2.tech"
 tech_name = "ihp-sg13g2"
@@ -595,7 +614,7 @@ timeout_seconds = 600
 type = "klayout-geometry-docker"
 
 [toolchain.backends.geometry.settings]
-image = "iclayout-bench-tools:local"
+image = "iclayout-eda-open:local"
 timeout_seconds = 120
 
 [toolchain.backends.simulation]
@@ -605,7 +624,10 @@ type = "ngspice-docker"
 support = "analog-models"
 
 [toolchain.backends.simulation.settings]
-image = "iclayout-bench-tools:local"
+max_parallel_jobs = 8
+threads = 1
+cpu_budget = 8
+image = "iclayout-eda-open:local"
 support = "build/support/analog-db-analog-models"
 timeout_seconds = 600
 

tasks/ihp-sg13g2/analog-db/cases/amp_001_5t/materials/testbench.spice

@@ -21,6 +21,7 @@ let bias_voltage = v(ibias)
 let supply_power = -v(vdd)*i(VDD)
 print output_bias bias_voltage supply_power
 write ota-op.raw all
+save i(vdd) v(ibias) v(vdd) v(vinn) v(vinp) v(vout)
 ac dec 100 1 100meg
 let transfer = v(vout)/(v(vinp)-v(vinn))
 let gain_db = db(transfer)

tasks/ihp-sg13g2/analog-db/cases/amp_001_5t/problem.md

@@ -55,43 +55,19 @@ PVT, noise, distortion, transient settling, EM or manufacturing signoff.
 
 ## Electrical Requirements and Scoring
 
-Physical checks and declared functional bounds remain mandatory. Quality has no
-fixed allowed-degradation threshold. Each `source_*` job simulates the declared
-source circuit with exactly the same testbench, model resources, parameters,
-load and measurement window as its paired extracted-candidate job. A source
-observation is the 100-point electrical baseline; it is independent of the
-submitted GDS. All individual pairs are retained in the evaluation report.
-
-For a post-layout observation x and its source observation b:
-
-- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,
-  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;
-  s is a normalization floor, not an allowed degradation or pass threshold.
-- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.
-- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and
-  zero-valued operating points are never divided directly.
-
-Scoring uses `layout`. A metric uses its worst paired quality q. The score is
-S = 100 * product(q_i ** w_i), including area quality
-q_area = area_reference / candidate_functional_area. The weights below sum to
-one. Dimensions describe measurements but do not determine their weights.
-Physical or functional rejection scores zero; missing or invalid measurements
-produce an unknown score, including measurements with zero weight.
-Source-equivalent performance at the area reference scores 100; improvements
-can exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.
-
-Measurement definitions below use the supplied SPICE node/source names.
-`v(n)` is node voltage and `i(V)` is current into a voltage source; delivered
-power therefore uses a minus sign. `db(z)=20*log10(abs(z))`, `mag/abs`
-denote magnitude, and `cph` is continuous phase in radians. `find`, `when`,
-`from/to`, and `rise/fall` retain the deck's interpolation, window and
-crossing conventions; SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/
-milli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv`
-mean the stated window average, extrema and sampled derivative. All
-declared conditions are measured separately and paired with the same
-source condition; a group uses its worst paired quality.
-
-| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | Dimension |
+Physical checks and the declared functional bounds must pass. Quality scoring imposes no fixed degradation allowance. Each `source_*` job and its corresponding candidate extracted circuit use exactly the same testbench, model resources, parameters, loads and measurement windows. Independent source observations define the 100-point electrical baseline without depending on the submitted GDS; reports retain every paired result.
+
+Let x be the post-layout measurement and b the source-circuit measurement under the same conditions:
+
+- Ratio normalization: maximize with q = x/b and minimize with q = b/x. When a numerical scale s is declared, use (x+s)/(b+s) and its reciprocal, respectively. The scale handles zero values as a normalization floor; it is neither an allowed degradation nor an acceptance bound.
+- Amplitude in dB: maximize with q = 10^((x-b)/20) and minimize with its reciprocal.
+- Target normalization: q = 1/(1+abs(x-b)/s), where s is the declared physical scale. Signed or zero-valued operating points are not divided directly.
+
+Use `layout` scoring. Each metric takes its worst paired quality q, and the total score is S = 100 * product(q_i ** w_i), with area quality q_area = area_reference / candidate_functional_area. The weights below sum to 1; metric dimensions describe measurements and do not determine weights. Physical or functional rejection scores zero; missing or invalid measurements leave the score unknown, and zero-weight observations must also be valid. Matching source-circuit performance at the reference area scores 100 points; better valid solutions may exceed 100. Weights express quality tradeoffs rather than hard bounds.
+
+The measurements below use the supplied SPICE node and source names. `v(n)` is a node voltage; `i(V)` is current flowing into a voltage source, so delivered power uses a negative sign. `db(z)=20*log10(abs(z))`; `mag/abs` denote magnitude, and `cph` denotes continuous phase in radians. `find`, `when`, `from/to` and `rise/fall` follow the deck's interpolation, window and crossing conventions. SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/milli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv` represent window averages, extrema and sampled derivatives. Measure each operating condition independently, pair it with the source result under that condition, and take the worst paired quality within each metric group.
+
+| Metric | Definition / observation | Unit | Quality normalization | Functional range | Scale | Dimension |
 | --- | --- | --- | --- | --- | --- | --- |
 | `low_frequency_gain` | AC: Value of `(db((v(vout)/(v(vinp)-v(vinn))))) at=1`. | dB | maximize / db20 | −∞ … +∞ | — | response |
 | `unity_gain_bandwidth` | AC: Crossing coordinate where `(db((v(vout)/(v(vinp)-v(vinn)))))=0 fall=1`. | Hz | maximize / ratio | 0 … +∞ | — | response |
@@ -100,15 +76,13 @@ source condition; a group uses its worst paired quality.
 | `bias_voltage` | DC operating point: `v(ibias)`. | V | target / target | 0 … 1.5 | 1.5 | bias |
 | `supply_power` | DC operating point: `-v(vdd)*i(VDD)`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |
 
-Area reference: **1198.35 um2**. 8 expanded device instances; sum of device/contact envelopes 754.0020 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.
-
-The capability coefficient remains **4**; it is independent of
-the reference-relative task score.
+Area reference: **1198.35 um2**. The expanded circuit has 8 device instances, a sum of device/contact envelopes 754.0020 um2, a one-sided envelope margin of 0.6 um, a routing allowance of 50%, and a total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across both sides, and the envelope sum is displayed to four decimal places. MOS/passive envelopes use W/L (or resistor dimensions) and multiplicity, including explicit contacts and HBT emitter/contact envelopes. This is a frozen engineering estimate, not a process minimum or a proven achievable area.
 
+The capability coefficient is **4**, independent of this task's reference-normalized score.
 
 ### Score weights
 
-Small-signal OTAs: gain 27%; bandwidth 22.5%; phase margin 22.5%; operating points 4.5%; power 13.5%; area 10%. Each objective's weight is divided equally among its metrics.
+Small-signal OTAs: gain 27%, bandwidth 22.5%, phase margin 22.5%, operating points 4.5%, power 13.5%, area 10%. Each objective's weight is divided equally among its metrics.
 
 | Metric | Weight |
 | --- | ---: |

tasks/ihp-sg13g2/analog-db/cases/amp_002_alfio_raffc/case.toml

@@ -1,15 +1,15 @@
-in_core = false
 kind = "layout_case"
 id = "ihp-sg13g2.analog-db.amp_002_alfio_raffc"
 title = "Current-Buffer and Active-Feedforward OTA"
 status = "qualified"
+in_core = false
 
 [[assets]]
 path = "materials/schematic.svg"
 role = "schematic"
 visibility = "maintainer"
 format = "svg"
-sha256 = "f0fd720849c6e636d0512d3866bf2dd20a72572547fb8228d44bef62cd8225c2"
+sha256 = "5b5d6437261a850f444341f917763ee4e626f0ca646d906169d2a6ff91b7bde6"
 
 [[assets]]
 path = "reference/amp_002_alfio_raffc.gds"
@@ -28,18 +28,18 @@ environment = "ihp-sg13g2-amp_002_alfio_raffc-nominal-rc"
 [task.inputs.description]
 path = "problem.md"
 format = "text"
-sha256 = "6145ab39c56eddbedf31f06adcc32dec8468eebdc215eaf70974f47a50026e64"
+sha256 = "5a979111556195b899d02be1bac3aa2a7250038a526019e05717343558130580"
 
 [task.inputs.netlist]
 path = "materials/circuit.cdl"
 format = "spice"
-sha256 = "da8813082f4c6fb73b07d677efa730e1f1c250c9ebd438233f3f725346ac88f9"
 subcircuit = "amp_002_alfio_raffc"
+sha256 = "da8813082f4c6fb73b07d677efa730e1f1c250c9ebd438233f3f725346ac88f9"
 
 [task.inputs.performance]
 path = "materials/testbench.spice"
 format = "spice"
-sha256 = "736eb30bb88a695ddefced6b9b40651955709b5e0a1b16f76c345db9a9095a49"
+sha256 = "5d1f948c2dd4a670cdfe512beb0fc0902c9bc1fd02f56a1d8e8d62bbc8d7d0fe"
 
 [task.inputs.simulation]
 path = "materials/circuit.spice"
@@ -483,8 +483,11 @@ baseline = [
 ]
 normalization = "target"
 scale = 1.2
+
+[task.evaluation.metrics.requirement]
 lower = 0
 upper = 1.2
+rationale = "The declared node voltage or voltage span must remain within its ground-to-supply operating envelope; precision relative to the source remains a scored objective."
 
 [[task.evaluation.metrics]]
 id = "bias_v"
@@ -505,8 +508,11 @@ baseline = [
 ]
 normalization = "target"
 scale = 1.2
+
+[task.evaluation.metrics.requirement]
 lower = 0
 upper = 1.2
+rationale = "The declared node voltage or voltage span must remain within its ground-to-supply operating envelope; precision relative to the source remains a scored objective."
 
 [[task.evaluation.metrics]]
 id = "power_w"
@@ -526,9 +532,12 @@ baseline = [
     "source_condition_2:power_w",
 ]
 normalization = "ratio"
-lower = 0
 scale = 1e-12
 
+[task.evaluation.metrics.requirement]
+lower = 0
+rationale = "The declared powered circuit or driven switching network must consume nonnegative net supply/driver energy or quiescent current under the complete stated observation."
+
 [[task.evaluation.metrics]]
 id = "dc_gain_db"
 category = "performance"
@@ -566,7 +575,10 @@ baseline = [
     "source_condition_2:unity_hz",
 ]
 normalization = "ratio"
+
+[task.evaluation.metrics.requirement]
 lower = 0
+rationale = "The observed frequency or ordered-event interval has a nonnegative measurement domain, and its required crossing must exist for a usable observation."
 
 [[task.evaluation.metrics]]
 id = "phase_margin_deg"
@@ -587,8 +599,11 @@ baseline = [
 ]
 normalization = "target"
 scale = 180
+
+[task.evaluation.metrics.requirement]
 lower = 0
 upper = 180
+rationale = "The declared negative-feedback loop must stay on the measured 0 to 180 degree stable-feedback branch at the required unity crossing; the amount of positive phase margin remains a scored objective."
 
 [[task.evaluation.metrics]]
 id = "recovery_up_v"
@@ -607,10 +622,13 @@ baseline = [
     "source_condition_1:recovery_up_v",
     "source_condition_2:recovery_up_v",
 ]
-normalization = "ratio"
-lower = 0
+normalization = "saturating_ratio"
 scale = 1e-06
 
+[task.evaluation.metrics.requirement]
+lower = 0
+rationale = "The absolute error, voltage span, charge magnitude or recovery deviation has a nonnegative measurement domain; its positive value remains a continuously scored quality observation."
+
 [[task.evaluation.metrics]]
 id = "recovery_down_v"
 category = "performance"
@@ -628,10 +646,13 @@ baseline = [
     "source_condition_1:recovery_down_v",
     "source_condition_2:recovery_down_v",
 ]
-normalization = "ratio"
-lower = 0
+normalization = "saturating_ratio"
 scale = 1e-06
 
+[task.evaluation.metrics.requirement]
+lower = 0
+rationale = "The absolute error, voltage span, charge magnitude or recovery deviation has a nonnegative measurement domain; its positive value remains a continuously scored quality observation."
+
 [[task.evaluation.metrics]]
 id = "step_gain"
 category = "performance"
@@ -670,9 +691,12 @@ baseline = [
     "source_condition_2:mean_power_w",
 ]
 normalization = "ratio"
-lower = 0
 scale = 1e-12
 
+[task.evaluation.metrics.requirement]
+lower = 0
+rationale = "The declared powered circuit or driven switching network must consume nonnegative net supply/driver energy or quiescent current under the complete stated observation."
+
 [[task.evaluation.metrics]]
 id = "peak_v"
 category = "performance"
@@ -692,8 +716,11 @@ baseline = [
 ]
 normalization = "target"
 scale = 1.2
+
+[task.evaluation.metrics.requirement]
 lower = 0
 upper = 1.2
+rationale = "The declared node voltage or voltage span must remain within its ground-to-supply operating envelope; precision relative to the source remains a scored objective."
 
 [[task.evaluation.metrics]]
 id = "trough_v"
@@ -714,14 +741,17 @@ baseline = [
 ]
 normalization = "target"
 scale = 1.2
+
+[task.evaluation.metrics.requirement]
 lower = 0
 upper = 1.2
+rationale = "The declared node voltage or voltage span must remain within its ground-to-supply operating envelope; precision relative to the source remains a scored objective."
 
 [task.evaluation.pre_layout]
-source_report_sha256 = "8f642ed35e2d4df18b0a38307b75ca6865c3cd30d9340d2149f39d3e6a25f15c"
+source_report_sha256 = "ea09a59573fa9e2630dfa568b51b32b02c3132b865d530d0fb8ab6f918c7da0e"
 
 [task.evaluation.pre_layout.backends]
-"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"ef9cb87fa27b849376472663b7362673979b89e012f161ba47bb5f6af6ede8eb\", \"compatibility\": null, \"execution_sha256\": \"5424b579002782bfddf0a729715b8fbf2a5f7f2b4cf14982d7616e352d5de9be\", \"image_id\": \"sha256:6562558774d43c085a289bbba696c55959eb8051a0996f96633451fbeb9c652d\", \"limits\": {\"cpus\": 4, \"memory_mb\": 4096, \"pids\": 256}, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"53371acbaa4d0ffa73dda7ad2e19190df1f6993be92a6fc17d97a1adc578e7ea\", \"timeout_seconds\": 600.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}"
+"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"dfbdf2f93297bbe7d8b576fb988504bd0ecf85b93ef47c314a0f2c9c8830c3e7\", \"compatibility\": null, \"cpu_budget\": 8, \"execution_sha256\": \"495aa9623759f70228a236eb4825c2ae443ef6a741816d8cfc17d1830841dcef\", \"image_id\": \"sha256:060fee64f9f6e71a647e5e958b788d723c9d51d2928ff93e6a295db1959bc37f\", \"limits\": {\"cpus\": 8, \"memory_mb\": 4096, \"pids\": 256}, \"max_parallel_jobs\": 8, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"a202c3d9d407fa71903be9db155aeb1eb3f9bccbb7ed18bfd0eaa1ea925dc151\", \"thread_environment\": {\"OMP_NUM_THREADS\": \"1\", \"OMP_THREAD_LIMIT\": \"1\"}, \"threads\": 1, \"timeout_seconds\": 600.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}"
 
 [task.evaluation.pre_layout.jobs.source_condition_0]
 operation = "circuit.simulate"
@@ -758,7 +788,7 @@ ac = "ac.raw"
 transient = "transient.raw"
 
 [task.evaluation.pre_layout.jobs.source_condition_0.input_sha256]
-deck = "736eb30bb88a695ddefced6b9b40651955709b5e0a1b16f76c345db9a9095a49"
+deck = "5d1f948c2dd4a670cdfe512beb0fc0902c9bc1fd02f56a1d8e8d62bbc8d7d0fe"
 dut = "101a8960de9230e887bc5e29cc5bb91b87749f88793a888baaa41529051c6469"
 
 [task.evaluation.pre_layout.jobs.source_condition_0.measurements.bias_v]
@@ -809,6 +839,11 @@ unit = "V"
 value = 1884332.0
 unit = "Hz"
 
+[task.evaluation.pre_layout.jobs.source_condition_0.output_sha256]
+op = "2a1e40d283124bfbcc66e3224aa49aceea8e26ba300c76866dfbd35bdbc6492a"
+ac = "d840ecdab6c7703a5878acfd41b8b095f717f86154416e53d9f5b2bc7f85e44d"
+transient = "5d6bd5fb38e3fa67add5412258a1be1b4625dd407170623a06e15761f296f4fb"
+
 [task.evaluation.pre_layout.jobs.source_condition_1]
 operation = "circuit.simulate"
 
@@ -844,7 +879,7 @@ ac = "ac.raw"
 transient = "transient.raw"
 
 [task.evaluation.pre_layout.jobs.source_condition_1.input_sha256]
-deck = "736eb30bb88a695ddefced6b9b40651955709b5e0a1b16f76c345db9a9095a49"
+deck = "5d1f948c2dd4a670cdfe512beb0fc0902c9bc1fd02f56a1d8e8d62bbc8d7d0fe"
 dut = "101a8960de9230e887bc5e29cc5bb91b87749f88793a888baaa41529051c6469"
 
 [task.evaluation.pre_layout.jobs.source_condition_1.measurements.bias_v]
@@ -895,6 +930,11 @@ unit = "V"
 value = 1894771.0
 unit = "Hz"
 
+[task.evaluation.pre_layout.jobs.source_condition_1.output_sha256]
+op = "2a1e40d283124bfbcc66e3224aa49aceea8e26ba300c76866dfbd35bdbc6492a"
+ac = "b5ff8c6188094211218eefad26cafcf13c2973e435a18ed9ba330b8006a7d77d"
+transient = "1c58d57d3867b157ecc5d19026c2232aed77ab32fe6ff9b82660aee3e539ba39"
+
 [task.evaluation.pre_layout.jobs.source_condition_2]
 operation = "circuit.simulate"
 
@@ -930,7 +970,7 @@ ac = "ac.raw"
 transient = "transient.raw"
 
 [task.evaluation.pre_layout.jobs.source_condition_2.input_sha256]
-deck = "736eb30bb88a695ddefced6b9b40651955709b5e0a1b16f76c345db9a9095a49"
+deck = "5d1f948c2dd4a670cdfe512beb0fc0902c9bc1fd02f56a1d8e8d62bbc8d7d0fe"
 dut = "101a8960de9230e887bc5e29cc5bb91b87749f88793a888baaa41529051c6469"
 
 [task.evaluation.pre_layout.jobs.source_condition_2.measurements.bias_v]
@@ -981,6 +1021,11 @@ unit = "V"
 value = 1910778.0
 unit = "Hz"
 
+[task.evaluation.pre_layout.jobs.source_condition_2.output_sha256]
+op = "2a1e40d283124bfbcc66e3224aa49aceea8e26ba300c76866dfbd35bdbc6492a"
+ac = "4774f65e432dc5642f984a9006cc1dd6eb63ce8091b86db2a3deb79dd9c9dc64"
+transient = "1b7cb1f88eaf3f84652acbefbcca5dbfa29bfd2d3812b070ed53a0b921891781"
+
 [toolchain.bindings]
 "layout.artifact" = "artifact"
 "layout.drc" = "drc"
@@ -993,7 +1038,7 @@ unit = "Hz"
 type = "klayout-docker"
 
 [toolchain.backends.artifact.settings]
-image = "iclayout-bench-tools:local"
+image = "iclayout-eda-open:local"
 check = "artifact"
 timeout_seconds = 600
 
@@ -1004,7 +1049,7 @@ type = "klayout-docker"
 support = "klayout"
 
 [toolchain.backends.drc.settings]
-image = "iclayout-bench-tools:local"
+image = "iclayout-eda-open:local"
 check = "drc"
 support = "build/support/input-pair-klayout"
 profile = "drc-upstream.json"
@@ -1017,7 +1062,7 @@ type = "klayout-docker"
 support = "klayout"
 
 [toolchain.backends.lvs.settings]
-image = "iclayout-bench-tools:local"
+image = "iclayout-eda-open:local"
 check = "lvs"
 support = "build/support/input-pair-klayout"
 profile = "lvs-upstream.json"
@@ -1030,7 +1075,7 @@ type = "magic-rc-docker"
 support = "magic"
 
 [toolchain.backends.rc.settings]
-image = "iclayout-bench-tools:local"
+image = "iclayout-eda-open:local"
 support = "build/support/input-pair-magic"
 technology = "magic/ihp-sg13g2.tech"
 tech_name = "ihp-sg13g2"
@@ -1044,7 +1089,7 @@ grid_subdivision = 2
 type = "klayout-geometry-docker"
 
 [toolchain.backends.geometry.settings]
-image = "iclayout-bench-tools:local"
+image = "iclayout-eda-open:local"
 timeout_seconds = 120
 
 [toolchain.backends.simulation]
@@ -1054,7 +1099,10 @@ type = "ngspice-docker"
 support = "analog-res-models"
 
 [toolchain.backends.simulation.settings]
-image = "iclayout-bench-tools:local"
+max_parallel_jobs = 8
+threads = 1
+cpu_budget = 8
+image = "iclayout-eda-open:local"
 support = "build/support/analog-res-models"
 timeout_seconds = 600
 

tasks/ihp-sg13g2/analog-db/cases/amp_002_alfio_raffc/materials/testbench.spice

@@ -21,6 +21,7 @@ let bias_v=v(net1)
 let power_w=-v(vdd)*i(VDD)
 print output_v bias_v power_w
 write op.raw v(vout) v(net1) i(VDD)
+save i(vdd) v(net1) v(vdd) v(vm) v(vout) v(vp)
 ac dec 150 0.01 100meg
 let transfer=-v(vout)/v(vm)
 let gain_db=db(transfer)

tasks/ihp-sg13g2/analog-db/cases/amp_002_alfio_raffc/problem.md

@@ -22,12 +22,11 @@ common source `net31`, electrically separate from the VDD well. No internal
 ideal bias source or output servo is introduced. Capacitor values are rounded
 to physical geometry; every branch remains internal to the DUT.
 
-
 ## Inputs and Interface
 
 - `materials/circuit.cdl`: authoritative native LVS circuit.
-- `materials/circuit.spice`: matching process-model circuit.
-- `materials/testbench.spice`: public bias, AC injection and transient deck.
+- `materials/circuit.spice`: simulation circuit bound to the process models.
+- `materials/testbench.spice`: bias, AC injection and transient tests.
 
 Ordered ports: `vss vdd vinn vinp vout net1`. VSS is return, VDD is supply,
 VINN/VINP are inverting/noninverting inputs, VOUT is output, and `net1`
@@ -38,30 +37,16 @@ all internal branches and total multiplicities in the authoritative netlist.
 Native equivalent parallel fingers are allowed only when LVS and electrical
 requirements pass. Do not short distinct ports or create extra driven monitors.
 
-Internal passives, distinct from the external load:
+Internal passive devices are listed below; external loads are declared separately:
 
 - `c0`: `net063` → `vout`, 3 parallel `cap_cmim` unit(s), each 43.46 × 43.46 um; nominal total 8.520333 pF.
 - `c1`: `net050` → `net013`, 1 parallel `cap_cmim` unit(s), each 36.515 × 36.515 um; nominal total 2.0058602 pF.
 
-
 ## Operating Conditions
 
-Use typical MOS/MIM/poly models, 27 C, VDD=1.2 V and the stated external bias.
-All output loads 5/10/20 pF must pass. At DC, VINP=0.5 V and VOUT drives VINN
-through a zero-volt measurement source. AC injects 1 V in series with this
-feedback connection, with VINP AC=0. The return ratio is
-`T=-V(vout)/V(vm)` at this high-impedance MOS input boundary. Sweep 0.01 Hz
-to 100 MHz at 150 points/decade. Use continuous phase without an arbitrary
-low-frequency phase-offset correction; the first descending 0 dB crossing
-defines unity frequency and `180+phase(T)` there defines phase margin.
-A missing crossing is an evaluator error.
-
-VINP rises 0.5→0.7 V at 2–2.02 us and falls at 10.02–10.04 us, repeating
-every 16 us. Simulate 0–18 us with Gear order 2, 2 ns maximum step,
-`rshunt=1e12`, `reltol=1e-5`, `abstol=1e-14`, `vntol=1e-8`.
-The numerical shunt is not a manufactured bias or startup device.
-PVT, mismatch, noise, distortion, rail-to-rail operation, supply startup and
-arbitrary-load stability remain outside the contract.
+Use typical MOS/MIM/poly models at 27 C, VDD=1.2 V and the declared external bias. All three output loads, 5/10/20 pF, must pass. At DC, VINP=0.5 V and VOUT feeds back to VINN through a zero-volt measurement source. For AC, inject 1 V in series with the feedback connection and set VINP AC=0; the return ratio at the high-impedance MOS input boundary is `T=-V(vout)/V(vm)`. Sweep 150 points per decade from 0.01 Hz to 100 MHz with continuous phase, without arbitrary correction of the low-frequency phase offset. The first falling 0 dB crossing defines unity-gain frequency, and `180+phase(T)` at that crossing defines phase margin. A missing crossing is an evaluation error.
+
+VINP rises from 0.5 V to 0.7 V during 2–2.02 us and falls during 10.02–10.04 us, repeating every 16 us. Simulate 0–18 us with second-order Gear, a maximum step of 2 ns, `rshunt=1e12`, `reltol=1e-5`, `abstol=1e-14` and `vntol=1e-8`. Numerical shunt branches are not physical bias or startup devices. PVT, mismatch, noise, distortion, rail-to-rail operation, power-up and stability under arbitrary loads are outside scope.
 
 ## Physical Requirements
 
@@ -72,50 +57,25 @@ functional envelope. All functional device, contact and routing drawing layers
 listed in the runtime `outline` constraint contribute to bounding-box area;
 annotation and pin-purpose layers do not.
 
-Post-layout simulation consumes candidate-derived Magic RC with the physical
-MIM/poly devices and interconnect parasitics. Half-grid GDS import is explicit.
-Magic idealizes substrate/well taps; source simulation retains finite tap models.
-Distributed substrate resistance/noise and fabrication signoff are unqualified.
+Post-layout simulation uses the candidate's Magic RC netlist, including physical MIM/poly devices and interconnect parasitics, with explicit handling of half-grid GDS import. Magic idealizes substrate/well contacts; source simulation retains finite contact models. Distributed substrate resistance, substrate noise and manufacturing signoff are outside scope.
 
 ## Electrical Requirements and Scoring
 
-Physical checks and declared functional bounds remain mandatory. Quality has no
-fixed allowed-degradation threshold. Each `source_*` job simulates the declared
-source circuit with exactly the same testbench, model resources, parameters,
-load and measurement window as its paired extracted-candidate job. A source
-observation is the 100-point electrical baseline; it is independent of the
-submitted GDS. All individual pairs are retained in the evaluation report.
-
-For a post-layout observation x and its source observation b:
-
-- Maximize: q = x/b; minimize: q = b/x. When a numerical scale s is declared,
-  use (x+s)/(b+s) or its inverse. This handles zero-valued error measurements;
-  s is a normalization floor, not an allowed degradation or pass threshold.
-- Amplitude dB: q = 10^((x-b)/20) for maximize, its inverse for minimize.
-- Target: q = 1/(1+abs(x-b)/s), with a declared physical scale s. Signed and
-  zero-valued operating points are never divided directly.
-
-Scoring uses `layout`. A metric uses its worst paired quality q. The score is
-S = 100 * product(q_i ** w_i), including area quality
-q_area = area_reference / candidate_functional_area. The weights below sum to
-one. Dimensions describe measurements but do not determine their weights.
-Physical or functional rejection scores zero; missing or invalid measurements
-produce an unknown score, including measurements with zero weight.
-Source-equivalent performance at the area reference scores 100; improvements
-can exceed 100. A weight expresses a tradeoff, not a hard acceptance limit.
-
-Measurement definitions below use the supplied SPICE node/source names.
-`v(n)` is node voltage and `i(V)` is current into a voltage source; delivered
-power therefore uses a minus sign. `db(z)=20*log10(abs(z))`, `mag/abs`
-denote magnitude, and `cph` is continuous phase in radians. `find`, `when`,
-`from/to`, and `rise/fall` retain the deck's interpolation, window and
-crossing conventions; SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/
-milli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv`
-mean the stated window average, extrema and sampled derivative. All
-declared conditions are measured separately and paired with the same
-source condition; a group uses its worst paired quality.
-
-| Metric | Definition / observations | Unit | Quality rule | Functional bounds | Scale | Dimension |
+Physical checks and the declared functional bounds must pass. Quality scoring imposes no fixed degradation allowance. Each `source_*` job and its corresponding candidate extracted circuit use exactly the same testbench, model resources, parameters, loads and measurement windows. Independent source observations define the 100-point electrical baseline without depending on the submitted GDS; reports retain every paired result.
+
+Let x be the post-layout measurement and b the source-circuit measurement under the same conditions:
+
+- Ratio normalization: maximize with q = x/b and minimize with q = b/x. When a numerical scale s is declared, use (x+s)/(b+s) and its reciprocal, respectively. The scale handles zero values as a normalization floor; it is neither an allowed degradation nor an acceptance bound.
+- Amplitude in dB: maximize with q = 10^((x-b)/20) and minimize with its reciprocal.
+- Target normalization: q = 1/(1+abs(x-b)/s), where s is the declared physical scale. Signed or zero-valued operating points are not divided directly.
+
+Use `layout` scoring. Each metric takes its worst paired quality q, and the total score is S = 100 * product(q_i ** w_i), with area quality q_area = area_reference / candidate_functional_area. The weights below sum to 1; metric dimensions describe measurements and do not determine weights. Physical or functional rejection scores zero; missing or invalid measurements leave the score unknown, and zero-weight observations must also be valid. Matching source-circuit performance at the reference area scores 100 points; better valid solutions may exceed 100. Weights express quality tradeoffs rather than hard bounds.
+
+The measurements below use the supplied SPICE node and source names. `v(n)` is a node voltage; `i(V)` is current flowing into a voltage source, so delivered power uses a negative sign. `db(z)=20*log10(abs(z))`; `mag/abs` denote magnitude, and `cph` denotes continuous phase in radians. `find`, `when`, `from/to` and `rise/fall` follow the deck's interpolation, window and crossing conventions. SPICE suffixes p/n/u/m/meg/g mean pico/nano/micro/milli/mega/giga. Nested `avg`, `min`, `max`, `vecmin/vecmax` and `deriv` represent window averages, extrema and sampled derivatives. Measure each operating condition independently, pair it with the source result under that condition, and take the worst paired quality within each metric group.
+
+`recovery_up_v` and `recovery_down_v` use `saturating_ratio`. Candidate error x, paired source error b and the positive scale s below define q = 2(b+s)/(b+x+2s). Source-equivalent error gives q=1; decreasing error approaches the upper quality limit 2 with diminishing returns. The scale retains its declared unit and numerical-floor meaning. Normalize each operating condition before taking the worst paired quality; other metrics retain their own declared normalization and functional requirements.
+
+| Metric | Definition / observation | Unit | Quality normalization | Functional range | Scale | Dimension |
 | --- | --- | --- | --- | --- | --- | --- |
 | `output_v` | DC operating point: `v(vout)`. | V | target / target | 0 … 1.2 | 1.2 | bias |
 | `bias_v` | DC operating point: `v(net1)`. | V | target / target | 0 … 1.2 | 1.2 | bias |
@@ -123,22 +83,20 @@ source condition; a group uses its worst paired quality.
 | `dc_gain_db` | AC: Value of `(db((-v(vout)/v(vm)))) at=0.01`. | dB | maximize / db20 | −∞ … +∞ | — | response |
 | `unity_hz` | AC: Crossing coordinate where `(db((-v(vout)/v(vm))))=0 fall=1`. | Hz | maximize / ratio | 0 … +∞ | — | response |
 | `phase_margin_deg` | AC: `180+(find (180*cph((-v(vout)/v(vm)))/pi) when (db((-v(vout)/v(vm))))=0 fall=1)`. | deg | target / target | 0 … 180 | 180 | response |
-| `recovery_up_v` | TRAN: Maximum of `(abs(v(vout)-v(vp))) from=5u to=9.5u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |
-| `recovery_down_v` | TRAN: Maximum of `(abs(v(vout)-v(vp))) from=13u to=17.5u`. | V | minimize / ratio | 0 … +∞ | 1e-06 | response |
+| `recovery_up_v` | TRAN: Maximum of `(abs(v(vout)-v(vp))) from=5u to=9.5u`. | V | minimize / saturating_ratio | 0 … +∞ | 1e-06 | response |
+| `recovery_down_v` | TRAN: Maximum of `(abs(v(vout)-v(vp))) from=13u to=17.5u`. | V | minimize / saturating_ratio | 0 … +∞ | 1e-06 | response |
 | `step_gain` | Transient: `((avg v(vout) from=9u to=9.5u)-(avg v(vout) from=17u to=17.5u))/0.2`. | V/V | target / target | −∞ … +∞ | 1.0 | response |
 | `mean_power_w` | TRAN: Mean of `(-v(vdd)*i(VDD)) from=2u to=18u`. | W | minimize / ratio | 0 … +∞ | 1e-12 | supply |
 | `peak_v` | TRAN: Maximum of `v(vout) from=2u to=10u`. | V | target / target | 0 … 1.2 | 1.2 | response |
 | `trough_v` | TRAN: Minimum of `v(vout) from=10.04u to=18u`. | V | target / target | 0 … 1.2 | 1.2 | response |
 
-Area reference: **20690.01 um2**. 96 expanded device instances; sum of device/contact envelopes 13605.7469 um2, per-side envelope allowance 0.6 um, 50% routing allowance and total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across two opposite sides; the envelope sum is displayed rounded to four decimals. MOS/passive envelopes use declared W/L (or resistor dimensions) and multiplicity; explicit tap areas and HBT emitter/contact envelopes are included. This is a frozen engineering estimate, not a foundry minimum or a feasibility claim.
-
-The capability coefficient remains **7**; it is independent of
-the reference-relative task score.
+Area reference: **20690.01 um2**. The expanded circuit has 96 device instances, a sum of device/contact envelopes 13605.7469 um2, a one-sided envelope margin of 0.6 um, a routing allowance of 50%, and a total outer width/height allowance 1.2 um. Estimate = ceil(100 * (1.5 * envelope_sum + 2 * margin * sqrt(envelope_sum) + margin^2)) / 100. Here margin is the total allowance across both sides, and the envelope sum is displayed to four decimal places. MOS/passive envelopes use W/L (or resistor dimensions) and multiplicity, including explicit contacts and HBT emitter/contact envelopes. This is a frozen engineering estimate, not a process minimum or a proven achievable area.
 
+The capability coefficient is **7**, independent of this task's reference-normalized score.
 
 ### Score weights
 
-Compensated feedback amplifiers: loaded recovery 28.6%; loop margin 20.5%; gain and bandwidth 16.4%; step transfer and extrema 8.18%; bias 4.09%; power 12.3%; area 10%. Each objective's weight is divided equally among its metrics.
+Compensated feedback amplifiers: loaded recovery 28.6%, loop margin 20.5%, gain and bandwidth 16.4%, step transfer and extrema 8.18%, bias 4.09%, power 12.3%, area 10%. Each objective's weight is divided equally among its metrics.
 
 | Metric | Weight |
 | --- | ---: |
@@ -160,8 +118,4 @@ Compensated feedback amplifiers: loaded recovery 28.6%; loop margin 20.5%; gain
 
 Solve budget: **3 hours**.
 
-Discover inputs, resources and feedback through `/protocol/task.json`,
-`/protocol/resources.json` and `/protocol/harness.json`. Use the supplied IHP
-primitives with KLayout, Magic and ngspice. Write `/workspace/output/final.gds`
-and explicitly submit through the harness protocol. Host configuration, source
-records and reference layouts are outside the standard solver inputs.
+Discover inputs, resources and feedback through `/protocol/task.json`, `/protocol/resources.json` and `/protocol/harness.json`. Use the provided IHP primitives and KLayout, Magic and ngspice. Write `/workspace/output/final.gds`, then submit explicitly through the runtime protocol. Host configuration, source records and reference layouts are not standard solver inputs.

tasks/ihp-sg13g2/analog-db/cases/amp_003_fan_smc/case.toml

@@ -1,15 +1,15 @@
-in_core = false
 kind = "layout_case"
 id = "ihp-sg13g2.analog-db.amp_003_fan_smc"
 title = "Single-Capacitor Three-Stage Feedforward OTA"
 status = "qualified"
+in_core = false
 
 [[assets]]
 path = "materials/schematic.svg"
 role = "schematic"
 visibility = "maintainer"
 format = "svg"
-sha256 = "c46caa05f6be4613f60fdce588b46f5ac2a7ace7ff42f323ca6b1f8af1a2b232"
+sha256 = "d4387977bdd4e3bb1da3ac1cfc994e720dad199e2a58444823c6db30bbf65ed0"
 
 [[assets]]
 path = "reference/amp_003_fan_smc.gds"
@@ -28,18 +28,18 @@ environment = "ihp-sg13g2-amp_003_fan_smc-nominal-rc"
 [task.inputs.description]
 path = "problem.md"
 format = "text"
-sha256 = "d4b1da37fa4b4f7b020340ea9296a4a9681c0bfd686cd90a98e46b8b885da830"
+sha256 = "e9d25003e087f344dd7c41a4f93178f342027f563e4a9c6ee8896df04113d107"
 
 [task.inputs.netlist]
 path = "materials/circuit.cdl"
 format = "spice"
-sha256 = "5c0aa44f171b64424a7dc717a4d76f332bc9da6b39923f4ae527433622c43601"
 subcircuit = "amp_003_fan_smc"
+sha256 = "5c0aa44f171b64424a7dc717a4d76f332bc9da6b39923f4ae527433622c43601"
 
 [task.inputs.performance]
 path = "materials/testbench.spice"
 format = "spice"
-sha256 = "cfe8a0580eaeb7b840697fbc99204ee9f6969015bcc1f4db6450899484c705cf"
+sha256 = "e6d4c2a9874f561b9380ff84f9273879d3d81fc1f6c23e9df84c2d26bba9d15d"
 
 [task.inputs.simulation]
 path = "materials/circuit.spice"
@@ -483,8 +483,11 @@ baseline = [
 ]
 normalization = "target"
 scale = 1.2
+
+[task.evaluation.metrics.requirement]
 lower = 0
 upper = 1.2
+rationale = "The declared node voltage or voltage span must remain within its ground-to-supply operating envelope; precision relative to the source remains a scored objective."
 
 [[task.evaluation.metrics]]
 id = "bias_v"
@@ -505,8 +508,11 @@ baseline = [
 ]
 normalization = "target"
 scale = 1.2
+
+[task.evaluation.metrics.requirement]
 lower = 0
 upper = 1.2
+rationale = "The declared node voltage or voltage span must remain within its ground-to-supply operating envelope; precision relative to the source remains a scored objective."
 
 [[task.evaluation.metrics]]
 id = "power_w"
@@ -526,9 +532,12 @@ baseline = [
     "source_condition_2:power_w",
 ]
 normalization = "ratio"
-lower = 0
 scale = 1e-12
 
+[task.evaluation.metrics.requirement]
+lower = 0
+rationale = "The declared powered circuit or driven switching network must consume nonnegative net supply/driver energy or quiescent current under the complete stated observation."
+
 [[task.evaluation.metrics]]
 id = "dc_gain_db"
 category = "performance"
@@ -566,7 +575,10 @@ baseline = [
     "source_condition_2:unity_hz",
 ]
 normalization = "ratio"
+
+[task.evaluation.metrics.requirement]
 lower = 0
+rationale = "The observed frequency or ordered-event interval has a nonnegative measurement domain, and its required crossing must exist for a usable observation."
 
 [[task.evaluation.metrics]]
 id = "phase_margin_deg"
@@ -587,8 +599,11 @@ baseline = [
 ]
 normalization = "target"
 scale = 180
+
+[task.evaluation.metrics.requirement]
 lower = 0
 upper = 180
+rationale = "The declared negative-feedback loop must stay on the measured 0 to 180 degree stable-feedback branch at the required unity crossing; the amount of positive phase margin remains a scored objective."
 
 [[task.evaluation.metrics]]
 id = "recovery_up_v"
@@ -607,10 +622,13 @@ baseline = [
     "source_condition_1:recovery_up_v",
     "source_condition_2:recovery_up_v",
 ]
-normalization = "ratio"
-lower = 0
+normalization = "saturating_ratio"
 scale = 1e-06
 
+[task.evaluation.metrics.requirement]
+lower = 0
+rationale = "The absolute error, voltage span, charge magnitude or recovery deviation has a nonnegative measurement domain; its positive value remains a continuously scored quality observation."
+
 [[task.evaluation.metrics]]
 id = "recovery_down_v"
 category = "performance"
@@ -628,10 +646,13 @@ baseline = [
     "source_condition_1:recovery_down_v",
     "source_condition_2:recovery_down_v",
 ]
-normalization = "ratio"
-lower = 0
+normalization = "saturating_ratio"
 scale = 1e-06
 
+[task.evaluation.metrics.requirement]
+lower = 0
+rationale = "The absolute error, voltage span, charge magnitude or recovery deviation has a nonnegative measurement domain; its positive value remains a continuously scored quality observation."
+
 [[task.evaluation.metrics]]
 id = "step_gain"
 category = "performance"
@@ -670,9 +691,12 @@ baseline = [
     "source_condition_2:mean_power_w",
 ]
 normalization = "ratio"
-lower = 0
 scale = 1e-12
 
+[task.evaluation.metrics.requirement]
+lower = 0
+rationale = "The declared powered circuit or driven switching network must consume nonnegative net supply/driver energy or quiescent current under the complete stated observation."
+
 [[task.evaluation.metrics]]
 id = "peak_v"
 category = "performance"
@@ -692,8 +716,11 @@ baseline = [
 ]
 normalization = "target"
 scale = 1.2
+
+[task.evaluation.metrics.requirement]
 lower = 0
 upper = 1.2
+rationale = "The declared node voltage or voltage span must remain within its ground-to-supply operating envelope; precision relative to the source remains a scored objective."
 
 [[task.evaluation.metrics]]
 id = "trough_v"
@@ -714,14 +741,17 @@ baseline = [
 ]
 normalization = "target"
 scale = 1.2
+
+[task.evaluation.metrics.requirement]
 lower = 0
 upper = 1.2
+rationale = "The declared node voltage or voltage span must remain within its ground-to-supply operating envelope; precision relative to the source remains a scored objective."
 
 [task.evaluation.pre_layout]
-source_report_sha256 = "4feeaa4d4aaf3bb42bfede25114adf0c3c6040b90f25e897a55d96b2972a5812"
+source_report_sha256 = "c278d8c22a2b0519f195736b5004a6f30122a79680a944e6720355f81e5bea2e"
 
 [task.evaluation.pre_layout.backends]
-"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"ef9cb87fa27b849376472663b7362673979b89e012f161ba47bb5f6af6ede8eb\", \"compatibility\": null, \"execution_sha256\": \"5424b579002782bfddf0a729715b8fbf2a5f7f2b4cf14982d7616e352d5de9be\", \"image_id\": \"sha256:6562558774d43c085a289bbba696c55959eb8051a0996f96633451fbeb9c652d\", \"limits\": {\"cpus\": 4, \"memory_mb\": 4096, \"pids\": 256}, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"3ed768d4ffb7f23f3607c41ecc3ea827c17cb3311d178014ef532319353417d7\", \"timeout_seconds\": 600.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}"
+"circuit.simulate" = "{\"adapter\": \"ngspice-docker\", \"adapter_sha256\": \"dfbdf2f93297bbe7d8b576fb988504bd0ecf85b93ef47c314a0f2c9c8830c3e7\", \"compatibility\": null, \"cpu_budget\": 8, \"execution_sha256\": \"495aa9623759f70228a236eb4825c2ae443ef6a741816d8cfc17d1830841dcef\", \"image_id\": \"sha256:060fee64f9f6e71a647e5e958b788d723c9d51d2928ff93e6a295db1959bc37f\", \"limits\": {\"cpus\": 8, \"memory_mb\": 4096, \"pids\": 256}, \"max_parallel_jobs\": 8, \"resistor_formulation\": \"conductance\", \"support_sha256\": \"a202c3d9d407fa71903be9db155aeb1eb3f9bccbb7ed18bfd0eaa1ea925dc151\", \"thread_environment\": {\"OMP_NUM_THREADS\": \"1\", \"OMP_THREAD_LIMIT\": \"1\"}, \"threads\": 1, \"timeout_seconds\": 600.0, \"tool_version\": \"******\\n** ngspice-45 : Circuit level simulation program\\n** Compiled with KLU Direct Linear Solver\\n** The U. C. Berkeley CAD Group\\n** Copyright 1985-1994, Regents of the University of California.\\n** Copyright 2001-2025, The ngspice team.\\n** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html\\n** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html\\n** Creation Date: Thu Sep 17 13:42:47 UTC 2026\\n******\"}"
 
 [task.evaluation.pre_layout.jobs.source_condition_0]
 operation = "circuit.simulate"
@@ -758,7 +788,7 @@ ac = "ac.raw"
 transient = "transient.raw"
 
 [task.evaluation.pre_layout.jobs.source_condition_0.input_sha256]
-deck = "cfe8a0580eaeb7b840697fbc99204ee9f6969015bcc1f4db6450899484c705cf"
+deck = "e6d4c2a9874f561b9380ff84f9273879d3d81fc1f6c23e9df84c2d26bba9d15d"
 dut = "2d129c21487a4415c752ba2bc08b7d102d8684cb55dc89915576a913c88ddf3d"
 
 [task.evaluation.pre_layout.jobs.source_condition_0.measurements.bias_v]
@@ -809,6 +839,11 @@ unit = "V"
 value = 1369789.0
 unit = "Hz"
 
+[task.evaluation.pre_layout.jobs.source_condition_0.output_sha256]
+op = "9d98fe0a95f86915678043de0b3f81ede7a5521ce3ded7f7370c253fde04f74f"
+ac = "3287978d96766b2bbedc13d2a7920390e0c40955cb22a515377e6eff54cab8a5"
+transient = "7668884835969d36c948502ef01c15786ccdccd2b83c7bab794ef5baeb13b7b3"
+
 [task.evaluation.pre_layout.jobs.source_condition_1]
 operation = "circuit.simulate"
 
@@ -844,7 +879,7 @@ ac = "ac.raw"
 transient = "transient.raw"
 
 [task.evaluation.pre_layout.jobs.source_condition_1.input_sha256]
-deck = "cfe8a0580eaeb7b840697fbc99204ee9f6969015bcc1f4db6450899484c705cf"
+deck = "e6d4c2a9874f561b9380ff84f9273879d3d81fc1f6c23e9df84c2d26bba9d15d"
 dut = "2d129c21487a4415c752ba2bc08b7d102d8684cb55dc89915576a913c88ddf3d"
 
 [task.evaluation.pre_layout.jobs.source_condition_1.measurements.bias_v]
@@ -895,6 +930,11 @@ unit = "V"
 value = 1374443.0
 unit = "Hz"
 
+[task.evaluation.pre_layout.jobs.source_condition_1.output_sha256]
+op = "9d98fe0a95f86915678043de0b3f81ede7a5521ce3ded7f7370c253fde04f74f"
+ac = "05bed7249233232ed391f6eb06b79e2b74c019f19319554d0acc0473568790fd"
+transient = "0201de800dacd10c50705e24172b5ea394d8c55108c1aa14e624aee910acfd02"
+
 [task.evaluation.pre_layout.jobs.source_condition_2]
 operation = "circuit.simulate"
 
@@ -930,7 +970,7 @@ ac = "ac.raw"
 transient = "transient.raw"
 
 [task.evaluation.pre_layout.jobs.source_condition_2.input_sha256]
-deck = "cfe8a0580eaeb7b840697fbc99204ee9f6969015bcc1f4db6450899484c705cf"
+deck = "e6d4c2a9874f561b9380ff84f9273879d3d81fc1f6c23e9df84c2d26bba9d15d"
 dut = "2d129c21487a4415c752ba2bc08b7d102d8684cb55dc89915576a913c88ddf3d"
 
 [task.evaluation.pre_layout.jobs.source_condition_2.measurements.bias_v]
@@ -981,6 +1021,11 @@ unit = "V"
 value = 1383658.0
 unit = "Hz"
 
+[task.evaluation.pre_layout.jobs.source_condition_2.output_sha256]
+op = "9d98fe0a95f86915678043de0b3f81ede7a5521ce3ded7f7370c253fde04f74f"
+ac = "bd4d5e77e9f501a5d6542925b4f41c1597ebe85f51299675f5245c704559e5b4"
+transient = "12f1303847522a85163ce11d987916477cd41d85468c1b130daf062bec490d7c"
+
 [toolchain.bindings]
 "layout.artifact" = "artifact"
 "layout.drc" = "drc"
@@ -993,7 +1038,7 @@ unit = "Hz"
 type = "klayout-docker"
 
 [toolchain.backends.artifact.settings]
-image = "iclayout-bench-tools:local"
+image = "iclayout-eda-open:local"
 check = "artifact"
 timeout_seconds = 600
 
@@ -1004,7 +1049,7 @@ type = "klayout-docker"
 support = "klayout"
 
 [toolchain.backends.drc.settings]
-image = "iclayout-bench-tools:local"
+image = "iclayout-eda-open:local"
 check = "drc"
 support = "build/support/input-pair-klayout"
 profile = "drc-upstream.json"
@@ -1017,7 +1062,7 @@ type = "klayout-docker"
 support = "klayout"
 
 [toolchain.backends.lvs.settings]
-image = "iclayout-bench-tools:local"
+image = "iclayout-eda-open:local"
 check = "lvs"
 support = "build/support/input-pair-klayout"
 profile = "lvs-upstream.json"
@@ -1030,7 +1075,7 @@ type = "magic-rc-docker"
 support = "magic"
 
 [toolchain.backends.rc.settings]
-image = "iclayout-bench-tools:local"
+image = "iclayout-eda-open:local"
 support = "build/support/input-pair-magic"
 technology = "magic/ihp-sg13g2.tech"
 tech_name = "ihp-sg13g2"
@@ -1044,7 +1089,7 @@ grid_subdivision = 2
 type = "klayout-geometry-docker"
 
 [toolchain.backends.geometry.settings]
-image = "iclayout-bench-tools:local"
+image = "iclayout-eda-open:local"
 timeout_seconds = 120
 
 [toolchain.backends.simulation]
@@ -1054,7 +1099,10 @@ type = "ngspice-docker"
 support = "analog-res-models"
 
 [toolchain.backends.simulation.settings]
-image = "iclayout-bench-tools:local"
+max_parallel_jobs = 8
+threads = 1
+cpu_budget = 8
+image = "iclayout-eda-open:local"
 support = "build/support/analog-res-models"
 timeout_seconds = 600
 

tasks/ihp-sg13g2/analog-db/cases/amp_003_fan_smc/materials/testbench.spice

@@ -21,6 +21,7 @@ let bias_v=v(net013)
 let power_w=-v(vdd)*i(VDD)
 print output_v bias_v power_w
 write op.raw v(vout) v(net013) i(VDD)
+save i(vdd) v(net013) v(vdd) v(vm) v(vout) v(vp)
 ac dec 150 0.01 100meg
 let transfer=-v(vout)/v(vm)
 let gain_db=db(transfer)