Publish logical MOS inputs and requalified static dataset

Designs source: 2aafe763ac9b696ceb9d86e16fd1b706f376daeb
Bench evaluator: 448394f52d76ae821badf0ec3048d8f687fe41cc

92 public tasks, including 21 core tasks. All reference input and witness bindings verified; all 21 core acceptance summaries checked. Static publication manifest contains 612 files. Retire 92 obsolete exported files.

README.md

@@ -17,325 +17,208 @@ configs:
 
 # ICLayout-Bench Dataset
 
-92 qualified public circuit-layout tasks: nine FreePDK45, 27 GF180MCU,
-49 IHP SG13G2 and seven SKY130A, for the
-[ICLayout-Bench evaluator](https://github.com/lizhangmai/ICLayout-Bench).
-Each task supplies a netlist, layout requirements, test stimuli, scoring contract
-and a reference layout. Available on [Hugging Face](https://huggingface.co/datasets/MAI716/ICLayout-Bench).
-
-## Load and select
+ICLayout-Bench provides **92 public circuit-layout tasks**, including a
+**21-task core benchmark**, for studying and evaluating automated IC layout.
+Given a transistor-level SPICE netlist and English requirements, a participant
+produces a GDS layout. The
+[ICLayout-Bench evaluator](https://github.com/lizhangmai/ICLayout-Bench) checks
+physical correctness and measures post-layout electrical behavior and area under
+each task's declared conditions.
+
+Each task includes requirements, a netlist, test stimuli, an evaluation contract
+and a qualified reference layout. Browsing these materials requires no EDA tools;
+running physical and electrical checks requires the evaluator and its declared
+external tools and process resources. Collection licenses differ, and the
+analog-db materials include noncommercial terms; see [licensing](#licensing).
+
+## Tasks and subsets
+
+| Process | All tasks | Core tasks | Circuit coverage | Resource declaration |
+| --- | ---: | ---: | --- | --- |
+| FreePDK45 | 9 | 3 | Logic cells, SRAM and peripheral circuits, differential amplifier | [pdk.toml](tasks/freepdk45/pdk.toml) |
+| GF180MCU | 27 | 7 | Amplifiers, comparators, regulators, temperature references, DAC, oscillator and scan logic | [pdk.toml](tasks/gf180mcuD/pdk.toml) |
+| IHP SG13G2 | 49 | 7 | Amplifiers, feedback and sampled circuits, regulators, references and SiGe circuits | [pdk.toml](tasks/ihp-sg13g2/pdk.toml) |
+| SKY130A | 7 | 4 | Amplifiers, comparator, current mirror, power-on reset, sample-and-hold and DAC | [pdk.toml](tasks/sky130A/pdk.toml) |
+| **Total** | **92** | **21** | | |
+
+The only Hugging Face configuration is `default`; its `test` split contains
+**all 92 tasks**. There are no separate training or validation splits. The core
+benchmark is a subset selected by `in_core`, not a separate split. Tasks outside
+core remain available for broader evaluation or focused exercises.
+
+The core covers logic, storage, passive networks, sampling, oscillation,
+high-frequency behavior and feedback control while reducing repeated circuit
+families. It is a selection for capability coverage, not a measured difficulty
+ranking. `core_order` gives the evaluator's dispatch order, not difficulty.
+The full corpus is weighted toward amplifiers and RF: its presentation categories
+contain 52 Amplifiers & RF, 17 Mixed-signal, 14 Power & references and 9 Logic &
+memory tasks. Report the selected subset and per-task results when comparing
+participants.
+
+## Browse and download
+
+To browse the task table with the Hugging Face `datasets` library:
 
 ```python
 from datasets import load_dataset
 
-repo_id = "MAI716/ICLayout-Bench"
-tasks = load_dataset(repo_id, split="test")  # Complete corpus.
-core = tasks.filter(lambda task: task["in_core"]).sort("core_order")  # Current 21-task benchmark.
+tasks = load_dataset("MAI716/ICLayout-Bench", split="test")
+core = tasks.filter(lambda task: task["in_core"]).sort("core_order")
 print(tasks[0]["problem"])
 ```
 
-`data.parquet` contains every task, sorted by stable ID. The boolean `in_core`
-field is generated from the same field in each `case.toml`;
-the corpus includes all currently qualified public cases, and changing this
-selection never removes tasks from it. See the
-[selection rationale](#core-selection-rationale). Participant experiments can choose
-`name = "all"` and a `tasks` filter without changing core.
-Core cases also declare a unique positive `core_order`. The evaluator inherits
-this ascending dispatch order when selecting `core`, starting longer tasks early
-and interleaving smaller circuits. Experiment configurations only need to select
-`core`; an explicit `tasks` list can override the order. Maintain membership and
-order in case metadata and regenerate the index together.
-
-Rows contain `id`, `in_core`, nullable integer `core_order`, `title`, `category`, `summary`, `pdk`, `collection`, `task_kind`,
-`status`, `source_url`, `problem`, and relative paths/digests for task files,
-netlists, process declarations and licenses. The typed, Zstd-compressed Parquet table is a generated view;
-`case.toml` owns task metadata and requirements.
-
-For assets, use a local checkout or `huggingface_hub.snapshot_download` with
-`repo_type="dataset"`. Pin the table and assets to the same repository commit
-using `revision` in both loading calls. A local checkout is also supported. When reloading an edited local checkout directly through
-`datasets`, pass `download_mode="reuse_cache_if_exists"` to refresh cached tables.
-
-## Contents
+This loads the table, including the requirements text. It does not download the
+netlists, GDS references or other files addressed by the table's paths.
 
-```text
-tasks/<pdk>/
-  pdk.toml        # Pinned process resources and profiles
-  README.md       # Process scope and limitations, where documented
-  <collection>/
-    LICENSE         # Collection terms
-    NOTICE          # Required attribution, where applicable
-    cases/<case>/
-      case.toml       # Metadata, input identities and evaluation contract
-      problem.md      # Complete participant-facing requirements
-      materials/      # Netlist, test stimuli and declared presentation assets
-      reference/      # Reference layout; excluded from standard solver inputs
-data.parquet      # Complete corpus with generated in_core membership
-```
+To download the complete dataset and read a task's files, use
+[`snapshot_download`](https://huggingface.co/docs/huggingface_hub/guides/download#download-an-entire-repository).
+The example loads the Parquet table from the same downloaded directory as the
+assets, keeping them at one revision:
 
-Source attribution is in `case.toml`; process and collection follow the directory
-hierarchy.
-
-## Licensing
-
-The root [LICENSE](LICENSE) covers original project metadata and documentation.
-Task materials retain the terms in each `tasks/<pdk>/<collection>/LICENSE` and,
-where present, `NOTICE`; the table exposes the corresponding license paths.
-Terms vary by collection, including noncommercial restrictions for analog-db
-materials. Retain applicable licenses, notices, source attribution and modification
-notices when redistributing materials. External PDKs and EDA tools have their own
-licenses. Technical qualification does not establish redistribution permission.
-
-## Scope and validation
-
-The problem and contract specify each task's operating points, physical checks,
-measurement definitions and score. Process scope for [GF180MCU](tasks/gf180mcuD/README.md),
-[FreePDK45](tasks/freepdk45/README.md) and [SKY130A](tasks/sky130A/README.md)
-describes resource assumptions and limitations. These are block-level benchmarks, not
-manufacturing signoff or evidence of model performance.
-
-Earlier revisions of the selected core and bounded-error tasks passed the former
-multi-run qualification protocol. Those reports remain historical; they do not
-establish current qualification under the installed evaluator. The current
-protocol needs one complete reference evaluation per changed evaluation contract.
-Qualification reports and acceptance records stay with the author. References are
-available for independent verification and excluded from standard solver inputs.
-
-Nonnegative error and residual metrics use the explicitly declared
-`saturating_ratio` rule: `q = 2(b+s)/(b+x+2s)`, with candidate error `x`,
-quality anchor `b`, and positive scale `s`. The anchor is the declared
-`quality_target.value`, or the paired source observation when no target is
-declared. Equality to the anchor has quality 1 and improvement approaches a
-ceiling of 2. Source measurements remain independently frozen and paired;
-engineering goals do not rewrite those observations. Selection follows the
-measurement definition, including accuracy, recovery, hold error, curvature,
-ripple and regulation aliases. Cost and loop-shape metrics keep their declared
-rules. The task score remains a weighted product and may exceed 100; the bounded
-rule limits individual error rewards rather than imposing a total-score cap.
-The 100-point level denotes challenging electrical and footprint goals, not
-the quality of the feasibility witness. A valid reference may score well below
-100. Repeated or nearly invariant observations remain diagnostic when their
-score weights are zero; all functional requirements continue to apply.
-The fully differential CMFB amplifier separately scores static common-mode
-accuracy and recovery relative to its own DC equilibria. Each problem declares
-the scales, windows and weights; no extra PVT conditions are implied.
-
-Install the evaluator separately to run a reference:
-
-```bash
-python -m benchmarking.engine.preview --dataset . run \
-  --case freepdk45.nangate45-pdk.NAND2_X1 --output build/reference-check
+```python
+from pathlib import Path
+from datasets import load_dataset
+from huggingface_hub import snapshot_download
+
+revision = "main"  # Use a full dataset commit hash for repeatable experiments.
+dataset_root = Path(snapshot_download(
+    repo_id="MAI716/ICLayout-Bench",
+    repo_type="dataset",
+    revision=revision,
+    local_dir="iclayout-bench-dataset",
+)).resolve()
+tasks = load_dataset(
+    "parquet",
+    data_files={"test": str(dataset_root / "data.parquet")},
+    split="test",
+)
+task = next(task for task in tasks if task["id"] == "freepdk45.nangate45-pdk.NAND2_X1")
+print(task["problem"])
+print((dataset_root / task["netlist_path"]).read_text())
+print("Contract:", dataset_root / task["case_path"])
+print("Dataset root:", dataset_root)
 ```
 
-The command creates local reports under the requested output directory. Setup,
-index generation and publication checks are documented in the evaluator's
-[tools guide](https://github.com/lizhangmai/ICLayout-Bench/blob/main/docs/tools.md)
-and [task qualification guide](https://github.com/lizhangmai/ICLayout-Bench/blob/main/CONTRIBUTING.md#task-qualification).
-
-## Core selection rationale
-
-The core is a secondary selection of the complete corpus, chosen for capability
-coverage. Its size is not a limit on the available tasks. Select capabilities
-from maintained netlists, testbenches and scoring contracts, rather than circuit
-names or upstream performance claims. Prefer a representative within each PDK;
-include related circuits when their measured requirements add distinct behavior.
-Do not fill coefficient bands or process quotas merely for numerical balance.
-
-<details>
-<summary>Detailed capabilities, alternatives and selection methodology</summary>
-
-
-Case-level `in_core` flags and scoring contracts own membership and weights. This document
-records the rationale for the secondary core selection from the full Dataset,
-independently of engine releases. All accepted tasks remain available in the default `test` table;
-being outside core does not mean a task is unfinished or excluded from Dataset.
-
-### Coefficient rubric
-
-The integer coefficient from 1 to 10 describes the capability required by the
-circuit and its evaluated requirements. It is used when aggregating tasks,
-separately from each task's score.
-
-| Coefficient | Capability scope |
-|---:|---|
-| 1 | A single local function, such as basic logic transitions or a current ratio at declared bias points |
-| 2 | A small block with coupled paths or supply states, such as compound logic or reset release under specified ramps |
-| 3 | Local analog or controlled driver behavior: bias, transfer or output states |
-| 4 | A complete compact circuit coupling gain, accuracy, load or a physical passive network |
-| 5 | Local feedback, clocked state or charge transfer with parasitic-dependent dynamics |
-| 6 | Regenerative decisions, storage integrity, coupled startup behavior or a complete compensated loop |
-| 7 | Multistage compensation or regulation maintaining frequency response and recovery across loads |
-| 8 | Active auxiliary compensation, self-oscillation or broader return-ratio and startup requirements |
-| 9 | Strongly interacting control goals or complex regulation combining startup, frequency response and recovery |
-| 10 | Clock modulation, signal feedback and actual common-mode control operating together |
-
-The coefficient is declared before participant evaluation and explained in the
-case documentation. It reflects measured requirements rather than the circuit
-name, transistor count, simulator runtime or observed participant success rate.
-A coefficient of 10 does not imply ten times the implementation effort of a
-coefficient of 1. Changes to coefficients or benchmark membership produce a new
-content identity through configuration and task-contract digests; no manual
-version field is required. Archived results retain their original weights. See
-[result aggregation](https://github.com/lizhangmai/ICLayout-Bench/blob/main/docs/running.md#result-storage-and-presentation).
-
-### Selected capabilities
-
-The current set contains 21 cases across four PDKs: three FreePDK45, seven
-GF180MCU, seven IHP SG13G2 and four SKY130A. Each link gives the full
-requirements and coefficient rationale. Coefficients below are the existing
-case coefficients, not new selection weights or estimates of solve time.
-
-| PDK | Selected case | Coefficient | Distinct contribution |
-| --- | --- | ---: | --- |
-| FreePDK45 | [NAND2](tasks/freepdk45/nangate45-pdk/cases/NAND2_X1/problem.md) | 1 | Basic connectivity, loaded logic levels and timing; an entry-level anchor. |
-| FreePDK45 | [SRAM write driver](tasks/freepdk45/OpenRAM/cases/write_driver/problem.md) | 3 | Complementary loaded outputs and enabled/disabled drive states. |
-| FreePDK45 | [6T SRAM cell](tasks/freepdk45/OpenRAM/cases/cell_6t/problem.md) | 6 | Storage integrity coupled to read and write access. |
-| GF180MCU | [Five-transistor OTA](tasks/gf180mcuD/Jianxun-OTA/cases/ota_5t/problem.md) | 4 | Compact differential gain and bias with separately measured common-mode rejection. |
-| GF180MCU | [Scan DFF](tasks/gf180mcuD/voidwalkers-scandff/cases/scan_dff/problem.md) | 5 | Clocked state and scan/data selection, exercised around setup and hold with output timing and slew. |
-| GF180MCU | [R-2R DAC](tasks/gf180mcuD/gf-r2r-dac/cases/r2r/problem.md) | 4 | A physical resistor ladder: full 256-code DC transfer with integral and differential nonlinearity, plus selected transient codes. |
-| GF180MCU | [StrongARM comparator](tasks/gf180mcuD/analog-db/cases/cmp_002_strongarm/problem.md) | 6 | Regenerative decisions across four input common modes, both input polarities and two clock-edge rates, with precharge, delay and slew measurements. |
-| GF180MCU | [Classic PTAT](tasks/gf180mcuD/analog-db/cases/tsn_002_ptat_classic/problem.md) | 6 | Temperature slope and curvature, startup time, isolated body connections and a coupled startup branch. |
-| GF180MCU | [Feedforward PMOS LDO](tasks/gf180mcuD/analog-db/cases/ldo_007_pmos/problem.md) | 7 | A larger pass-device array, feedback divider and feedforward compensation with regulation and recovery checks. |
-| GF180MCU | [Four-phase VCO](tasks/gf180mcuD/tt_tnt_gf_vco/cases/vco/problem.md) | 8 | Self-oscillation, tuning and relative output phases across control settings, three temperatures and three output loads. |
-| IHP SG13G2 | [NMOS track-and-hold](tasks/ihp-sg13g2/analog-db/cases/smp_001_nmos_th/problem.md) | 5 | Physical charge storage, pedestal, drift, feedthrough and reacquisition across input/temperature conditions. |
-| IHP SG13G2 | [SiGe PAM4 driver](tasks/ihp-sg13g2/analog-db/cases/drv_001_pam4_sige_dac/problem.md) | 4 | Weighted HBT current steering with gain and port-reflection observations extending to 50 GHz. |
-| IHP SG13G2 | [Output-controlled auxiliary-compensation OTA](tasks/ihp-sg13g2/analog-db/cases/amp_006_leung_dfcfc1/problem.md) | 8 | Three-stage routing and auxiliary compensation, with sampled return-ratio and recovery observations across loads and biases. |
-| IHP SG13G2 | [Ramos PFC amplifier](tasks/ihp-sg13g2/analog-db/cases/amp_014_ramos_pfc/problem.md) | 7 | A large expanded device array and cross-stage compensation create the suite's upper layout-scale case. |
-| IHP SG13G2 | [Fully differential two-stage OTA](tasks/ihp-sg13g2/analog-db/cases/amp_023_fer_fd2s/problem.md) | 9 | Coupled differential and common-mode control with compensation, transient response and a hot-temperature stability check. |
-| IHP SG13G2 | [Mirror-OTA LDO](tasks/ihp-sg13g2/analog-db/cases/ldo_008_fer_mirror_ota/problem.md) | 9 | Complex regulation combining return-ratio crossings, startup, line/load response, recovery and closed-loop PSRR. |
-| IHP SG13G2 | [Chopper IA with CMFB](tasks/ihp-sg13g2/analog-db/cases/ia_006_fan_chopper_cmfb/problem.md) | 10 | Clock modulation, signal feedback and common-mode feedback, with common-mode-to-differential sensitivity under two loads. |
-| SKY130A | [Current mirror](tasks/sky130A/OpenFASOC/cases/current_mirror/problem.md) | 1 | Current-ratio accuracy across three bias currents and an output-voltage sweep. |
-| SKY130A | [Power-on reset](tasks/sky130A/sky130_ef_ip__simple_por/cases/simple_por/problem.md) | 2 | Dual-supply startup and reset release under three ramp durations. |
-| SKY130A | [Buffered sample and hold](tasks/sky130A/sky130_ef_ip__samplehold/cases/samplehold/problem.md) | 4 | Tracking, held-value error under input reversal, droop and reacquisition. |
-| SKY130A | [Eight-bit buffered resistor DAC](tasks/sky130A/sky130_ef_ip__rdac3v_8bit/cases/rdac3v_8bit/problem.md) | 4 | Full 256-code transfer, monotonicity, INL/DNL, power and full-scale transition checks. |
-
-The selection retains distinct compact logic, storage, passive-network, sampled,
-RF, oscillator and coupled-feedback problems. It reduces repeated compensated
-amplifier and regulator cases without removing them from the complete corpus:
-
-- `amp_015_sau_cfcc` remains an alternative to `amp_006_leung_dfcfc1`; their
-  current contracts substantially overlap in load/bias sweeps, return-ratio
-  observations and step recovery. The core retains the latter's auxiliary loop.
-- `amp_016_song_dacfc` remains available for its particular transient regime.
-  Its frozen source has about 44 mV late error and 152 mV ripple in the declared
-  windows. Those observations make it a less clear representative of settled
-  amplifier accuracy than the retained cases; they are not evidence that the
-  task is physically invalid.
-- `ldo_001_analoggym_basic` remains a regulator alternative. The core retains the
-  GF180 pass-array/feedforward problem and the IHP mirror-OTA regulator with
-  explicit closed-loop PSRR, avoiding a third broadly overlapping LDO.
-
-`amp_014_ramos_pfc` stays for its large expanded physical array, while
-`amp_023_fer_fd2s` and the chopper IA stay for distinct common-mode and switched
-feedback behavior. The bare NMOS sampler and buffered SKY130 sample-and-hold
-also remain separate: passive storage/feedthrough and active-buffer recovery
-pose different layout tradeoffs. These choices describe capability coverage,
-not an empirical ordering of difficulty.
-
-The RF driver remains coefficient 4 because its contract covers a compact
-feedforward circuit; its specialized devices and extraction flow do not make
-the coefficient an estimate of participant effort. Coefficients are capability
-categories, not a measured difficulty scale.
-
-### Boundaries and alternatives
-
-The five-transistor OTA, fully differential OTA and compensated amplifiers
-progress from compact gain/bias to interacting signal, common-mode and auxiliary
-paths. The feedforward PMOS LDO and IHP mirror-OTA regulator add distinct
-pass-array, recovery, loop and supply-rejection demands. The IHP-heavy demanding end follows
-the available qualified contracts rather than a per-PDK quota; report results by
-task and PDK so one toolchain does not obscure the rest of the suite.
-
-NAND2 supplies the basic logic anchor; the other simple logic cells remain in the
-corpus. The separate SRAM sense amplifier overlaps the regenerative-decision
-capability represented by StrongARM, whose contract includes precharge, slew,
-four common modes and two clock-edge rates. The standalone chopper switch
-overlaps clock modulation in the complete chopper IA. The small NMOS
-track-and-hold remains because its charge retention and reacquisition checks are
-distinct from the complete SKY130 buffered sample-and-hold.
-
-The GF180 R-2R DAC evaluates a physical resistor ladder over all 256 static
-codes plus selected transient codes. The SKY130 DAC adds a complete buffered
-interface and all-code monotonicity, INL and DNL gates. The MIM capacitor bank
-remains in the corpus; its candidate RC extraction behavior needs clarification
-before it returns to core. The basic GF180 PMOS LDO also remains available; the
-selected feedforward version adds layout and compensation demands. Smaller gain
-stages, bias/reference cells, variable resistors and standalone CMFB blocks
-remain useful focused exercises outside core.
-
-The SiGe driver supplies explicitly measured high-frequency behavior. In
-particular, the case named `DC_to_130_GHz_TIA.design_1` currently measures AC
-behavior only through 100 MHz, so its name is not evidence of 130 GHz benchmark
-coverage. The selected driver uses KLayout-PEX capacitance extraction; it does
-not establish distributed interconnect resistance/inductance, eye quality or
-complete RF signoff. Likewise, the VCO contract does not measure phase noise or
-jitter. These limits apply when describing benchmark coverage.
-
-### Evidence and revision
-
-This selection is a structural coverage judgment grounded in published case
-contracts and validation associations. It does not yet establish empirical
-participant discrimination. Validate that separately with complete runs from
-multiple participants and repeated trials: compare per-case success rates,
-score spread, completion cost and correlations between related cases. Separate
-tool errors from physical/electrical failures; do not treat unknown scores as
-zero. A universally easy or hard case can still serve as an anchor, but it
-should not dominate the suite through redundant companions.
-
-Revisit membership when evidence shows redundant outcomes or a missing
-capability. Configuration and task-contract digests identify changes automatically; retain
-archived definitions and avoid tuning case coefficients to obtain a preferred
-ranking.
-
-</details>
-
-## Receiving authored tasks
-
-Task requirements, scoring, testbenches and reference assets are maintained in
-Designs and exported as static files. This Dataset remains independently readable;
-using it does not require the authoring package or a Designs checkout.
-
-After reviewing material rights and obtaining the affected author qualification,
-stage one explicitly selected public case in a fresh directory. Set `case_id` to
-its stable ID and `evidence` to the author-owned directory containing its
-`qualification.json`; keep that evidence outside this Dataset.
+A full dataset commit hash can also be passed as `revision` to
+[`load_dataset`](https://huggingface.co/docs/datasets/loading#hugging-face-hub).
+For comparisons, record that revision together with the evaluator version,
+selected task IDs and evaluation environment.
 
-```bash
-case_id=freepdk45.nangate45-pdk.NAND2_X1
-bench_python=/path/to/installed-bench/bin/python
-staging=/path/to/new-staging
-dataset=/path/to/Dataset
-evidence=/path/to/author-case/verification
-
-iclayout-designs export --case "$case_id" --root /path/to/Designs \
-  --output "$staging" --bench-python "$bench_python"
-"$bench_python" -I -m benchmarking.engine.qualification verify \
-  --dataset "$staging" --case "$case_id" --output "$evidence"
+## Files and table fields
+
+```text
+README.md
+LICENSE
+data.parquet                  # One row per task
+tasks/<pdk>/
+  pdk.toml                    # Pinned external resources and evaluation profiles
+  <collection>/
+    LICENSE                   # Collection and component terms
+    NOTICE                    # Attribution, where present
+    cases/<case>/
+      case.toml               # Task metadata, inputs and evaluation contract
+      problem.md              # Participant-facing requirements
+      materials/              # Netlist and test stimuli
+      reference/              # Reference layout
 ```
 
-Only after the staged reference and declared inputs pass verification, update
-that selected case and verify the final recipient against the same evidence:
+All table paths are relative to the **dataset root**. Paths inside `case.toml`
+are resolved relative to the case directory as specified by the evaluator.
+The table is a convenient view; the complete requirements and evaluation
+contract are in `problem.md` and `case.toml`.
+
+| Field | Meaning |
+| --- | --- |
+| `id` | Stable task identifier used for selection and evaluation. |
+| `title` | Human-readable task title. |
+| `pdk`, `collection` | Process and source collection in the directory hierarchy. |
+| `category`, `summary` | Presentation category and brief circuit description. |
+| `in_core` | Boolean membership in the core benchmark. |
+| `core_order` | Positive integer dispatch order for core tasks; null outside core. |
+| `task_kind`, `status` | Task type and qualification status; current tasks are qualified layout tasks. |
+| `source_url` | Original circuit or design source for attribution. |
+| `problem` | Full English requirements text, also available through `description_path`. |
+| `case_path`, `case_sha256` | Contract file path and SHA-256 of its bytes. |
+| `pdk_path`, `pdk_sha256` | Process resource declaration path and SHA-256 of its bytes. |
+| `description_path` | Path to the requirements file. |
+| `netlist_path`, `netlist_sha256` | Input SPICE netlist path and SHA-256 of its bytes. |
+| `license_path` | Path to the collection license; also read any accompanying `NOTICE`. |
+
+Reference layouts are available for inspection.
+The standard benchmark runner provides only declared solver inputs and approved
+process resources to a participant; reference layouts are excluded. Use that
+runner when measuring participant performance to preserve the input boundary.
+
+## Evaluate a layout or check a reference
+
+Install and configure the evaluator using its
+[setup and tools guide](https://github.com/lizhangmai/ICLayout-Bench/blob/main/docs/tools.md).
+The dataset declares external PDK resources and evaluation profiles; it does
+not bundle the installed PDKs or EDA executables.
+
+After preparing the required tools and resources, a reference check can use the
+directory downloaded above. Run this from the directory containing
+`iclayout-bench-dataset`, and choose a fresh output directory:
 
 ```bash
-iclayout-designs export --case "$case_id" --root /path/to/Designs \
-  --output "$dataset" --update --bench-python "$bench_python"
-"$bench_python" -I -m benchmarking.engine.qualification verify \
-  --dataset "$dataset" --case "$case_id" --output "$evidence"
+python -m benchmarking.engine.preview --dataset ./iclayout-bench-dataset run \
+  --case freepdk45.nangate45-pdk.NAND2_X1 --output ./reference-check
 ```
 
-Mark the accepted case `qualified` in its `case.toml`, then regenerate and check
-the complete index:
+This evaluates the supplied reference and writes local reports. It does not run
+a participant. For submitting candidate layouts or configuring participant
+experiments, see the
+[evaluation guide](https://github.com/lizhangmai/ICLayout-Bench/blob/main/docs/running.md)
+and [participant examples](https://github.com/lizhangmai/ICLayout-Bench/tree/main/examples).
+
+Evaluation checks the submitted artifact, design rules (DRC), netlist equivalence
+(LVS), declared geometry constraints and post-layout electrical requirements.
+Scores range from **0 to 100** and combine declared electrical quality with
+functional layout area. A valid reference demonstrates feasibility; it need not
+score 100. Tool failures or unavailable measurements can leave a score unknown;
+completed physical or functional rejections score zero. Exact checks, targets,
+weights and operating conditions belong to each task contract. See the evaluator's
+[scoring definition](https://github.com/lizhangmai/ICLayout-Bench/blob/main/docs/tasks.md#validity-and-quality).
+
+## Validation scope and limitations
+
+The supplied references have passed their declared qualification plans. This
+establishes feasibility under the evaluated conditions. It does not measure
+participant performance or establish manufacturing signoff. Supplies, loads,
+temperatures, stimuli and observation windows vary by task; only the stated
+conditions are covered.
+
+- **FreePDK45** uses predictive device models and estimated Magic RC extraction.
+  Its community physical-check deck has known coverage limits, including an
+  unimplemented different-potential well-spacing check.
+- **GF180MCU** uses the declared variant-D block-level checks and extraction.
+  Chip-level density and seal-ring closure are outside this benchmark's scope.
+- **IHP SG13G2** includes CMOS and SiGe tasks with case-specific extraction
+  profiles. The core SiGe driver uses capacitance extraction; its high-frequency
+  checks do not establish distributed resistance, inductance or complete RF signoff.
+- **SKY130A** uses the declared TT, 27 °C fixtures and distributed RC extraction;
+  these tasks do not establish process-corner yield, mismatch or reliability.
+
+Circuit names are source identifiers, not frequency or performance guarantees.
+For example, the case named `DC_to_130_GHz_TIA.design_1` evaluates AC behavior
+only through 100 MHz. The VCO task evaluates the stated tuning and phase behavior,
+without a phase-noise or jitter claim. Read each problem before interpreting a
+result as evidence of circuit coverage.
 
-```bash
-iclayout-designs index --dataset "$dataset"
-iclayout-designs index --dataset "$dataset" --check
-```
+## Licensing
 
-For several authorized cases, use repeated `--case` selections and verify each
-case at both boundaries. The exporter
-preserves recipient selection and presentation, including unselected tasks. Changed
-inputs become candidates; complete affected qualification and verify the retained
-external reports before accepting them. Export and local acceptance are separate
-from publication. Task-semantic fixes return to the authoring source so subsequent
-exports remain reproducible. Selection, corpus documentation and publication policy
-continue to be maintained here.
+The root [LICENSE](LICENSE) is MIT and covers original project metadata and
+documentation. It does **not** replace the terms for task materials. Each row's
+`license_path` points to the applicable collection terms.
+
+| Task materials | Tasks | Included terms |
+| --- | ---: | --- |
+| analog-db derivatives in [GF180MCU](tasks/gf180mcuD/analog-db/LICENSE) and [IHP SG13G2](tasks/ihp-sg13g2/analog-db/LICENSE) | 62 | PolyForm Noncommercial 1.0.0, with additional retained component terms where applicable. |
+| [OpenRAM](tasks/freepdk45/OpenRAM/LICENSE) | 3 | GPL-3.0. |
+| [CircuitOpt](tasks/freepdk45/CircuitOpt/LICENSE), [Jianxun-OTA](tasks/gf180mcuD/Jianxun-OTA/LICENSE) and [scan DFF](tasks/gf180mcuD/voidwalkers-scandff/LICENSE) | 3 | MIT. |
+| Other collections | 24 | Apache-2.0; see each collection's `LICENSE` and `NOTICE`. |
+
+The dataset therefore uses component-specific license metadata on Hugging Face.
+Read the included terms for your selected tasks and retain applicable licenses,
+notices, attribution and modification notices when redistributing materials.
+External PDKs and EDA tools have separate licenses.

data.parquet

@@ -1,3 +1,3 @@
 version https://git-lfs.github.com/spec/v1
-oid sha256:8dd140d6c86e020af2696495b21793026fe0ce595335cfb6697365923a6d6a4d
-size 168633
+oid sha256:95f50d45914c71bd207d49c5508104f0f74f4356a72228da925677207a211e10
+size 169850

tasks/freepdk45/OpenRAM/cases/cell_6t/case.toml

@@ -5,13 +5,6 @@ status = "qualified"
 in_core = true
 core_order = 10
 
-[[assets]]
-path = "materials/schematic.svg"
-role = "schematic"
-visibility = "maintainer"
-format = "svg"
-sha256 = "6335fd502eecee2e7657d6d74c543b98cf8191180bbb55a351191ed397631ee2"
-
 [[assets]]
 path = "reference/cell_6t.gds"
 role = "reference"

tasks/freepdk45/OpenRAM/cases/sense_amp/case.toml

@@ -4,13 +4,6 @@ title = "Clocked SRAM Sense Amplifier"
 status = "qualified"
 in_core = false
 
-[[assets]]
-path = "materials/schematic.svg"
-role = "schematic"
-visibility = "maintainer"
-format = "svg"
-sha256 = "e02a8bf40f0dc6c9e1dd9d90053c0d12edbdfef24f99ac34a997de03c2051dc7"
-
 [[assets]]
 path = "reference/sense_amp.gds"
 role = "reference"

tasks/freepdk45/OpenRAM/cases/write_driver/case.toml

@@ -5,13 +5,6 @@ status = "qualified"
 in_core = true
 core_order = 12
 
-[[assets]]
-path = "materials/schematic.svg"
-role = "schematic"
-visibility = "maintainer"
-format = "svg"
-sha256 = "cce2fe9d51a33854eea6b518c9ffcc666dec5a6f8610fed04468112a9f09d9d2"
-
 [[assets]]
 path = "reference/write_driver.gds"
 role = "reference"

tasks/freepdk45/README.md

@@ -1,58 +0,0 @@
-# FreePDK45 Process Scope
-
-Process manifests pin resources; each case contract defines its operating conditions.
-For installation, caching and reference execution, use the evaluator
-[tools guide](https://github.com/lizhangmai/ICLayout-Bench/blob/main/docs/tools.md).
-
-The selected FreePDK45 tasks cover NAND logic, SRAM storage and write drive.
-References use the nominal predictive BSIM4 models and candidate-derived Magic
-RC under the conditions declared by each case. The
-[process manifest](pdk.toml) owns pinned resources and profiles.
-
-Each problem is self-contained. Its configuration owns the exact devices, loads,
-stimuli, observation times, bounds, dimensions and area anchors. Source simulation defines the electrical scoring baseline. Standard-cell area
-uses the reference layout; other areas use the frozen compact estimate. Witnesses
-are excluded from standard solver inputs.
-
-## Physical and extraction scope
-
-The KLayout profile enables all implemented DRC, manufacturing-grid and antenna
-checks without waivers. The community deck's POLY.3 spacing is 50 nm, as documented
-upstream for Nangate compatibility. The source deck explicitly lacks its different-potential
-well-spacing check, so a pass is not complete manufacturing signoff. Strict LVS
-flattens an isolated candidate copy with its labels, removes library-specific
-`cheat` blocks and implicit/global rail joins, and compares models, W/L, named
-ports and real well/tap connectivity. The upstream audit profile is separate and
-retains the original library assumptions; it is not the task judge.
-
-The functional footprint includes drawing layers 1/0 through 29/0, including all
-ten routing metals and nine vias. The same layer set supplies the hard 100 by
-100 um envelope and scored bounding-box area. Annotation and pin-purpose shapes
-are excluded; the contract requires functional routing on drawing layers.
-
-Magic imports the candidate on its exact DBU grid, filters electrical text to
-poly/metal drawing layers and aliases case-insensitive SPICE port names. It
-extracts resistances and capacitances from the GDS, with no schematic replacement.
-Independent LVS selects the applicable VTG or VTL model class first. The native
-RC topology is checked during qualification against the source after removing
-capacitors and collapsing parasitic resistors. Simulation always uses the full,
-unchanged extracted RC network.
-
-The predictive extraction uses the community Magic technology's estimated
-resistance/capacitance coefficients and its native placement of coupling and
-ground capacitance, with nominal VTG/VTL ngspice models at 27 C. Wells and substrate
-are lumped connections. This is not calibrated field-solver extraction or a
-foundry signoff claim; process variation, substrate noise and RF/EM are outside scope.
-
-Use `/resources/support/magic-vtg/freepdk45.tech` or the `magic-vtl` counterpart
-for evaluation-equivalent extraction, as specified by the case problem. The unified
-PDK directory retains the upstream views; reviewed profiles include the adaptations.
-
-The explicit manifest adaptations map MOS extraction to the LVS-selected model
-class, import threshold/annotation markers as non-electrical comments, and correct
-`lambda` from 0.025 to **2.5**. Magic expresses this length in centimicrons, so 2.5
-represents the technology's 25 nm internal grid; the upstream value otherwise
-extracts a 50 nm gate as 0.5 nm. Upstream coefficients are retained. Qualification
-checks the selected published layouts through the complete extraction and simulation
-path. This does not establish stream-out equivalence between Magic and KLayout;
-the community repository documents known via/metal stream-out differences.

tasks/freepdk45/nangate45-pdk/cases/AOI21_X1/case.toml

@@ -11,13 +11,6 @@ visibility = "maintainer"
 format = "gds"
 sha256 = "1ebcc6f4d7a8f5c50846b5cdfd60f3039fb96caf455b89f2d7f30568c5a2af94"
 
-[[assets]]
-path = "materials/schematic.svg"
-role = "schematic"
-visibility = "maintainer"
-format = "svg"
-sha256 = "e9e418eff15b2d7ef5a99215c0288a8b104f0d1a21c2956586a21b1d675c4e62"
-
 [task]
 hours = 3
 kind = "netlist_to_gds"

tasks/freepdk45/nangate45-pdk/cases/NAND2_X1/case.toml

@@ -12,13 +12,6 @@ visibility = "maintainer"
 format = "gds"
 sha256 = "d077499ea242e1c8506c7a992ce713d46ea513c52b80073a2b7ae6d6515f2d3f"
 
-[[assets]]
-path = "materials/schematic.svg"
-role = "schematic"
-visibility = "maintainer"
-format = "svg"
-sha256 = "f7f06cd9039e53754770235f69f15f0a0a01f202047caaf92cf9e82c13048f5c"
-
 [task]
 hours = 1
 kind = "netlist_to_gds"

tasks/gf180mcuD/2AMLogic-sar-adc/cases/track_switch/case.toml

@@ -4,13 +4,6 @@ title = "Dummy-Compensated Track Switch"
 status = "qualified"
 in_core = false
 
-[[assets]]
-path = "materials/schematic.svg"
-role = "schematic"
-visibility = "maintainer"
-format = "svg"
-sha256 = "a9a5333989af2baaba17d6660a93510536810860dd53ac43161118419da2e692"
-
 [[assets]]
 path = "reference/adc_tgate_dum.gds"
 role = "reference"

tasks/gf180mcuD/Chipathon2023_ADC/cases/comparator/case.toml

@@ -4,13 +4,6 @@ title = "Dynamic Comparator"
 status = "qualified"
 in_core = false
 
-[[assets]]
-path = "materials/schematic.svg"
-role = "schematic"
-visibility = "maintainer"
-format = "svg"
-sha256 = "ffeab4b81b6f04616837c935feca4f5d8e6b1313cd1648c6b80e3e9740aded33"
-
 [[assets]]
 path = "reference/comp_20240331.gds"
 role = "reference"

tasks/gf180mcuD/Jianxun-OTA/cases/ota_5t/case.toml

@@ -5,13 +5,6 @@ status = "qualified"
 in_core = true
 core_order = 8
 
-[[assets]]
-path = "materials/schematic.svg"
-role = "schematic"
-visibility = "maintainer"
-format = "svg"
-sha256 = "a2f3f2d3d55c5224b39a37e59688fc586d284cb8c96cdc4ef8735b9016a752fc"
-
 [[assets]]
 path = "reference/ota_5t.gds"
 role = "reference"

tasks/gf180mcuD/README.md

@@ -1,47 +0,0 @@
-# GF180MCU Process Scope
-
-Process manifests pin resources; each case contract defines its operating conditions.
-For installation, caching and reference execution, use the evaluator
-[tools guide](https://github.com/lizhangmai/ICLayout-Bench/blob/main/docs/tools.md).
-
-The GF180 cases use the explicit operating conditions and frozen scoring anchors
-in their task contracts. Core membership is defined by the `in_core` field in each case contract, reflected in the generated root [data.parquet](../../data.parquet), and
-[selection rationale](../../README.md#core-selection-rationale) describes the represented circuit capabilities.
-
-The PDK manifest ([pdk.toml](pdk.toml)) binds `models`, `physical` and
-`magic` profiles to one open-pdks installation. `models` uses nominal primitive
-ngspice files; `physical` uses the qualified official KLayout rules for variant D,
-including geometric/connectivity/off-grid DRC and antenna checks; `magic` uses the
-upstream technology built for five metals, 1.1 um top metal and 1 kOhm/square poly.
-The prebuilt release and library selection are explicit in the manifest.
-The rule files and extraction coefficients come from that release; only the
-SPICE reader adapter below modifies an upstream file. DRC runs all rule groups
-except chip-level density, including dummy fill and 0.001 um database-unit checks.
-The upstream isolated-worker mode keeps antenna connectivity changes separate
-from the geometry/connectivity rule groups.
-The KLayout reader adapter recognizes the official `nfet_03v3`,
-`pfet_03v3` and `ppolyf_u_1k` X wrappers using their actual SI dimensions and MOS
-total width. Named top-level pin correspondence is required independently of
-KLayout's topology match.
-
-The Magic profile uses nominal `ngspice()` extraction and a 10-way subdivision
-of its 0.05 um internal grid before GDS import. This preserves 5 nm geometry and
-port locations during resistance extraction. Candidate-derived MOS/passive
-parameters, coupled capacitance and distributed interconnect resistance feed the
-same published testbench used for source calibration. Physically distinct
-source/body nodes must remain distinct; the model boundary does not include a
-distributed silicon substrate network. The standalone-block scope excludes
-chip-level density and seal-ring closure, statistical yield and RF/EM analysis.
-The isolated-body PTAT uses a physical `nfet_03v3_dn` primitive for native LVS,
-with its corresponding four-terminal `nfet_03v3` simulator call. Its independent
-witness retains an output-tied isolated P-well, supply-tied deep N-well and an
-explicit N-well annulus. The annulus keeps Magic's extresist substrate filling
-from joining that body to the outer substrate return. This is a validated
-layout route with the existing decks, not a change to PDK extraction rules.
-The case additionally qualifies zero-state startup at its declared 100 fF load,
-temperatures and supply ramps; larger loads are not covered.
-
-StrongARM uses its declared 3.3 V CMOS binding and dynamic timing/decision
-measurements. Other model families, such as GF180 BJTs, are outside these
-published contracts. Use a compatible tool image as specified by the
-[evaluator tools guide](https://github.com/lizhangmai/ICLayout-Bench/blob/main/docs/tools.md).

tasks/gf180mcuD/analog-db/cases/amp_004_folded_cascode/case.toml

@@ -4,13 +4,6 @@ title = "Externally Biased PMOS-Input Folded-Cascode OTA"
 status = "qualified"
 in_core = false
 
-[[assets]]
-path = "materials/schematic.svg"
-role = "schematic"
-visibility = "maintainer"
-format = "svg"
-sha256 = "48c6706e3cae42f7b8557b9af4784ba8f43e4c0d4a3e92cd0f1e8146649924ef"
-
 [[assets]]
 path = "reference/amp_004_folded_cascode.gds"
 role = "physical-witness"

tasks/gf180mcuD/analog-db/cases/amp_017_tan_clia/case.toml

@@ -4,13 +4,6 @@ title = "Tan CLIA Three-Stage Amplifier"
 status = "qualified"
 in_core = false
 
-[[assets]]
-path = "materials/schematic.svg"
-role = "schematic"
-visibility = "maintainer"
-format = "svg"
-sha256 = "96089d982396b1636c9585946b6ac3b7e1dd0d7ff5bf4e04949798cf8fc22fe3"
-
 [[assets]]
 path = "reference/amp_017_tan_clia.gds"
 role = "physical-witness"

tasks/gf180mcuD/analog-db/cases/amp_018_telescopic_cascode/case.toml

@@ -4,13 +4,6 @@ title = "Tail-Referenced Telescopic Cascode Amplifier"
 status = "qualified"
 in_core = false
 
-[[assets]]
-path = "materials/schematic.svg"
-role = "schematic"
-visibility = "maintainer"
-format = "svg"
-sha256 = "a0c1cac7ee9169f75aee339de93ee5e66e2343f7b361e42733dd26143e611336"
-
 [[assets]]
 path = "reference/amp_018_telescopic_cascode.gds"
 role = "physical-witness"

tasks/gf180mcuD/analog-db/cases/amp_019_ti_ldo_error/case.toml

@@ -4,13 +4,6 @@ title = "Externally Biased TI-Architecture Error Amplifier"
 status = "qualified"
 in_core = false
 
-[[assets]]
-path = "materials/schematic.svg"
-role = "schematic"
-visibility = "maintainer"
-format = "svg"
-sha256 = "3877db1eacb0c847928306e6aafa5705ddc84e0e1c3f6eabba14d099838be54d"
-
 [[assets]]
 path = "reference/amp_019_ti_ldo_error.gds"
 role = "physical-witness"

tasks/gf180mcuD/analog-db/cases/amp_032_ti_ldo_error_selfbias/case.toml

@@ -4,13 +4,6 @@ title = "Self-Biased LDO Error Amplifier"
 status = "qualified"
 in_core = false
 
-[[assets]]
-path = "materials/schematic.svg"
-role = "schematic"
-visibility = "maintainer"
-format = "svg"
-sha256 = "9712137b8c384eabead2a587c4d3edf430493ba35bd2c71997868b2e51089bc4"
-
 [[assets]]
 path = "reference/amp_032_ti_ldo_error_selfbias.gds"
 role = "physical-witness"

tasks/gf180mcuD/analog-db/cases/amp_033_ti_ldo_ref_selfbias/case.toml

@@ -4,13 +4,6 @@ title = "Self-Biased LDO Reference Amplifier"
 status = "qualified"
 in_core = false
 
-[[assets]]
-path = "materials/schematic.svg"
-role = "schematic"
-visibility = "maintainer"
-format = "svg"
-sha256 = "3a60e5ac289e157e6ceb21e205297bab3364801e6e6c0371740cd86005a74204"
-
 [[assets]]
 path = "reference/amp_033_ti_ldo_ref_selfbias.gds"
 role = "physical-witness"

tasks/gf180mcuD/analog-db/cases/cmfb_003_5t_nmos_input/case.toml

@@ -4,13 +4,6 @@ title = "Segmented-Resistor NMOS Common-Mode Controller"
 status = "qualified"
 in_core = false
 
-[[assets]]
-path = "materials/schematic.svg"
-role = "schematic"
-visibility = "maintainer"
-format = "svg"
-sha256 = "e72dd81bd5455bb1676402b03936c909f00cd6305e13b84ac78748749e690c7d"
-
 [[assets]]
 path = "reference/cmfb_003_5t_nmos_input.gds"
 role = "physical-witness"

tasks/gf180mcuD/analog-db/cases/cmp_001_hyst_diffpair/case.toml

@@ -4,13 +4,6 @@ title = "Resistive-Feedback Hysteretic Comparator"
 status = "qualified"
 in_core = false
 
-[[assets]]
-path = "materials/schematic.svg"
-role = "schematic"
-visibility = "maintainer"
-format = "svg"
-sha256 = "35ce9376096cd5be1cc888d88452a90b77c24fba5b1a30331911b6d50cf9ac07"
-
 [[assets]]
 path = "reference/cmp_001_hyst_diffpair.gds"
 role = "physical-witness"

tasks/gf180mcuD/analog-db/cases/cmp_002_strongarm/case.toml

@@ -5,13 +5,6 @@ status = "qualified"
 in_core = true
 core_order = 18
 
-[[assets]]
-path = "materials/schematic.svg"
-role = "schematic"
-visibility = "maintainer"
-format = "svg"
-sha256 = "5aad5646b68087127a52b264d5bf88ef61ca1f69ba8bdedc59ef93d76e63064a"
-
 [[assets]]
 path = "reference/cmp_002_strongarm.gds"
 role = "physical-witness"

tasks/gf180mcuD/analog-db/cases/dp_001_resistive_load/case.toml

@@ -4,13 +4,6 @@ title = "Resistively Loaded Differential Pair"
 status = "qualified"
 in_core = false
 
-[[assets]]
-path = "materials/schematic.svg"
-role = "schematic"
-visibility = "maintainer"
-format = "svg"
-sha256 = "c0e54c8393f7decf7f5d56880180cd24066618738d7e45172c213919211632c6"
-
 [[assets]]
 path = "reference/dp_001_resistive_load.gds"
 role = "physical-witness"

tasks/gf180mcuD/analog-db/cases/gs_001_cascode_cs/case.toml

@@ -4,13 +4,6 @@ title = "Self-Biased Cascode Common-Source Gain Stage"
 status = "qualified"
 in_core = false
 
-[[assets]]
-path = "materials/schematic.svg"
-role = "schematic"
-visibility = "maintainer"
-format = "svg"
-sha256 = "963fd971e795de0261eff9e143ca95134293fbec4adbda8927a8c2fc97e16887"
-
 [[assets]]
 path = "reference/gs_001_cascode_cs.gds"
 role = "physical-witness"

tasks/gf180mcuD/analog-db/cases/ldo_002_analoggym_folded_cascode/case.toml

@@ -4,13 +4,6 @@ title = "Folded-Cascode LDO"
 status = "qualified"
 in_core = false
 
-[[assets]]
-path = "materials/schematic.svg"
-role = "schematic"
-visibility = "maintainer"
-format = "svg"
-sha256 = "ad4eeffa3d8ecbe74a6b69a46af5e2067e640ea6e8b2c68d8019a7111d832110"
-
 [[assets]]
 path = "reference/ldo_002_analoggym_folded_cascode.gds"
 role = "physical-witness"

tasks/gf180mcuD/analog-db/cases/ldo_003_analoggym_simple/case.toml

@@ -4,13 +4,6 @@ title = "Simple Unity-Feedback LDO"
 status = "qualified"
 in_core = false
 
-[[assets]]
-path = "materials/schematic.svg"
-role = "schematic"
-visibility = "maintainer"
-format = "svg"
-sha256 = "a223a98879e607a78a8842a8df6b4cad3f6ef1e233084f6c7b152c566f46970a"
-
 [[assets]]
 path = "reference/ldo_003_analoggym_simple.gds"
 role = "physical-witness"

tasks/gf180mcuD/analog-db/cases/ldo_004_basic_pmos/case.toml

@@ -4,13 +4,6 @@ title = "Externally Biased 1.8 V PMOS Regulator Core"
 status = "qualified"
 in_core = false
 
-[[assets]]
-path = "materials/schematic.svg"
-role = "schematic"
-visibility = "maintainer"
-format = "svg"
-sha256 = "4db4e5eb0cf08e3391cf074eb290d28e680668fe3a70156a4ec40bc2313ef6e4"
-
 [[assets]]
 path = "reference/ldo_004_basic_pmos.gds"
 role = "physical-witness"

tasks/gf180mcuD/analog-db/cases/ldo_005_buffered_ref/case.toml

@@ -4,13 +4,6 @@ title = "Buffered-Reference LDO"
 status = "qualified"
 in_core = false
 
-[[assets]]
-path = "materials/schematic.svg"
-role = "schematic"
-visibility = "maintainer"
-format = "svg"
-sha256 = "16844a2fe1c8dd18bb3176ab0e3510df7cbc8df9807b4cda3ecbe5d74787f4c1"
-
 [[assets]]
 path = "reference/ldo_005_buffered_ref.gds"
 role = "physical-witness"