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testbench/UTOSS_risc-v_pr70/open_tool_p2p_buggy.log

@@ -0,0 +1,14 @@
+INFO: open-tool P2P fallback (buggy)
+
+### native_sim:.
+'sh' '-c' 'mkdir -p test/vcd && iverilog -g2012 -I. -Isrc -Itest -Isrc/Instruction_Decode -o __p2p_rf_tb.vvp src/Instruction_Decode/RegisterFile.v test/rf_tb.sv && vvp -N __p2p_rf_tb.vvp +VCD_PATH=test/vcd'
+Starting Register File Testbench...
+VCD info: dumpfile test/vcd/rf_tb.vcd opened for output.
+PASS: current baseAddr output: deadbeef; expected baseAddr output: DEADBEEF
+PASS: current writeData output: cafebabe; expected writeData output: CAFEBABE
+PASS: Write to register 15 verified. current reg 15 output: 12345678; expected reg 15 output: 12345678
+PASS: Write to register 0 verified. current reg 0 output: 00000000; expected reg 0 output: 0
+test/rf_tb.sv:85: $finish called at 36000 (1ps)
+
+rc=0
+PASS: native simulation P2P passed in buggy phase: .: 'sh' '-c' 'mkdir -p test/vcd && iverilog -g2012 -I. -Isrc -Itest -Isrc/Instruction_Decode -o __p2p_rf_tb.vvp src/Instruction_Decode/RegisterFile.v test/rf_tb.sv && vvp -N __p2p_rf_tb.vvp +VCD_PATH=test/vcd'

testbench/UTOSS_risc-v_pr70/open_tool_p2p_fixed.log

@@ -0,0 +1,14 @@
+INFO: open-tool P2P fallback (fixed)
+
+### native_sim:.
+'sh' '-c' 'mkdir -p test/vcd && iverilog -g2012 -I. -Isrc -Itest -Isrc/Instruction_Decode -o __p2p_rf_tb.vvp src/Instruction_Decode/RegisterFile.v test/rf_tb.sv && vvp -N __p2p_rf_tb.vvp +VCD_PATH=test/vcd'
+Starting Register File Testbench...
+VCD info: dumpfile test/vcd/rf_tb.vcd opened for output.
+PASS: current baseAddr output: deadbeef; expected baseAddr output: DEADBEEF
+PASS: current writeData output: cafebabe; expected writeData output: CAFEBABE
+PASS: Write to register 15 verified. current reg 15 output: 12345678; expected reg 15 output: 12345678
+PASS: Write to register 0 verified. current reg 0 output: 00000000; expected reg 0 output: 0
+test/rf_tb.sv:85: $finish called at 36000 (1ps)
+
+rc=0
+PASS: native simulation P2P passed in fixed phase: .: 'sh' '-c' 'mkdir -p test/vcd && iverilog -g2012 -I. -Isrc -Itest -Isrc/Instruction_Decode -o __p2p_rf_tb.vvp src/Instruction_Decode/RegisterFile.v test/rf_tb.sv && vvp -N __p2p_rf_tb.vvp +VCD_PATH=test/vcd'

testbench/UTOSS_risc-v_pr70/repo_native_buggy.log

@@ -0,0 +1 @@
+PASS: repo native simulation P2P passed in buggy phase

testbench/UTOSS_risc-v_pr70/repo_native_fixed.log

@@ -0,0 +1 @@
+PASS: repo native simulation P2P passed in fixed phase

testbench/UTOSS_risc-v_pr70/repo_native_source.path

@@ -0,0 +1 @@
+test/alu_branchifeq_tb.sv

testbench/UTOSS_risc-v_pr70/run_once.sh

@@ -0,0 +1,4 @@
+#!/bin/bash
+set -u
+HERE="$(cd "$(dirname "${BASH_SOURCE[0]:-$0}")" && pwd)"
+exec python3 "$HERE/../_run_once_from_run_verilator.py" "$HERE/run_verilator.sh"

testbench/UTOSS_risc-v_pr70/run_verilator.sh

@@ -0,0 +1,78 @@
+#!/bin/bash
+set -u
+
+HERE="$(cd "$(dirname "${BASH_SOURCE[0]:-$0}")" && pwd)"
+cd "$HERE"
+. "$HERE/../_testcase_minimum.sh"
+. "$HERE/../_repo_native_p2p_smoke.sh"
+export HWE_AUTO_COVERAGE=1
+
+NAME="UTOSS_risc-v_pr70"
+DATA_ROOT="$(cd "$HERE/../.." && pwd)"
+SNAPSHOT="$DATA_ROOT/snapshots/$NAME"
+PATCH_FILE="$DATA_ROOT/patches/$NAME.patch"
+SCRATCH="$HERE/snapshot_scratch"
+PATCH_TARGETS=(
+  "$SCRATCH/src/Instruction_Decode/Instruction_Decode.v"
+  "$SCRATCH/src/Instruction_Decode/RegisterFile.v"
+  "$SCRATCH/src/fetch.sv"
+  "$SCRATCH/test/nop_tb.sv"
+)
+
+run_phase() {
+  local tag="$1"
+
+  rm -rf obj_dir "verilator_${tag}_build.log" "verilator_${tag}.log"
+  run_repo_native_p2p_smoke "$tag" || return $?
+
+  verilator --binary --timing --assert \
+    --Wno-fatal --Wno-WIDTH --Wno-UNOPTFLAT --Wno-UNUSEDSIGNAL \
+    --Wno-UNUSEDPARAM --Wno-LATCH --Wno-STMTDLY --Wno-PINMISSING \
+    --Wno-PINCONNECTEMPTY --Wno-DECLFILENAME --Wno-ASSIGNIN --Wno-ENUMVALUE \
+    --timescale 1ns/1ps \
+    -I"$SCRATCH" -I"$SCRATCH/src" -I"$SCRATCH/test" \
+    "$SCRATCH/src/top.v" \
+    "$SCRATCH/src/ControlFSM.sv" \
+    "$SCRATCH/src/fetch.sv" \
+    "$SCRATCH/src/utils/MA.v" \
+    "$SCRATCH/src/Instruction_Decode/Instruction_Decode.v" \
+    "$SCRATCH/src/Instruction_Decode/RegisterFile.v" \
+    "$SCRATCH/src/ALU_ALUdecoder/ALU.v" \
+    "$SCRATCH/src/ALU_ALUdecoder/ALUdecoder.v" \
+    "$HERE/tb_utoss_riscv_pr70_verilator.sv" \
+    --top-module tb_utoss_riscv_pr70_verilator \
+    -o simv_vlt 2>&1 | tee "verilator_${tag}_build.log" >/dev/null
+
+  [ ! -x obj_dir/simv_vlt ] && return 2
+
+  timeout 20 ./obj_dir/simv_vlt 2>&1 | tee "verilator_${tag}.log" >/dev/null
+  grep -qE '(^|[^A-Za-z])PASS:' "verilator_${tag}.log" && \
+    ! grep -qE '(^|[^A-Za-z])(FAIL:|\\$fatal|Aborting\\.\\.\\.)' "verilator_${tag}.log"
+}
+
+rm -rf "$SCRATCH"
+cp -r "$SNAPSHOT" "$SCRATCH"
+chmod -R u+w "$SCRATCH"
+echo BUGGY
+(cd "$SCRATCH" && patch -p1 -R -f --no-backup-if-mismatch < "$PATCH_FILE" >/dev/null 2>&1) || true
+run_phase buggy
+rc_buggy=$?
+
+rm -rf "$SCRATCH"
+cp -r "$SNAPSHOT" "$SCRATCH"
+chmod -R u+w "$SCRATCH"
+echo FIXED
+(cd "$SCRATCH" && patch -p1 -f --no-backup-if-mismatch < "$PATCH_FILE" >/dev/null 2>&1) || true
+run_phase fixed
+rc_fixed=$?
+
+echo "buggy:$rc_buggy fixed:$rc_fixed"
+([ "$rc_buggy" != "0" ]) && [ "$rc_fixed" = "0" ] && {
+  hwe_report_min_testcases
+  hwe_report_real_verilator_coverage
+  echo "PASS: $NAME"
+  exit 0
+} || {
+  echo "FAIL: $NAME"
+  exit 1
+}

testbench/UTOSS_risc-v_pr70/tb_utoss_riscv_pr70_verilator.sv

@@ -0,0 +1,84 @@
+`timescale 1ns/1ps
+
+`include "test/utils.svh"
+
+module tb_utoss_riscv_pr70_verilator;
+  reg clk;
+  reg reset;
+
+  top uut ( .clk(clk), .reset(reset) );
+
+  task wait_till_next_cfsm_state(input [5:0] expected_state);
+    @(posedge clk); #1;
+    `assert_equal(expected_state, uut.control_fsm.current_state)
+  endtask
+
+  initial begin
+    clk = 0;
+    forever #5 clk = ~clk;
+  end
+
+  initial begin
+    reset <= `TRUE;
+
+    uut.memory.M[0] = 32'h00000013; // nop = addi x0, x0, 0
+    // 2nd instruction (coverage stimulus): beq x0, x0, 8 -> always taken since
+    // x0 == x0, so the branch FSM selects PC_SRC__JUMP and the fetch unit
+    // evaluates pc_next = pc_cur + imm_ext (fetch.sv line 26).
+    uut.memory.M[1] = 32'h00000463; // beq x0, x0, 8
+    uut.instruction_decode.instanceRegFile.RFMem[0] = 32'h01010101;
+    uut.instruction_decode.instanceRegFile.RFMem[1] = 32'h0000000A;
+    uut.instruction_decode.instanceRegFile.RFMem[2] = 32'h00000014;
+
+    wait_till_next_cfsm_state(uut.control_fsm.FETCH);
+    reset <= `FALSE;
+
+    wait_till_next_cfsm_state(uut.control_fsm.DECODE);
+    `assert_equal(7'b0010011, uut.opcode)
+    `assert_equal(0, uut.instruction_decode.rs1)
+    `assert_equal(0, uut.instruction_decode.rd)
+    `assert_equal(0, uut.instruction_decode.imm_ext)
+
+    wait_till_next_cfsm_state(uut.control_fsm.EXECUTEI);
+    `assert_equal(32'h0, uut.alu.a)
+    `assert_equal(32'h0, uut.alu.b)
+    `assert_equal(32'h0, uut.alu.out)
+    if (uut.alu.a !== 32'h0 || uut.alu.b !== 32'h0 || uut.alu.out !== 32'h0) begin
+      $display("FAIL: NOP used nonzero x0 operand/result a=%08h b=%08h out=%08h",
+               uut.alu.a, uut.alu.b, uut.alu.out);
+      $fatal(1);
+    end
+
+    wait_till_next_cfsm_state(uut.control_fsm.ALUWB);
+    wait_till_next_cfsm_state(uut.control_fsm.FETCH);
+
+    `assert_equal(32'h0, uut.instruction_decode.instanceRegFile.RFMem[0])
+    `assert_equal(4, uut.fetch.pc_cur)
+    if (uut.instruction_decode.instanceRegFile.RFMem[0] !== 32'h0 ||
+        uut.fetch.pc_cur !== 32'h4) begin
+      $display("FAIL: post-NOP state x0=%08h pc=%08h",
+               uut.instruction_decode.instanceRegFile.RFMem[0], uut.fetch.pc_cur);
+      $fatal(1);
+    end
+
+    // Coverage stimulus: walk the taken branch through DECODE -> BRANCHIFEQ so
+    // the fetch unit computes the jump target (pc_cur + imm_ext). No new asserts.
+    wait_till_next_cfsm_state(uut.control_fsm.DECODE);
+    wait_till_next_cfsm_state(uut.control_fsm.BRANCHIFEQ);
+    @(posedge clk); #1; // settle: PCUpdate + PC_SRC__JUMP drive pc_next
+
+    // Coverage stimulus: present an R-type "add x3, x1, x2" to the decoder so
+    // the register file reads nonzero source addresses (rs1=1, rs2=2). This
+    // exercises the (Addr1!=0)/(Addr2!=0) sides of the baseAddr/writeData
+    // ternaries (the existing flow only ever reads x0). RFMem[1]/RFMem[2] are
+    // preloaded above. No new assertions are added.
+    uut.instruction = 32'h002081B3; // add x3, x1, x2
+    #1; // combinational settle of rs1/rs2 -> Addr1/Addr2 -> baseAddr/writeData
+    @(posedge clk); #1;
+
+    $display("PASS: UTOSS_risc-v_pr70 x0 stays hard-wired to zero");
+    $finish;
+  end
+
+  `SETUP_VCD_DUMP(tb_utoss_riscv_pr70_verilator)
+endmodule

testbench/UTOSS_risc-v_pr70/verilator_buggy.log

@@ -0,0 +1,3 @@
+[26000] %Fatal: tb_utoss_riscv_pr70_verilator.sv:43: Assertion failed in TOP.tb_utoss_riscv_pr70_verilator: Expected `0`, got `1010101`
+%Error: testbench/UTOSS_risc-v_pr70/tb_utoss_riscv_pr70_verilator.sv:43: Verilog $stop
+Aborting...

testbench/UTOSS_risc-v_pr70/verilator_buggy_build.log

@@ -0,0 +1,245 @@
+%Warning-CASEINCOMPLETE: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/Instruction_Decode/Instruction_Decode.v:123:3: Case values incompletely covered (example pattern 0x0)
+  123 |   case(opcode)
+      |   ^~~~
+                         ... For warning description see https://verilator.org/warn/CASEINCOMPLETE?v=5.047
+                         ... Use "/* verilator lint_off CASEINCOMPLETE */" and lint_on around source to disable this message.
+%Warning-INITIALDLY: testbench/UTOSS_risc-v_pr70/tb_utoss_riscv_pr70_verilator.sv:22:11: Non-blocking assignment '<=' in initial/final block
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+   22 |     reset <= 1'b1;
+      |           ^~
+                     ... For warning description see https://verilator.org/warn/INITIALDLY?v=5.047
+                     ... Use "/* verilator lint_off INITIALDLY */" and lint_on around source to disable this message.
+%Warning-INITIALDLY: testbench/UTOSS_risc-v_pr70/tb_utoss_riscv_pr70_verilator.sv:34:11: Non-blocking assignment '<=' in initial/final block
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+   34 |     reset <= 1'b0;
+      |           ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:114:12: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  114 |     Branch <= 1'b0;
+      |            ^~
+                  ... For warning description see https://verilator.org/warn/COMBDLY?v=5.047
+                  ... Use "/* verilator lint_off COMBDLY */" and lint_on around source to disable this message.
+                  *** See https://verilator.org/warn/COMBDLY?v=5.047 before disabling this,
+                  else you may end up with different sim results.
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:115:12: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  115 |     pc_src <= 1'b0;
+      |            ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:116:14: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  116 |     PCUpdate <= 1'b0;
+      |              ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:117:13: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  117 |     IRWrite <= 1'b0;
+      |             ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:118:14: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  118 |     MemWrite <= 1'b0;
+      |              ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:120:12: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  120 |   FSMState <= current_state;
+      |            ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:233:12: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  233 |     AdrSrc <= ADR_SRC__PC;
+      |            ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:234:13: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  234 |     IRWrite <= 1'b1;
+      |             ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:142:13: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  142 |     ALUSrcA <= ALU_SRC_A__OLD_PC;
+      |             ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:143:13: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  143 |     ALUSrcB <= ALU_SRC_B__IMM_EXT;
+      |             ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:144:11: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  144 |     ALUOp <= 2'b00;
+      |           ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:150:13: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  150 |     ALUSrcA <= ALU_SRC_A__ZERO;
+      |             ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:151:13: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  151 |     ALUSrcB <= ALU_SRC_B__IMM_EXT;
+      |             ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:152:11: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  152 |     ALUOp <= 2'b00;
+      |           ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:192:13: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  192 |     ALUSrcA <= ALU_SRC_A__RD1;
+      |             ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:193:13: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  193 |     ALUSrcB <= ALU_SRC_B__RD2;
+      |             ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:194:11: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  194 |     ALUOp <= 2'b01;
+      |           ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:195:15: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  195 |     ResultSrc <= RESULT_SRC__ALU_OUT;
+      |               ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:196:12: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  196 |     Branch <= 1'b1;
+      |            ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:197:16: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  197 |         pc_src <= zero_flag ? PC_SRC__JUMP : PC_SRC__INCREMENT;
+      |                ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:198:18: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  198 |         PCUpdate <= 1'b1;
+      |                  ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:226:15: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  226 |     ResultSrc <= RESULT_SRC__DATA;
+      |               ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:227:14: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  227 |     RegWrite <= 1'b1;
+      |              ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:219:15: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  219 |     ResultSrc <= RESULT_SRC__ALU_OUT;
+      |               ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:220:12: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  220 |     AdrSrc <= ADR_SRC__RESULT;
+      |            ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:211:15: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  211 |     ResultSrc <= RESULT_SRC__ALU_OUT;
+      |               ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:212:12: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  212 |     AdrSrc <= ADR_SRC__RESULT;
+      |            ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:213:14: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  213 |     MemWrite <= 1'b1;
+      |              ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:204:15: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  204 |     ResultSrc <= RESULT_SRC__ALU_OUT;
+      |               ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:205:14: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  205 |     RegWrite <= 1'b1;
+      |              ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:184:13: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  184 |     ALUSrcA <= ALU_SRC_A__RD1;
+      |             ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:185:13: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  185 |     ALUSrcB <= ALU_SRC_B__IMM_EXT;
+      |             ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:186:11: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  186 |     ALUOp <= 2'b00;
+      |           ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:166:13: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  166 |     ALUSrcA <= ALU_SRC_A__RD1;
+      |             ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:167:13: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  167 |     ALUSrcB <= ALU_SRC_B__IMM_EXT;
+      |             ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:168:11: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  168 |     ALUOp <= 2'b11;
+      |           ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:174:13: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  174 |     ALUSrcA <= ALU_SRC_A__OLD_PC;
+      |             ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:175:13: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  175 |     ALUSrcB <= ALU_SRC_B__4;
+      |             ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:176:11: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  176 |     ALUOp <= 2'b00;
+      |           ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:177:15: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  177 |     ResultSrc <= RESULT_SRC__ALU_OUT;
+      |               ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:178:18: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  178 |         PCUpdate <= 1'b1;
+      |                  ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:158:13: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  158 |     ALUSrcA <= ALU_SRC_A__RD1;
+      |             ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:159:13: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  159 |     ALUSrcB <= ALU_SRC_B__RD2;
+      |             ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:160:11: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  160 |     ALUOp <= 2'b10;
+      |           ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:134:13: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  134 |     ALUSrcA <= ALU_SRC_A__OLD_PC;
+      |             ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:135:13: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  135 |     ALUSrcB <= ALU_SRC_B__IMM_EXT;
+      |             ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:136:11: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  136 |     ALUOp <= 2'b00;
+      |           ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:126:12: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  126 |     AdrSrc <= ADR_SRC__PC;
+      |            ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:127:13: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  127 |     IRWrite <= 1'b1;
+      |             ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:128:18: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  128 |         PCUpdate <= 1'b1;
+      |                  ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/fetch.sv:26:36: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                 : ... This will be executed as a blocking assignment '='!
+   26 |         PC_SRC__JUMP:      pc_next <= pc_cur + imm_ext;
+      |                                    ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/fetch.sv:25:36: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                 : ... This will be executed as a blocking assignment '='!
+   25 |         PC_SRC__INCREMENT: pc_next <= pc_cur + 32'h4;
+      |                                    ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/fetch.sv:29:15: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                 : ... This will be executed as a blocking assignment '='!
+   29 |       pc_next <= pc_cur;
+      |               ^~
+make: Entering directory 'testbench/UTOSS_risc-v_pr70/obj_dir'
+g++ -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -Os  -c -o _coverage_main.o testbench/UTOSS_risc-v_pr70/../_coverage_main.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -c -o verilated.o /opt/oss-cad-suite/share/verilator/include/verilated.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -c -o verilated_cov.o /opt/oss-cad-suite/share/verilator/include/verilated_cov.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -c -o verilated_timing.o /opt/oss-cad-suite/share/verilator/include/verilated_timing.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -c -o verilated_threads.o /opt/oss-cad-suite/share/verilator/include/verilated_threads.cpp
+python3 /opt/oss-cad-suite/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vhwe_cov_top.cpp Vhwe_cov_top___024root__0.cpp Vhwe_cov_top___024root__Slow.cpp Vhwe_cov_top___024root__0__Slow.cpp Vhwe_cov_top___024unit__Slow.cpp Vhwe_cov_top___024unit__0__Slow.cpp Vhwe_cov_top__Syms__Slow.cpp > Vhwe_cov_top__ALL.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -c -o Vhwe_cov_top__ALL.o Vhwe_cov_top__ALL.cpp
+g++ -Wl,-O2 -Wl,--sort-common -Wl,--as-needed -Wl,-z,relro -Wl,-z,now -Wl,--disable-new-dtags -Wl,--gc-sections -Wl,--allow-shlib-undefined -Wl,-rpath,/home/user/miniforge3/lib -Wl,-rpath-link,/home/user/miniforge3/lib -L/home/user/miniforge3/lib    _coverage_main.o verilated.o verilated_cov.o verilated_timing.o verilated_threads.o Vhwe_cov_top__ALL.a    -pthread -lpthread -latomic   -o simv_vlt
+rm Vhwe_cov_top__ALL.verilator_deplist.tmp
+make: Leaving directory 'testbench/UTOSS_risc-v_pr70/obj_dir'
+- V e r i l a t i o n   R e p o r t: Verilator 5.047 devel rev v5.046-293-ge82bd52fa (mod)
+- Verilator: Built from 0.501 MB sources in 11 modules, into 0.367 MB in 7 C++ files needing 0.000 MB
+- Verilator: Walltime 8.408 s (elab=0.002, cvt=0.018, bld=8.378); cpu 0.030 s on 1 threads; allocated 22.891 MB

testbench/UTOSS_risc-v_pr70/verilator_fixed.log

@@ -0,0 +1,2 @@
+PASS: UTOSS_risc-v_pr70 x0 stays hard-wired to zero
+- testbench/UTOSS_risc-v_pr70/tb_utoss_riscv_pr70_verilator.sv:80: Verilog $finish

testbench/UTOSS_risc-v_pr70/verilator_fixed_build.log

@@ -0,0 +1,245 @@
+%Warning-CASEINCOMPLETE: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/Instruction_Decode/Instruction_Decode.v:123:3: Case values incompletely covered (example pattern 0x0)
+  123 |   case(opcode)
+      |   ^~~~
+                         ... For warning description see https://verilator.org/warn/CASEINCOMPLETE?v=5.047
+                         ... Use "/* verilator lint_off CASEINCOMPLETE */" and lint_on around source to disable this message.
+%Warning-INITIALDLY: testbench/UTOSS_risc-v_pr70/tb_utoss_riscv_pr70_verilator.sv:22:11: Non-blocking assignment '<=' in initial/final block
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+   22 |     reset <= 1'b1;
+      |           ^~
+                     ... For warning description see https://verilator.org/warn/INITIALDLY?v=5.047
+                     ... Use "/* verilator lint_off INITIALDLY */" and lint_on around source to disable this message.
+%Warning-INITIALDLY: testbench/UTOSS_risc-v_pr70/tb_utoss_riscv_pr70_verilator.sv:34:11: Non-blocking assignment '<=' in initial/final block
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+   34 |     reset <= 1'b0;
+      |           ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:114:12: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  114 |     Branch <= 1'b0;
+      |            ^~
+                  ... For warning description see https://verilator.org/warn/COMBDLY?v=5.047
+                  ... Use "/* verilator lint_off COMBDLY */" and lint_on around source to disable this message.
+                  *** See https://verilator.org/warn/COMBDLY?v=5.047 before disabling this,
+                  else you may end up with different sim results.
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:115:12: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  115 |     pc_src <= 1'b0;
+      |            ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:116:14: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  116 |     PCUpdate <= 1'b0;
+      |              ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:117:13: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  117 |     IRWrite <= 1'b0;
+      |             ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:118:14: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  118 |     MemWrite <= 1'b0;
+      |              ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:120:12: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  120 |   FSMState <= current_state;
+      |            ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:233:12: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  233 |     AdrSrc <= ADR_SRC__PC;
+      |            ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:234:13: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  234 |     IRWrite <= 1'b1;
+      |             ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:142:13: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  142 |     ALUSrcA <= ALU_SRC_A__OLD_PC;
+      |             ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:143:13: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  143 |     ALUSrcB <= ALU_SRC_B__IMM_EXT;
+      |             ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:144:11: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  144 |     ALUOp <= 2'b00;
+      |           ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:150:13: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  150 |     ALUSrcA <= ALU_SRC_A__ZERO;
+      |             ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:151:13: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  151 |     ALUSrcB <= ALU_SRC_B__IMM_EXT;
+      |             ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:152:11: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  152 |     ALUOp <= 2'b00;
+      |           ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:192:13: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  192 |     ALUSrcA <= ALU_SRC_A__RD1;
+      |             ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:193:13: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  193 |     ALUSrcB <= ALU_SRC_B__RD2;
+      |             ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:194:11: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  194 |     ALUOp <= 2'b01;
+      |           ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:195:15: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  195 |     ResultSrc <= RESULT_SRC__ALU_OUT;
+      |               ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:196:12: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  196 |     Branch <= 1'b1;
+      |            ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:197:16: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  197 |         pc_src <= zero_flag ? PC_SRC__JUMP : PC_SRC__INCREMENT;
+      |                ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:198:18: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  198 |         PCUpdate <= 1'b1;
+      |                  ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:226:15: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  226 |     ResultSrc <= RESULT_SRC__DATA;
+      |               ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:227:14: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  227 |     RegWrite <= 1'b1;
+      |              ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:219:15: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  219 |     ResultSrc <= RESULT_SRC__ALU_OUT;
+      |               ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:220:12: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  220 |     AdrSrc <= ADR_SRC__RESULT;
+      |            ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:211:15: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  211 |     ResultSrc <= RESULT_SRC__ALU_OUT;
+      |               ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:212:12: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  212 |     AdrSrc <= ADR_SRC__RESULT;
+      |            ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:213:14: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  213 |     MemWrite <= 1'b1;
+      |              ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:204:15: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  204 |     ResultSrc <= RESULT_SRC__ALU_OUT;
+      |               ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:205:14: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  205 |     RegWrite <= 1'b1;
+      |              ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:184:13: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  184 |     ALUSrcA <= ALU_SRC_A__RD1;
+      |             ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:185:13: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  185 |     ALUSrcB <= ALU_SRC_B__IMM_EXT;
+      |             ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:186:11: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  186 |     ALUOp <= 2'b00;
+      |           ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:166:13: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  166 |     ALUSrcA <= ALU_SRC_A__RD1;
+      |             ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:167:13: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  167 |     ALUSrcB <= ALU_SRC_B__IMM_EXT;
+      |             ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:168:11: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  168 |     ALUOp <= 2'b11;
+      |           ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:174:13: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  174 |     ALUSrcA <= ALU_SRC_A__OLD_PC;
+      |             ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:175:13: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  175 |     ALUSrcB <= ALU_SRC_B__4;
+      |             ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:176:11: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  176 |     ALUOp <= 2'b00;
+      |           ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:177:15: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  177 |     ResultSrc <= RESULT_SRC__ALU_OUT;
+      |               ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:178:18: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  178 |         PCUpdate <= 1'b1;
+      |                  ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:158:13: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  158 |     ALUSrcA <= ALU_SRC_A__RD1;
+      |             ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:159:13: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  159 |     ALUSrcB <= ALU_SRC_B__RD2;
+      |             ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:160:11: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  160 |     ALUOp <= 2'b10;
+      |           ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:134:13: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  134 |     ALUSrcA <= ALU_SRC_A__OLD_PC;
+      |             ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:135:13: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  135 |     ALUSrcB <= ALU_SRC_B__IMM_EXT;
+      |             ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:136:11: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  136 |     ALUOp <= 2'b00;
+      |           ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:126:12: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  126 |     AdrSrc <= ADR_SRC__PC;
+      |            ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:127:13: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  127 |     IRWrite <= 1'b1;
+      |             ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ControlFSM.sv:128:18: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                       : ... This will be executed as a blocking assignment '='!
+  128 |         PCUpdate <= 1'b1;
+      |                  ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/fetch.sv:26:37: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                 : ... This will be executed as a blocking assignment '='!
+   26 |         PC_SRC__JUMP:       pc_next <= pc_cur + imm_ext;
+      |                                     ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/fetch.sv:25:36: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                 : ... This will be executed as a blocking assignment '='!
+   25 |         PC_SRC__INCREMENT: pc_next <= pc_cur + 32'h4;
+      |                                    ^~
+%Warning-COMBDLY: testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/fetch.sv:29:15: Non-blocking assignment '<=' in combinational logic process
+                                                                                                                                 : ... This will be executed as a blocking assignment '='!
+   29 |       pc_next <= pc_cur;
+      |               ^~
+make: Entering directory 'testbench/UTOSS_risc-v_pr70/obj_dir'
+g++ -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -Os  -c -o _coverage_main.o testbench/UTOSS_risc-v_pr70/../_coverage_main.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -c -o verilated.o /opt/oss-cad-suite/share/verilator/include/verilated.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -c -o verilated_cov.o /opt/oss-cad-suite/share/verilator/include/verilated_cov.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -c -o verilated_timing.o /opt/oss-cad-suite/share/verilator/include/verilated_timing.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -c -o verilated_threads.o /opt/oss-cad-suite/share/verilator/include/verilated_threads.cpp
+python3 /opt/oss-cad-suite/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vhwe_cov_top.cpp Vhwe_cov_top___024root__0.cpp Vhwe_cov_top___024root__Slow.cpp Vhwe_cov_top___024root__0__Slow.cpp Vhwe_cov_top___024unit__Slow.cpp Vhwe_cov_top___024unit__0__Slow.cpp Vhwe_cov_top__Syms__Slow.cpp > Vhwe_cov_top__ALL.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -c -o Vhwe_cov_top__ALL.o Vhwe_cov_top__ALL.cpp
+g++ -Wl,-O2 -Wl,--sort-common -Wl,--as-needed -Wl,-z,relro -Wl,-z,now -Wl,--disable-new-dtags -Wl,--gc-sections -Wl,--allow-shlib-undefined -Wl,-rpath,/home/user/miniforge3/lib -Wl,-rpath-link,/home/user/miniforge3/lib -L/home/user/miniforge3/lib    _coverage_main.o verilated.o verilated_cov.o verilated_timing.o verilated_threads.o Vhwe_cov_top__ALL.a    -pthread -lpthread -latomic   -o simv_vlt
+rm Vhwe_cov_top__ALL.verilator_deplist.tmp
+make: Leaving directory 'testbench/UTOSS_risc-v_pr70/obj_dir'
+- V e r i l a t i o n   R e p o r t: Verilator 5.047 devel rev v5.046-293-ge82bd52fa (mod)
+- Verilator: Built from 0.502 MB sources in 11 modules, into 0.370 MB in 7 C++ files needing 0.000 MB
+- Verilator: Walltime 8.373 s (elab=0.002, cvt=0.018, bld=8.343); cpu 0.030 s on 1 threads; allocated 22.910 MB

testbench/UTOSS_risc-v_pr70/verilator_fixed_coverage.info

@@ -0,0 +1,2943 @@
+TN:verilator_coverage
+SF:testbench/UTOSS_risc-v_pr70/snapshot_scratch/src/ALU_ALUdecoder/ALU.v
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+BRDA:3,0,48,0
+BRDA:3,0,49,0
+BRDA:3,0,50,0
+BRDA:3,0,51,0
+BRDA:3,0,52,1
+BRDA:3,0,53,0
+BRDA:3,0,54,0
+BRDA:3,0,55,0
+BRDA:3,0,56,0
+BRDA:3,0,57,0
+BRDA:3,0,58,0
+BRDA:3,0,59,0
+BRDA:3,0,60,0
+BRDA:3,0,61,0
+BRDA:3,0,62,0
+BRDA:3,0,63,0
+DA:4,0
+BRDA:4,0,0,0
+BRDA:4,0,1,0
+DA:5,9
+BRDA:5,0,0,9
+BRDA:5,0,1,8
+DA:6,1
+BRDA:6,0,0,1
+BRDA:6,0,1,1
+BRDA:6,0,2,1
+BRDA:6,0,3,1
+BRDA:6,0,4,0
+BRDA:6,0,5,0
+BRDA:6,0,6,0
+BRDA:6,0,7,0
+BRDA:6,0,8,0
+BRDA:6,0,9,0
+BRDA:6,0,10,0
+BRDA:6,0,11,0
+BRDA:6,0,12,0
+BRDA:6,0,13,0
+BRDA:6,0,14,0
+BRDA:6,0,15,0
+BRDA:6,0,16,0
+BRDA:6,0,17,0
+BRDA:6,0,18,0
+BRDA:6,0,19,0
+BRDA:6,0,20,0
+BRDA:6,0,21,0
+BRDA:6,0,22,1
+BRDA:6,0,23,1
+BRDA:6,0,24,0
+BRDA:6,0,25,0
+BRDA:6,0,26,0
+BRDA:6,0,27,0
+BRDA:6,0,28,0
+BRDA:6,0,29,0
+BRDA:6,0,30,0
+BRDA:6,0,31,0
+BRDA:6,0,32,0
+BRDA:6,0,33,0
+BRDA:6,0,34,0
+BRDA:6,0,35,0
+BRDA:6,0,36,0
+BRDA:6,0,37,0
+BRDA:6,0,38,0
+BRDA:6,0,39,0
+BRDA:6,0,40,0
+BRDA:6,0,41,0
+BRDA:6,0,42,0
+BRDA:6,0,43,0
+BRDA:6,0,44,0
+BRDA:6,0,45,0
+BRDA:6,0,46,0
+BRDA:6,0,47,0
+BRDA:6,0,48,0
+BRDA:6,0,49,0
+BRDA:6,0,50,0
+BRDA:6,0,51,0
+BRDA:6,0,52,1
+BRDA:6,0,53,1
+BRDA:6,0,54,1
+BRDA:6,0,55,1
+BRDA:6,0,56,1
+BRDA:6,0,57,1
+BRDA:6,0,58,0
+BRDA:6,0,59,0
+BRDA:6,0,60,0
+BRDA:6,0,61,0
+BRDA:6,0,62,0
+BRDA:6,0,63,0
+DA:11,1
+DA:12,1
+DA:14,1
+BRDA:14,0,0,0
+BRDA:14,0,1,1
+DA:15,0
+DA:16,0
+DA:17,0
+DA:23,9
+DA:24,9
+BRDA:24,0,0,9
+BRDA:24,0,1,0
+DA:25,0
+BRF:200
+BRH:0
+end_of_record
+SF:testbench/UTOSS_risc-v_pr70/tb_utoss_riscv_pr70_verilator.sv
+DA:6,9
+BRDA:6,0,0,9
+BRDA:6,0,1,8
+DA:7,1
+BRDA:7,0,0,1
+BRDA:7,0,1,1
+DA:16,0
+DA:17,0
+DA:18,17
+BRDA:18,0,0,0
+BRDA:18,0,1,0
+BRDA:18,0,2,17
+DA:83,1
+BRDA:83,0,0,1
+BRDA:83,0,1,0
+BRDA:83,0,2,1
+BRDA:83,0,3,0
+BRDA:83,0,4,0
+BRF:12
+BRH:1
+end_of_record

testbench/YosysHQ_picorv32_pr229/open_tool_p2p_buggy.log

@@ -0,0 +1,283 @@
+INFO: open-tool P2P fallback (buggy)
+
+### native_sim:.
+'make' 'test_ez'
+iverilog -o testbench_ez.vvp -DCOMPRESSED_ISA testbench_ez.v picorv32.v
+chmod -x testbench_ez.vvp
+vvp -N testbench_ez.vvp
+ifetch 0x00000000: 0x3fc00093
+ifetch 0x00000004: 0x0000a023
+ifetch 0x00000008: 0x0000a103
+write  0x000003fc: 0x00000000 (wstrb=1111)
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x00000000
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x00000001 (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x00000001
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x00000002 (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x00000002
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x00000003 (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x00000003
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x00000004 (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x00000004
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x00000005 (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x00000005
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x00000006 (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x00000006
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x00000007 (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x00000007
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x00000008 (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x00000008
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x00000009 (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x00000009
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x0000000a (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x0000000a
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x0000000b (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x0000000b
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x0000000c (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x0000000c
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x0000000d (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x0000000d
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x0000000e (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x0000000e
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x0000000f (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x0000000f
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x00000010 (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x00000010
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x00000011 (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x00000011
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x00000012 (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x00000012
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x00000013 (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x00000013
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x00000014 (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x00000014
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x00000015 (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x00000015
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x00000016 (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x00000016
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x00000017 (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x00000017
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x00000018 (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x00000018
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x00000019 (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x00000019
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x0000001a (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x0000001a
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x0000001b (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x0000001b
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x0000001c (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x0000001c
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x0000001d (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x0000001d
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x0000001e (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x0000001e
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x0000001f (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x0000001f
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x00000020 (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x00000020
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x00000021 (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x00000021
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x00000022 (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x00000022
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x00000023 (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x00000023
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x00000024 (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x00000024
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x00000025 (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x00000025
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x00000026 (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x00000026
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x00000027 (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x00000027
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x00000028 (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x00000028
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x00000029 (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x00000029
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x0000002a (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x0000002a
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x0000002b (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x0000002b
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x0000002c (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x0000002c
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+testbench_ez.v:25: $finish called at 11000000 (1ps)
+
+rc=0
+PASS: native simulation P2P passed in buggy phase: .: 'make' 'test_ez'

testbench/YosysHQ_picorv32_pr229/open_tool_p2p_fixed.log

@@ -0,0 +1,283 @@
+INFO: open-tool P2P fallback (fixed)
+
+### native_sim:.
+'make' 'test_ez'
+iverilog -o testbench_ez.vvp -DCOMPRESSED_ISA testbench_ez.v picorv32.v
+chmod -x testbench_ez.vvp
+vvp -N testbench_ez.vvp
+ifetch 0x00000000: 0x3fc00093
+ifetch 0x00000004: 0x0000a023
+ifetch 0x00000008: 0x0000a103
+write  0x000003fc: 0x00000000 (wstrb=1111)
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x00000000
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x00000001 (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x00000001
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x00000002 (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x00000002
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x00000003 (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x00000003
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x00000004 (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x00000004
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x00000005 (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x00000005
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x00000006 (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x00000006
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x00000007 (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x00000007
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x00000008 (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x00000008
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x00000009 (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x00000009
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x0000000a (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x0000000a
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x0000000b (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x0000000b
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x0000000c (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x0000000c
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x0000000d (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x0000000d
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x0000000e (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x0000000e
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x0000000f (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x0000000f
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x00000010 (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x00000010
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x00000011 (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x00000011
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x00000012 (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x00000012
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x00000013 (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x00000013
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x00000014 (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x00000014
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x00000015 (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x00000015
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x00000016 (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x00000016
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x00000017 (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x00000017
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x00000018 (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x00000018
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x00000019 (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x00000019
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x0000001a (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x0000001a
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x0000001b (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x0000001b
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x0000001c (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x0000001c
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x0000001d (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x0000001d
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x0000001e (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x0000001e
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x0000001f (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x0000001f
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x00000020 (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x00000020
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x00000021 (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x00000021
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x00000022 (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x00000022
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x00000023 (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x00000023
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x00000024 (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x00000024
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x00000025 (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x00000025
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x00000026 (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x00000026
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x00000027 (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x00000027
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x00000028 (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x00000028
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x00000029 (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x00000029
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x0000002a (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x0000002a
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x0000002b (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x0000002b
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+write  0x000003fc: 0x0000002c (wstrb=1111)
+ifetch 0x00000008: 0x0000a103
+ifetch 0x0000000c: 0x00110113
+read   0x000003fc: 0x0000002c
+ifetch 0x00000010: 0x0020a023
+ifetch 0x00000014: 0xff5ff06f
+testbench_ez.v:25: $finish called at 11000000 (1ps)
+
+rc=0
+PASS: native simulation P2P passed in fixed phase: .: 'make' 'test_ez'

testbench/YosysHQ_picorv32_pr229/repo_native_buggy.log

@@ -0,0 +1 @@
+PASS: repo native simulation P2P passed in buggy phase

testbench/YosysHQ_picorv32_pr229/repo_native_fixed.log

@@ -0,0 +1 @@
+PASS: repo native simulation P2P passed in fixed phase

testbench/YosysHQ_picorv32_pr229/run_once.sh

@@ -0,0 +1,4 @@
+#!/bin/bash
+set -u
+HERE="$(cd "$(dirname "${BASH_SOURCE[0]:-$0}")" && pwd)"
+exec python3 "$HERE/../_run_once_from_run_verilator.py" "$HERE/run_verilator.sh"

testbench/YosysHQ_picorv32_pr229/run_verilator.sh

@@ -0,0 +1,30 @@
+#!/bin/bash
+set -u
+HERE="$(cd "$(dirname "${BASH_SOURCE[0]:-$0}")" && pwd)"; cd "$HERE"
+. "$HERE/../_testcase_minimum.sh"
+. "$HERE/../_repo_native_p2p_smoke.sh"
+export HWE_AUTO_COVERAGE=1
+NAME=YosysHQ_picorv32_pr229
+REPO_ROOT="$(cd "$HERE/../.." && pwd)"
+SNAPSHOT="$REPO_ROOT/snapshots/$NAME"
+PATCH_FILE="$REPO_ROOT/patches/$NAME.patch"
+SCRATCH="$HERE/snapshot_scratch"
+TARGET="picorv32.v"
+run_phase() {
+  local tag="$1"
+  rm -rf obj_dir verilator_${tag}_build.log verilator_${tag}.log
+  run_repo_native_p2p_smoke "$tag" || return $?
+  verilator --binary --timing --Wno-fatal --Wno-WIDTH --Wno-UNOPTFLAT --Wno-UNUSEDSIGNAL --Wno-UNUSEDPARAM --Wno-LATCH --Wno-STMTDLY --Wno-PINMISSING --Wno-PINCONNECTEMPTY --Wno-DECLFILENAME --Wno-CASEINCOMPLETE --Wno-MULTIDRIVEN --Wno-CASEX --Wno-IMPLICIT --Wno-SELRANGE --timescale 1ns/1ps "$SCRATCH/$TARGET" "$HERE/tb_picorv32_fence_verilator.sv" --top-module tb_picorv32_fence_verilator -o simv_vlt 2>&1 | tee verilator_${tag}_build.log >/dev/null
+  [ ! -x obj_dir/simv_vlt ] && return 2
+  timeout 30 ./obj_dir/simv_vlt 2>&1 | tee verilator_${tag}.log >/dev/null
+  grep -qE "(^|[^A-Za-z])PASS:" verilator_${tag}.log && ! grep -qE "(^|[^A-Za-z])FAIL:" verilator_${tag}.log && return 0
+  return 1
+}
+rm -rf "$SCRATCH"; cp -r "$SNAPSHOT" "$SCRATCH"; chmod -R u+w "$SCRATCH"
+echo BUGGY; (cd "$SCRATCH" && patch -p1 -R -f --no-backup-if-mismatch < "$PATCH_FILE" >/dev/null 2>&1) || true
+run_phase buggy; rc_buggy=$?
+rm -rf "$SCRATCH"; cp -r "$SNAPSHOT" "$SCRATCH"; chmod -R u+w "$SCRATCH"
+echo FIXED; (cd "$SCRATCH" && patch -p1 -f --no-backup-if-mismatch < "$PATCH_FILE" >/dev/null 2>&1) || true
+run_phase fixed; rc_fixed=$?
+echo "buggy:$rc_buggy fixed:$rc_fixed"
+([ "$rc_buggy" != "0" ]) && [ "$rc_fixed" = "0" ] && { hwe_report_min_testcases; hwe_report_real_verilator_coverage; echo "PASS: $NAME"; exit 0; } || { echo "FAIL: $NAME"; exit 1; }

testbench/YosysHQ_picorv32_pr229/tb_picorv32_fence_verilator.sv

@@ -0,0 +1,104 @@
+// pr229: picorv32 gains an `instr_fence` decode. Pre-patch the signal does not
+// exist; any hierarchical reference to dut.instr_fence makes elaboration fail.
+// Post-patch the signal is present. The TB also drives a fence opcode through
+// the instruction fetch path to confirm the decoder asserts instr_fence.
+`timescale 1ns/1ps
+module tb_picorv32_fence_verilator;
+  reg clk = 0;
+  reg resetn = 0;
+  wire trap;
+
+  wire mem_valid;
+  wire mem_instr;
+  reg  mem_ready = 0;
+  wire [31:0] mem_addr;
+  wire [31:0] mem_wdata;
+  wire [ 3:0] mem_wstrb;
+  reg  [31:0] mem_rdata = 0;
+
+  wire mem_la_read, mem_la_write;
+  wire [31:0] mem_la_addr;
+  wire [31:0] mem_la_wdata;
+  wire [ 3:0] mem_la_wstrb;
+
+  wire pcpi_valid;
+  wire [31:0] pcpi_insn;
+  wire [31:0] pcpi_rs1, pcpi_rs2;
+  reg  pcpi_wr = 0;
+  reg  [31:0] pcpi_rd = 0;
+  reg  pcpi_wait = 0;
+  reg  pcpi_ready = 0;
+
+  reg  [31:0] irq = 0;
+  wire [31:0] eoi;
+
+  wire trace_valid;
+  wire [35:0] trace_data;
+
+  always #5 clk = ~clk;
+
+  picorv32 #(
+    .ENABLE_COUNTERS(0),
+    .ENABLE_COUNTERS64(0),
+    .ENABLE_IRQ(0),
+    .ENABLE_PCPI(0)
+  ) dut (
+    .clk(clk), .resetn(resetn),
+    .trap(trap),
+    .mem_valid(mem_valid), .mem_instr(mem_instr), .mem_ready(mem_ready),
+    .mem_addr(mem_addr), .mem_wdata(mem_wdata), .mem_wstrb(mem_wstrb),
+    .mem_rdata(mem_rdata),
+    .mem_la_read(mem_la_read), .mem_la_write(mem_la_write),
+    .mem_la_addr(mem_la_addr), .mem_la_wdata(mem_la_wdata),
+    .mem_la_wstrb(mem_la_wstrb),
+    .pcpi_valid(pcpi_valid), .pcpi_insn(pcpi_insn),
+    .pcpi_rs1(pcpi_rs1), .pcpi_rs2(pcpi_rs2),
+    .pcpi_wr(pcpi_wr), .pcpi_rd(pcpi_rd),
+    .pcpi_wait(pcpi_wait), .pcpi_ready(pcpi_ready),
+    .irq(irq), .eoi(eoi),
+    .trace_valid(trace_valid), .trace_data(trace_data)
+  );
+
+  // Serve instruction fetches with a FENCE opcode (opcode = 7'b0001111, funct3 = 0).
+  // Packed into 32 bits: funct3=0 at bits [14:12], opcode at bits [6:0].
+  localparam [31:0] FENCE_INSTR = 32'h0000000F;
+  localparam [31:0] ADDI_INSTR  = 32'h00000013;  // nop
+
+  // Simple memory model: serve FENCE once, then NOPs.
+  int fetch_count = 0;
+  always @(posedge clk) begin
+    if (mem_valid && !mem_ready) begin
+      mem_ready <= 1'b1;
+      if (mem_instr) begin
+        mem_rdata <= (fetch_count == 0) ? FENCE_INSTR : ADDI_INSTR;
+        fetch_count <= fetch_count + 1;
+      end else begin
+        mem_rdata <= 32'h0;
+      end
+    end else begin
+      mem_ready <= 1'b0;
+    end
+  end
+
+  int fence_seen = 0;
+  // Observe internal decoded fence flag (requires the signal to exist => fixed).
+  always @(posedge clk) begin
+    if (resetn && dut.instr_fence) fence_seen <= 1;
+  end
+
+  initial begin
+    resetn = 0;
+    repeat(5) @(posedge clk);
+    resetn = 1;
+    // Give the pipeline time to fetch, latch, and decode the FENCE.
+    repeat(40) @(posedge clk);
+
+    if (fence_seen == 1)
+      $display("PASS: picorv32 decoded fence instruction");
+    else
+      $display("FAIL: fence decode not observed (fence_seen=%0d)", fence_seen);
+    $finish;
+  end
+
+  initial begin #10000; $display("FAIL: timeout"); $finish; end
+endmodule

testbench/YosysHQ_picorv32_pr229/verilator_buggy_build.log

@@ -0,0 +1,11 @@
+%Error: testbench/YosysHQ_picorv32_pr229/tb_picorv32_fence_verilator.sv:86:23: Can't find definition of 'instr_fence' in dotted variable/method: 'dut.instr_fence'
+   86 |     if (resetn && dut.instr_fence) fence_seen <= 1;
+      |                       ^~~~~~~~~~~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=5.047 for more assistance.
+%Error: Exiting due to 1 error(s)
+HWE_AUTO_COVERAGE: retrying with --coverage-line
+%Error: testbench/YosysHQ_picorv32_pr229/tb_picorv32_fence_verilator.sv:86:23: Can't find definition of 'instr_fence' in dotted variable/method: 'dut.instr_fence'
+   86 |     if (resetn && dut.instr_fence) fence_seen <= 1;
+      |                       ^~~~~~~~~~~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=5.047 for more assistance.
+%Error: Exiting due to 1 error(s)

testbench/YosysHQ_picorv32_pr229/verilator_fixed.log

@@ -0,0 +1,2 @@
+PASS: picorv32 decoded fence instruction
+- testbench/YosysHQ_picorv32_pr229/tb_picorv32_fence_verilator.sv:100: Verilog $finish

testbench/YosysHQ_picorv32_pr229/verilator_fixed_build.log

@@ -0,0 +1,14 @@
+make: Entering directory 'testbench/YosysHQ_picorv32_pr229/obj_dir'
+g++ -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -Os  -c -o _coverage_main.o testbench/YosysHQ_picorv32_pr229/../_coverage_main.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -c -o verilated.o /opt/oss-cad-suite/share/verilator/include/verilated.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -c -o verilated_cov.o /opt/oss-cad-suite/share/verilator/include/verilated_cov.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -c -o verilated_timing.o /opt/oss-cad-suite/share/verilator/include/verilated_timing.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -c -o verilated_threads.o /opt/oss-cad-suite/share/verilator/include/verilated_threads.cpp
+python3 /opt/oss-cad-suite/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vhwe_cov_top.cpp Vhwe_cov_top___024root__0.cpp Vhwe_cov_top___024root__Slow.cpp Vhwe_cov_top___024root__0__Slow.cpp Vhwe_cov_top__Syms__Slow.cpp > Vhwe_cov_top__ALL.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -c -o Vhwe_cov_top__ALL.o Vhwe_cov_top__ALL.cpp
+g++ -Wl,-O2 -Wl,--sort-common -Wl,--as-needed -Wl,-z,relro -Wl,-z,now -Wl,--disable-new-dtags -Wl,--gc-sections -Wl,--allow-shlib-undefined -Wl,-rpath,/home/user/miniforge3/lib -Wl,-rpath-link,/home/user/miniforge3/lib -L/home/user/miniforge3/lib    _coverage_main.o verilated.o verilated_cov.o verilated_timing.o verilated_threads.o Vhwe_cov_top__ALL.a    -pthread -lpthread -latomic   -o simv_vlt
+rm Vhwe_cov_top__ALL.verilator_deplist.tmp
+make: Leaving directory 'testbench/YosysHQ_picorv32_pr229/obj_dir'
+- V e r i l a t i o n   R e p o r t: Verilator 5.047 devel rev v5.046-293-ge82bd52fa (mod)
+- Verilator: Built from 0.279 MB sources in 10 modules, into 1.030 MB in 5 C++ files needing 0.001 MB
+- Verilator: Walltime 9.778 s (elab=0.009, cvt=0.047, bld=9.702); cpu 0.076 s on 1 threads; allocated 26.441 MB

testbench/jotego_jtcores_pr1202/open_tool_p2p_fixed.log

@@ -0,0 +1,9 @@
+INFO: open-tool P2P fallback (fixed)
+
+### native_sim:modules/jtframe/ver/cen
+'sh' '-c' 'PATH=.:$PATH bash sim.sh'
+LXT info: dumpfile test.lxt opened for output.
+test.v:45: $finish called at 2000000 (1ps)
+
+rc=0
+PASS: native simulation P2P passed in fixed phase: modules/jtframe/ver/cen: 'sh' '-c' 'PATH=.:$PATH bash sim.sh'

testbench/jotego_jtcores_pr1202/repo_native_buggy.log

@@ -0,0 +1 @@
+PASS: repo native simulation P2P passed in buggy phase

testbench/jotego_jtcores_pr1202/repo_native_fixed.log

@@ -0,0 +1 @@
+PASS: repo native simulation P2P passed in fixed phase

testbench/jotego_jtcores_pr1202/run_once.sh

@@ -0,0 +1,4 @@
+#!/bin/bash
+set -u
+HERE="$(cd "$(dirname "${BASH_SOURCE[0]:-$0}")" && pwd)"
+exec python3 "$HERE/../_run_once_from_run_verilator.py" "$HERE/run_verilator.sh"

testbench/jotego_jtcores_pr1202/tb_jtkarnov_obj_xoff_verilator.sv

@@ -0,0 +1,109 @@
+// Driven-signal TB for jotego_jtcores_pr1202 (jtkarnov_obj dr_xpos offset).
+// The fix introduces an intermediate register `xoff = flip ? 24 : 8` and
+// replaces
+//     dr_xpos <= xpos + (flip ? -25 : -7);     // buggy
+// with
+//     dr_xpos <= xpos - xoff;                  // fixed
+// giving a 1-pixel shift in both flip orientations.
+//
+// We force the FSM state registers directly to drop the DUT into the
+// `st == 3` branch with dr_busy low, xpos = 100, flip = 0.  After one
+// clock edge:
+//   Buggy : dr_xpos = 100 + -7  = 93 = 9'h05D
+//   Fixed : dr_xpos = 100 -  8  = 92 = 9'h05C
+// We observe `dut.dr_xpos` hierarchically.
+`timescale 1ns/1ps
+
+module tb_jtkarnov_obj_xoff_verilator;
+  logic         rst = 1, clk = 0;
+  logic         pxl_cen = 1;
+  logic         hs = 0;
+  logic         flip = 0;
+  logic [8:0]   hdump = 0;
+  logic [8:0]   vrender = 0;
+  wire  [11:1]  dma_addr;
+  logic         dma_start = 0;
+  wire          dma_we;
+  wire  [11:1]  ram_addr;
+  logic [15:0]  ram_data = 16'h0;
+  wire  [18:2]  rom_addr;
+  logic [31:0]  rom_data = 32'h0;
+  wire          rom_cs;
+  logic         rom_ok = 1;
+  logic [7:0]   debug_bus = 0;
+  wire  [7:0]   pxl;
+
+  jtkarnov_obj dut (
+    .rst(rst), .clk(clk), .pxl_cen(pxl_cen),
+    .hs(hs), .flip(flip),
+    .hdump(hdump), .vrender(vrender),
+    .dma_addr(dma_addr), .dma_start(dma_start), .dma_we(dma_we),
+    .ram_addr(ram_addr), .ram_data(ram_data),
+    .rom_addr(rom_addr), .rom_data(rom_data), .rom_cs(rom_cs), .rom_ok(rom_ok),
+    .debug_bus(debug_bus), .pxl(pxl)
+  );
+
+  always #5 clk = ~clk;
+
+  initial begin
+    rst = 1;
+    flip = 0;
+    repeat (4) @(posedge clk);
+    rst = 0;
+    repeat (2) @(posedge clk);
+
+    // Force the FSM into st==3 with xpos=100, dr_busy=0, done=0, cen=1
+    // on the next clock edge the dr_xpos reg captures xpos + offset.
+    @(negedge clk);
+    force dut.st      = 2'd3;
+    force dut.xpos    = 9'd100;
+    force dut.done    = 1'b0;
+    force dut.cen     = 1'b1;
+    force dut.u_objdraw.busy = 1'b0;   // drive dr_busy input
+    force dut.obj_cnt = 9'd10;         // ensure adv path does not clobber
+    force dut.adv     = 1'b0;
+    @(posedge clk);
+    @(negedge clk);
+
+    $display("INFO: flip=%0b xpos=%0d dr_xpos=%0d (0x%03h)",
+             flip, dut.xpos, dut.dr_xpos, dut.dr_xpos);
+
+    if (dut.dr_xpos === 9'd92)
+      $display("PASS: dr_xpos uses xoff=8 -> xpos-8 (fix verified).");
+    else if (dut.dr_xpos === 9'd93)
+      $display("FAIL: dr_xpos = xpos-7 (buggy offset).");
+    else
+      $display("FAIL: unexpected dr_xpos=%0d", dut.dr_xpos);
+
+    // ---- Coverage stimulus (no assertions): exercise the remaining
+    // directions of the flip/pxl_cen conditionals in jtkarnov_obj.v:
+    //   L64  xoff = flip ? 9'd24 : 9'd8        (flip TRUE side)
+    //   L71  if(flip) hdf[7] <= ...            (flip TRUE side)
+    //   L69  always @(posedge clk) if(pxl_cen) (pxl_cen FALSE side)
+    release dut.st;
+    release dut.xpos;
+    release dut.done;
+    release dut.cen;
+    release dut.u_objdraw.busy;
+    release dut.obj_cnt;
+    release dut.adv;
+
+    flip = 1'b1;                  // flip TRUE -> L64/L71 true sides
+    pxl_cen = 1'b1;
+    hdump = 9'h1A5;
+    repeat (4) @(posedge clk);    // clock the if(flip) hdf update
+    pxl_cen = 1'b0;               // pxl_cen FALSE -> L69 body skipped
+    repeat (4) @(posedge clk);
+    pxl_cen = 1'b1;
+    flip = 1'b0;
+    repeat (2) @(posedge clk);
+
+    $finish;
+  end
+
+  initial begin
+    #10000;
+    $display("FAIL: timeout");
+    $finish;
+  end
+endmodule

testbench/jotego_jtcores_pr1202/verilator_buggy.log

@@ -0,0 +1,3 @@
+INFO: flip=0 xpos=100 dr_xpos=93 (0x05d)
+FAIL: dr_xpos = xpos-7 (buggy offset).
+- testbench/jotego_jtcores_pr1202/tb_jtkarnov_obj_xoff_verilator.sv:101: Verilog $finish

testbench/jotego_jtcores_pr1202/verilator_fixed.log

@@ -0,0 +1,3 @@
+INFO: flip=0 xpos=100 dr_xpos=92 (0x05c)
+PASS: dr_xpos uses xoff=8 -> xpos-8 (fix verified).
+- testbench/jotego_jtcores_pr1202/tb_jtkarnov_obj_xoff_verilator.sv:101: Verilog $finish

testbench/jotego_jtcores_pr1202/verilator_fixed_build.log

@@ -0,0 +1,14 @@
+make: Entering directory 'testbench/jotego_jtcores_pr1202/obj_dir'
+g++ -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -Os  -c -o _coverage_main.o testbench/jotego_jtcores_pr1202/../_coverage_main.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -c -o verilated.o /opt/oss-cad-suite/share/verilator/include/verilated.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -c -o verilated_cov.o /opt/oss-cad-suite/share/verilator/include/verilated_cov.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -c -o verilated_timing.o /opt/oss-cad-suite/share/verilator/include/verilated_timing.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -c -o verilated_threads.o /opt/oss-cad-suite/share/verilator/include/verilated_threads.cpp
+python3 /opt/oss-cad-suite/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vhwe_cov_top.cpp Vhwe_cov_top___024root__0.cpp Vhwe_cov_top___024root__Slow.cpp Vhwe_cov_top___024root__0__Slow.cpp Vhwe_cov_top__Syms__Slow.cpp > Vhwe_cov_top__ALL.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -c -o Vhwe_cov_top__ALL.o Vhwe_cov_top__ALL.cpp
+g++ -Wl,-O2 -Wl,--sort-common -Wl,--as-needed -Wl,-z,relro -Wl,-z,now -Wl,--disable-new-dtags -Wl,--gc-sections -Wl,--allow-shlib-undefined -Wl,-rpath,/home/user/miniforge3/lib -Wl,-rpath-link,/home/user/miniforge3/lib -L/home/user/miniforge3/lib    _coverage_main.o verilated.o verilated_cov.o verilated_timing.o verilated_threads.o Vhwe_cov_top__ALL.a    -pthread -lpthread -latomic   -o simv_vlt
+rm Vhwe_cov_top__ALL.verilator_deplist.tmp
+make: Leaving directory 'testbench/jotego_jtcores_pr1202/obj_dir'
+- V e r i l a t i o n   R e p o r t: Verilator 5.047 devel rev v5.046-293-ge82bd52fa (mod)
+- Verilator: Built from 0.119 MB sources in 11 modules, into 0.524 MB in 5 C++ files needing 0.001 MB
+- Verilator: Walltime 8.506 s (elab=0.004, cvt=0.022, bld=8.467); cpu 0.040 s on 1 threads; allocated 23.836 MB

testbench/jotego_jtcores_pr1202/verilator_fixed_coverage.info

@@ -0,0 +1,2968 @@
+TN:verilator_coverage
+SF:testbench/jotego_jtcores_pr1202/snapshot_scratch/cores/karnov/hdl/jtkarnov_obj.v
+DA:20,1
+BRDA:20,0,0,1
+BRDA:20,0,1,1
+DA:21,17
+BRDA:21,0,0,17
+BRDA:21,0,1,16
+DA:22,2
+BRDA:22,0,0,2
+BRDA:22,0,1,1
+DA:24,0
+BRDA:24,0,0,0
+BRDA:24,0,1,0
+DA:25,1
+BRDA:25,0,0,1
+BRDA:25,0,1,1
+DA:26,1
+BRDA:26,0,0,1
+BRDA:26,0,1,0
+BRDA:26,0,2,0
+BRDA:26,0,3,0
+BRDA:26,0,4,1
+BRDA:26,0,5,0
+BRDA:26,0,6,0
+BRDA:26,0,7,0
+BRDA:26,0,8,0
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+BRDA:26,0,10,1
+BRDA:26,0,11,0
+BRDA:26,0,12,0
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+BRDA:26,0,14,1
+BRDA:26,0,15,0
+BRDA:26,0,16,1
+BRDA:26,0,17,0
+DA:27,0
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+DA:30,0
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+DA:32,0
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+DA:34,4
+BRDA:34,0,0,0
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+BRDA:34,0,2,0
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+BRDA:34,0,4,1
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+BRDA:34,0,6,1
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+DA:35,0
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+BRDA:35,0,29,0
+BRDA:35,0,30,0
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+DA:37,1
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+BRDA:29,0,12,0
+BRDA:29,0,13,0
+BRDA:29,0,14,0
+BRDA:29,0,15,0
+BRDA:29,0,16,0
+BRDA:29,0,17,0
+BRDA:29,0,18,1
+BRDA:29,0,19,0
+BRDA:29,0,20,0
+BRDA:29,0,21,0
+BRDA:29,0,22,0
+BRDA:29,0,23,0
+BRDA:29,0,24,0
+BRDA:29,0,25,0
+BRDA:29,0,26,1
+BRDA:29,0,27,0
+BRDA:29,0,28,0
+BRDA:29,0,29,0
+BRDA:29,0,30,0
+BRDA:29,0,31,0
+BRDA:29,0,32,0
+BRDA:29,0,33,0
+DA:30,1
+BRDA:30,0,0,0
+BRDA:30,0,1,0
+BRDA:30,0,2,0
+BRDA:30,0,3,0
+BRDA:30,0,4,0
+BRDA:30,0,5,0
+BRDA:30,0,6,0
+BRDA:30,0,7,0
+BRDA:30,0,8,0
+BRDA:30,0,9,0
+BRDA:30,0,10,0
+BRDA:30,0,11,0
+BRDA:30,0,12,0
+BRDA:30,0,13,0
+BRDA:30,0,14,0
+BRDA:30,0,15,0
+BRDA:30,0,16,0
+BRDA:30,0,17,0
+BRDA:30,0,18,0
+BRDA:30,0,19,0
+BRDA:30,0,20,0
+BRDA:30,0,21,0
+BRDA:30,0,22,0
+BRDA:30,0,23,0
+BRDA:30,0,24,0
+BRDA:30,0,25,0
+BRDA:30,0,26,0
+BRDA:30,0,27,0
+BRDA:30,0,28,0
+BRDA:30,0,29,0
+BRDA:30,0,30,0
+BRDA:30,0,31,0
+BRDA:30,0,32,0
+BRDA:30,0,33,0
+BRDA:30,0,34,0
+BRDA:30,0,35,0
+BRDA:30,0,36,0
+BRDA:30,0,37,0
+BRDA:30,0,38,0
+BRDA:30,0,39,0
+BRDA:30,0,40,0
+BRDA:30,0,41,0
+BRDA:30,0,42,0
+BRDA:30,0,43,0
+BRDA:30,0,44,0
+BRDA:30,0,45,0
+BRDA:30,0,46,0
+BRDA:30,0,47,0
+BRDA:30,0,48,0
+BRDA:30,0,49,0
+BRDA:30,0,50,0
+BRDA:30,0,51,0
+BRDA:30,0,52,0
+BRDA:30,0,53,0
+BRDA:30,0,54,0
+BRDA:30,0,55,0
+BRDA:30,0,56,0
+BRDA:30,0,57,0
+BRDA:30,0,58,0
+BRDA:30,0,59,0
+BRDA:30,0,60,0
+BRDA:30,0,61,0
+BRDA:30,0,62,0
+BRDA:30,0,63,0
+BRDA:30,0,64,1
+DA:31,1
+BRDA:31,0,0,1
+BRDA:31,0,1,0
+DA:32,1
+BRDA:32,0,0,1
+BRDA:32,0,1,0
+BRDA:32,0,2,1
+DA:33,1
+BRDA:33,0,0,0
+BRDA:33,0,1,0
+BRDA:33,0,2,0
+BRDA:33,0,3,0
+BRDA:33,0,4,0
+BRDA:33,0,5,0
+BRDA:33,0,6,0
+BRDA:33,0,7,0
+BRDA:33,0,8,0
+BRDA:33,0,9,0
+BRDA:33,0,10,0
+BRDA:33,0,11,0
+BRDA:33,0,12,0
+BRDA:33,0,13,0
+BRDA:33,0,14,0
+BRDA:33,0,15,0
+BRDA:33,0,16,1
+DA:34,0
+BRDA:34,0,0,0
+BRDA:34,0,1,0
+BRDA:34,0,2,0
+BRDA:34,0,3,0
+BRDA:34,0,4,0
+BRDA:34,0,5,0
+BRDA:34,0,6,0
+BRDA:34,0,7,0
+BRDA:34,0,8,0
+BRDA:34,0,9,0
+BRDA:34,0,10,0
+BRDA:34,0,11,0
+BRDA:34,0,12,0
+BRDA:34,0,13,0
+BRDA:34,0,14,0
+BRDA:34,0,15,0
+DA:46,33
+BRDA:46,0,0,16
+BRDA:46,0,1,17
+BRDA:46,0,2,33
+DA:48,1
+DA:49,1
+DA:50,1
+DA:51,4
+BRDA:51,0,0,1
+BRDA:51,0,1,4
+DA:52,1
+DA:53,2
+BRDA:53,0,0,1
+BRDA:53,0,1,2
+DA:57,1
+DA:58,1
+DA:59,1
+DA:60,1
+DA:61,1
+DA:62,1
+DA:63,1
+DA:64,1
+DA:65,1
+DA:66,1
+DA:68,1
+DA:69,1
+DA:71,1
+DA:72,1
+DA:73,0
+BRDA:73,0,0,0
+BRDA:73,0,1,0
+DA:74,0
+DA:76,0
+DA:83,1
+DA:84,1
+DA:85,1
+DA:86,1
+DA:87,1
+DA:88,1
+DA:89,1
+DA:91,1
+DA:92,1
+DA:93,1
+DA:94,4
+BRDA:94,0,0,1
+BRDA:94,0,1,4
+DA:95,1
+DA:96,4
+BRDA:96,0,0,1
+BRDA:96,0,1,4
+DA:97,1
+DA:98,1
+DA:99,2
+BRDA:99,0,0,1
+BRDA:99,0,1,2
+DA:101,1
+DA:104,0
+DA:105,0
+DA:106,0
+DA:107,0
+BRF:287
+BRH:5
+end_of_record

testbench/jotego_jtcores_pr654/open_tool_p2p_fixed.log

@@ -0,0 +1,217 @@
+INFO: open-tool P2P fallback (fixed)
+INFO: native simulation P2P not applicable for this case
+
+### filelist_surelog:cores/tora/ver/adpcm/gather.f
+'surelog' '-sv' '-parse' '-nocomp' '-Itestbench/jotego_jtcores_pr654/snapshot_scratch' '-Itestbench/jotego_jtcores_pr654/snapshot_scratch/cores/toki/hdl' '-Itestbench/jotego_jtcores_pr654/snapshot_scratch/cores/toki/ver/ram2gfx' '-f' 'testbench/jotego_jtcores_pr654/snapshot_scratch/cores/tora/ver/adpcm/gather.f' '-odir' 'testbench/jotego_jtcores_pr654/open_tool_fixed_fl'
+[INF:CM0023] Creating log file "testbench/jotego_jtcores_pr654/open_tool_fixed_fl/slpp_all/surelog.log".
+
+[FTL:CM0008] Verilog File "./modules/jtframe/hdl/cpu/jtframe_z80.v" does not exist.
+
+[FTL:CM0008] Verilog File "./modules/jtframe/hdl/jtframe_z80wait.v" does not exist.
+
+[FTL:CM0008] Verilog File "./modules/jtframe/hdl/ram/jtframe_ram.v" does not exist.
+
+[FTL:CM0008] Verilog File "./modules/jtgng_cen.v" does not exist.
+
+[FTL:CM0008] Verilog File "./modules/jtgng_cenp384.v" does not exist.
+
+[FTL:CM0008] Verilog File "./modules/jtgng_cen3p57.v" does not exist.
+
+[FTL:CM0008] Verilog File "./modules/jtgng_sound.v" does not exist.
+
+[FTL:CM0008] Verilog File "./modules/jtgng_obj32.v" does not exist.
+
+[FTL:CM0008] Verilog File "./modules/jt12/jt49/hdl/filter/jt49_dcrm2.v" does not exist.
+
+[FTL:CM0008] Verilog File "./modules/jt12/hdl/mixer/jt12_mixer.v" does not exist.
+
+[FTL:CM0008] Verilog File "testbench/hdl/jttora_adpcm.v" does not exist.
+
+[WRN:CM0005] Include path "./modules/jtframe/hdl/cpu" does not exist.
+
+[WRN:CM0005] Include path "./modules/jtframe/hdl" does not exist.
+
+[WRN:CM0005] Include path "./modules/jtframe/hdl/ram" does not exist.
+
+[WRN:CM0005] Include path "./modules" does not exist.
+
+[WRN:CM0005] Include path "./modules/jt12/jt49/hdl/filter" does not exist.
+
+[WRN:CM0005] Include path "./modules/jt12/hdl/mixer" does not exist.
+
+[WRN:CM0005] Include path "testbench/hdl" does not exist.
+
+[  FATAL] : 11
+[ SYNTAX] : 0
+[  ERROR] : 0
+[WARNING] : 7
+[   NOTE] : 0
+
+rc=1
+
+### filelist_verilator:cores/tora/ver/adpcm/gather.f
+'verilator' '--lint-only' '--sv' '--Wno-fatal' '--Wno-DECLFILENAME' '--Wno-MULTITOP' '--Wno-UNUSEDSIGNAL' '--Wno-UNUSEDPARAM' '--Wno-WIDTH' '-Itestbench/jotego_jtcores_pr654/snapshot_scratch' '-Itestbench/jotego_jtcores_pr654/snapshot_scratch/cores/toki/hdl' '-Itestbench/jotego_jtcores_pr654/snapshot_scratch/cores/toki/ver/ram2gfx' '-f' 'testbench/jotego_jtcores_pr654/snapshot_scratch/cores/tora/ver/adpcm/gather.f'
+%Error: Cannot find file containing module: '../../../modules/jtframe/hdl/jtframe_z80wait.v'
+        ... See the manual at https://verilator.org/verilator_doc.html?v=5.047 for more assistance.
+        ... Looked in:
+             testbench/jotego_jtcores_pr654/snapshot_scratch/../../../modules/jtframe/hdl/jtframe_z80wait.v
+             testbench/jotego_jtcores_pr654/snapshot_scratch/../../../modules/jtframe/hdl/jtframe_z80wait.v.v
+             testbench/jotego_jtcores_pr654/snapshot_scratch/../../../modules/jtframe/hdl/jtframe_z80wait.v.sv
+             testbench/jotego_jtcores_pr654/snapshot_scratch/cores/toki/hdl/../../../modules/jtframe/hdl/jtframe_z80wait.v
+             testbench/jotego_jtcores_pr654/snapshot_scratch/cores/toki/hdl/../../../modules/jtframe/hdl/jtframe_z80wait.v.v
+             testbench/jotego_jtcores_pr654/snapshot_scratch/cores/toki/hdl/../../../modules/jtframe/hdl/jtframe_z80wait.v.sv
+             testbench/jotego_jtcores_pr654/snapshot_scratch/cores/toki/ver/ram2gfx/../../../modules/jtframe/hdl/jtframe_z80wait.v
+             testbench/jotego_jtcores_pr654/snapshot_scratch/cores/toki/ver/ram2gfx/../../../modules/jtframe/hdl/jtframe_z80wait.v.v
+             testbench/jotego_jtcores_pr654/snapshot_scratch/cores/toki/ver/ram2gfx/../../../modules/jtframe/hdl/jtframe_z80wait.v.sv
+             ../../../modules/jtframe/hdl/jtframe_z80wait.v
+             ../../../modules/jtframe/hdl/jtframe_z80wait.v.v
+             ../../../modules/jtframe/hdl/jtframe_z80wait.v.sv
+             obj_dir/../../../modules/jtframe/hdl/jtframe_z80wait.v
+             obj_dir/../../../modules/jtframe/hdl/jtframe_z80wait.v.v
+             obj_dir/../../../modules/jtframe/hdl/jtframe_z80wait.v.sv
+        ... With current working directory 'testbench/jotego_jtcores_pr654/snapshot_scratch'
+%Error: Cannot find file containing module: '../../../modules/jtgng_cen.v'
+%Error: Cannot find file containing module: '../../../modules/jtgng_cenp384.v'
+%Error: Cannot find file containing module: '../../../modules/jtgng_cen3p57.v'
+%Error: Cannot find file containing module: '../../../modules/jtgng_sound.v'
+%Error: Cannot find file containing module: '../../../modules/jtgng_obj32.v'
+%Error: Cannot find file containing module: '../../../modules/jt12/jt49/hdl/filter/jt49_dcrm2.v'
+%Error: Cannot find file containing module: '../../../modules/jt12/hdl/mixer/jt12_mixer.v'
+%Error: Cannot find file containing module: '../../hdl/jttora_adpcm.v'
+%Error: Exiting due to 9 error(s)
+
+rc=1
+
+### filelist_surelog:cores/tora/ver/sound/gather.f
+'surelog' '-sv' '-parse' '-nocomp' '-Itestbench/jotego_jtcores_pr654/snapshot_scratch' '-Itestbench/jotego_jtcores_pr654/snapshot_scratch/cores/toki/hdl' '-Itestbench/jotego_jtcores_pr654/snapshot_scratch/cores/toki/ver/ram2gfx' '-f' 'testbench/jotego_jtcores_pr654/snapshot_scratch/cores/tora/ver/sound/gather.f' '-odir' 'testbench/jotego_jtcores_pr654/open_tool_fixed_fl'
+[INF:CM0023] Creating log file "testbench/jotego_jtcores_pr654/open_tool_fixed_fl/slpp_all/surelog.log".
+
+[FTL:CM0008] Verilog File "./modules/jtframe/hdl/cpu/jtframe_z80.v" does not exist.
+
+[FTL:CM0008] Verilog File "./modules/jtframe/hdl/jtframe_z80wait.v" does not exist.
+
+[FTL:CM0008] Verilog File "./modules/jtframe/hdl/ram/jtframe_ram.v" does not exist.
+
+[FTL:CM0008] Verilog File "./modules/jtgng_cen3p57.v" does not exist.
+
+[FTL:CM0008] Verilog File "./modules/jtgng_sound.v" does not exist.
+
+[FTL:CM0008] Verilog File "./modules/jtgng_obj32.v" does not exist.
+
+[FTL:CM0008] Verilog File "./modules/jt12/jt49/hdl/filter/jt49_dcrm2.v" does not exist.
+
+[FTL:CM0008] Verilog File "./modules/jt12/hdl/mixer/jt12_mixer.v" does not exist.
+
+[WRN:CM0005] Include path "./modules/jtframe/hdl/cpu" does not exist.
+
+[WRN:CM0005] Include path "./modules/jtframe/hdl" does not exist.
+
+[WRN:CM0005] Include path "./modules/jtframe/hdl/ram" does not exist.
+
+[WRN:CM0005] Include path "./modules" does not exist.
+
+[WRN:CM0005] Include path "./modules/jt12/jt49/hdl/filter" does not exist.
+
+[WRN:CM0005] Include path "./modules/jt12/hdl/mixer" does not exist.
+
+[  FATAL] : 8
+[ SYNTAX] : 0
+[  ERROR] : 0
+[WARNING] : 6
+[   NOTE] : 0
+
+rc=1
+
+### filelist_verilator:cores/tora/ver/sound/gather.f
+'verilator' '--lint-only' '--sv' '--Wno-fatal' '--Wno-DECLFILENAME' '--Wno-MULTITOP' '--Wno-UNUSEDSIGNAL' '--Wno-UNUSEDPARAM' '--Wno-WIDTH' '-Itestbench/jotego_jtcores_pr654/snapshot_scratch' '-Itestbench/jotego_jtcores_pr654/snapshot_scratch/cores/toki/hdl' '-Itestbench/jotego_jtcores_pr654/snapshot_scratch/cores/toki/ver/ram2gfx' '-f' 'testbench/jotego_jtcores_pr654/snapshot_scratch/cores/tora/ver/sound/gather.f'
+%Error: Cannot find file containing module: '../../../modules/jtframe/hdl/jtframe_z80wait.v'
+        ... See the manual at https://verilator.org/verilator_doc.html?v=5.047 for more assistance.
+        ... Looked in:
+             testbench/jotego_jtcores_pr654/snapshot_scratch/../../../modules/jtframe/hdl/jtframe_z80wait.v
+             testbench/jotego_jtcores_pr654/snapshot_scratch/../../../modules/jtframe/hdl/jtframe_z80wait.v.v
+             testbench/jotego_jtcores_pr654/snapshot_scratch/../../../modules/jtframe/hdl/jtframe_z80wait.v.sv
+             testbench/jotego_jtcores_pr654/snapshot_scratch/cores/toki/hdl/../../../modules/jtframe/hdl/jtframe_z80wait.v
+             testbench/jotego_jtcores_pr654/snapshot_scratch/cores/toki/hdl/../../../modules/jtframe/hdl/jtframe_z80wait.v.v
+             testbench/jotego_jtcores_pr654/snapshot_scratch/cores/toki/hdl/../../../modules/jtframe/hdl/jtframe_z80wait.v.sv
+             testbench/jotego_jtcores_pr654/snapshot_scratch/cores/toki/ver/ram2gfx/../../../modules/jtframe/hdl/jtframe_z80wait.v
+             testbench/jotego_jtcores_pr654/snapshot_scratch/cores/toki/ver/ram2gfx/../../../modules/jtframe/hdl/jtframe_z80wait.v.v
+             testbench/jotego_jtcores_pr654/snapshot_scratch/cores/toki/ver/ram2gfx/../../../modules/jtframe/hdl/jtframe_z80wait.v.sv
+             ../../../modules/jtframe/hdl/jtframe_z80wait.v
+             ../../../modules/jtframe/hdl/jtframe_z80wait.v.v
+             ../../../modules/jtframe/hdl/jtframe_z80wait.v.sv
+             obj_dir/../../../modules/jtframe/hdl/jtframe_z80wait.v
+             obj_dir/../../../modules/jtframe/hdl/jtframe_z80wait.v.v
+             obj_dir/../../../modules/jtframe/hdl/jtframe_z80wait.v.sv
+        ... With current working directory 'testbench/jotego_jtcores_pr654/snapshot_scratch'
+%Error: Cannot find file containing module: '../../../modules/jtgng_cen3p57.v'
+%Error: Cannot find file containing module: '../../../modules/jtgng_sound.v'
+%Error: Cannot find file containing module: '../../../modules/jtgng_obj32.v'
+%Error: Cannot find file containing module: '../../../modules/jt12/jt49/hdl/filter/jt49_dcrm2.v'
+%Error: Cannot find file containing module: '../../../modules/jt12/hdl/mixer/jt12_mixer.v'
+%Error: Exiting due to 6 error(s)
+
+rc=1
+
+### filelist_surelog:modules/jtframe/hdl/cpu/mc6502/mc6502.f
+'surelog' '-sv' '-parse' '-nocomp' '-Itestbench/jotego_jtcores_pr654/snapshot_scratch' '-Itestbench/jotego_jtcores_pr654/snapshot_scratch/cores/toki/hdl' '-Itestbench/jotego_jtcores_pr654/snapshot_scratch/cores/toki/ver/ram2gfx' '-f' 'testbench/jotego_jtcores_pr654/snapshot_scratch/modules/jtframe/hdl/cpu/mc6502/mc6502.f' '-odir' 'testbench/jotego_jtcores_pr654/open_tool_fixed_fl'
+[INF:CM0023] Creating log file "testbench/jotego_jtcores_pr654/open_tool_fixed_fl/slpp_all/surelog.log".
+
+[FTL:CM0008] Verilog File "testbench/jotego_jtcores_pr654/snapshot_scratch/MC6502Accumulator.v" does not exist.
+
+[FTL:CM0008] Verilog File "testbench/jotego_jtcores_pr654/snapshot_scratch/MC6502ExecutionController.v" does not exist.
+
+[FTL:CM0008] Verilog File "testbench/jotego_jtcores_pr654/snapshot_scratch/MC6502InstructionDecode.v" does not exist.
+
+[FTL:CM0008] Verilog File "testbench/jotego_jtcores_pr654/snapshot_scratch/MC6502InterruptLogic.v" does not exist.
+
+[FTL:CM0008] Verilog File "testbench/jotego_jtcores_pr654/snapshot_scratch/MC6502MemoryController.v" does not exist.
+
+[FTL:CM0008] Verilog File "testbench/jotego_jtcores_pr654/snapshot_scratch/MC6502ProcessorStatusRegister.v" does not exist.
+
+[FTL:CM0008] Verilog File "testbench/jotego_jtcores_pr654/snapshot_scratch/MC6502RegisterFile.v" does not exist.
+
+[FTL:CM0008] Verilog File "testbench/jotego_jtcores_pr654/snapshot_scratch/MC6502Shifter.v" does not exist.
+
+[FTL:CM0008] Verilog File "testbench/jotego_jtcores_pr654/snapshot_scratch/MC6502.v" does not exist.
+
+[  FATAL] : 9
+[ SYNTAX] : 0
+[  ERROR] : 0
+[WARNING] : 0
+[   NOTE] : 0
+
+rc=1
+
+### filelist_verilator:modules/jtframe/hdl/cpu/mc6502/mc6502.f
+'verilator' '--lint-only' '--sv' '--Wno-fatal' '--Wno-DECLFILENAME' '--Wno-MULTITOP' '--Wno-UNUSEDSIGNAL' '--Wno-UNUSEDPARAM' '--Wno-WIDTH' '-Itestbench/jotego_jtcores_pr654/snapshot_scratch' '-Itestbench/jotego_jtcores_pr654/snapshot_scratch/cores/toki/hdl' '-Itestbench/jotego_jtcores_pr654/snapshot_scratch/cores/toki/ver/ram2gfx' '-f' 'testbench/jotego_jtcores_pr654/snapshot_scratch/modules/jtframe/hdl/cpu/mc6502/mc6502.f'
+%Error: Cannot find file containing module: 'MC6502Accumulator.v'
+        ... See the manual at https://verilator.org/verilator_doc.html?v=5.047 for more assistance.
+        ... Looked in:
+             testbench/jotego_jtcores_pr654/snapshot_scratch/MC6502Accumulator.v
+             testbench/jotego_jtcores_pr654/snapshot_scratch/MC6502Accumulator.v.v
+             testbench/jotego_jtcores_pr654/snapshot_scratch/MC6502Accumulator.v.sv
+             testbench/jotego_jtcores_pr654/snapshot_scratch/cores/toki/hdl/MC6502Accumulator.v
+             testbench/jotego_jtcores_pr654/snapshot_scratch/cores/toki/hdl/MC6502Accumulator.v.v
+             testbench/jotego_jtcores_pr654/snapshot_scratch/cores/toki/hdl/MC6502Accumulator.v.sv
+             testbench/jotego_jtcores_pr654/snapshot_scratch/cores/toki/ver/ram2gfx/MC6502Accumulator.v
+             testbench/jotego_jtcores_pr654/snapshot_scratch/cores/toki/ver/ram2gfx/MC6502Accumulator.v.v
+             testbench/jotego_jtcores_pr654/snapshot_scratch/cores/toki/ver/ram2gfx/MC6502Accumulator.v.sv
+             MC6502Accumulator.v
+             MC6502Accumulator.v.v
+             MC6502Accumulator.v.sv
+             obj_dir/MC6502Accumulator.v
+             obj_dir/MC6502Accumulator.v.v
+             obj_dir/MC6502Accumulator.v.sv
+        ... With current working directory 'testbench/jotego_jtcores_pr654/snapshot_scratch'
+%Error: Cannot find file containing module: 'MC6502ExecutionController.v'
+%Error: Cannot find file containing module: 'MC6502InstructionDecode.v'
+%Error: Cannot find file containing module: 'MC6502InterruptLogic.v'
+%Error: Cannot find file containing module: 'MC6502MemoryController.v'
+%Error: Cannot find file containing module: 'MC6502ProcessorStatusRegister.v'
+%Error: Cannot find file containing module: 'MC6502RegisterFile.v'
+%Error: Cannot find file containing module: 'MC6502Shifter.v'
+%Error: Cannot find file containing module: 'MC6502.v'
+%Error: Exiting due to 9 error(s)
+
+rc=1
+PASS: open-tool P2P fallback not applicable: no open-tool check passed

testbench/jotego_jtcores_pr654/repo_native_buggy.log

@@ -0,0 +1 @@
+PASS: repo native P2P smoke not applicable in buggy phase: no multi-file open-tool check passed

testbench/jotego_jtcores_pr654/repo_native_fixed.log

@@ -0,0 +1 @@
+PASS: repo native P2P smoke not applicable in fixed phase: no multi-file open-tool check passed

testbench/jotego_jtcores_pr654/run_once.sh

@@ -0,0 +1,4 @@
+#!/bin/bash
+set -u
+HERE="$(cd "$(dirname "${BASH_SOURCE[0]:-$0}")" && pwd)"
+exec python3 "$HERE/../_run_once_from_run_verilator.py" "$HERE/run_verilator.sh"

testbench/jotego_jtcores_pr654/run_verilator.sh

@@ -0,0 +1,32 @@
+#!/bin/bash
+set -u
+HERE="$(cd "$(dirname "${BASH_SOURCE[0]:-$0}")" && pwd)"; cd "$HERE"
+. "$HERE/../_testcase_minimum.sh"
+. "$HERE/../_repo_native_p2p_smoke.sh"
+export HWE_AUTO_COVERAGE=1
+NAME=jotego_jtcores_pr654
+REPO_ROOT="$(cd "$HERE/../.." && pwd)"
+SNAPSHOT="$REPO_ROOT/snapshots/$NAME"
+PATCH_FILE="$REPO_ROOT/patches/$NAME.patch"
+SCRATCH="$HERE/snapshot_scratch"
+TARGET="cores/toki/hdl/dual_ram_buffer.v"
+run_phase() {
+  local tag="$1"
+  rm -rf obj_dir verilator_${tag}_build.log verilator_${tag}.log
+  run_repo_native_p2p_smoke "$tag" || return $?
+  find "$SCRATCH" -type f \( -name '*.sv' -o -name '*.v' -o -name '*.vh' \) >/dev/null
+  local src=""
+  [ -f "$SCRATCH/$TARGET" ] && src="$SCRATCH/$TARGET"
+  verilator --binary --timing --Wno-fatal --Wno-WIDTH --Wno-UNOPTFLAT --Wno-UNUSEDSIGNAL --Wno-UNUSEDPARAM --Wno-LATCH --Wno-STMTDLY --Wno-PINMISSING --Wno-PINCONNECTEMPTY --Wno-DECLFILENAME --timescale 1ns/1ps $src "$HERE/tb_dual_ram_buffer_verilator.sv" --top-module tb_dual_ram_buffer_verilator -o simv_vlt 2>&1 | tee verilator_${tag}_build.log >/dev/null
+  [ ! -x obj_dir/simv_vlt ] && return 2
+  timeout 20 ./obj_dir/simv_vlt 2>&1 | tee verilator_${tag}.log >/dev/null
+  return ${PIPESTATUS[0]}
+}
+rm -rf "$SCRATCH"; cp -r "$SNAPSHOT" "$SCRATCH"; chmod -R u+w "$SCRATCH"
+echo BUGGY; (cd "$SCRATCH" && patch -p1 -R -f --no-backup-if-mismatch < "$PATCH_FILE" >/dev/null 2>&1) || true
+run_phase buggy; rc_buggy=$?
+rm -rf "$SCRATCH"; cp -r "$SNAPSHOT" "$SCRATCH"; chmod -R u+w "$SCRATCH"
+echo FIXED; (cd "$SCRATCH" && patch -p1 -f --no-backup-if-mismatch < "$PATCH_FILE" >/dev/null 2>&1) || true
+run_phase fixed; rc_fixed=$?
+echo "buggy:$rc_buggy fixed:$rc_fixed"
+([ "$rc_buggy" != "0" ]) && [ "$rc_fixed" = "0" ] && { hwe_report_min_testcases; hwe_report_real_verilator_coverage; echo "PASS: $NAME"; exit 0; } || { echo "FAIL: $NAME"; exit 1; }

testbench/jotego_jtcores_pr654/tb_dual_ram_buffer_verilator.sv

@@ -0,0 +1,69 @@
+// pr654: introduces cores/toki/hdl/dual_ram_buffer.v — 8-bit dual-banked RAM
+// that copies primary bank into a shadow when `trigger` is high. Pre-patch the
+// module is absent; post-patch the TB writes two primary-bank entries, reads
+// them back via q_in, pulses trigger to copy to the shadow, then reads the
+// shadow via q.
+`timescale 1ns/1ps
+module tb_dual_ram_buffer_verilator;
+  localparam int W = 4;
+  reg            clk = 0;
+  reg            trigger = 0;
+  reg            we = 0;
+  reg  [W-1:0]   addr_in = 0;
+  reg  [7:0]     data = 0;
+  wire [7:0]     q_in;
+  reg  [W-1:0]   addr_out = 0;
+  wire [7:0]     q;
+
+  always #5 clk = ~clk;
+
+  dual_ram_buffer #(.W(W)) dut (
+    .clk     (clk),
+    .trigger (trigger),
+    .we      (we),
+    .addr_in (addr_in),
+    .data    (data),
+    .q_in    (q_in),
+    .addr_out(addr_out),
+    .q       (q)
+  );
+
+  int errors = 0;
+  initial begin
+    // Write 0xA5 at addr 3 and 0x3C at addr 7 via primary port.
+    @(posedge clk);
+    we = 1; addr_in = 4'd3; data = 8'hA5;
+    @(posedge clk);
+    we = 1; addr_in = 4'd7; data = 8'h3C;
+    @(posedge clk);
+    we = 0;
+
+    // Read via primary (q_in).
+    addr_in = 4'd3; @(posedge clk); #1;
+    if (q_in !== 8'hA5) begin errors++; $display("FAIL: q_in@3=%h expected A5", q_in); end
+
+    addr_in = 4'd7; @(posedge clk); #1;
+    if (q_in !== 8'h3C) begin errors++; $display("FAIL: q_in@7=%h expected 3C", q_in); end
+
+    // Trigger a full copy into shadow. Needs 2**W cycles.
+    trigger = 1;
+    repeat (2**W + 4) @(posedge clk);
+    trigger = 0;
+    repeat (4) @(posedge clk);
+
+    // Read shadow via q.
+    addr_out = 4'd3; @(posedge clk); #1;
+    if (q !== 8'hA5) begin errors++; $display("FAIL: shadow@3 q=%h expected A5", q); end
+
+    addr_out = 4'd7; @(posedge clk); #1;
+    if (q !== 8'h3C) begin errors++; $display("FAIL: shadow@7 q=%h expected 3C", q); end
+
+    if (errors == 0)
+      $display("PASS: dual_ram_buffer primary write + shadow copy behave");
+    else
+      $fatal(1, "FAIL: %0d errors", errors);
+    $finish;
+  end
+
+  initial begin #5000; $fatal(1, "FAIL: timeout"); end
+endmodule

testbench/jotego_jtcores_pr654/verilator_buggy_phase.log

@@ -0,0 +1 @@
+FAIL: buggy phase exited rc=2

testbench/jotego_jtcores_pr654/verilator_fixed.log

@@ -0,0 +1,2 @@
+PASS: dual_ram_buffer primary write + shadow copy behave
+- testbench/jotego_jtcores_pr654/tb_dual_ram_buffer_verilator.sv:65: Verilog $finish

testbench/jotego_jtcores_pr654/verilator_fixed_build.log

@@ -0,0 +1,14 @@
+make: Entering directory 'testbench/jotego_jtcores_pr654/obj_dir'
+g++ -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -Os  -c -o _coverage_main.o testbench/jotego_jtcores_pr654/../_coverage_main.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -c -o verilated.o /opt/oss-cad-suite/share/verilator/include/verilated.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -c -o verilated_cov.o /opt/oss-cad-suite/share/verilator/include/verilated_cov.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -c -o verilated_timing.o /opt/oss-cad-suite/share/verilator/include/verilated_timing.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -c -o verilated_threads.o /opt/oss-cad-suite/share/verilator/include/verilated_threads.cpp
+python3 /opt/oss-cad-suite/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vhwe_cov_top.cpp Vhwe_cov_top___024root__0.cpp Vhwe_cov_top___024root__Slow.cpp Vhwe_cov_top___024root__0__Slow.cpp Vhwe_cov_top__Syms__Slow.cpp > Vhwe_cov_top__ALL.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -c -o Vhwe_cov_top__ALL.o Vhwe_cov_top__ALL.cpp
+g++ -Wl,-O2 -Wl,--sort-common -Wl,--as-needed -Wl,-z,relro -Wl,-z,now -Wl,--disable-new-dtags -Wl,--gc-sections -Wl,--allow-shlib-undefined -Wl,-rpath,/home/user/miniforge3/lib -Wl,-rpath-link,/home/user/miniforge3/lib -L/home/user/miniforge3/lib    _coverage_main.o verilated.o verilated_cov.o verilated_timing.o verilated_threads.o Vhwe_cov_top__ALL.a    -pthread -lpthread -latomic   -o simv_vlt
+rm Vhwe_cov_top__ALL.verilator_deplist.tmp
+make: Leaving directory 'testbench/jotego_jtcores_pr654/obj_dir'
+- V e r i l a t i o n   R e p o r t: Verilator 5.047 devel rev v5.046-293-ge82bd52fa (mod)
+- Verilator: Built from 0.052 MB sources in 3 modules, into 0.129 MB in 5 C++ files needing 0.000 MB
+- Verilator: Walltime 8.241 s (elab=0.001, cvt=0.005, bld=8.231); cpu 0.010 s on 1 threads; allocated 21.078 MB

testbench/jotego_jtcores_pr654/verilator_fixed_coverage.info

@@ -0,0 +1,760 @@
+TN:verilator_coverage
+SF:testbench/jotego_jtcores_pr654/snapshot_scratch/cores/toki/hdl/dual_ram_buffer.v
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+DA:24,8
+BRDA:24,0,0,8
+BRDA:24,0,1,8
+BRDA:24,0,2,4
+BRDA:24,0,3,4
+BRDA:24,0,4,2
+BRDA:24,0,5,2
+BRDA:24,0,6,1
+BRDA:24,0,7,1
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+BRDA:24,0,10,1
+DA:26,31
+DA:27,31
+BRDA:27,0,0,31
+BRDA:27,0,1,0
+DA:28,16
+BRDA:28,0,0,4
+BRDA:28,0,1,12
+BRDA:28,0,2,16
+BRDA:28,0,3,16
+DA:29,16
+DA:30,16
+DA:32,14
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+BRDA:32,0,3,1
+BRDA:32,0,4,3
+DA:33,1
+DA:35,29
+BRDA:35,0,0,2
+BRDA:35,0,1,29
+DA:36,2
+DA:38,31
+DA:39,31
+BRF:606
+BRH:9
+end_of_record
+SF:testbench/jotego_jtcores_pr654/tb_dual_ram_buffer_verilator.sv
+DA:9,31
+BRDA:9,0,0,31
+BRDA:9,0,1,30
+BRDA:9,0,2,1
+DA:10,1
+BRDA:10,0,0,1
+BRDA:10,0,1,1
+BRDA:10,0,2,1
+DA:11,1
+BRDA:11,0,0,1
+BRDA:11,0,1,1
+BRDA:11,0,2,1
+DA:12,2
+BRDA:12,0,0,1
+BRDA:12,0,1,0
+BRDA:12,0,2,1
+BRDA:12,0,3,0
+BRDA:12,0,4,2
+BRDA:12,0,5,1
+BRDA:12,0,6,0
+BRDA:12,0,7,0
+BRDA:12,0,8,1
+DA:13,1
+BRDA:13,0,0,1
+BRDA:13,0,1,1
+BRDA:13,0,2,0
+BRDA:13,0,3,0
+BRDA:13,0,4,1
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+BRDA:13,0,13,0
+BRDA:13,0,14,1
+BRDA:13,0,15,1
+BRDA:13,0,16,1
+DA:14,1
+BRDA:14,0,0,1
+BRDA:14,0,1,1
+BRDA:14,0,2,0
+BRDA:14,0,3,0
+BRDA:14,0,4,1
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+BRDA:14,0,12,0
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+DA:15,1
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+DA:16,1
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+DA:50,20
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+DA:58,1
+DA:59,1
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+BRDA:59,0,1,1
+DA:61,1
+DA:62,1
+DA:65,1
+BRF:91
+BRH:6
+end_of_record

testbench/jotego_jtcores_pr654/verilator_fixed_phase.log

@@ -0,0 +1 @@
+PASS: fixed phase exited rc=0

testbench/lnis-uofu_OpenFPGA_pr2164/open_tool_p2p_buggy.log

@@ -0,0 +1,119 @@
+INFO: open-tool P2P fallback (buggy)
+INFO: native simulation P2P not applicable for this case
+
+### filelist_surelog:openfpga_flow/openfpga_cell_library/verilog_sources.f
+'surelog' '-sv' '-parse' '-nocomp' '-Itestbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch' '-Itestbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/libs/libarchopenfpga/src' '-Itestbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/libs/libopenfpgautil/src' '-Itestbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga/src/annotation' '-Itestbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga/src/fpga_bitstream' '-Itestbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga/src/repack' '-f' 'testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga_flow/openfpga_cell_library/verilog_sources.f' '-odir' 'testbench/lnis-uofu_OpenFPGA_pr2164/open_tool_buggy_fl'
+[INF:CM0023] Creating log file "testbench/lnis-uofu_OpenFPGA_pr2164/open_tool_buggy_fl/slpp_all/surelog.log".
+
+[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/adder.v" does not exist.
+
+[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/aib.v" does not exist.
+
+[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/buf4.v" does not exist.
+
+[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/dff.v" does not exist.
+
+[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/dpram.v" does not exist.
+
+[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/dpram16k.v" does not exist.
+
+[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/dpram1k.v" does not exist.
+
+[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/dpram8k.v" does not exist.
+
+[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/dpram_2048x8.v" does not exist.
+
+[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/frac_mem_32k.v" does not exist.
+
+[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/frac_mult_16x16.v" does not exist.
+
+[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/gpio.v" does not exist.
+
+[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/inv.v" does not exist.
+
+[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/latch.v" does not exist.
+
+[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/lut6.v" does not exist.
+
+[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/mult_32x32.v" does not exist.
+
+[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/mult_36x36.v" does not exist.
+
+[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/mult_8x8.v" does not exist.
+
+[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/mux2.v" does not exist.
+
+[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/or2.v" does not exist.
+
+[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/spram_4x1.v" does not exist.
+
+[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/sram.v" does not exist.
+
+[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/tap_buf4.v" does not exist.
+
+[WRN:CM0005] Include path "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog" does not exist.
+
+[  FATAL] : 23
+[ SYNTAX] : 0
+[  ERROR] : 0
+[WARNING] : 1
+[   NOTE] : 0
+
+rc=1
+
+### filelist_verilator:openfpga_flow/openfpga_cell_library/verilog_sources.f
+'verilator' '--lint-only' '--sv' '--Wno-fatal' '--Wno-DECLFILENAME' '--Wno-MULTITOP' '--Wno-UNUSEDSIGNAL' '--Wno-UNUSEDPARAM' '--Wno-WIDTH' '-Itestbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch' '-Itestbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/libs/libarchopenfpga/src' '-Itestbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/libs/libopenfpgautil/src' '-Itestbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga/src/annotation' '-Itestbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga/src/fpga_bitstream' '-Itestbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga/src/repack' '-f' 'testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga_flow/openfpga_cell_library/verilog_sources.f'
+%Error: Cannot find file containing module: 'verilog/adder.v'
+        ... See the manual at https://verilator.org/verilator_doc.html?v=5.047 for more assistance.
+        ... Looked in:
+             testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/adder.v
+             testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/adder.v.v
+             testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/adder.v.sv
+             testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/libs/libarchopenfpga/src/verilog/adder.v
+             testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/libs/libarchopenfpga/src/verilog/adder.v.v
+             testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/libs/libarchopenfpga/src/verilog/adder.v.sv
+             testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/libs/libopenfpgautil/src/verilog/adder.v
+             testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/libs/libopenfpgautil/src/verilog/adder.v.v
+             testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/libs/libopenfpgautil/src/verilog/adder.v.sv
+             testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga/src/annotation/verilog/adder.v
+             testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga/src/annotation/verilog/adder.v.v
+             testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga/src/annotation/verilog/adder.v.sv
+             testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga/src/fpga_bitstream/verilog/adder.v
+             testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga/src/fpga_bitstream/verilog/adder.v.v
+             testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga/src/fpga_bitstream/verilog/adder.v.sv
+             testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga/src/repack/verilog/adder.v
+             testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga/src/repack/verilog/adder.v.v
+             testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga/src/repack/verilog/adder.v.sv
+             verilog/adder.v
+             verilog/adder.v.v
+             verilog/adder.v.sv
+             obj_dir/verilog/adder.v
+             obj_dir/verilog/adder.v.v
+             obj_dir/verilog/adder.v.sv
+        ... With current working directory 'testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch'
+%Error: Cannot find file containing module: 'verilog/aib.v'
+%Error: Cannot find file containing module: 'verilog/buf4.v'
+%Error: Cannot find file containing module: 'verilog/dff.v'
+%Error: Cannot find file containing module: 'verilog/dpram.v'
+%Error: Cannot find file containing module: 'verilog/dpram16k.v'
+%Error: Cannot find file containing module: 'verilog/dpram1k.v'
+%Error: Cannot find file containing module: 'verilog/dpram8k.v'
+%Error: Cannot find file containing module: 'verilog/dpram_2048x8.v'
+%Error: Cannot find file containing module: 'verilog/frac_mem_32k.v'
+%Error: Cannot find file containing module: 'verilog/frac_mult_16x16.v'
+%Error: Cannot find file containing module: 'verilog/gpio.v'
+%Error: Cannot find file containing module: 'verilog/inv.v'
+%Error: Cannot find file containing module: 'verilog/latch.v'
+%Error: Cannot find file containing module: 'verilog/lut6.v'
+%Error: Cannot find file containing module: 'verilog/mult_32x32.v'
+%Error: Cannot find file containing module: 'verilog/mult_36x36.v'
+%Error: Cannot find file containing module: 'verilog/mult_8x8.v'
+%Error: Cannot find file containing module: 'verilog/mux2.v'
+%Error: Cannot find file containing module: 'verilog/or2.v'
+%Error: Cannot find file containing module: 'verilog/spram_4x1.v'
+%Error: Cannot find file containing module: 'verilog/sram.v'
+%Error: Cannot find file containing module: 'verilog/tap_buf4.v'
+%Error: Exiting due to 23 error(s)
+
+rc=1
+PASS: open-tool P2P fallback not applicable: no open-tool check passed

testbench/lnis-uofu_OpenFPGA_pr2164/open_tool_p2p_fixed.log

@@ -0,0 +1,128 @@
+INFO: open-tool P2P fallback (fixed)
+INFO: native simulation P2P not applicable for this case
+
+### filelist_surelog:openfpga_flow/openfpga_cell_library/verilog_sources.f
+'surelog' '-sv' '-parse' '-nocomp' '-Itestbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch' '-Itestbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/libs/libarchopenfpga/src' '-Itestbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/libs/libopenfpgautil/src' '-Itestbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga/src/annotation' '-Itestbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga/src/fpga_bitstream' '-Itestbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga/src/repack' '-Itestbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga_flow/benchmarks/micro_benchmark/mult/dual_mult8_mix_regin' '-Itestbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga_flow/openfpga_cell_library/verilog' '-Itestbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga_flow/openfpga_yosys_techlib' '-f' 'testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga_flow/openfpga_cell_library/verilog_sources.f' '-odir' 'testbench/lnis-uofu_OpenFPGA_pr2164/open_tool_fixed_fl'
+[INF:CM0023] Creating log file "testbench/lnis-uofu_OpenFPGA_pr2164/open_tool_fixed_fl/slpp_all/surelog.log".
+
+[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/adder.v" does not exist.
+
+[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/aib.v" does not exist.
+
+[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/buf4.v" does not exist.
+
+[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/dff.v" does not exist.
+
+[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/dpram.v" does not exist.
+
+[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/dpram16k.v" does not exist.
+
+[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/dpram1k.v" does not exist.
+
+[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/dpram8k.v" does not exist.
+
+[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/dpram_2048x8.v" does not exist.
+
+[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/frac_mem_32k.v" does not exist.
+
+[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/frac_mult_16x16.v" does not exist.
+
+[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/gpio.v" does not exist.
+
+[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/inv.v" does not exist.
+
+[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/latch.v" does not exist.
+
+[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/lut6.v" does not exist.
+
+[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/mult_32x32.v" does not exist.
+
+[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/mult_36x36.v" does not exist.
+
+[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/mult_8x8.v" does not exist.
+
+[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/mux2.v" does not exist.
+
+[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/or2.v" does not exist.
+
+[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/spram_4x1.v" does not exist.
+
+[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/sram.v" does not exist.
+
+[FTL:CM0008] Verilog File "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/tap_buf4.v" does not exist.
+
+[WRN:CM0005] Include path "testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog" does not exist.
+
+[  FATAL] : 23
+[ SYNTAX] : 0
+[  ERROR] : 0
+[WARNING] : 1
+[   NOTE] : 0
+
+rc=1
+
+### filelist_verilator:openfpga_flow/openfpga_cell_library/verilog_sources.f
+'verilator' '--lint-only' '--sv' '--Wno-fatal' '--Wno-DECLFILENAME' '--Wno-MULTITOP' '--Wno-UNUSEDSIGNAL' '--Wno-UNUSEDPARAM' '--Wno-WIDTH' '-Itestbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch' '-Itestbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/libs/libarchopenfpga/src' '-Itestbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/libs/libopenfpgautil/src' '-Itestbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga/src/annotation' '-Itestbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga/src/fpga_bitstream' '-Itestbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga/src/repack' '-Itestbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga_flow/benchmarks/micro_benchmark/mult/dual_mult8_mix_regin' '-Itestbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga_flow/openfpga_cell_library/verilog' '-Itestbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga_flow/openfpga_yosys_techlib' '-f' 'testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga_flow/openfpga_cell_library/verilog_sources.f'
+%Error: Cannot find file containing module: 'verilog/adder.v'
+        ... See the manual at https://verilator.org/verilator_doc.html?v=5.047 for more assistance.
+        ... Looked in:
+             testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/adder.v
+             testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/adder.v.v
+             testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/verilog/adder.v.sv
+             testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/libs/libarchopenfpga/src/verilog/adder.v
+             testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/libs/libarchopenfpga/src/verilog/adder.v.v
+             testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/libs/libarchopenfpga/src/verilog/adder.v.sv
+             testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/libs/libopenfpgautil/src/verilog/adder.v
+             testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/libs/libopenfpgautil/src/verilog/adder.v.v
+             testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/libs/libopenfpgautil/src/verilog/adder.v.sv
+             testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga/src/annotation/verilog/adder.v
+             testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga/src/annotation/verilog/adder.v.v
+             testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga/src/annotation/verilog/adder.v.sv
+             testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga/src/fpga_bitstream/verilog/adder.v
+             testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga/src/fpga_bitstream/verilog/adder.v.v
+             testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga/src/fpga_bitstream/verilog/adder.v.sv
+             testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga/src/repack/verilog/adder.v
+             testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga/src/repack/verilog/adder.v.v
+             testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga/src/repack/verilog/adder.v.sv
+             testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga_flow/benchmarks/micro_benchmark/mult/dual_mult8_mix_regin/verilog/adder.v
+             testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga_flow/benchmarks/micro_benchmark/mult/dual_mult8_mix_regin/verilog/adder.v.v
+             testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga_flow/benchmarks/micro_benchmark/mult/dual_mult8_mix_regin/verilog/adder.v.sv
+             testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga_flow/openfpga_cell_library/verilog/verilog/adder.v
+             testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga_flow/openfpga_cell_library/verilog/verilog/adder.v.v
+             testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga_flow/openfpga_cell_library/verilog/verilog/adder.v.sv
+             testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga_flow/openfpga_yosys_techlib/verilog/adder.v
+             testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga_flow/openfpga_yosys_techlib/verilog/adder.v.v
+             testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch/openfpga_flow/openfpga_yosys_techlib/verilog/adder.v.sv
+             verilog/adder.v
+             verilog/adder.v.v
+             verilog/adder.v.sv
+             obj_dir/verilog/adder.v
+             obj_dir/verilog/adder.v.v
+             obj_dir/verilog/adder.v.sv
+        ... With current working directory 'testbench/lnis-uofu_OpenFPGA_pr2164/snapshot_scratch'
+%Error: Cannot find file containing module: 'verilog/aib.v'
+%Error: Cannot find file containing module: 'verilog/buf4.v'
+%Error: Cannot find file containing module: 'verilog/dff.v'
+%Error: Cannot find file containing module: 'verilog/dpram.v'
+%Error: Cannot find file containing module: 'verilog/dpram16k.v'
+%Error: Cannot find file containing module: 'verilog/dpram1k.v'
+%Error: Cannot find file containing module: 'verilog/dpram8k.v'
+%Error: Cannot find file containing module: 'verilog/dpram_2048x8.v'
+%Error: Cannot find file containing module: 'verilog/frac_mem_32k.v'
+%Error: Cannot find file containing module: 'verilog/frac_mult_16x16.v'
+%Error: Cannot find file containing module: 'verilog/gpio.v'
+%Error: Cannot find file containing module: 'verilog/inv.v'
+%Error: Cannot find file containing module: 'verilog/latch.v'
+%Error: Cannot find file containing module: 'verilog/lut6.v'
+%Error: Cannot find file containing module: 'verilog/mult_32x32.v'
+%Error: Cannot find file containing module: 'verilog/mult_36x36.v'
+%Error: Cannot find file containing module: 'verilog/mult_8x8.v'
+%Error: Cannot find file containing module: 'verilog/mux2.v'
+%Error: Cannot find file containing module: 'verilog/or2.v'
+%Error: Cannot find file containing module: 'verilog/spram_4x1.v'
+%Error: Cannot find file containing module: 'verilog/sram.v'
+%Error: Cannot find file containing module: 'verilog/tap_buf4.v'
+%Error: Exiting due to 23 error(s)
+
+rc=1
+PASS: open-tool P2P fallback not applicable: no open-tool check passed

testbench/lnis-uofu_OpenFPGA_pr2164/repo_native_buggy.log

@@ -0,0 +1 @@
+PASS: repo native P2P smoke not applicable in buggy phase: no multi-file open-tool check passed

testbench/lnis-uofu_OpenFPGA_pr2164/repo_native_fixed.log

@@ -0,0 +1 @@
+PASS: repo native P2P smoke not applicable in fixed phase: no multi-file open-tool check passed

testbench/lnis-uofu_OpenFPGA_pr2164/run_once.sh

@@ -0,0 +1,4 @@
+#!/bin/bash
+set -u
+HERE="$(cd "$(dirname "${BASH_SOURCE[0]:-$0}")" && pwd)"
+exec python3 "$HERE/../_run_once_from_run_verilator.py" "$HERE/run_verilator.sh"

testbench/lnis-uofu_OpenFPGA_pr2164/run_verilator.sh

@@ -0,0 +1,37 @@
+#!/bin/bash
+set -u
+HERE="$(cd "$(dirname "${BASH_SOURCE[0]:-$0}")" && pwd)"; cd "$HERE"
+. "$HERE/../_testcase_minimum.sh"
+. "$HERE/../_repo_native_p2p_smoke.sh"
+export HWE_AUTO_COVERAGE=1
+NAME=lnis-uofu_OpenFPGA_pr2164
+REPO_ROOT="$(cd "$HERE/../.." && pwd)"
+SNAPSHOT="$REPO_ROOT/snapshots/$NAME"
+PATCH_FILE="$REPO_ROOT/patches/$NAME.patch"
+SCRATCH="$HERE/snapshot_scratch"
+TARGET="openfpga_flow/openfpga_cell_library/verilog/frac_mult_16x16_regin.v"
+PATCH_TARGETS=(
+  "$SCRATCH/openfpga_flow/openfpga_cell_library/verilog/frac_mult_16x16_regin.v"
+  "$SCRATCH/openfpga_flow/benchmarks/micro_benchmark/mult/dual_mult8_mix_regin/dual_mult8_mix_regin.v"
+  "$SCRATCH/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_frac_dsp16_regin_nonLR_caravel_io_skywater130nm_cell_sim.v"
+)
+run_phase() {
+  local tag="$1"
+  rm -rf obj_dir verilator_${tag}_build.log verilator_${tag}.log
+  run_repo_native_p2p_smoke "$tag" || return $?
+  local src=""
+  [ -f "$SCRATCH/$TARGET" ] && src="$SCRATCH/$TARGET"
+  verilator --binary --timing --Wno-fatal --Wno-WIDTH --Wno-UNOPTFLAT --Wno-UNUSEDSIGNAL --Wno-UNUSEDPARAM --Wno-LATCH --Wno-STMTDLY --Wno-PINMISSING --Wno-PINCONNECTEMPTY --Wno-DECLFILENAME --Wno-ASCRANGE --timescale 1ns/1ps $src "$HERE/tb_frac_mult_verilator.sv" --top-module tb_frac_mult_verilator -o simv_vlt 2>&1 | tee verilator_${tag}_build.log >/dev/null
+  [ ! -x obj_dir/simv_vlt ] && return 2
+  timeout 20 ./obj_dir/simv_vlt 2>&1 | tee verilator_${tag}.log >/dev/null
+  grep -qE "(^|[^A-Za-z])PASS:" verilator_${tag}.log && ! grep -qE "(^|[^A-Za-z])FAIL:" verilator_${tag}.log && return 0
+  return 1
+}
+rm -rf "$SCRATCH"; cp -r "$SNAPSHOT" "$SCRATCH"; chmod -R u+w "$SCRATCH"
+echo BUGGY; (cd "$SCRATCH" && patch -p1 -R -f --no-backup-if-mismatch < "$PATCH_FILE" >/dev/null 2>&1) || true
+run_phase buggy; rc_buggy=$?
+rm -rf "$SCRATCH"; cp -r "$SNAPSHOT" "$SCRATCH"; chmod -R u+w "$SCRATCH"
+echo FIXED; (cd "$SCRATCH" && patch -p1 -f --no-backup-if-mismatch < "$PATCH_FILE" >/dev/null 2>&1) || true
+run_phase fixed; rc_fixed=$?
+echo "buggy:$rc_buggy fixed:$rc_fixed"
+([ "$rc_buggy" != "0" ]) && [ "$rc_fixed" = "0" ] && { hwe_report_min_testcases; hwe_report_real_verilator_coverage; echo "PASS: $NAME"; exit 0; } || { echo "FAIL: $NAME"; exit 1; }