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33

Add missing snapshots (batch 4/24)

#13
by Zanehpn - opened
base: refs/heads/main
←
from: refs/pr/13
Discussion Files changed
+1433403
-0
This view is limited to 50 files because it contains too many changes. See the raw diff here.
Files changed (50) hide show
  1. .gitattributes +45 -0
  2. snapshots/MiSTer-devel_ao486_MiSTer_pr72/releases/ao486_20190308.rbf +3 -0
  3. snapshots/MiSTer-devel_ao486_MiSTer_pr72/releases/ao486_20190425.rbf +3 -0
  4. snapshots/MiSTer-devel_ao486_MiSTer_pr72/releases/ao486_20190719.rbf +3 -0
  5. snapshots/MiSTer-devel_ao486_MiSTer_pr72/releases/ao486_20190927.rbf +3 -0
  6. snapshots/MiSTer-devel_ao486_MiSTer_pr72/releases/ao486_20191221.rbf +3 -0
  7. snapshots/MiSTer-devel_ao486_MiSTer_pr72/releases/ao486_20200421.rbf +3 -0
  8. snapshots/MiSTer-devel_ao486_MiSTer_pr72/releases/ao486_20200510.rbf +3 -0
  9. snapshots/MiSTer-devel_ao486_MiSTer_pr72/releases/ao486_20200814.rbf +3 -0
  10. snapshots/MiSTer-devel_ao486_MiSTer_pr72/releases/ao486_20200816.rbf +3 -0
  11. snapshots/MiSTer-devel_ao486_MiSTer_pr72/releases/ao486_20200822.rbf +3 -0
  12. snapshots/MiSTer-devel_ao486_MiSTer_pr72/releases/ao486_20200831.rbf +3 -0
  13. snapshots/MiSTer-devel_ao486_MiSTer_pr72/releases/ao486_20200907.rbf +3 -0
  14. snapshots/MiSTer-devel_ao486_MiSTer_pr72/releases/ao486_20200917.rbf +3 -0
  15. snapshots/MiSTer-devel_ao486_MiSTer_pr72/releases/ao486_20200922.rbf +3 -0
  16. snapshots/MiSTer-devel_ao486_MiSTer_pr72/releases/ao486_20201101.rbf +3 -0
  17. snapshots/MiSTer-devel_ao486_MiSTer_pr72/releases/ao486_20201106.rbf +3 -0
  18. snapshots/MiSTer-devel_ao486_MiSTer_pr72/releases/ao486_20210103.rbf +3 -0
  19. snapshots/MiSTer-devel_ao486_MiSTer_pr72/releases/ao486_20210107.rbf +3 -0
  20. snapshots/MiSTer-devel_ao486_MiSTer_pr72/releases/ao486_20210109.rbf +3 -0
  21. snapshots/MiSTer-devel_ao486_MiSTer_pr72/releases/ao486_20210117.rbf +3 -0
  22. snapshots/MiSTer-devel_ao486_MiSTer_pr72/releases/ao486_20210226.rbf +3 -0
  23. snapshots/MiSTer-devel_ao486_MiSTer_pr72/releases/ao486_20210324.rbf +3 -0
  24. snapshots/MiSTer-devel_ao486_MiSTer_pr72/releases/ao486_20210329.rbf +3 -0
  25. snapshots/MiSTer-devel_ao486_MiSTer_pr72/releases/bios/boot0.rom +0 -0
  26. snapshots/MiSTer-devel_ao486_MiSTer_pr72/releases/bios/boot1.rom +0 -0
  27. snapshots/MiSTer-devel_ao486_MiSTer_pr72/releases/bios/boot1_opensource.rom +0 -0
  28. snapshots/MiSTer-devel_ao486_MiSTer_pr72/releases/drv/MISTERFB.DRV +0 -0
  29. snapshots/MiSTer-devel_ao486_MiSTer_pr72/releases/drv/MISTERFB.INF +63 -0
  30. snapshots/MiSTer-devel_ao486_MiSTer_pr72/releases/drv/imgset.exe +0 -0
  31. snapshots/MiSTer-devel_ao486_MiSTer_pr72/releases/drv/misterfs.exe +0 -0
  32. snapshots/MiSTer-devel_ao486_MiSTer_pr72/releases/drv/modem9x.inf +68 -0
  33. snapshots/MiSTer-devel_ao486_MiSTer_pr72/releases/drv/mpuctl.exe +0 -0
  34. snapshots/MiSTer-devel_ao486_MiSTer_pr72/releases/drv/sbctl.exe +0 -0
  35. snapshots/MiSTer-devel_ao486_MiSTer_pr72/releases/drv/sysctl.exe +0 -0
  36. snapshots/MiSTer-devel_ao486_MiSTer_pr72/rtl/ao486/ao486.qip +45 -0
  37. snapshots/MiSTer-devel_ao486_MiSTer_pr72/rtl/ao486/ao486.v +781 -0
  38. snapshots/MiSTer-devel_ao486_MiSTer_pr72/rtl/ao486/autogen/decode_commands.v +737 -0
  39. snapshots/MiSTer-devel_ao486_MiSTer_pr72/rtl/ao486/autogen/defines.v +449 -0
  40. snapshots/MiSTer-devel_ao486_MiSTer_pr72/rtl/ao486/autogen/exception.v +95 -0
  41. snapshots/MiSTer-devel_ao486_MiSTer_pr72/rtl/ao486/autogen/execute_commands.v +1157 -0
  42. snapshots/MiSTer-devel_ao486_MiSTer_pr72/rtl/ao486/autogen/memory_write.v +74 -0
  43. snapshots/MiSTer-devel_ao486_MiSTer_pr72/rtl/ao486/autogen/microcode_commands.v +926 -0
  44. snapshots/MiSTer-devel_ao486_MiSTer_pr72/rtl/ao486/autogen/prefetch_control.v +60 -0
  45. snapshots/MiSTer-devel_ao486_MiSTer_pr72/rtl/ao486/autogen/read_commands.v +1440 -0
  46. snapshots/MiSTer-devel_ao486_MiSTer_pr72/rtl/ao486/autogen/tlb.v +478 -0
  47. snapshots/MiSTer-devel_ao486_MiSTer_pr72/rtl/ao486/autogen/write_commands.v +1665 -0
  48. snapshots/MiSTer-devel_ao486_MiSTer_pr72/rtl/ao486/commands/CMD_AAA_AAS_DAA_DAS.txt +140 -0
  49. snapshots/MiSTer-devel_ao486_MiSTer_pr72/rtl/ao486/commands/CMD_AAD_AAM.txt +72 -0
  50. snapshots/MiSTer-devel_ao486_MiSTer_pr72/rtl/ao486/commands/CMD_ARPL.txt +73 -0
.gitattributes CHANGED
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+ snapshots/Wren6991_Hazard3_pr28/doc/hazard3.pdf filter=lfs diff=lfs merge=lfs -text
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+ snapshots/ZipCPU_wb2axip_pr71/doc/busprops.pdf filter=lfs diff=lfs merge=lfs -text
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+ snapshots/ZipCPU_wb2axip_pr71/doc/chexpo-2021.pdf filter=lfs diff=lfs merge=lfs -text
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+ snapshots/ZipCPU_wb2axip_pr71/doc/demo2019.pdf filter=lfs diff=lfs merge=lfs -text
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1
+
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+ ;
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+ ; MiSTer Display
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+ ;
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+ [version]
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+ signature="$CHICAGO$"
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+ Provider=%MiSTer%
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+
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+ [DestinationDirs]
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+ DefaultDestDir =11 ;LDID_SYS
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+
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+ [SourceDisksNames]
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+ 1="Windows 9x MiSTer Driver Disk",,diskt
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+
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+ [SourceDisksFiles]
17
+ MiSTerFB.drv=1
18
+
19
+ [Manufacturer]
20
+ %MiSTer%=MiSTer
21
+
22
+ [MiSTer]
23
+ %*PNP0906.DeviceDesc%=ET4000, *PNP0906
24
+
25
+ [ET4000]
26
+ CopyFiles=ET4000.Copy
27
+ DelReg=Prev.DelReg
28
+ AddReg=ET4000.AddReg
29
+
30
+ [ET4000.Copy]
31
+ MiSTerFB.drv
32
+
33
+ [Prev.DelReg]
34
+ HKR,,Ver
35
+ HKR,,DevLoader
36
+ HKR,,EnumPropPages
37
+ HKR,INFO
38
+ HKR,DEFAULT
39
+ HKR,MODES
40
+ HKR,CURRENT
41
+
42
+ [ET4000.AddReg]
43
+ HKR,,Ver,,4.0
44
+ HKR,,DevLoader,,*vdd
45
+ HKR,DEFAULT,Mode,,"8,640,480"
46
+ HKR,DEFAULT,drv,,MiSTerFB.drv
47
+ HKR,DEFAULT,vdd,,"*vdd,*vflatd"
48
+ HKR,"MODES\4\640,480",drv,,vga.drv
49
+ HKR,"MODES\4\640,480",vdd,,*vdd
50
+ HKR,"MODES\4\800,600",drv,,supervga.drv
51
+ HKR,"MODES\4\800,600",vdd,,*vdd
52
+ HKR,"MODES\8\640,480"
53
+ HKR,"MODES\8\800,600"
54
+ HKR,"MODES\8\1024,768"
55
+ HKR,"MODES\8\1280,1024"
56
+ HKR,"MODES\16\640,480"
57
+ HKR,"MODES\16\800,600"
58
+ HKR,"MODES\16\1024,768"
59
+ HKR,"MODES\24\640,480"
60
+
61
+ [Strings]
62
+ MiSTer="MiSTer"
63
+ *PNP0906.DeviceDesc="MiSTer ET4000+"
snapshots/MiSTer-devel_ao486_MiSTer_pr72/releases/drv/imgset.exe ADDED
Binary file (9.72 kB). View file
 
snapshots/MiSTer-devel_ao486_MiSTer_pr72/releases/drv/misterfs.exe ADDED
Binary file (7.01 kB). View file
 
snapshots/MiSTer-devel_ao486_MiSTer_pr72/releases/drv/modem9x.inf ADDED
@@ -0,0 +1,68 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ ; Modified 23 May 98 per e-mail
2
+
3
+ [Version]
4
+ Signature="$CHICAGO$"
5
+ Class=Modem
6
+ ClassGUID={4D36E96D-E325-11CE-BFC1-08002BE10318}
7
+ Provider=%MC%
8
+ LayoutFile=LAYOUT.INF
9
+
10
+ [Manufacturer]
11
+ %Man% = Null
12
+
13
+ [Null]
14
+ %MC02% = MC02, RAS-GENERIC
15
+
16
+ [MC02]
17
+ AddReg=All, Common, MC02Reg, 115200, EXTERNAL
18
+
19
+ [All]
20
+ HKR,,FriendlyDriver,,Unimodem.vxd
21
+ HKR,,DevLoader,,*VCOMM
22
+ HKR,,PortSubClass,1,02
23
+ HKR,,ConfigDialog,,modemui.dll
24
+ HKR,,EnumPropPages,,"modemui.dll,EnumPropPages"
25
+
26
+ [EXTERNAL]
27
+ HKR,, DeviceType, 1, 01
28
+
29
+ [Common]
30
+ HKR, Answer, 1,,""
31
+ HKR, Hangup, 1,, "Bye"
32
+ HKR, Hangup, 2,, "NoResponse"
33
+ HKR, Settings, DialSuffix,, ""
34
+
35
+ ; DCB's - dwords and words are byte reversed
36
+ ; ByteSize (Number of bits/byte, 4-8)
37
+ ; Parity (0-4=None,Odd,Even,Mark,Space)
38
+ ; StopBits (0,1,2 = 1, 1.5, 2)
39
+ ; |DCBLength |BaudRate |Bit Mask |Rsvd |XonLim|XofLim| | | |Xon|Xof|Err|Eof|Evt
40
+ [115200]
41
+ HKR,, DCB, 1, 1C,00,00,00, 00,c2,01,00, 15,20,00,00, 00,00, 0a,00, 0a,00, 08, 00, 00, 11, 13, 00, 00, 00
42
+
43
+ [MC02Reg] ; Null-Modem
44
+ HKR, Init, 1,, "<cr><cr>"
45
+ HKR, Init, 2,, "NoResponse"
46
+ HKR, Settings, Prefix,,""
47
+ HKR, Settings, DialPrefix,, "HELLO<cr>"
48
+ HKR, Settings, Terminator,, "<cr>"
49
+ HKR, Monitor, 1,, "None"
50
+ HKR, Answer, 1,, "HELLO"
51
+ HKR, Answer, 2,, "NoResponse"
52
+ ; Properties - dwords and words are byte reversed
53
+ ; |Dial Options |InactivityTimeout |Speaker Mode |Max DTE Rate
54
+ ; |CallSetupFailTimeout |Speaker Volume |Modem Options |Max DCE Rate
55
+ HKR,, Properties, 1, 00,00,00,00, 00,00,00,00, 00,00,00,00, 00,00,00,00, 00,00,00,00, 30,00,00,00, 00,c2,01,00, 00,c2,01,00
56
+ HKR, Responses, "<h00>", 1, 02, 00, 00, 00, 00, 00, 00,00,00,00 ; Accept any recvd data as CONNECTED.
57
+
58
+ ; 23 May 98 added
59
+ HKR, Responses, "<hff>", 1, 02, 00, 00, 00, 00, 00, 00,00,00,00 ; Accept any recvd data as CONNECTED.
60
+ HKR, Responses, "<cr>", 1, 02, 00, 00, 00, 00, 00, 00,00,00,00 ; Accept any recvd data as CONNECTED.
61
+ HKR, Responses, "<lf>", 1, 02, 00, 00, 00, 00, 00, 00,00,00,00 ; Accept any recvd data as CONNECTED.
62
+ HKR, Responses, "<cr><lf>", 1, 02, 00, 00, 00, 00, 00, 00,00,00,00 ; Accept any recvd data as CONNECTED.
63
+ ; end of 23 May 98 addition
64
+
65
+ [Strings]
66
+ MC = "Mark Crossley v2"
67
+ Man = "(NULL Modem Types)"
68
+ MC02 = "Generic NULL Modem"
snapshots/MiSTer-devel_ao486_MiSTer_pr72/releases/drv/mpuctl.exe ADDED
Binary file (14.5 kB). View file
 
snapshots/MiSTer-devel_ao486_MiSTer_pr72/releases/drv/sbctl.exe ADDED
Binary file (9.38 kB). View file
 
snapshots/MiSTer-devel_ao486_MiSTer_pr72/releases/drv/sysctl.exe ADDED
Binary file (9.82 kB). View file
 
snapshots/MiSTer-devel_ao486_MiSTer_pr72/rtl/ao486/ao486.qip ADDED
@@ -0,0 +1,45 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pipeline/condition.v ]
2
+ set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pipeline/decode.v ]
3
+ set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pipeline/decode_commands.v ]
4
+ set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pipeline/decode_prefix.v ]
5
+ set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pipeline/decode_ready.v ]
6
+ set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pipeline/decode_regs.v ]
7
+ set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pipeline/execute.v ]
8
+ set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pipeline/execute_commands.v ]
9
+ set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pipeline/execute_divide.v ]
10
+ set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pipeline/execute_multiply.v ]
11
+ set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pipeline/execute_offset.v ]
12
+ set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pipeline/execute_shift.v ]
13
+ set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pipeline/fetch.v ]
14
+ set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pipeline/microcode.v ]
15
+ set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pipeline/microcode_commands.v ]
16
+ set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pipeline/pipeline.v ]
17
+ set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pipeline/read.v ]
18
+ set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pipeline/read_commands.v ]
19
+ set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pipeline/read_debug.v ]
20
+ set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pipeline/read_effective_address.v ]
21
+ set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pipeline/read_mutex.v ]
22
+ set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pipeline/read_segment.v ]
23
+ set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pipeline/write.v ]
24
+ set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pipeline/write_commands.v ]
25
+ set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pipeline/write_debug.v ]
26
+ set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pipeline/write_register.v ]
27
+ set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pipeline/write_stack.v ]
28
+ set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pipeline/write_string.v ]
29
+ set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) memory/avalon_mem.v ]
30
+ set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) memory/icache.v ]
31
+ set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) memory/link_dcacheread.v ]
32
+ set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) memory/link_dcachewrite.v ]
33
+ set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) memory/memory.v ]
34
+ set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) memory/memory_read.v ]
35
+ set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) memory/memory_write.v ]
36
+ set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) memory/prefetch.v ]
37
+ set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) memory/prefetch_control.v ]
38
+ set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) memory/prefetch_fifo.v ]
39
+ set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) memory/tlb.v ]
40
+ set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) memory/tlb_memtype.v ]
41
+ set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) memory/tlb_regs.v ]
42
+ set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) exception.v ]
43
+ set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) global_regs.v ]
44
+ set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) defines.v ]
45
+ set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ao486.v ]
snapshots/MiSTer-devel_ao486_MiSTer_pr72/rtl/ao486/ao486.v ADDED
@@ -0,0 +1,781 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ /*
2
+ * Copyright (c) 2014, Aleksander Osman
3
+ * All rights reserved.
4
+ *
5
+ * Redistribution and use in source and binary forms, with or without
6
+ * modification, are permitted provided that the following conditions are met:
7
+ *
8
+ * * Redistributions of source code must retain the above copyright notice, this
9
+ * list of conditions and the following disclaimer.
10
+ *
11
+ * * Redistributions in binary form must reproduce the above copyright notice,
12
+ * this list of conditions and the following disclaimer in the documentation
13
+ * and/or other materials provided with the distribution.
14
+ *
15
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
18
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
19
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
22
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
23
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
24
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25
+ */
26
+
27
+ `include "defines.v"
28
+
29
+ module ao486 (
30
+ input clk,
31
+ input rst_n,
32
+
33
+ input a20_enable,
34
+
35
+ input cache_disable,
36
+
37
+ //--------------------------------------------------------------------------
38
+ input interrupt_do,
39
+ input [7:0] interrupt_vector,
40
+ output interrupt_done,
41
+
42
+ //-------------------------------------------------------------------------- memory bus
43
+ output [29:0] avm_address,
44
+ output [31:0] avm_writedata,
45
+ output [3:0] avm_byteenable,
46
+ output [3:0] avm_burstcount,
47
+ output avm_write,
48
+ output avm_read,
49
+
50
+ input avm_waitrequest,
51
+ input avm_readdatavalid,
52
+ input [31:0] avm_readdata,
53
+
54
+ //-------------------------------------------------------------------------- dma bus
55
+ input [23:0] dma_address,
56
+ input dma_16bit,
57
+ input dma_write,
58
+ input [15:0] dma_writedata,
59
+ input dma_read,
60
+ output [15:0] dma_readdata,
61
+ output dma_readdatavalid,
62
+ output dma_waitrequest,
63
+
64
+ //-------------------------------------------------------------------------- io bus
65
+ output io_read_do,
66
+ output [15:0] io_read_address,
67
+ output [2:0] io_read_length,
68
+ input [31:0] io_read_data,
69
+ input io_read_done,
70
+
71
+ output io_write_do,
72
+ output [15:0] io_write_address,
73
+ output [2:0] io_write_length,
74
+ output [31:0] io_write_data,
75
+ input io_write_done
76
+ );
77
+
78
+ //------------------------------------------------------------------------------
79
+
80
+ wire dec_gp_fault;
81
+ wire dec_ud_fault;
82
+ wire dec_pf_fault;
83
+ wire rd_seg_gp_fault;
84
+ wire rd_descriptor_gp_fault;
85
+ wire rd_seg_ss_fault;
86
+ wire rd_io_allow_fault;
87
+ wire rd_ss_esp_from_tss_fault;
88
+ wire exe_div_exception;
89
+ wire exe_trigger_gp_fault;
90
+ wire exe_trigger_ts_fault;
91
+ wire exe_trigger_ss_fault;
92
+ wire exe_trigger_np_fault;
93
+ wire exe_trigger_nm_fault;
94
+ wire exe_trigger_db_fault;
95
+ wire exe_trigger_pf_fault;
96
+ wire exe_bound_fault;
97
+ wire exe_load_seg_gp_fault;
98
+ wire exe_load_seg_ss_fault;
99
+ wire exe_load_seg_np_fault;
100
+ wire wr_debug_init;
101
+ wire wr_new_push_ss_fault;
102
+ wire wr_string_es_fault;
103
+ wire wr_push_ss_fault;
104
+
105
+ wire read_ac_fault;
106
+ wire read_page_fault;
107
+ wire write_ac_fault;
108
+ wire write_page_fault;
109
+ wire [15:0] tlb_code_pf_error_code;
110
+ wire [15:0] tlb_check_pf_error_code;
111
+ wire [15:0] tlb_write_pf_error_code;
112
+ wire [15:0] tlb_read_pf_error_code;
113
+
114
+ wire wr_int;
115
+ wire wr_int_soft_int;
116
+ wire wr_int_soft_int_ib;
117
+ wire [7:0] wr_int_vector;
118
+ wire wr_exception_external_set;
119
+ wire wr_exception_finished;
120
+
121
+ wire [31:0] eip;
122
+ wire [31:0] dec_eip;
123
+ wire [31:0] rd_eip;
124
+ wire [31:0] exe_eip;
125
+ wire [31:0] wr_eip;
126
+ wire [3:0] rd_consumed;
127
+ wire [3:0] exe_consumed;
128
+ wire [3:0] wr_consumed;
129
+
130
+ wire rd_dec_is_front;
131
+ wire rd_is_front;
132
+ wire exe_is_front;
133
+ wire wr_is_front;
134
+
135
+ wire wr_interrupt_possible;
136
+ wire wr_string_in_progress_final;
137
+ wire wr_is_esp_speculative;
138
+
139
+ wire real_mode;
140
+
141
+ wire [15:0] rd_error_code;
142
+ wire [15:0] exe_error_code;
143
+ wire [15:0] wr_error_code;
144
+
145
+ wire exc_dec_reset;
146
+ wire exc_micro_reset;
147
+ wire exc_rd_reset;
148
+ wire exc_exe_reset;
149
+ wire exc_wr_reset;
150
+
151
+ wire exc_restore_esp;
152
+ wire exc_set_rflag;
153
+ wire exc_debug_start;
154
+ wire exc_init;
155
+ wire exc_load;
156
+ wire [31:0] exc_eip;
157
+ wire [7:0] exc_vector;
158
+ wire [15:0] exc_error_code;
159
+ wire exc_push_error;
160
+ wire exc_soft_int;
161
+ wire exc_soft_int_ib;
162
+ wire exc_pf_read;
163
+ wire exc_pf_write;
164
+ wire exc_pf_code;
165
+ wire exc_pf_check;
166
+
167
+ wire [31:2] avm_address_pre;
168
+ assign avm_address = {avm_address_pre[31:21], avm_address_pre[20] & a20_enable, avm_address_pre[19:2]};
169
+
170
+ wire read_do;
171
+ wire read_done;
172
+
173
+ wire [1:0] read_cpl;
174
+ wire [31:0] read_address;
175
+ wire [3:0] read_length;
176
+ wire read_lock;
177
+ wire read_rmw;
178
+ wire [63:0] read_data;
179
+
180
+ wire write_do;
181
+ wire write_done;
182
+
183
+ wire [1:0] write_cpl;
184
+ wire [31:0] write_address;
185
+ wire [2:0] write_length;
186
+ wire write_lock;
187
+ wire write_rmw;
188
+ wire [31:0] write_data;
189
+
190
+ wire tlbcheck_do;
191
+ wire tlbcheck_done;
192
+ wire tlbcheck_page_fault;
193
+ wire [31:0] tlbcheck_address;
194
+ wire tlbcheck_rw;
195
+
196
+ wire tlbflushsingle_do;
197
+ wire tlbflushsingle_done;
198
+ wire [31:0] tlbflushsingle_address;
199
+
200
+ wire tlbflushall_do;
201
+ wire invdcode_do;
202
+ wire invdcode_done;
203
+ wire invddata_do;
204
+ wire invddata_done;
205
+ wire wbinvddata_do;
206
+ wire wbinvddata_done;
207
+
208
+ wire [1:0] prefetch_cpl;
209
+ wire [31:0] prefetch_eip;
210
+ wire [63:0] cs_cache;
211
+
212
+ wire cr0_pg;
213
+ wire cr0_wp;
214
+ wire cr0_am;
215
+ wire cr0_cd;
216
+ wire cr0_nw;
217
+
218
+ wire acflag;
219
+
220
+ wire [31:0] cr3;
221
+
222
+ wire prefetchfifo_accept_do;
223
+ wire [67:0] prefetchfifo_accept_data;
224
+ wire prefetchfifo_accept_empty;
225
+
226
+ wire pipeline_after_read_empty;
227
+ wire pipeline_after_prefetch_empty;
228
+
229
+ wire [31:0] tlb_code_pf_cr2;
230
+ wire [31:0] tlb_check_pf_cr2;
231
+ wire [31:0] tlb_write_pf_cr2;
232
+ wire [31:0] tlb_read_pf_cr2;
233
+
234
+ wire pr_reset;
235
+ wire rd_reset;
236
+ wire exe_reset;
237
+ wire wr_reset;
238
+
239
+
240
+ exception exception_inst(
241
+ .clk (clk),
242
+ .rst_n (rst_n),
243
+
244
+ //exception indicators
245
+ .dec_gp_fault (dec_gp_fault), //input
246
+ .dec_ud_fault (dec_ud_fault), //input
247
+ .dec_pf_fault (dec_pf_fault), //input
248
+
249
+ .rd_seg_gp_fault (rd_seg_gp_fault), //input
250
+ .rd_descriptor_gp_fault (rd_descriptor_gp_fault), //input
251
+ .rd_seg_ss_fault (rd_seg_ss_fault), //input
252
+ .rd_io_allow_fault (rd_io_allow_fault), //input
253
+ .rd_ss_esp_from_tss_fault (rd_ss_esp_from_tss_fault), //input
254
+
255
+ .exe_div_exception (exe_div_exception), //input
256
+ .exe_trigger_gp_fault (exe_trigger_gp_fault), //input
257
+ .exe_trigger_ts_fault (exe_trigger_ts_fault), //input
258
+ .exe_trigger_ss_fault (exe_trigger_ss_fault), //input
259
+ .exe_trigger_np_fault (exe_trigger_np_fault), //input
260
+ .exe_trigger_nm_fault (exe_trigger_nm_fault), //input
261
+ .exe_trigger_db_fault (exe_trigger_db_fault), //input
262
+ .exe_trigger_pf_fault (exe_trigger_pf_fault), //input
263
+ .exe_bound_fault (exe_bound_fault), //input
264
+ .exe_load_seg_gp_fault (exe_load_seg_gp_fault), //input
265
+ .exe_load_seg_ss_fault (exe_load_seg_ss_fault), //input
266
+ .exe_load_seg_np_fault (exe_load_seg_np_fault), //input
267
+
268
+ .wr_debug_init (wr_debug_init), //input
269
+ .wr_new_push_ss_fault (wr_new_push_ss_fault), //input
270
+ .wr_string_es_fault (wr_string_es_fault), //input
271
+ .wr_push_ss_fault (wr_push_ss_fault), //input
272
+
273
+ //from memory
274
+ .read_ac_fault (read_ac_fault), //input
275
+ .read_page_fault (read_page_fault), //input
276
+
277
+ .write_ac_fault (write_ac_fault), //input
278
+ .write_page_fault (write_page_fault), //input
279
+
280
+ .tlb_code_pf_error_code (tlb_code_pf_error_code), //input [15:0]
281
+ .tlb_check_pf_error_code (tlb_check_pf_error_code), //input [15:0]
282
+ .tlb_write_pf_error_code (tlb_write_pf_error_code), //input [15:0]
283
+ .tlb_read_pf_error_code (tlb_read_pf_error_code), //input [15:0]
284
+
285
+ //wr_int
286
+ .wr_int (wr_int), //input
287
+ .wr_int_soft_int (wr_int_soft_int), //input
288
+ .wr_int_soft_int_ib (wr_int_soft_int_ib), //input
289
+ .wr_int_vector (wr_int_vector), //input [7:0]
290
+
291
+ .wr_exception_external_set (wr_exception_external_set), //input
292
+ .wr_exception_finished (wr_exception_finished), //input
293
+
294
+ //eip
295
+ .eip (eip), //input [31:0]
296
+ .dec_eip (dec_eip), //input [31:0]
297
+ .rd_eip (rd_eip), //input [31:0]
298
+ .exe_eip (exe_eip), //input [31:0]
299
+ .wr_eip (wr_eip), //input [31:0]
300
+
301
+ .rd_consumed (rd_consumed), //input [3:0]
302
+ .exe_consumed (exe_consumed), //input [3:0]
303
+ .wr_consumed (wr_consumed), //input [3:0]
304
+
305
+ //pipeline
306
+ .rd_dec_is_front (rd_dec_is_front), //input
307
+ .rd_is_front (rd_is_front), //input
308
+ .exe_is_front (exe_is_front), //input
309
+ .wr_is_front (wr_is_front), //input
310
+
311
+ //interrupt
312
+ .interrupt_vector (interrupt_vector), //input [7:0]
313
+ .interrupt_done (interrupt_done), //output
314
+
315
+ //input
316
+ .wr_interrupt_possible (wr_interrupt_possible), //input
317
+ .wr_string_in_progress_final (wr_string_in_progress_final), //input
318
+ .wr_is_esp_speculative (wr_is_esp_speculative), //input
319
+
320
+ .real_mode (real_mode), //input
321
+
322
+ .rd_error_code (rd_error_code), //input [15:0]
323
+ .exe_error_code (exe_error_code), //input [15:0]
324
+ .wr_error_code (wr_error_code), //input [15:0]
325
+
326
+ //output
327
+ .exc_dec_reset (exc_dec_reset), //output
328
+ .exc_micro_reset (exc_micro_reset), //output
329
+ .exc_rd_reset (exc_rd_reset), //output
330
+ .exc_exe_reset (exc_exe_reset), //output
331
+ .exc_wr_reset (exc_wr_reset), //output
332
+
333
+ //exception output
334
+ .exc_restore_esp (exc_restore_esp), //output
335
+ .exc_set_rflag (exc_set_rflag), //output
336
+ .exc_debug_start (exc_debug_start), //output
337
+
338
+ .exc_init (exc_init), //output
339
+ .exc_load (exc_load), //output
340
+ .exc_eip (exc_eip), //output [31:0]
341
+
342
+ .exc_vector (exc_vector), //output [7:0]
343
+ .exc_error_code (exc_error_code), //output [15:0]
344
+ .exc_push_error (exc_push_error), //output
345
+ .exc_soft_int (exc_soft_int), //output
346
+ .exc_soft_int_ib (exc_soft_int_ib), //output
347
+
348
+ .exc_pf_read (exc_pf_read), //output
349
+ .exc_pf_write (exc_pf_write), //output
350
+ .exc_pf_code (exc_pf_code), //output
351
+ .exc_pf_check (exc_pf_check) //output
352
+ );
353
+
354
+
355
+ //------------------------------------------------------------------------------
356
+
357
+ wire glob_param_1_set;
358
+ wire [31:0] glob_param_1_value;
359
+ wire glob_param_2_set;
360
+ wire [31:0] glob_param_2_value;
361
+ wire glob_param_3_set;
362
+ wire [31:0] glob_param_3_value;
363
+ wire glob_param_4_set;
364
+ wire [31:0] glob_param_4_value;
365
+ wire glob_param_5_set;
366
+ wire [31:0] glob_param_5_value;
367
+ wire glob_descriptor_set;
368
+ wire [63:0] glob_descriptor_value;
369
+ wire glob_descriptor_2_set;
370
+ wire [63:0] glob_descriptor_2_value;
371
+ wire [31:0] glob_param_1;
372
+ wire [31:0] glob_param_2;
373
+ wire [31:0] glob_param_3;
374
+ wire [31:0] glob_param_4;
375
+ wire [31:0] glob_param_5;
376
+ wire [63:0] glob_descriptor;
377
+ wire [63:0] glob_descriptor_2;
378
+ wire [31:0] glob_desc_base;
379
+ wire [31:0] glob_desc_limit;
380
+ wire [31:0] glob_desc_2_limit;
381
+
382
+ global_regs global_regs_inst(
383
+ .clk (clk),
384
+ .rst_n (rst_n),
385
+
386
+ //input
387
+ .glob_param_1_set (glob_param_1_set), //input
388
+ .glob_param_1_value (glob_param_1_value), //input [31:0]
389
+ .glob_param_2_set (glob_param_2_set), //input
390
+ .glob_param_2_value (glob_param_2_value), //input [31:0]
391
+ .glob_param_3_set (glob_param_3_set), //input
392
+ .glob_param_3_value (glob_param_3_value), //input [31:0]
393
+ .glob_param_4_set (glob_param_4_set), //input
394
+ .glob_param_4_value (glob_param_4_value), //input [31:0]
395
+ .glob_param_5_set (glob_param_5_set), //input
396
+ .glob_param_5_value (glob_param_5_value), //input [31:0]
397
+ .glob_descriptor_set (glob_descriptor_set), //input
398
+ .glob_descriptor_value (glob_descriptor_value), //input [63:0]
399
+ .glob_descriptor_2_set (glob_descriptor_2_set), //input
400
+ .glob_descriptor_2_value (glob_descriptor_2_value), //input [63:0]
401
+
402
+ //output
403
+ .glob_param_1 (glob_param_1), //output [31:0]
404
+ .glob_param_2 (glob_param_2), //output [31:0]
405
+ .glob_param_3 (glob_param_3), //output [31:0]
406
+ .glob_param_4 (glob_param_4), //output [31:0]
407
+ .glob_param_5 (glob_param_5), //output [31:0]
408
+ .glob_descriptor (glob_descriptor), //output [63:0]
409
+ .glob_descriptor_2 (glob_descriptor_2), //output [63:0]
410
+ .glob_desc_base (glob_desc_base), //output [31:0]
411
+ .glob_desc_limit (glob_desc_limit), //output [31:0]
412
+ .glob_desc_2_limit (glob_desc_2_limit) //output [31:0]
413
+ );
414
+
415
+ //------------------------------------------------------------------------------
416
+
417
+
418
+ memory memory_inst(
419
+ .clk (clk),
420
+ .rst_n (rst_n),
421
+
422
+ .cache_disable (cache_disable),
423
+
424
+ //REQ:
425
+ .read_do (read_do), //input
426
+ .read_done (read_done), //output
427
+ .read_page_fault (read_page_fault), //output
428
+ .read_ac_fault (read_ac_fault), //output
429
+
430
+ .read_cpl (read_cpl), //input [1:0]
431
+ .read_address (read_address), //input [31:0]
432
+ .read_length (read_length), //input [3:0]
433
+ .read_lock (read_lock), //input
434
+ .read_rmw (read_rmw), //input
435
+ .read_data (read_data), //output [63:0]
436
+ //END
437
+
438
+ //REQ:
439
+ .write_do (write_do), //input
440
+ .write_done (write_done), //output
441
+ .write_page_fault (write_page_fault), //output
442
+ .write_ac_fault (write_ac_fault), //output
443
+
444
+ .write_cpl (write_cpl), //input [1:0]
445
+ .write_address (write_address), //input [31:0]
446
+ .write_length (write_length), //input [2:0]
447
+ .write_lock (write_lock), //input
448
+ .write_rmw (write_rmw), //input
449
+ .write_data (write_data), //input [31:0]
450
+ //END
451
+
452
+ //REQ:
453
+ .tlbcheck_do (tlbcheck_do), //input
454
+ .tlbcheck_done (tlbcheck_done), //output
455
+ .tlbcheck_page_fault (tlbcheck_page_fault), //output
456
+
457
+ .tlbcheck_address (tlbcheck_address), //input [31:0]
458
+ .tlbcheck_rw (tlbcheck_rw), //input
459
+ //END
460
+
461
+ //RESP:
462
+ .tlbflushsingle_do (tlbflushsingle_do), //input
463
+ .tlbflushsingle_done (tlbflushsingle_done), //output
464
+ .tlbflushsingle_address (tlbflushsingle_address), //input [31:0]
465
+ //END
466
+
467
+ .tlbflushall_do (tlbflushall_do), //input
468
+
469
+ .invdcode_do (invdcode_do), //input
470
+ .invdcode_done (invdcode_done), //output
471
+
472
+ .invddata_do (invddata_do), //input
473
+ .invddata_done (invddata_done), //output
474
+
475
+ .wbinvddata_do (wbinvddata_do), //input
476
+ .wbinvddata_done (wbinvddata_done), //output
477
+
478
+ // prefetch exported
479
+ .prefetch_cpl (prefetch_cpl), //input [1:0]
480
+ .prefetch_eip (prefetch_eip), //input [31:0]
481
+ .cs_cache (cs_cache), //input [63:0]
482
+
483
+ .cr0_pg (cr0_pg), //input
484
+ .cr0_wp (cr0_wp), //input
485
+ .cr0_am (cr0_am), //input
486
+ .cr0_cd (cr0_cd), //input
487
+ .cr0_nw (cr0_nw), //input
488
+
489
+ .acflag (acflag), //input
490
+
491
+ .cr3 (cr3), //input [31:0]
492
+
493
+ // prefetch_fifo exported
494
+ .prefetchfifo_accept_do (prefetchfifo_accept_do), //input
495
+ .prefetchfifo_accept_data (prefetchfifo_accept_data), //output [67:0]
496
+ .prefetchfifo_accept_empty (prefetchfifo_accept_empty), //output
497
+
498
+ // pipeline state
499
+ .pipeline_after_read_empty (pipeline_after_read_empty), //input
500
+ .pipeline_after_prefetch_empty (pipeline_after_prefetch_empty), //input
501
+
502
+ .tlb_code_pf_error_code (tlb_code_pf_error_code), //output [15:0]
503
+ .tlb_check_pf_error_code (tlb_check_pf_error_code), //output [15:0]
504
+ .tlb_write_pf_error_code (tlb_write_pf_error_code), //output [15:0]
505
+ .tlb_read_pf_error_code (tlb_read_pf_error_code), //output [15:0]
506
+
507
+ .tlb_code_pf_cr2 (tlb_code_pf_cr2), //output [31:0]
508
+ .tlb_check_pf_cr2 (tlb_check_pf_cr2), //output [31:0]
509
+ .tlb_write_pf_cr2 (tlb_write_pf_cr2), //output [31:0]
510
+ .tlb_read_pf_cr2 (tlb_read_pf_cr2), //output [31:0]
511
+
512
+ // reset exported
513
+ .pr_reset (pr_reset), //input
514
+ .rd_reset (rd_reset), //input
515
+ .exe_reset (exe_reset), //input
516
+ .wr_reset (wr_reset), //input
517
+
518
+ // avalon master
519
+ .avm_address (avm_address_pre), //output [31:0]
520
+ .avm_writedata (avm_writedata), //output [31:0]
521
+ .avm_byteenable (avm_byteenable), //output [3:0]
522
+ .avm_burstcount (avm_burstcount), //output [3:0]
523
+ .avm_write (avm_write), //output
524
+ .avm_read (avm_read), //output
525
+ .avm_waitrequest (avm_waitrequest), //input
526
+ .avm_readdatavalid (avm_readdatavalid), //input
527
+ .avm_readdata (avm_readdata), //input [31:0]
528
+
529
+ .dma_address (dma_address),
530
+ .dma_16bit (dma_16bit),
531
+ .dma_write (dma_write),
532
+ .dma_writedata (dma_writedata),
533
+ .dma_read (dma_read),
534
+ .dma_readdata (dma_readdata),
535
+ .dma_readdatavalid (dma_readdatavalid),
536
+ .dma_waitrequest (dma_waitrequest)
537
+ );
538
+
539
+ //------------------------------------------------------------------------------
540
+
541
+ pipeline pipeline_inst(
542
+ .clk (clk),
543
+ .rst_n (rst_n),
544
+
545
+ //to memory
546
+ .pr_reset (pr_reset), //output
547
+ .rd_reset (rd_reset), //output
548
+ .exe_reset (exe_reset), //output
549
+ .wr_reset (wr_reset), //output
550
+
551
+ .real_mode (real_mode), //output
552
+
553
+ //exception
554
+ .exc_restore_esp (exc_restore_esp), //input
555
+ .exc_set_rflag (exc_set_rflag), //input
556
+ .exc_debug_start (exc_debug_start), //input
557
+
558
+ .exc_init (exc_init), //input
559
+ .exc_load (exc_load), //input
560
+ .exc_eip (exc_eip), //input [31:0]
561
+
562
+ .exc_vector (exc_vector), //input [7:0]
563
+ .exc_error_code (exc_error_code), //input [15:0]
564
+ .exc_push_error (exc_push_error), //input
565
+ .exc_soft_int (exc_soft_int), //input
566
+ .exc_soft_int_ib (exc_soft_int_ib), //input
567
+
568
+ .exc_pf_read (exc_pf_read), //input
569
+ .exc_pf_write (exc_pf_write), //input
570
+ .exc_pf_code (exc_pf_code), //input
571
+ .exc_pf_check (exc_pf_check), //input
572
+
573
+ //pipeline eip
574
+ .eip (eip), //output [31:0]
575
+ .dec_eip (dec_eip), //output [31:0]
576
+ .rd_eip (rd_eip), //output [31:0]
577
+ .exe_eip (exe_eip), //output [31:0]
578
+ .wr_eip (wr_eip), //output [31:0]
579
+
580
+ .rd_consumed (rd_consumed), //output [3:0]
581
+ .exe_consumed (exe_consumed), //output [3:0]
582
+ .wr_consumed (wr_consumed), //output [3:0]
583
+
584
+ //exception reset
585
+ .exc_dec_reset (exc_dec_reset), //input
586
+ .exc_micro_reset (exc_micro_reset), //input
587
+ .exc_rd_reset (exc_rd_reset), //input
588
+ .exc_exe_reset (exc_exe_reset), //input
589
+ .exc_wr_reset (exc_wr_reset), //input
590
+
591
+ //global
592
+ .glob_param_1 (glob_param_1), //input [31:0]
593
+ .glob_param_2 (glob_param_2), //input [31:0]
594
+ .glob_param_3 (glob_param_3), //input [31:0]
595
+ .glob_param_4 (glob_param_4), //input [31:0]
596
+ .glob_param_5 (glob_param_5), //input [31:0]
597
+
598
+ .glob_descriptor (glob_descriptor), //input [63:0]
599
+ .glob_descriptor_2 (glob_descriptor_2), //input [63:0]
600
+
601
+ .glob_desc_base (glob_desc_base), //input [31:0]
602
+
603
+ .glob_desc_limit (glob_desc_limit), //input [31:0]
604
+ .glob_desc_2_limit (glob_desc_2_limit), //input [31:0]
605
+
606
+ //pipeline state
607
+ .rd_dec_is_front (rd_dec_is_front), //output
608
+ .rd_is_front (rd_is_front), //output
609
+ .exe_is_front (exe_is_front), //output
610
+ .wr_is_front (wr_is_front), //output
611
+
612
+ .pipeline_after_read_empty (pipeline_after_read_empty), //output
613
+ .pipeline_after_prefetch_empty (pipeline_after_prefetch_empty), //output
614
+
615
+ //dec exceptions
616
+ .dec_gp_fault (dec_gp_fault), //output
617
+ .dec_ud_fault (dec_ud_fault), //output
618
+ .dec_pf_fault (dec_pf_fault), //output
619
+
620
+ //rd exception
621
+ .rd_io_allow_fault (rd_io_allow_fault), //output
622
+ .rd_descriptor_gp_fault (rd_descriptor_gp_fault), //output
623
+ .rd_seg_gp_fault (rd_seg_gp_fault), //output
624
+ .rd_seg_ss_fault (rd_seg_ss_fault), //output
625
+ .rd_ss_esp_from_tss_fault (rd_ss_esp_from_tss_fault), //output
626
+
627
+ //exe exception
628
+ .exe_bound_fault (exe_bound_fault), //output
629
+ .exe_trigger_gp_fault (exe_trigger_gp_fault), //output
630
+ .exe_trigger_ts_fault (exe_trigger_ts_fault), //output
631
+ .exe_trigger_ss_fault (exe_trigger_ss_fault), //output
632
+ .exe_trigger_np_fault (exe_trigger_np_fault), //output
633
+ .exe_trigger_pf_fault (exe_trigger_pf_fault), //output
634
+ .exe_trigger_db_fault (exe_trigger_db_fault), //output
635
+ .exe_trigger_nm_fault (exe_trigger_nm_fault), //output
636
+ .exe_load_seg_gp_fault (exe_load_seg_gp_fault), //output
637
+ .exe_load_seg_ss_fault (exe_load_seg_ss_fault), //output
638
+ .exe_load_seg_np_fault (exe_load_seg_np_fault), //output
639
+ .exe_div_exception (exe_div_exception), //output
640
+
641
+ //wr exception
642
+ .wr_debug_init (wr_debug_init), //output
643
+ .wr_new_push_ss_fault (wr_new_push_ss_fault), //output
644
+ .wr_string_es_fault (wr_string_es_fault), //output
645
+ .wr_push_ss_fault (wr_push_ss_fault), //output
646
+
647
+ //error code
648
+ .rd_error_code (rd_error_code), //output [15:0]
649
+ .exe_error_code (exe_error_code), //output [15:0]
650
+ .wr_error_code (wr_error_code), //output [15:0]
651
+
652
+ //glob output
653
+ .glob_descriptor_set (glob_descriptor_set), //output
654
+ .glob_descriptor_value (glob_descriptor_value), //output [63:0]
655
+ .glob_descriptor_2_set (glob_descriptor_2_set), //output
656
+ .glob_descriptor_2_value (glob_descriptor_2_value), //output [63:0]
657
+
658
+ .glob_param_1_set (glob_param_1_set), //output
659
+ .glob_param_1_value (glob_param_1_value), //output [31:0]
660
+ .glob_param_2_set (glob_param_2_set), //output
661
+ .glob_param_2_value (glob_param_2_value), //output [31:0]
662
+ .glob_param_3_set (glob_param_3_set), //output
663
+ .glob_param_3_value (glob_param_3_value), //output [31:0]
664
+ .glob_param_4_set (glob_param_4_set), //output
665
+ .glob_param_4_value (glob_param_4_value), //output [31:0]
666
+ .glob_param_5_set (glob_param_5_set), //output
667
+ .glob_param_5_value (glob_param_5_value), //output [31:0]
668
+
669
+ // prefetch
670
+ .prefetch_cpl (prefetch_cpl), //output [1:0]
671
+ .prefetch_eip (prefetch_eip), //output [31:0]
672
+
673
+ .cs_cache (cs_cache), //output [63:0]
674
+
675
+ .cr0_pg (cr0_pg), //output
676
+ .cr0_wp (cr0_wp), //output
677
+ .cr0_am (cr0_am), //output
678
+ .cr0_cd (cr0_cd), //output
679
+ .cr0_nw (cr0_nw), //output
680
+
681
+ .acflag (acflag), //output
682
+
683
+ .cr3 (cr3), //output [31:0]
684
+
685
+ // prefetch_fifo
686
+ .prefetchfifo_accept_do (prefetchfifo_accept_do), //output
687
+ .prefetchfifo_accept_data (prefetchfifo_accept_data), //input [67:0]
688
+ .prefetchfifo_accept_empty (prefetchfifo_accept_empty), //input
689
+
690
+ //io_read
691
+ .io_read_do (io_read_do), //output
692
+ .io_read_address (io_read_address), //output [15:0]
693
+ .io_read_length (io_read_length), //output [2:0]
694
+ .io_read_data (io_read_data), //input [31:0]
695
+ .io_read_done (io_read_done), //input
696
+
697
+ //read memory
698
+ .read_do (read_do), //output
699
+ .read_done (read_done), //input
700
+ .read_page_fault (read_page_fault), //input
701
+ .read_ac_fault (read_ac_fault), //input
702
+
703
+ .read_cpl (read_cpl), //output [1:0]
704
+ .read_address (read_address), //output [31:0]
705
+ .read_length (read_length), //output [3:0]
706
+ .read_lock (read_lock), //output
707
+ .read_rmw (read_rmw), //output
708
+ .read_data (read_data), //input [63:0]
709
+
710
+ //tlbcheck
711
+ .tlbcheck_do (tlbcheck_do), //output
712
+ .tlbcheck_done (tlbcheck_done), //input
713
+ .tlbcheck_page_fault (tlbcheck_page_fault), //input
714
+
715
+ .tlbcheck_address (tlbcheck_address), //output [31:0]
716
+ .tlbcheck_rw (tlbcheck_rw), //output
717
+
718
+ //tlbflushsingle
719
+ .tlbflushsingle_do (tlbflushsingle_do), //output
720
+ .tlbflushsingle_done (tlbflushsingle_done), //input
721
+
722
+ .tlbflushsingle_address (tlbflushsingle_address), //output [31:0]
723
+
724
+ //flush tlb
725
+ .tlbflushall_do (tlbflushall_do), //output
726
+
727
+ .invdcode_do (invdcode_do), //output
728
+ .invdcode_done (invdcode_done), //input
729
+
730
+ .invddata_do (invddata_do), //output
731
+ .invddata_done (invddata_done), //input
732
+
733
+ .wbinvddata_do (wbinvddata_do), //output
734
+ .wbinvddata_done (wbinvddata_done), //input
735
+
736
+ //interrupt
737
+ .interrupt_do (interrupt_do), //input
738
+
739
+ .wr_interrupt_possible (wr_interrupt_possible), //output
740
+ .wr_string_in_progress_final (wr_string_in_progress_final), //output
741
+ .wr_is_esp_speculative (wr_is_esp_speculative), //output
742
+
743
+ //software interrupt
744
+ .wr_int (wr_int), //output
745
+ .wr_int_soft_int (wr_int_soft_int), //output
746
+ .wr_int_soft_int_ib (wr_int_soft_int_ib), //output
747
+ .wr_int_vector (wr_int_vector), //output [7:0]
748
+
749
+ .wr_exception_external_set (wr_exception_external_set), //output
750
+ .wr_exception_finished (wr_exception_finished), //output
751
+
752
+ //memory page fault
753
+ .tlb_code_pf_cr2 (tlb_code_pf_cr2), //input [31:0]
754
+ .tlb_write_pf_cr2 (tlb_write_pf_cr2), //input [31:0]
755
+ .tlb_read_pf_cr2 (tlb_read_pf_cr2), //input [31:0]
756
+ .tlb_check_pf_cr2 (tlb_check_pf_cr2), //input [31:0]
757
+
758
+ //memory write
759
+ .write_do (write_do), //output
760
+ .write_done (write_done), //input
761
+ .write_page_fault (write_page_fault), //input
762
+ .write_ac_fault (write_ac_fault), //input
763
+
764
+ .write_cpl (write_cpl), //output [1:0]
765
+ .write_address (write_address), //output [31:0]
766
+ .write_length (write_length), //output [2:0]
767
+ .write_lock (write_lock), //output
768
+ .write_rmw (write_rmw), //output
769
+ .write_data (write_data), //output [31:0]
770
+
771
+ //io write
772
+ .io_write_do (io_write_do), //output
773
+ .io_write_address (io_write_address), //output [15:0]
774
+ .io_write_length (io_write_length), //output [2:0]
775
+ .io_write_data (io_write_data), //output [31:0]
776
+ .io_write_done (io_write_done) //input
777
+ );
778
+
779
+ //------------------------------------------------------------------------------
780
+
781
+ endmodule
snapshots/MiSTer-devel_ao486_MiSTer_pr72/rtl/ao486/autogen/decode_commands.v ADDED
@@ -0,0 +1,737 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ //======================================================== conditions
2
+ wire cond_0 = dec_ready_2byte_modregrm && { decoder[7:1], 1'b0 } == 8'hC0;
3
+ wire cond_1 = prefix_group_1_lock && `DEC_MODREGRM_IS_MOD_11;
4
+ wire cond_2 = decoder[0] == 1'b0;
5
+ wire cond_3 = dec_ready_one_one && decoder[7:0] == 8'hE3;
6
+ wire cond_4 = prefix_group_1_lock ;
7
+ wire cond_5 = dec_ready_call_jmp_imm && (decoder[7:0] == 8'h9A || decoder[7:0] == 8'hE8);
8
+ wire cond_6 = decoder[1] == 1'b0;
9
+ wire cond_7 = dec_ready_modregrm_one && decoder[7:0] == 8'hFF && (decoder[13:11] == 3'd2 || decoder[13:11] == 3'd3);
10
+ wire cond_8 = prefix_group_1_lock || (decoder[13:11] == 3'd3 && `DEC_MODREGRM_IS_MOD_11);
11
+ wire cond_9 = decoder[11] == 1'b0;
12
+ wire cond_10 = (dec_ready_one && (decoder[7:0] == 8'h06 || decoder[7:0] == 8'h16 || decoder[7:0] == 8'h0E || decoder[7:0] == 8'h1E)) || (dec_ready_2byte_one && (decoder[7:0] == 8'hA0 || decoder[7:0] == 8'hA8));
13
+ wire cond_11 = dec_ready_modregrm_one && decoder[7:0] == 8'h8C;
14
+ wire cond_12 = prefix_group_1_lock || decoder[13:11] >= 3'd6;
15
+ wire cond_13 = dec_ready_2byte_modregrm && decoder[7:0] == 8'h00 && decoder[13:11] == 3'd0;
16
+ wire cond_14 = prefix_group_1_lock || ~(protected_mode);
17
+ wire cond_15 = dec_ready_2byte_modregrm && decoder[7:0] == 8'h00 && decoder[13:11] == 3'd1;
18
+ wire cond_16 = dec_ready_modregrm_one && { decoder[7:1], 1'b0 } == 8'hF6 && decoder[13:11] == 3'd3;
19
+ wire cond_17 = (dec_ready_one_one && decoder[7:4] == 4'h7) || (dec_ready_2byte_imm && decoder[7:4] == 4'h8);
20
+ wire cond_18 = ~(dec_prefix_2byte);
21
+ wire cond_19 = dec_prefix_2byte;
22
+ wire cond_20 = dec_ready_2byte_one && decoder[7:0] == 8'h08;
23
+ wire cond_21 = dec_ready_2byte_modregrm && decoder[7:0] == 8'h01 && decoder[13:11] == 3'd7;
24
+ wire cond_22 = prefix_group_1_lock || `DEC_MODREGRM_IS_MOD_11;
25
+ wire cond_23 = dec_ready_one && decoder[7:0] == 8'hF4;
26
+ wire cond_24 = dec_ready_one && { decoder[7:1], 1'b0 } == 8'hAE;
27
+ wire cond_25 = dec_prefix_group_1_rep != 2'd0;
28
+ wire cond_26 = dec_ready_one && decoder[7:4] == 4'h4;
29
+ wire cond_27 = dec_ready_modregrm_one && { decoder[7:1], 1'b0 } == 8'hFE && { decoder[13:12], 1'b0 } == 3'b000;
30
+ wire cond_28 = (dec_ready_one && decoder[7:0] == 8'hC3) || (dec_ready_one_two && decoder[7:0] == 8'hC2);
31
+ wire cond_29 = dec_ready_modregrm_one && decoder[7:0] == 8'h63;
32
+ wire cond_30 = dec_ready_2byte_one && { decoder[7:3], 3'b000 } == 8'hC8;
33
+ wire cond_31 = (dec_ready_modregrm_one && (decoder[7:0] == 8'hC4 || decoder[7:0] == 8'hC5)) || (dec_ready_2byte_modregrm && (decoder[7:0] == 8'hB2 || decoder[7:0] == 8'hB4 || decoder[7:0] == 8'hB5));
34
+ wire cond_32 = dec_ready_modregrm_one && decoder[7:0] == 8'h8E;
35
+ wire cond_33 = prefix_group_1_lock || decoder[13:11] >= 3'd6 || decoder[13:11] == 3'd1;
36
+ wire cond_34 = dec_ready_2byte_modregrm && decoder[7:0] == 8'h00 && decoder[13:11] == 3'd2;
37
+ wire cond_35 = dec_ready_2byte_modregrm && decoder[7:0] == 8'h00 && decoder[13:11] == 3'd3;
38
+ wire cond_36 = dec_ready_one && decoder[7:0] == 8'hF8;
39
+ wire cond_37 = dec_ready_one && decoder[7:0] == 8'hFC;
40
+ wire cond_38 = dec_ready_one && decoder[7:0] == 8'hF5;
41
+ wire cond_39 = dec_ready_one && decoder[7:0] == 8'hF9;
42
+ wire cond_40 = dec_ready_one && decoder[7:0] == 8'hFD;
43
+ wire cond_41 = dec_ready_one && decoder[7:0] == 8'h9E;
44
+ wire cond_42 = dec_ready_one_one && decoder[7:0] == 8'hD5;
45
+ wire cond_43 = dec_ready_one_one && decoder[7:0] == 8'hD4;
46
+ wire cond_44 = (dec_ready_one && (decoder[7:0] == 8'h07 || decoder[7:0] == 8'h17 || decoder[7:0] == 8'h1F)) || (dec_ready_2byte_one && (decoder[7:0] == 8'hA1 || decoder[7:0] == 8'hA9));
47
+ wire cond_45 = (dec_ready_2byte_modregrm && decoder[7:0] == 8'hA3) || (dec_ready_2byte_modregrm_imm && decoder[7:0] == 8'hBA && decoder[13:11] == 3'd4);
48
+ wire cond_46 = (dec_ready_2byte_modregrm && decoder[7:0] == 8'hB3) || (dec_ready_2byte_modregrm_imm && decoder[7:0] == 8'hBA && decoder[13:11] == 3'd6);
49
+ wire cond_47 = (dec_ready_2byte_modregrm && decoder[7:0] == 8'hAB) || (dec_ready_2byte_modregrm_imm && decoder[7:0] == 8'hBA && decoder[13:11] == 3'd5);
50
+ wire cond_48 = (dec_ready_2byte_modregrm && decoder[7:0] == 8'hBB) || (dec_ready_2byte_modregrm_imm && decoder[7:0] == 8'hBA && decoder[13:11] == 3'd7);
51
+ wire cond_49 = dec_ready_one && decoder[7:0] == 8'hCF;
52
+ wire cond_50 = ~(protected_mode);
53
+ wire cond_51 = dec_ready_one && { decoder[7:3], 3'b0 } == 8'h58;
54
+ wire cond_52 = dec_ready_modregrm_one && decoder[7:0] == 8'h8F && decoder[13:11] == 3'd0;
55
+ wire cond_53 = dec_ready_modregrm_one && { decoder[7:1], 1'b0 } == 8'hF6 && decoder[13:11] == 3'd6;
56
+ wire cond_54 = dec_ready_modregrm_one && { decoder[7:1], 1'b0 } == 8'hF6 && decoder[13:11] == 3'd7;
57
+ wire cond_55 = dec_ready_modregrm_one && { decoder[7:2], 2'b0 } == 8'hD0;
58
+ wire cond_56 = decoder[1];
59
+ wire cond_57 = dec_ready_modregrm_imm && { decoder[7:1], 1'b0 } == 8'hC0;
60
+ wire cond_58 = dec_ready_one && { decoder[7:1], 1'b0 } == 8'hA6;
61
+ wire cond_59 = dec_ready_2byte_modregrm && decoder[7:0] == 8'h01 && decoder[13:11] == 3'd4;
62
+ wire cond_60 = dec_ready_2byte_modregrm && decoder[7:0] == 8'h01 && decoder[13:11] == 3'd6;
63
+ wire cond_61 = dec_ready_2byte_modregrm && { decoder[7:2], 1'b0, decoder[0] } == 8'h20;
64
+ wire cond_62 = prefix_group_1_lock || (decoder[13:11] != 3'd0 && decoder[13:11] != 3'd2 && decoder[13:11] != 3'd3);
65
+ wire cond_63 = dec_ready_2byte_modregrm && decoder[7:0] == 8'h01 && decoder[13:11] == 3'd2;
66
+ wire cond_64 = dec_ready_2byte_modregrm && decoder[7:0] == 8'h01 && decoder[13:11] == 3'd3;
67
+ wire cond_65 = dec_ready_one && decoder[7:0] == 8'h60;
68
+ wire cond_66 = dec_ready_one && decoder[7:0] == 8'h9B;
69
+ wire cond_67 = dec_ready_modregrm_one && { decoder[7:3], 3'b0 } == 8'hD8;
70
+ wire cond_68 = dec_ready_2byte_modregrm && decoder[7:4] == 4'h9;
71
+ wire cond_69 = dec_ready_2byte_modregrm && { decoder[7:1], 1'b0 } == 8'hB0;
72
+ wire cond_70 = dec_ready_one_three && decoder[7:0] == 8'hC8;
73
+ wire cond_71 = (dec_ready_modregrm_one && ({ decoder[7:1], 1'b0 } == 8'hF6 && decoder[13:11] == 3'd5)) || (dec_ready_2byte_modregrm && decoder[7:0] == 8'hAF);
74
+ wire cond_72 = dec_ready_modregrm_imm && (decoder[7:0] == 8'h69 || decoder[7:0] == 8'h6B);
75
+ wire cond_73 = dec_ready_one && decoder[7:0] == 8'hC9;
76
+ wire cond_74 = (dec_ready_2byte_modregrm && decoder[7:0] == 8'hA5) || (dec_ready_2byte_modregrm_imm && decoder[7:0] == 8'hA4);
77
+ wire cond_75 = decoder[0];
78
+ wire cond_76 = (dec_ready_2byte_modregrm && decoder[7:0] == 8'hAD) || (dec_ready_2byte_modregrm_imm && decoder[7:0] == 8'hAC);
79
+ wire cond_77 = dec_ready_2byte_one && decoder[7:0] == 8'h09;
80
+ wire cond_78 = dec_ready_one_imm && decoder[7:6] == 2'b00 && decoder[2:1] == 2'b10;
81
+ wire cond_79 = dec_ready_modregrm_one && decoder[7:6] == 2'b00 && decoder[2] == 1'b0;
82
+ wire cond_80 = prefix_group_1_lock && (decoder[1] == 1'b1 || `DEC_MODREGRM_IS_MOD_11 || decoder[5:3] == 3'b111);
83
+ wire cond_81 = dec_ready_modregrm_imm && { decoder[7:2], 2'b00 } == 8'h80;
84
+ wire cond_82 = prefix_group_1_lock && (decoder[13:11] == 3'b111 || `DEC_MODREGRM_IS_MOD_11);
85
+ wire cond_83 = dec_ready_modregrm_one && { decoder[7:1], 1'b0 } == 8'hF6 && decoder[13:11] == 3'd4;
86
+ wire cond_84 = dec_ready_one_one && (decoder[7:0] == 8'hE0 || decoder[7:0] == 8'hE1 || decoder[7:0] == 8'hE2);
87
+ wire cond_85 = dec_ready_one_imm && { decoder[7:1], 1'b0 } == 8'hA8;
88
+ wire cond_86 = dec_ready_modregrm_one && { decoder[7:1], 1'b0 } == 8'h84;
89
+ wire cond_87 = dec_ready_modregrm_imm && { decoder[7:1], 1'b0 } == 8'hF6 && { decoder[13:12], 1'b0 } == 3'd0;
90
+ wire cond_88 = dec_ready_2byte_one && decoder[7:0] == 8'h06;
91
+ wire cond_89 = (dec_ready_one && decoder[7:0] == 8'hCB) || (dec_ready_one_two && decoder[7:0] == 8'hCA);
92
+ wire cond_90 = dec_ready_one && { decoder[7:1], 1'b0 } == 8'hAC;
93
+ wire cond_91 = dec_ready_one && { decoder[7:3], 3'b0 } == 8'h90;
94
+ wire cond_92 = dec_ready_modregrm_one && { decoder[7:1], 1'b0 } == 8'h86;
95
+ wire cond_93 = dec_ready_one && { decoder[7:3], 3'b0 } == 8'h50;
96
+ wire cond_94 = dec_ready_one_imm && (decoder[7:0] == 8'h6A || decoder[7:0] == 8'h68);
97
+ wire cond_95 = dec_ready_modregrm_one && decoder[7:0] == 8'hFF && decoder[13:11] == 3'd6;
98
+ wire cond_96 = (dec_ready_one && (decoder[7:0] == 8'hCC || decoder[7:0] == 8'hCE || decoder[7:0] == 8'hF1)) || (dec_ready_one_one && decoder[7:0] == 8'hCD);
99
+ wire cond_97 = (decoder[0] ^ decoder[2]) == 1'b1;
100
+ wire cond_98 = dec_ready_2byte_one && decoder[7:0] == 8'hA2;
101
+ wire cond_99 = (dec_ready_one && { decoder[7:1], 1'b0 } == 8'hEC) || (dec_ready_one_one && { decoder[7:1], 1'b0 } == 8'hE4);
102
+ wire cond_100 = decoder[3];
103
+ wire cond_101 = decoder[3] == 1'b1;
104
+ wire cond_102 = dec_ready_modregrm_one && { decoder[7:1], 1'b0 } == 8'hF6 && decoder[13:11] == 3'd2;
105
+ wire cond_103 = dec_ready_2byte_modregrm && decoder[7:0] == 8'h00 && decoder[13:11] == 3'd4;
106
+ wire cond_104 = dec_ready_2byte_modregrm && decoder[7:0] == 8'h00 && decoder[13:11] == 3'd5;
107
+ wire cond_105 = dec_ready_2byte_modregrm && decoder[7:0] == 8'h02;
108
+ wire cond_106 = dec_ready_2byte_modregrm && decoder[7:0] == 8'h03;
109
+ wire cond_107 = dec_ready_one && { decoder[7:1], 1'b0 } == 8'hAA;
110
+ wire cond_108 = dec_ready_one && { decoder[7:1], 1'b0 } == 8'h6C;
111
+ wire cond_109 = dec_ready_one && { decoder[7:1], 1'b0 } == 8'h6E;
112
+ wire cond_110 = dec_ready_one && decoder[7:0] == 8'h9C;
113
+ wire cond_111 = dec_ready_call_jmp_imm && (decoder[7:0] == 8'hEA || decoder[7:0] == 8'hE9 || decoder[7:0] == 8'hEB);
114
+ wire cond_112 = decoder[3:0] == 4'hB;
115
+ wire cond_113 = dec_ready_modregrm_one && decoder[7:0] == 8'hFF && (decoder[13:11] == 3'd4 || decoder[13:11] == 3'd5);
116
+ wire cond_114 = prefix_group_1_lock || (decoder[13:11] == 3'd5 && `DEC_MODREGRM_IS_MOD_11);
117
+ wire cond_115 = (dec_ready_one && { decoder[7:1], 1'b0 } == 8'hEE) || (dec_ready_one_one && { decoder[7:1], 1'b0 } == 8'hE6);
118
+ wire cond_116 = dec_ready_mem_offset && { decoder[7:2], 2'b0 } == 8'hA0;
119
+ wire cond_117 = dec_ready_one_imm && decoder[7:4] == 4'hB;
120
+ wire cond_118 = decoder[3] == 1'b0;
121
+ wire cond_119 = dec_ready_modregrm_one && { decoder[7:2], 2'b0 } == 8'h88;
122
+ wire cond_120 = dec_ready_modregrm_imm && { decoder[7:1], 1'b0 } == 8'hC6 && decoder[13:11] == 3'd0;
123
+ wire cond_121 = dec_ready_one && decoder[7:0] == 8'h9F;
124
+ wire cond_122 = dec_ready_one && decoder[7:0] == 8'h98;
125
+ wire cond_123 = dec_ready_one && decoder[7:0] == 8'h99;
126
+ wire cond_124 = dec_ready_one && decoder[7:0] == 8'h9D;
127
+ wire cond_125 = dec_ready_one && decoder[7:0] == 8'hFA;
128
+ wire cond_126 = dec_ready_one && decoder[7:0] == 8'hFB;
129
+ wire cond_127 = dec_ready_modregrm_one && decoder[7:0] == 8'h62;
130
+ wire cond_128 = dec_ready_one && decoder[7:0] == 8'hD6;
131
+ wire cond_129 = dec_ready_modregrm_one && decoder[7:0] == 8'h8D;
132
+ wire cond_130 = dec_ready_2byte_modregrm && decoder[7:0] == 8'h01 && decoder[13:11] == 3'd0;
133
+ wire cond_131 = dec_ready_2byte_modregrm && decoder[7:0] == 8'h01 && decoder[13:11] == 3'd1;
134
+ wire cond_132 = dec_ready_one && { decoder[7:1], 1'b0 } == 8'hA4;
135
+ wire cond_133 = dec_ready_2byte_modregrm && { decoder[7:1], 1'b0 } == 8'hB6;
136
+ wire cond_134 = dec_ready_2byte_modregrm && { decoder[7:1], 1'b0 } == 8'hBE;
137
+ wire cond_135 = dec_ready_one && decoder[7:0] == 8'h61;
138
+ wire cond_136 = dec_ready_2byte_modregrm && { decoder[7:2], 1'b0, decoder[0] } == 8'h21;
139
+ wire cond_137 = dec_ready_one && decoder[7:0] == 8'hD7;
140
+ wire cond_138 = dec_ready_one && decoder[7:0] == 8'h37;
141
+ wire cond_139 = dec_ready_one && decoder[7:0] == 8'h3F;
142
+ wire cond_140 = dec_ready_one && decoder[7:0] == 8'h27;
143
+ wire cond_141 = dec_ready_one && decoder[7:0] == 8'h2F;
144
+ wire cond_142 = dec_ready_2byte_modregrm && decoder[7:0] == 8'hBC;
145
+ wire cond_143 = dec_ready_2byte_modregrm && decoder[7:0] == 8'hBD;
146
+ //======================================================== saves
147
+ //======================================================== always
148
+ //======================================================== sets
149
+ assign consume_mem_offset =
150
+ (cond_116 && ~cond_4)? (`TRUE) :
151
+ 1'd0;
152
+ assign dec_cmd =
153
+ (cond_0 && ~cond_1)? ( `CMD_XADD) :
154
+ (cond_3 && ~cond_4)? ( `CMD_JCXZ) :
155
+ (cond_5 && ~cond_4)? ( `CMD_CALL) :
156
+ (cond_7 && ~cond_8)? ( `CMD_CALL) :
157
+ (cond_10 && ~cond_4)? ( `CMD_PUSH_MOV_SEG) :
158
+ (cond_11 && ~cond_12)? ( `CMD_PUSH_MOV_SEG) :
159
+ (cond_13 && ~cond_14)? ( `CMD_PUSH_MOV_SEG) :
160
+ (cond_15 && ~cond_14)? ( `CMD_PUSH_MOV_SEG) :
161
+ (cond_16 && ~cond_1)? ( `CMD_NEG) :
162
+ (cond_17 && ~cond_4)? ( `CMD_Jcc) :
163
+ (cond_20 && ~cond_4)? ( `CMD_INVD) :
164
+ (cond_21 && ~cond_22)? ( `CMD_INVLPG) :
165
+ (cond_23 && ~cond_4)? ( `CMD_HLT) :
166
+ (cond_24 && ~cond_4)? ( `CMD_SCAS) :
167
+ (cond_26 && ~cond_4)? ( `CMD_INC_DEC) :
168
+ (cond_27 && ~cond_1)? ( `CMD_INC_DEC) :
169
+ (cond_28 && ~cond_4)? ( `CMD_RET_near) :
170
+ (cond_29 && ~cond_14)? ( `CMD_ARPL) :
171
+ (cond_30 && ~cond_4)? ( `CMD_BSWAP) :
172
+ (cond_31 && ~cond_22)? ( `CMD_LxS) :
173
+ (cond_32 && ~cond_33)? ( `CMD_MOV_to_seg) :
174
+ (cond_34 && ~cond_14)? ( `CMD_LLDT) :
175
+ (cond_35 && ~cond_14)? ( `CMD_LTR) :
176
+ (cond_36 && ~cond_4)? ( `CMD_CLC) :
177
+ (cond_37 && ~cond_4)? ( `CMD_CLD) :
178
+ (cond_38 && ~cond_4)? ( `CMD_CMC) :
179
+ (cond_39 && ~cond_4)? ( `CMD_STC) :
180
+ (cond_40 && ~cond_4)? ( `CMD_STD) :
181
+ (cond_41 && ~cond_4)? ( `CMD_SAHF) :
182
+ (cond_42 && ~cond_4)? ( `CMD_AAD) :
183
+ (cond_43 && ~cond_4)? ( `CMD_AAM) :
184
+ (cond_44 && ~cond_4)? ( `CMD_POP_seg) :
185
+ (cond_45 && ~cond_4)? ( `CMD_BT) :
186
+ (cond_46 && ~cond_1)? ( `CMD_BTR) :
187
+ (cond_47 && ~cond_1)? ( `CMD_BTS) :
188
+ (cond_48 && ~cond_1)? ( `CMD_BTC) :
189
+ (cond_49 && ~cond_4)? ( `CMD_IRET) :
190
+ (cond_51 && ~cond_4)? ( `CMD_POP) :
191
+ (cond_52 && ~cond_4)? ( `CMD_POP) :
192
+ (cond_53 && ~cond_4)? ( `CMD_DIV) :
193
+ (cond_54 && ~cond_4)? ( `CMD_IDIV) :
194
+ (cond_55 && ~cond_4)? ( `CMD_Shift) :
195
+ (cond_57 && ~cond_4)? ( `CMD_Shift) :
196
+ (cond_58 && ~cond_4)? ( `CMD_CMPS) :
197
+ (cond_59 && ~cond_4)? ( `CMD_control_reg) :
198
+ (cond_60 && ~cond_4)? ( `CMD_control_reg) :
199
+ (cond_61 && ~cond_62)? ( `CMD_control_reg) :
200
+ (cond_63 && ~cond_22)? ( `CMD_LGDT) :
201
+ (cond_64 && ~cond_22)? ( `CMD_LIDT) :
202
+ (cond_65 && ~cond_4)? ( `CMD_PUSHA) :
203
+ (cond_66 && ~cond_4)? ( `CMD_fpu) :
204
+ (cond_67 && ~cond_4)? ( `CMD_fpu) :
205
+ (cond_68 && ~cond_4)? ( `CMD_SETcc) :
206
+ (cond_69 && ~cond_1)? ( `CMD_CMPXCHG) :
207
+ (cond_70 && ~cond_4)? ( `CMD_ENTER) :
208
+ (cond_71 && ~cond_4)? ( `CMD_IMUL) :
209
+ (cond_72 && ~cond_4)? ( `CMD_IMUL) :
210
+ (cond_73 && ~cond_4)? ( `CMD_LEAVE) :
211
+ (cond_74 && ~cond_4)? ( `CMD_SHLD) :
212
+ (cond_76 && ~cond_4)? ( `CMD_SHRD) :
213
+ (cond_77 && ~cond_4)? ( `CMD_WBINVD) :
214
+ (cond_78 && ~cond_4)? ( {`CMD_Arith | { 4'd0, decoder[5:3] } }) :
215
+ (cond_79 && ~cond_80)? ( {`CMD_Arith | { 4'd0, decoder[5:3] } }) :
216
+ (cond_81 && ~cond_82)? ( {`CMD_Arith | { 4'd0, decoder[13:11] } }) :
217
+ (cond_83 && ~cond_4)? ( `CMD_MUL) :
218
+ (cond_84 && ~cond_4)? ( `CMD_LOOP) :
219
+ (cond_85 && ~cond_4)? ( `CMD_TEST) :
220
+ (cond_86 && ~cond_4)? ( `CMD_TEST) :
221
+ (cond_87 && ~cond_4)? ( `CMD_TEST) :
222
+ (cond_88 && ~cond_4)? ( `CMD_CLTS) :
223
+ (cond_89 && ~cond_4)? ( `CMD_RET_far) :
224
+ (cond_90 && ~cond_4)? ( `CMD_LODS) :
225
+ (cond_91 && ~cond_4)? ( `CMD_XCHG) :
226
+ (cond_92 && ~cond_1)? ( `CMD_XCHG) :
227
+ (cond_93 && ~cond_4)? ( `CMD_PUSH) :
228
+ (cond_94 && ~cond_4)? ( `CMD_PUSH) :
229
+ (cond_95 && ~cond_4)? ( `CMD_PUSH) :
230
+ (cond_96 && ~cond_4)? ( `CMD_INT_INTO) :
231
+ (cond_98 && ~cond_4)? ( `CMD_CPUID) :
232
+ (cond_99 && ~cond_4)? ( `CMD_IN) :
233
+ (cond_102 && ~cond_1)? ( `CMD_NOT) :
234
+ (cond_103 && ~cond_14)? ( `CMD_VERR) :
235
+ (cond_104 && ~cond_14)? ( `CMD_VERW) :
236
+ (cond_105 && ~cond_14)? ( `CMD_LAR) :
237
+ (cond_106 && ~cond_14)? ( `CMD_LSL) :
238
+ (cond_107 && ~cond_4)? ( `CMD_STOS) :
239
+ (cond_108 && ~cond_4)? ( `CMD_INS) :
240
+ (cond_109 && ~cond_4)? ( `CMD_OUTS) :
241
+ (cond_110 && ~cond_4)? ( `CMD_PUSHF) :
242
+ (cond_111 && ~cond_4)? ( `CMD_JMP) :
243
+ (cond_113 && ~cond_114)? ( `CMD_JMP) :
244
+ (cond_115 && ~cond_4)? ( `CMD_OUT) :
245
+ (cond_116 && ~cond_4)? ( `CMD_MOV) :
246
+ (cond_117 && ~cond_4)? ( `CMD_MOV) :
247
+ (cond_119 && ~cond_4)? ( `CMD_MOV) :
248
+ (cond_120 && ~cond_4)? ( `CMD_MOV) :
249
+ (cond_121 && ~cond_4)? ( `CMD_LAHF) :
250
+ (cond_122 && ~cond_4)? ( `CMD_CBW) :
251
+ (cond_123 && ~cond_4)? ( `CMD_CWD) :
252
+ (cond_124 && ~cond_4)? ( `CMD_POPF) :
253
+ (cond_125 && ~cond_4)? ( `CMD_CLI) :
254
+ (cond_126 && ~cond_4)? ( `CMD_STI) :
255
+ (cond_127 && ~cond_22)? ( `CMD_BOUND) :
256
+ (cond_128 && ~cond_4)? ( `CMD_SALC) :
257
+ (cond_129 && ~cond_22)? ( `CMD_LEA) :
258
+ (cond_130 && ~cond_22)? ( `CMD_SGDT) :
259
+ (cond_131 && ~cond_22)? ( `CMD_SIDT) :
260
+ (cond_132 && ~cond_4)? ( `CMD_MOVS) :
261
+ (cond_133 && ~cond_4)? ( `CMD_MOVZX) :
262
+ (cond_134 && ~cond_4)? ( `CMD_MOVSX) :
263
+ (cond_135 && ~cond_4)? ( `CMD_POPA) :
264
+ (cond_136 && ~cond_4)? ( `CMD_debug_reg) :
265
+ (cond_137 && ~cond_4)? ( `CMD_XLAT) :
266
+ (cond_138 && ~cond_4)? ( `CMD_AAA) :
267
+ (cond_139 && ~cond_4)? ( `CMD_AAS) :
268
+ (cond_140 && ~cond_4)? ( `CMD_DAA) :
269
+ (cond_141 && ~cond_4)? ( `CMD_DAS) :
270
+ (cond_142 && ~cond_4)? ( `CMD_BSF) :
271
+ (cond_143 && ~cond_4)? ( `CMD_BSR) :
272
+ 7'd0;
273
+ assign dec_is_complex =
274
+ (cond_0 && ~cond_1)? (`TRUE) :
275
+ (cond_5 && ~cond_4)? (`TRUE) :
276
+ (cond_7 && ~cond_8)? (`TRUE) :
277
+ (cond_20 && ~cond_4)? (`TRUE) :
278
+ (cond_21 && ~cond_22)? (`TRUE) :
279
+ (cond_23 && ~cond_4)? (`TRUE) :
280
+ (cond_24 && ~cond_4 && cond_25)? (`TRUE) :
281
+ (cond_28 && ~cond_4)? (`TRUE) :
282
+ (cond_31 && ~cond_22)? (`TRUE) :
283
+ (cond_32 && ~cond_33)? (`TRUE) :
284
+ (cond_34 && ~cond_14)? (`TRUE) :
285
+ (cond_35 && ~cond_14)? (`TRUE) :
286
+ (cond_44 && ~cond_4)? (`TRUE) :
287
+ (cond_49 && ~cond_4)? (`TRUE) :
288
+ (cond_52 && ~cond_4)? (`TRUE) :
289
+ (cond_58 && ~cond_4)? (`TRUE) :
290
+ (cond_60 && ~cond_4)? (`TRUE) :
291
+ (cond_61 && ~cond_62 && cond_56)? (`TRUE) :
292
+ (cond_63 && ~cond_22)? (`TRUE) :
293
+ (cond_64 && ~cond_22)? (`TRUE) :
294
+ (cond_65 && ~cond_4)? (`TRUE) :
295
+ (cond_70 && ~cond_4)? (`TRUE) :
296
+ (cond_77 && ~cond_4)? (`TRUE) :
297
+ (cond_88 && ~cond_4)? (`TRUE) :
298
+ (cond_89 && ~cond_4)? (`TRUE) :
299
+ (cond_90 && ~cond_4 && cond_25)? (`TRUE) :
300
+ (cond_92 && ~cond_1)? (`TRUE) :
301
+ (cond_96 && ~cond_4)? (`TRUE) :
302
+ (cond_98 && ~cond_4)? (`TRUE) :
303
+ (cond_99 && ~cond_4)? (`TRUE) :
304
+ (cond_103 && ~cond_14)? (`TRUE) :
305
+ (cond_104 && ~cond_14)? (`TRUE) :
306
+ (cond_105 && ~cond_14)? (`TRUE) :
307
+ (cond_106 && ~cond_14)? (`TRUE) :
308
+ (cond_107 && ~cond_4 && cond_25)? (`TRUE) :
309
+ (cond_108 && ~cond_4)? (`TRUE) :
310
+ (cond_109 && ~cond_4)? (`TRUE) :
311
+ (cond_111 && ~cond_4)? (`TRUE) :
312
+ (cond_113 && ~cond_114)? (`TRUE) :
313
+ (cond_115 && ~cond_4)? (`TRUE) :
314
+ (cond_124 && ~cond_4)? (`TRUE) :
315
+ (cond_127 && ~cond_22)? (`TRUE) :
316
+ (cond_130 && ~cond_22)? (`TRUE) :
317
+ (cond_131 && ~cond_22)? (`TRUE) :
318
+ (cond_132 && ~cond_4 && cond_25)? (`TRUE) :
319
+ (cond_135 && ~cond_4)? (`TRUE) :
320
+ (cond_136 && ~cond_4 && cond_56)? (`TRUE) :
321
+ 1'd0;
322
+ assign consume_one_two =
323
+ (cond_28 && ~cond_4 && cond_2)? (`TRUE) :
324
+ (cond_89 && ~cond_4 && cond_2)? (`TRUE) :
325
+ 1'd0;
326
+ assign consume_modregrm_imm =
327
+ (cond_45 && ~cond_4 && cond_2)? (`TRUE) :
328
+ (cond_46 && ~cond_1 && cond_2)? (`TRUE) :
329
+ (cond_47 && ~cond_1 && cond_2)? (`TRUE) :
330
+ (cond_48 && ~cond_1 && cond_2)? (`TRUE) :
331
+ (cond_57 && ~cond_4)? (`TRUE) :
332
+ (cond_72 && ~cond_4)? (`TRUE) :
333
+ (cond_74 && ~cond_4 && cond_2)? (`TRUE) :
334
+ (cond_76 && ~cond_4 && cond_2)? (`TRUE) :
335
+ (cond_81 && ~cond_82)? (`TRUE) :
336
+ (cond_87 && ~cond_4)? (`TRUE) :
337
+ (cond_120 && ~cond_4)? (`TRUE) :
338
+ 1'd0;
339
+ assign consume_one =
340
+ (cond_10 && ~cond_4)? (`TRUE) :
341
+ (cond_20 && ~cond_4)? (`TRUE) :
342
+ (cond_23 && ~cond_4)? (`TRUE) :
343
+ (cond_24 && ~cond_4)? (`TRUE) :
344
+ (cond_26 && ~cond_4)? (`TRUE) :
345
+ (cond_28 && ~cond_4 && ~cond_2)? (`TRUE) :
346
+ (cond_30 && ~cond_4)? (`TRUE) :
347
+ (cond_36 && ~cond_4)? (`TRUE) :
348
+ (cond_37 && ~cond_4)? (`TRUE) :
349
+ (cond_38 && ~cond_4)? (`TRUE) :
350
+ (cond_39 && ~cond_4)? (`TRUE) :
351
+ (cond_40 && ~cond_4)? (`TRUE) :
352
+ (cond_41 && ~cond_4)? (`TRUE) :
353
+ (cond_44 && ~cond_4)? (`TRUE) :
354
+ (cond_49 && ~cond_4)? (`TRUE) :
355
+ (cond_51 && ~cond_4)? (`TRUE) :
356
+ (cond_58 && ~cond_4)? (`TRUE) :
357
+ (cond_65 && ~cond_4)? (`TRUE) :
358
+ (cond_66 && ~cond_4)? (`TRUE) :
359
+ (cond_73 && ~cond_4)? (`TRUE) :
360
+ (cond_77 && ~cond_4)? (`TRUE) :
361
+ (cond_88 && ~cond_4)? (`TRUE) :
362
+ (cond_89 && ~cond_4 && ~cond_2)? (`TRUE) :
363
+ (cond_90 && ~cond_4)? (`TRUE) :
364
+ (cond_91 && ~cond_4)? (`TRUE) :
365
+ (cond_93 && ~cond_4)? (`TRUE) :
366
+ (cond_96 && ~cond_4 && cond_97)? (`TRUE) :
367
+ (cond_98 && ~cond_4)? (`TRUE) :
368
+ (cond_99 && ~cond_4 && cond_101)? (`TRUE) :
369
+ (cond_107 && ~cond_4)? (`TRUE) :
370
+ (cond_108 && ~cond_4)? (`TRUE) :
371
+ (cond_109 && ~cond_4)? (`TRUE) :
372
+ (cond_110 && ~cond_4)? (`TRUE) :
373
+ (cond_115 && ~cond_4 && cond_101)? (`TRUE) :
374
+ (cond_121 && ~cond_4)? (`TRUE) :
375
+ (cond_122 && ~cond_4)? (`TRUE) :
376
+ (cond_123 && ~cond_4)? (`TRUE) :
377
+ (cond_124 && ~cond_4)? (`TRUE) :
378
+ (cond_125 && ~cond_4)? (`TRUE) :
379
+ (cond_126 && ~cond_4)? (`TRUE) :
380
+ (cond_128 && ~cond_4)? (`TRUE) :
381
+ (cond_132 && ~cond_4)? (`TRUE) :
382
+ (cond_135 && ~cond_4)? (`TRUE) :
383
+ (cond_137 && ~cond_4)? (`TRUE) :
384
+ (cond_138 && ~cond_4)? (`TRUE) :
385
+ (cond_139 && ~cond_4)? (`TRUE) :
386
+ (cond_140 && ~cond_4)? (`TRUE) :
387
+ (cond_141 && ~cond_4)? (`TRUE) :
388
+ 1'd0;
389
+ assign consume_one_one =
390
+ (cond_3 && ~cond_4)? (`TRUE) :
391
+ (cond_17 && ~cond_4 && ~cond_19)? (`TRUE) :
392
+ (cond_42 && ~cond_4)? (`TRUE) :
393
+ (cond_43 && ~cond_4)? (`TRUE) :
394
+ (cond_84 && ~cond_4)? (`TRUE) :
395
+ (cond_96 && ~cond_4 && ~cond_97)? (`TRUE) :
396
+ (cond_99 && ~cond_4 && ~cond_101)? (`TRUE) :
397
+ (cond_115 && ~cond_4 && ~cond_101)? (`TRUE) :
398
+ 1'd0;
399
+ assign exception_ud =
400
+ (cond_0 && cond_1)? (`TRUE) :
401
+ (cond_3 && cond_4)? (`TRUE) :
402
+ (cond_5 && cond_4)? (`TRUE) :
403
+ (cond_7 && cond_8)? (`TRUE) :
404
+ (cond_10 && cond_4)? (`TRUE) :
405
+ (cond_11 && cond_12)? (`TRUE) :
406
+ (cond_13 && cond_14)? (`TRUE) :
407
+ (cond_15 && cond_14)? (`TRUE) :
408
+ (cond_16 && cond_1)? (`TRUE) :
409
+ (cond_17 && cond_4)? (`TRUE) :
410
+ (cond_20 && cond_4)? (`TRUE) :
411
+ (cond_21 && cond_22)? (`TRUE) :
412
+ (cond_23 && cond_4)? (`TRUE) :
413
+ (cond_24 && cond_4)? (`TRUE) :
414
+ (cond_26 && cond_4)? (`TRUE) :
415
+ (cond_27 && cond_1)? (`TRUE) :
416
+ (cond_28 && cond_4)? (`TRUE) :
417
+ (cond_29 && cond_14)? (`TRUE) :
418
+ (cond_30 && cond_4)? (`TRUE) :
419
+ (cond_31 && cond_22)? (`TRUE) :
420
+ (cond_32 && cond_33)? (`TRUE) :
421
+ (cond_34 && cond_14)? (`TRUE) :
422
+ (cond_35 && cond_14)? (`TRUE) :
423
+ (cond_36 && cond_4)? (`TRUE) :
424
+ (cond_37 && cond_4)? (`TRUE) :
425
+ (cond_38 && cond_4)? (`TRUE) :
426
+ (cond_39 && cond_4)? (`TRUE) :
427
+ (cond_40 && cond_4)? (`TRUE) :
428
+ (cond_41 && cond_4)? (`TRUE) :
429
+ (cond_42 && cond_4)? (`TRUE) :
430
+ (cond_43 && cond_4)? (`TRUE) :
431
+ (cond_44 && cond_4)? (`TRUE) :
432
+ (cond_45 && cond_4)? (`TRUE) :
433
+ (cond_46 && cond_1)? (`TRUE) :
434
+ (cond_47 && cond_1)? (`TRUE) :
435
+ (cond_48 && cond_1)? (`TRUE) :
436
+ (cond_49 && cond_4)? (`TRUE) :
437
+ (cond_51 && cond_4)? (`TRUE) :
438
+ (cond_52 && cond_4)? (`TRUE) :
439
+ (cond_53 && cond_4)? (`TRUE) :
440
+ (cond_54 && cond_4)? (`TRUE) :
441
+ (cond_55 && cond_4)? (`TRUE) :
442
+ (cond_57 && cond_4)? (`TRUE) :
443
+ (cond_58 && cond_4)? (`TRUE) :
444
+ (cond_59 && cond_4)? (`TRUE) :
445
+ (cond_60 && cond_4)? (`TRUE) :
446
+ (cond_61 && cond_62)? (`TRUE) :
447
+ (cond_63 && cond_22)? (`TRUE) :
448
+ (cond_64 && cond_22)? (`TRUE) :
449
+ (cond_65 && cond_4)? (`TRUE) :
450
+ (cond_66 && cond_4)? (`TRUE) :
451
+ (cond_67 && cond_4)? (`TRUE) :
452
+ (cond_68 && cond_4)? (`TRUE) :
453
+ (cond_69 && cond_1)? (`TRUE) :
454
+ (cond_70 && cond_4)? (`TRUE) :
455
+ (cond_71 && cond_4)? (`TRUE) :
456
+ (cond_72 && cond_4)? (`TRUE) :
457
+ (cond_73 && cond_4)? (`TRUE) :
458
+ (cond_74 && cond_4)? (`TRUE) :
459
+ (cond_76 && cond_4)? (`TRUE) :
460
+ (cond_77 && cond_4)? (`TRUE) :
461
+ (cond_78 && cond_4)? (`TRUE) :
462
+ (cond_79 && cond_80)? (`TRUE) :
463
+ (cond_81 && cond_82)? (`TRUE) :
464
+ (cond_83 && cond_4)? (`TRUE) :
465
+ (cond_84 && cond_4)? (`TRUE) :
466
+ (cond_85 && cond_4)? (`TRUE) :
467
+ (cond_86 && cond_4)? (`TRUE) :
468
+ (cond_87 && cond_4)? (`TRUE) :
469
+ (cond_88 && cond_4)? (`TRUE) :
470
+ (cond_89 && cond_4)? (`TRUE) :
471
+ (cond_90 && cond_4)? (`TRUE) :
472
+ (cond_91 && cond_4)? (`TRUE) :
473
+ (cond_92 && cond_1)? (`TRUE) :
474
+ (cond_93 && cond_4)? (`TRUE) :
475
+ (cond_94 && cond_4)? (`TRUE) :
476
+ (cond_95 && cond_4)? (`TRUE) :
477
+ (cond_96 && cond_4)? (`TRUE) :
478
+ (cond_98 && cond_4)? (`TRUE) :
479
+ (cond_99 && cond_4)? (`TRUE) :
480
+ (cond_102 && cond_1)? (`TRUE) :
481
+ (cond_103 && cond_14)? (`TRUE) :
482
+ (cond_104 && cond_14)? (`TRUE) :
483
+ (cond_105 && cond_14)? (`TRUE) :
484
+ (cond_106 && cond_14)? (`TRUE) :
485
+ (cond_107 && cond_4)? (`TRUE) :
486
+ (cond_108 && cond_4)? (`TRUE) :
487
+ (cond_109 && cond_4)? (`TRUE) :
488
+ (cond_110 && cond_4)? (`TRUE) :
489
+ (cond_111 && cond_4)? (`TRUE) :
490
+ (cond_113 && cond_114)? (`TRUE) :
491
+ (cond_115 && cond_4)? (`TRUE) :
492
+ (cond_116 && cond_4)? (`TRUE) :
493
+ (cond_117 && cond_4)? (`TRUE) :
494
+ (cond_119 && cond_4)? (`TRUE) :
495
+ (cond_120 && cond_4)? (`TRUE) :
496
+ (cond_121 && cond_4)? (`TRUE) :
497
+ (cond_122 && cond_4)? (`TRUE) :
498
+ (cond_123 && cond_4)? (`TRUE) :
499
+ (cond_124 && cond_4)? (`TRUE) :
500
+ (cond_125 && cond_4)? (`TRUE) :
501
+ (cond_126 && cond_4)? (`TRUE) :
502
+ (cond_127 && cond_22)? (`TRUE) :
503
+ (cond_128 && cond_4)? (`TRUE) :
504
+ (cond_129 && cond_22)? (`TRUE) :
505
+ (cond_130 && cond_22)? (`TRUE) :
506
+ (cond_131 && cond_22)? (`TRUE) :
507
+ (cond_132 && cond_4)? (`TRUE) :
508
+ (cond_133 && cond_4)? (`TRUE) :
509
+ (cond_134 && cond_4)? (`TRUE) :
510
+ (cond_135 && cond_4)? (`TRUE) :
511
+ (cond_136 && cond_4)? (`TRUE) :
512
+ (cond_137 && cond_4)? (`TRUE) :
513
+ (cond_138 && cond_4)? (`TRUE) :
514
+ (cond_139 && cond_4)? (`TRUE) :
515
+ (cond_140 && cond_4)? (`TRUE) :
516
+ (cond_141 && cond_4)? (`TRUE) :
517
+ (cond_142 && cond_4)? (`TRUE) :
518
+ (cond_143 && cond_4)? (`TRUE) :
519
+ 1'd0;
520
+ assign consume_one_imm =
521
+ (cond_17 && ~cond_4 && cond_19)? (`TRUE) :
522
+ (cond_78 && ~cond_4)? (`TRUE) :
523
+ (cond_85 && ~cond_4)? (`TRUE) :
524
+ (cond_94 && ~cond_4)? (`TRUE) :
525
+ (cond_117 && ~cond_4)? (`TRUE) :
526
+ 1'd0;
527
+ assign consume_call_jmp_imm =
528
+ (cond_5 && ~cond_4)? (`TRUE) :
529
+ (cond_111 && ~cond_4)? (`TRUE) :
530
+ 1'd0;
531
+ assign consume_modregrm_one =
532
+ (cond_0 && ~cond_1)? (`TRUE) :
533
+ (cond_7 && ~cond_8)? (`TRUE) :
534
+ (cond_11 && ~cond_12)? (`TRUE) :
535
+ (cond_13 && ~cond_14)? (`TRUE) :
536
+ (cond_15 && ~cond_14)? (`TRUE) :
537
+ (cond_16 && ~cond_1)? (`TRUE) :
538
+ (cond_21 && ~cond_22)? (`TRUE) :
539
+ (cond_27 && ~cond_1)? (`TRUE) :
540
+ (cond_29 && ~cond_14)? (`TRUE) :
541
+ (cond_31 && ~cond_22)? (`TRUE) :
542
+ (cond_32 && ~cond_33)? (`TRUE) :
543
+ (cond_34 && ~cond_14)? (`TRUE) :
544
+ (cond_35 && ~cond_14)? (`TRUE) :
545
+ (cond_45 && ~cond_4 && ~cond_2)? (`TRUE) :
546
+ (cond_46 && ~cond_1 && ~cond_2)? (`TRUE) :
547
+ (cond_47 && ~cond_1 && ~cond_2)? (`TRUE) :
548
+ (cond_48 && ~cond_1 && ~cond_2)? (`TRUE) :
549
+ (cond_52 && ~cond_4)? (`TRUE) :
550
+ (cond_53 && ~cond_4)? (`TRUE) :
551
+ (cond_54 && ~cond_4)? (`TRUE) :
552
+ (cond_55 && ~cond_4)? (`TRUE) :
553
+ (cond_59 && ~cond_4)? (`TRUE) :
554
+ (cond_60 && ~cond_4)? (`TRUE) :
555
+ (cond_61 && ~cond_62)? (`TRUE) :
556
+ (cond_63 && ~cond_22)? (`TRUE) :
557
+ (cond_64 && ~cond_22)? (`TRUE) :
558
+ (cond_67 && ~cond_4)? (`TRUE) :
559
+ (cond_68 && ~cond_4)? (`TRUE) :
560
+ (cond_69 && ~cond_1)? (`TRUE) :
561
+ (cond_71 && ~cond_4)? (`TRUE) :
562
+ (cond_74 && ~cond_4 && ~cond_2)? (`TRUE) :
563
+ (cond_76 && ~cond_4 && ~cond_2)? (`TRUE) :
564
+ (cond_79 && ~cond_80)? (`TRUE) :
565
+ (cond_83 && ~cond_4)? (`TRUE) :
566
+ (cond_86 && ~cond_4)? (`TRUE) :
567
+ (cond_92 && ~cond_1)? (`TRUE) :
568
+ (cond_95 && ~cond_4)? (`TRUE) :
569
+ (cond_102 && ~cond_1)? (`TRUE) :
570
+ (cond_103 && ~cond_14)? (`TRUE) :
571
+ (cond_104 && ~cond_14)? (`TRUE) :
572
+ (cond_105 && ~cond_14)? (`TRUE) :
573
+ (cond_106 && ~cond_14)? (`TRUE) :
574
+ (cond_113 && ~cond_114)? (`TRUE) :
575
+ (cond_119 && ~cond_4)? (`TRUE) :
576
+ (cond_127 && ~cond_22)? (`TRUE) :
577
+ (cond_129 && ~cond_22)? (`TRUE) :
578
+ (cond_130 && ~cond_22)? (`TRUE) :
579
+ (cond_131 && ~cond_22)? (`TRUE) :
580
+ (cond_133 && ~cond_4)? (`TRUE) :
581
+ (cond_134 && ~cond_4)? (`TRUE) :
582
+ (cond_136 && ~cond_4)? (`TRUE) :
583
+ (cond_142 && ~cond_4)? (`TRUE) :
584
+ (cond_143 && ~cond_4)? (`TRUE) :
585
+ 1'd0;
586
+ assign consume_one_three =
587
+ (cond_70 && ~cond_4)? (`TRUE) :
588
+ 1'd0;
589
+ assign dec_is_8bit =
590
+ (cond_0 && ~cond_1 && cond_2)? (`TRUE) :
591
+ (cond_3 && ~cond_4)? (`TRUE) :
592
+ (cond_16 && ~cond_1 && cond_2)? (`TRUE) :
593
+ (cond_17 && ~cond_4 && cond_18)? (`TRUE) :
594
+ (cond_24 && ~cond_4 && cond_2)? (`TRUE) :
595
+ (cond_27 && ~cond_1 && cond_2)? (`TRUE) :
596
+ (cond_42 && ~cond_4)? (`TRUE) :
597
+ (cond_43 && ~cond_4)? (`TRUE) :
598
+ (cond_53 && ~cond_4 && cond_2)? (`TRUE) :
599
+ (cond_54 && ~cond_4 && cond_2)? (`TRUE) :
600
+ (cond_55 && ~cond_4 && cond_2)? (`TRUE) :
601
+ (cond_57 && ~cond_4 && cond_2)? (`TRUE) :
602
+ (cond_58 && ~cond_4 && cond_2)? (`TRUE) :
603
+ (cond_68 && ~cond_4)? (`TRUE) :
604
+ (cond_69 && ~cond_1 && cond_2)? (`TRUE) :
605
+ (cond_71 && ~cond_4 && cond_2)? (`TRUE) :
606
+ (cond_78 && ~cond_4 && cond_2)? (`TRUE) :
607
+ (cond_79 && ~cond_80 && cond_2)? (`TRUE) :
608
+ (cond_81 && ~cond_82 && cond_2)? (`TRUE) :
609
+ (cond_83 && ~cond_4 && cond_2)? (`TRUE) :
610
+ (cond_84 && ~cond_4)? (`TRUE) :
611
+ (cond_85 && ~cond_4 && cond_2)? (`TRUE) :
612
+ (cond_86 && ~cond_4 && cond_2)? (`TRUE) :
613
+ (cond_87 && ~cond_4 && cond_2)? (`TRUE) :
614
+ (cond_90 && ~cond_4 && cond_2)? (`TRUE) :
615
+ (cond_92 && ~cond_1 && cond_2)? (`TRUE) :
616
+ (cond_99 && ~cond_4 && cond_2)? (`TRUE) :
617
+ (cond_102 && ~cond_1 && cond_2)? (`TRUE) :
618
+ (cond_107 && ~cond_4 && cond_2)? (`TRUE) :
619
+ (cond_108 && ~cond_4 && cond_2)? (`TRUE) :
620
+ (cond_109 && ~cond_4 && cond_2)? (`TRUE) :
621
+ (cond_111 && ~cond_4 && cond_112)? (`TRUE) :
622
+ (cond_115 && ~cond_4 && cond_2)? (`TRUE) :
623
+ (cond_116 && ~cond_4 && cond_2)? (`TRUE) :
624
+ (cond_117 && ~cond_4 && cond_118)? (`TRUE) :
625
+ (cond_119 && ~cond_4 && cond_2)? (`TRUE) :
626
+ (cond_120 && ~cond_4 && cond_2)? (`TRUE) :
627
+ (cond_132 && ~cond_4 && cond_2)? (`TRUE) :
628
+ (cond_133 && ~cond_4 && cond_2)? (`TRUE) :
629
+ (cond_134 && ~cond_4 && cond_2)? (`TRUE) :
630
+ (cond_137 && ~cond_4)? (`TRUE) :
631
+ (cond_138 && ~cond_4)? (`TRUE) :
632
+ (cond_139 && ~cond_4)? (`TRUE) :
633
+ (cond_140 && ~cond_4)? (`TRUE) :
634
+ (cond_141 && ~cond_4)? (`TRUE) :
635
+ 1'd0;
636
+ assign dec_cmdex =
637
+ (cond_5 && ~cond_4 && cond_6)? ( `CMDEX_CALL_Jv_STEP_0) :
638
+ (cond_5 && ~cond_4 && ~cond_6)? ( `CMDEX_CALL_Ap_STEP_0) :
639
+ (cond_7 && ~cond_8 && cond_9)? ( `CMDEX_CALL_Ev_STEP_0) :
640
+ (cond_7 && ~cond_8 && ~cond_9)? ( `CMDEX_CALL_Ep_STEP_0) :
641
+ (cond_10 && ~cond_4)? ( `CMDEX_PUSH_MOV_SEG_implicit | { 1'b0, decoder[5:3] }) :
642
+ (cond_11 && ~cond_12)? ( `CMDEX_PUSH_MOV_SEG_modregrm | { 1'b0, decoder[13:11] }) :
643
+ (cond_13 && ~cond_14)? ( `CMDEX_PUSH_MOV_SEG_modregrm_LDT) :
644
+ (cond_15 && ~cond_14)? ( `CMDEX_PUSH_MOV_SEG_modregrm_TR) :
645
+ (cond_20 && ~cond_4)? ( `CMDEX_INVD_STEP_0) :
646
+ (cond_21 && ~cond_22)? ( `CMDEX_INVLPG_STEP_0) :
647
+ (cond_23 && ~cond_4)? ( `CMDEX_HLT_STEP_0) :
648
+ (cond_24 && ~cond_4)? ( `CMDEX_SCAS_STEP_0) :
649
+ (cond_26 && ~cond_4)? ( `CMDEX_INC_DEC_increment_implicit | { 3'd0, decoder[3] }) :
650
+ (cond_27 && ~cond_1)? ( `CMDEX_INC_DEC_increment_modregrm | { 3'd0, decoder[11] }) :
651
+ (cond_28 && ~cond_4 && cond_2)? ( `CMDEX_RET_near_imm) :
652
+ (cond_28 && ~cond_4 && ~cond_2)? ( `CMDEX_RET_near) :
653
+ (cond_31 && ~cond_22)? ( `CMDEX_LxS_STEP_1) :
654
+ (cond_32 && ~cond_33)? ( `CMDEX_MOV_to_seg_LLDT_LTR_STEP_1) :
655
+ (cond_34 && ~cond_14)? ( `CMDEX_MOV_to_seg_LLDT_LTR_STEP_1) :
656
+ (cond_35 && ~cond_14)? ( `CMDEX_MOV_to_seg_LLDT_LTR_STEP_1) :
657
+ (cond_44 && ~cond_4)? ( `CMDEX_POP_seg_STEP_1) :
658
+ (cond_45 && ~cond_4 && cond_2)? ( `CMDEX_BTx_modregrm_imm) :
659
+ (cond_45 && ~cond_4 && ~cond_2)? ( `CMDEX_BTx_modregrm) :
660
+ (cond_46 && ~cond_1 && cond_2)? ( `CMDEX_BTx_modregrm_imm) :
661
+ (cond_46 && ~cond_1 && ~cond_2)? ( `CMDEX_BTx_modregrm) :
662
+ (cond_47 && ~cond_1 && cond_2)? ( `CMDEX_BTx_modregrm_imm) :
663
+ (cond_47 && ~cond_1 && ~cond_2)? ( `CMDEX_BTx_modregrm) :
664
+ (cond_48 && ~cond_1 && cond_2)? ( `CMDEX_BTx_modregrm_imm) :
665
+ (cond_48 && ~cond_1 && ~cond_2)? ( `CMDEX_BTx_modregrm) :
666
+ (cond_49 && ~cond_4 && cond_50)? ( `CMDEX_IRET_real_v86_STEP_0) :
667
+ (cond_49 && ~cond_4 && ~cond_50)? ( `CMDEX_IRET_protected_STEP_0) :
668
+ (cond_51 && ~cond_4)? ( `CMDEX_POP_implicit) :
669
+ (cond_52 && ~cond_4)? ( `CMDEX_POP_modregrm_STEP_0) :
670
+ (cond_55 && ~cond_4 && cond_56)? ( `CMDEX_Shift_implicit) :
671
+ (cond_55 && ~cond_4 && ~cond_56)? ( `CMDEX_Shift_modregrm) :
672
+ (cond_57 && ~cond_4)? ( `CMDEX_Shift_modregrm_imm) :
673
+ (cond_58 && ~cond_4)? (`CMDEX_CMPS_FIRST) :
674
+ (cond_59 && ~cond_4)? ( `CMDEX_control_reg_SMSW_STEP_0) :
675
+ (cond_60 && ~cond_4)? ( `CMDEX_control_reg_LMSW_STEP_0) :
676
+ (cond_61 && ~cond_62 && cond_56)? ( `CMDEX_control_reg_MOV_load_STEP_0) :
677
+ (cond_61 && ~cond_62 && ~cond_56)? ( `CMDEX_control_reg_MOV_store_STEP_0) :
678
+ (cond_63 && ~cond_22)? ( `CMDEX_LGDT_LIDT_STEP_1) :
679
+ (cond_64 && ~cond_22)? ( `CMDEX_LGDT_LIDT_STEP_1) :
680
+ (cond_65 && ~cond_4)? ( `CMDEX_PUSHA_STEP_0) :
681
+ (cond_66 && ~cond_4)? ( `CMDEX_WAIT_STEP_0) :
682
+ (cond_67 && ~cond_4)? ( `CMDEX_ESC_STEP_0) :
683
+ (cond_70 && ~cond_4)? ( `CMDEX_ENTER_FIRST) :
684
+ (cond_71 && ~cond_4)? ( `CMDEX_IMUL_modregrm) :
685
+ (cond_72 && ~cond_4)? ( `CMDEX_IMUL_modregrm_imm) :
686
+ (cond_74 && ~cond_4 && cond_75)? ( `CMDEX_SHxD_implicit) :
687
+ (cond_74 && ~cond_4 && ~cond_75)? ( `CMDEX_SHxD_modregrm_imm) :
688
+ (cond_76 && ~cond_4 && cond_75)? ( `CMDEX_SHxD_implicit) :
689
+ (cond_76 && ~cond_4 && ~cond_75)? ( `CMDEX_SHxD_modregrm_imm) :
690
+ (cond_77 && ~cond_4)? ( `CMDEX_WBINVD_STEP_0) :
691
+ (cond_78 && ~cond_4)? ( `CMDEX_Arith_immediate) :
692
+ (cond_79 && ~cond_80)? ( `CMDEX_Arith_modregrm) :
693
+ (cond_81 && ~cond_82)? ( `CMDEX_Arith_modregrm_imm) :
694
+ (cond_84 && ~cond_4)? ( (decoder[1:0] == 2'b00)? `CMDEX_LOOP_NE : (decoder[1:0] == 2'b01)? `CMDEX_LOOP_E : `CMDEX_LOOP) :
695
+ (cond_85 && ~cond_4)? ( `CMDEX_TEST_immediate) :
696
+ (cond_86 && ~cond_4)? ( `CMDEX_TEST_modregrm) :
697
+ (cond_87 && ~cond_4)? ( `CMDEX_TEST_modregrm_imm) :
698
+ (cond_88 && ~cond_4)? (`CMDEX_CLTS_STEP_FIRST) :
699
+ (cond_89 && ~cond_4)? ( `CMDEX_RET_far_STEP_1) :
700
+ (cond_90 && ~cond_4)? ( `CMDEX_LODS_STEP_0) :
701
+ (cond_91 && ~cond_4)? ( `CMDEX_XCHG_implicit) :
702
+ (cond_92 && ~cond_1)? ( `CMDEX_XCHG_modregrm) :
703
+ (cond_93 && ~cond_4)? ( `CMDEX_PUSH_implicit) :
704
+ (cond_94 && ~cond_4 && cond_56)? ( `CMDEX_PUSH_immediate_se) :
705
+ (cond_94 && ~cond_4 && ~cond_56)? ( `CMDEX_PUSH_immediate) :
706
+ (cond_95 && ~cond_4)? ( `CMDEX_PUSH_modregrm) :
707
+ (cond_96 && ~cond_4)? ( (decoder[2:0] == 3'b100)? `CMDEX_INT_INTO_INT3_STEP_0 : (decoder[2:0] == 3'b101)? `CMDEX_INT_INTO_INT_STEP_0 : (decoder[2:0] == 3'b110)? `CMDEX_INT_INTO_INTO_STEP_0 : `CMDEX_INT_INTO_INT1_STEP_0) :
708
+ (cond_98 && ~cond_4)? ( `CMDEX_CPUID_STEP_LAST) :
709
+ (cond_99 && ~cond_4 && cond_100)? ( `CMDEX_IN_dx) :
710
+ (cond_99 && ~cond_4 && ~cond_100)? ( `CMDEX_IN_imm) :
711
+ (cond_103 && ~cond_14)? ( `CMDEX_LAR_LSL_VERR_VERW_STEP_1) :
712
+ (cond_104 && ~cond_14)? ( `CMDEX_LAR_LSL_VERR_VERW_STEP_1) :
713
+ (cond_105 && ~cond_14)? (`CMDEX_LAR_LSL_VERR_VERW_STEP_1) :
714
+ (cond_106 && ~cond_14)? ( `CMDEX_LAR_LSL_VERR_VERW_STEP_1) :
715
+ (cond_107 && ~cond_4)? ( `CMDEX_STOS_STEP_0) :
716
+ (cond_108 && ~cond_4)? ( `CMDEX_INS_real_1) :
717
+ (cond_109 && ~cond_4)? ( `CMDEX_OUTS_first) :
718
+ (cond_111 && ~cond_4 && cond_2)? ( `CMDEX_JMP_Ap_STEP_0) :
719
+ (cond_111 && ~cond_4 && ~cond_2)? ( `CMDEX_JMP_Jv_STEP_0) :
720
+ (cond_113 && ~cond_114 && cond_9)? ( `CMDEX_JMP_Ev_STEP_0) :
721
+ (cond_113 && ~cond_114 && ~cond_9)? ( `CMDEX_JMP_Ep_STEP_0) :
722
+ (cond_115 && ~cond_4 && cond_100)? ( `CMDEX_OUT_dx) :
723
+ (cond_115 && ~cond_4 && ~cond_100)? ( `CMDEX_OUT_imm) :
724
+ (cond_116 && ~cond_4)? ( `CMDEX_MOV_memoffset) :
725
+ (cond_117 && ~cond_4)? ( `CMDEX_MOV_immediate) :
726
+ (cond_119 && ~cond_4)? ( `CMDEX_MOV_modregrm) :
727
+ (cond_120 && ~cond_4)? ( `CMDEX_MOV_modregrm_imm) :
728
+ (cond_124 && ~cond_4)? ( `CMDEX_POPF_STEP_0) :
729
+ (cond_127 && ~cond_22)? ( `CMDEX_BOUND_STEP_FIRST) :
730
+ (cond_128 && ~cond_4)? ( `CMDEX_SALC_STEP_0) :
731
+ (cond_130 && ~cond_22)? ( `CMDEX_SGDT_SIDT_STEP_1) :
732
+ (cond_131 && ~cond_22)? ( `CMDEX_SGDT_SIDT_STEP_1) :
733
+ (cond_132 && ~cond_4)? ( `CMDEX_MOVS_STEP_0) :
734
+ (cond_135 && ~cond_4)? ( `CMDEX_POPA_STEP_0) :
735
+ (cond_136 && ~cond_4 && cond_56)? ( `CMDEX_debug_reg_MOV_load_STEP_0) :
736
+ (cond_136 && ~cond_4 && ~cond_56)? ( `CMDEX_debug_reg_MOV_store_STEP_0) :
737
+ 4'd0;
snapshots/MiSTer-devel_ao486_MiSTer_pr72/rtl/ao486/autogen/defines.v ADDED
@@ -0,0 +1,449 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ `define CMDEX_POP_implicit 4'd0
2
+ `define CMDEX_TEST_immediate 4'd0
3
+ `define CMDEX_JMP_protected_STEP_1 4'd10
4
+ `define CMDEX_JMP_protected_STEP_0 4'd9
5
+ `define CMDEX_LODS_STEP_0 4'd0
6
+ `define CMDEX_XADD_LAST 4'd1
7
+ `define CMD_ADD 7'd64
8
+ `define CMDEX_PUSH_immediate 4'd2
9
+ `define CMD_ADC 7'd66
10
+ `define CMDEX_POP_seg_STEP_1 4'd0
11
+ `define CMDEX_INC_DEC_implicit 4'd0
12
+ `define CMD_SBB 7'd67
13
+ `define CMDEX_JMP_Jv_STEP_0 4'd1
14
+ `define CMD_LEA 7'd103
15
+ `define CMD_MOV 7'd90
16
+ `define CMD_NOT 7'd78
17
+ `define CMDEX_MOVS_STEP_0 4'd0
18
+ `define CMDEX_task_switch_4_STEP_6 4'd6
19
+ `define CMDEX_int_2_int_trap_gate_more_STEP_3 4'd9
20
+ `define CMDEX_task_switch_4_STEP_5 4'd5
21
+ `define CMDEX_int_2_int_trap_gate_more_STEP_2 4'd8
22
+ `define CMDEX_task_switch_4_STEP_8 4'd8
23
+ `define CMDEX_int_2_int_trap_gate_more_STEP_5 4'd11
24
+ `define CMDEX_task_switch_4_STEP_7 4'd7
25
+ `define CMDEX_int_2_int_trap_gate_more_STEP_4 4'd10
26
+ `define CMDEX_int_2_int_trap_gate_more_STEP_7 4'd13
27
+ `define CMDEX_task_switch_4_STEP_9 4'd9
28
+ `define CMDEX_int_2_int_trap_gate_more_STEP_6 4'd12
29
+ `define CMDEX_PUSH_MOV_SEG_implicit_DS 4'd3
30
+ `define CMDEX_int_2_int_trap_gate_more_STEP_9 4'd15
31
+ `define CMDEX_int_2_int_trap_gate_more_STEP_8 4'd14
32
+ `define CMD_AAM 7'd32
33
+ `define CMDEX_int_real_STEP_1 4'd3
34
+ `define CMDEX_int_real_STEP_0 4'd2
35
+ `define CMDEX_XCHG_modregrm_LAST 4'd2
36
+ `define CMDEX_int_real_STEP_3 4'd5
37
+ `define CMDEX_int_real_STEP_2 4'd4
38
+ `define CMD_PUSH_MOV_SEG 7'd6
39
+ `define CMD_SGDT 7'd104
40
+ `define CMD_AAS 7'd113
41
+ `define CMDEX_int_2_int_trap_gate_more_STEP_1 4'd7
42
+ `define CMDEX_int_2_int_trap_gate_more_STEP_0 4'd6
43
+ `define CMD_MOVSX 7'd108
44
+ `define CMD_SIDT 7'd105
45
+ `define CMD_LAHF 7'd91
46
+ `define CMDEX_MOV_to_seg_LLDT_LTR_STEP_1 4'd0
47
+ `define CMDEX_task_switch_4_STEP_0 4'd0
48
+ `define CMDEX_task_switch_4_STEP_1 4'd1
49
+ `define CMDEX_task_switch_4_STEP_2 4'd2
50
+ `define CMDEX_task_switch_4_STEP_3 4'd3
51
+ `define TASK_SWITCH_FROM_IRET 2'd0
52
+ `define CMDEX_task_switch_4_STEP_4 4'd4
53
+ `define CMDEX_int_int_trap_gate_STEP_0 4'd13
54
+ `define CMDEX_int_int_trap_gate_STEP_1 4'd14
55
+ `define CMDEX_int_int_trap_gate_STEP_2 4'd15
56
+ `define CMDEX_PUSH_MOV_SEG_implicit_CS 4'd1
57
+ `define CMD_CMPS 7'd45
58
+ `define CMDEX_INVD_STEP_0 4'd0
59
+ `define CMD_CBW 7'd92
60
+ `define CMDEX_INVD_STEP_1 4'd1
61
+ `define CMD_BT 7'd36
62
+ `define CMDEX_INVD_STEP_2 4'd2
63
+ `define CMDEX_RET_near_imm 4'd1
64
+ `define CMD_OUT 7'd89
65
+ `define CMD_int_3 7'd30
66
+ `define CMD_SCAS 7'd13
67
+ `define CMD_int_2 7'd29
68
+ `define CMD_INT_INTO 7'd75
69
+ `define CMDEX_LAR_LSL_VERR_VERW_STEP_1 4'd0
70
+ `define CMDEX_LAR_LSL_VERR_VERW_STEP_2 4'd1
71
+ `define CMD_IRET_2 7'd40
72
+ `define CMD_load_seg 7'd33
73
+ `define CMDEX_XCHG_modregrm 4'd1
74
+ `define CMDEX_PUSH_MOV_SEG_modregrm_LDT 4'd14
75
+ `define CMD_SAHF 7'd27
76
+ `define CMDEX_INS_real_1 4'd0
77
+ `define CMDEX_INS_real_2 4'd1
78
+ `define CMDEX_PUSH_MOV_SEG_modregrm_CS 4'd9
79
+ `define CMDEX_TEST_modregrm 4'd1
80
+ `define CMD_LGDT 7'd47
81
+ `define CMD_MUL 7'd59
82
+ `define CMD_CPUID 7'd76
83
+ `define CMDEX_ENTER_LOOP 4'd3
84
+ `define CMDEX_RET_far_same_STEP_3 4'd4
85
+ `define CMDEX_RET_far_same_STEP_4 4'd5
86
+ `define CMDEX_PUSH_MOV_SEG_modregrm_DS 4'd11
87
+ `define CMD_AAD 7'd31
88
+ `define CMD_AAA 7'd112
89
+ `define CMD_Jcc 7'd8
90
+ `define CMD_BSWAP 7'd17
91
+ `define CMDEX_CALL_2_call_gate_same_STEP_0 4'd8
92
+ `define CMDEX_SCAS_STEP_0 4'd0
93
+ `define CMDEX_CALL_2_call_gate_same_STEP_2 4'd10
94
+ `define CMDEX_CALL_2_call_gate_same_STEP_1 4'd9
95
+ `define CMDEX_CALL_2_call_gate_same_STEP_3 4'd11
96
+ `define CMD_PUSH 7'd74
97
+ `define CMDEX_BTx_modregrm 4'd1
98
+ `define CMDEX_SGDT_SIDT_STEP_1 4'd0
99
+ `define CMDEX_PUSH_MOV_SEG_modregrm_ES 4'd8
100
+ `define CMDEX_SGDT_SIDT_STEP_2 4'd1
101
+ `define CMDEX_CLTS_STEP_FIRST 4'd0
102
+ `define CMDEX_CALL_2_call_gate_more_STEP_2 4'd14
103
+ `define CMDEX_CMPS_FIRST 4'd0
104
+ `define CMDEX_CALL_2_call_gate_more_STEP_3 4'd15
105
+ `define CMDEX_CALL_2_call_gate_more_STEP_0 4'd12
106
+ `define CMDEX_CALL_2_call_gate_more_STEP_1 4'd13
107
+ `define CMDEX_WAIT_STEP_0 4'd0
108
+ `define CMDEX_PUSH_MOV_SEG_modregrm 4'd8
109
+ `define CMD_DIV 7'd42
110
+ `define TASK_SWITCH_FROM_INT 2'd1
111
+ `define CMDEX_HLT_STEP_0 4'd0
112
+ `define CMDEX_BOUND_STEP_FIRST 4'd0
113
+ `define CMDEX_LOOP_E 4'd1
114
+ `define CMDEX_CALL_3_call_gate_more_STEP_10 4'd6
115
+ `define CMDEX_int_STEP_1 4'd1
116
+ `define CMD_MOV_to_seg 7'd19
117
+ `define CMD_Shift 7'd44
118
+ `define CMDEX_PUSH_MOV_SEG_modregrm_FS 4'd12
119
+ `define CMDEX_PUSH_modregrm 4'd3
120
+ `define CMDEX_INT_INTO_INT3_STEP_0 4'd1
121
+ `define CMD_INVLPG 7'd10
122
+ `define CMDEX_MOV_modregrm_imm 4'd2
123
+ `define CMDEX_IN_protected 4'd2
124
+ `define CMD_control_reg 7'd46
125
+ `define CMDEX_control_reg_LMSW_STEP_0 4'd1
126
+ `define CMDEX_CALL_2_protected_seg_STEP_3 4'd0
127
+ `define CMD_io_allow 7'd11
128
+ `define CMDEX_control_reg_LMSW_STEP_1 4'd2
129
+ `define CMDEX_IN_imm 4'd0
130
+ `define CMDEX_CLTS_STEP_LAST 4'd1
131
+ `define CMDEX_IRET_protected_STEP_3 4'd9
132
+ `define CMDEX_IRET_protected_STEP_2 4'd8
133
+ `define CMDEX_CALL_2_protected_seg_STEP_4 4'd1
134
+ `define CMDEX_IRET_protected_STEP_1 4'd7
135
+ `define CMDEX_IRET_protected_STEP_0 4'd4
136
+ `define CMD_IDIV 7'd43
137
+ `define CMDEX_OUT_protected 4'd2
138
+ `define CMDEX_PUSH_MOV_SEG_implicit_LDT 4'd6
139
+ `define CMDEX_Arith_immediate 4'd0
140
+ `define CMDEX_task_switch_STEP_3 4'd3
141
+ `define CMDEX_task_switch_STEP_2 4'd2
142
+ `define CMDEX_task_switch_STEP_1 4'd1
143
+ `define CMDEX_task_switch_STEP_7 4'd7
144
+ `define CMDEX_task_switch_4_STEP_10 4'd10
145
+ `define CMDEX_task_switch_STEP_6 4'd6
146
+ `define CMDEX_task_switch_STEP_5 4'd5
147
+ `define CMDEX_task_switch_STEP_4 4'd4
148
+ `define CMD_task_switch 7'd99
149
+ `define CMDEX_task_switch_STEP_9 4'd9
150
+ `define CMDEX_task_switch_2_STEP_13 4'd13
151
+ `define CMDEX_task_switch_STEP_8 4'd8
152
+ `define CMDEX_task_switch_2_STEP_11 4'd11
153
+ `define CMDEX_OUT_idle 4'd3
154
+ `define CMDEX_LGDT_LIDT_STEP_LAST 4'd10
155
+ `define CMDEX_control_reg_SMSW_STEP_0 4'd0
156
+ `define CMDEX_CALL_Ep_STEP_1 4'd5
157
+ `define CMDEX_CALL_Ep_STEP_0 4'd2
158
+ `define CMDEX_INS_protected_2 4'd3
159
+ `define CMDEX_INS_protected_1 4'd2
160
+ `define CMDEX_control_reg_MOV_load_STEP_1 4'd5
161
+ `define CMDEX_control_reg_MOV_load_STEP_0 4'd4
162
+ `define CMDEX_LOOP_NE 4'd0
163
+ `define CMD_LODS 7'd72
164
+ `define CMDEX_JMP_real_v8086_STEP_1 4'd8
165
+ `define CMDEX_JMP_real_v8086_STEP_0 4'd7
166
+ `define CMD_MOVZX 7'd107
167
+ `define CMD_TEST 7'd61
168
+ `define CMDEX_IN_dx 4'd1
169
+ `define CMD_LIDT 7'd48
170
+ `define CMDEX_PUSH_MOV_SEG_implicit 4'd0
171
+ `define CMDEX_PUSH_MOV_SEG_implicit_GS 4'd5
172
+ `define CMD_MOVS 7'd106
173
+ `define CMD_PUSHA 7'd49
174
+ `define CMDEX_SHxD_implicit 4'd0
175
+ `define CMD_PUSHF 7'd86
176
+ `define CMDEX_CALL_real_v8086_STEP_3 4'd10
177
+ `define CMDEX_LGDT_LIDT_STEP_1 4'd8
178
+ `define CMDEX_CALL_real_v8086_STEP_2 4'd9
179
+ `define CMDEX_LGDT_LIDT_STEP_2 4'd9
180
+ `define CMD_SETcc 7'd51
181
+ `define CMDEX_CALL_real_v8086_STEP_1 4'd8
182
+ `define CMDEX_CALL_real_v8086_STEP_0 4'd7
183
+ `define CMDEX_Arith_modregrm_imm 4'd2
184
+ `define CMD_fpu 7'd50
185
+ `define CMDEX_OUTS_protected 4'd1
186
+ `define CMDEX_PUSH_MOV_SEG_implicit_FS 4'd4
187
+ `define CMD_Arith 7'd64
188
+ `define CMDEX_task_switch_STEP_13 4'd13
189
+ `define CMDEX_task_switch_STEP_14 4'd14
190
+ `define CMDEX_POPF_STEP_1 4'd1
191
+ `define CMDEX_task_switch_STEP_11 4'd11
192
+ `define CMDEX_POPF_STEP_0 4'd0
193
+ `define CMDEX_task_switch_STEP_12 4'd12
194
+ `define CMDEX_ESC_STEP_0 4'd1
195
+ `define CMDEX_task_switch_STEP_10 4'd10
196
+ `define CMDEX_debug_reg_MOV_store_STEP_0 4'd0
197
+ `define CMD_LAR 7'd79
198
+ `define CMDEX_CALL_Jv_STEP_0 4'd1
199
+ `define CMDEX_JMP_Ep_STEP_1 4'd5
200
+ `define CMD_DAA 7'd114
201
+ `define CMDEX_JMP_Ep_STEP_0 4'd2
202
+ `define CMDEX_PUSH_MOV_SEG_implicit_ES 4'd0
203
+ `define CMD_WBINVD 7'd58
204
+ `define CMDEX_IN_idle 4'd3
205
+ `define CMDEX_int_protected_STEP_0 4'd8
206
+ `define CMDEX_int_protected_STEP_1 4'd9
207
+ `define CMDEX_int_protected_STEP_2 4'd10
208
+ `define CMDEX_INC_DEC_increment_modregrm 4'd2
209
+ `define CMDEX_INT_INTO_INTO_STEP_0 4'd2
210
+ `define CMDEX_IRET_2_idle 4'd0
211
+ `define CMDEX_PUSHA_STEP_1 4'd1
212
+ `define CMDEX_PUSHA_STEP_2 4'd2
213
+ `define CMDEX_PUSHA_STEP_3 4'd3
214
+ `define CMDEX_PUSHA_STEP_4 4'd4
215
+ `define CMDEX_PUSHA_STEP_5 4'd5
216
+ `define CMDEX_CPUID_STEP_LAST 4'd0
217
+ `define CMDEX_PUSHA_STEP_6 4'd6
218
+ `define CMDEX_PUSHA_STEP_7 4'd7
219
+ `define CMD_DAS 7'd115
220
+ `define CMDEX_PUSHA_STEP_0 4'd0
221
+ `define CMDEX_CALL_protected_seg_STEP_2 4'd15
222
+ `define CMDEX_CALL_protected_seg_STEP_1 4'd14
223
+ `define CMD_LxS 7'd18
224
+ `define CMDEX_CALL_protected_seg_STEP_0 4'd13
225
+ `define CMDEX_ENTER_FIRST 4'd0
226
+ `define CMDEX_IRET_real_v86_STEP_2 4'd2
227
+ `define CMDEX_BTx_modregrm_imm 4'd0
228
+ `define CMDEX_IRET_real_v86_STEP_3 4'd3
229
+ `define CMDEX_IRET_real_v86_STEP_0 4'd0
230
+ `define CMDEX_IRET_real_v86_STEP_1 4'd1
231
+ `define CMDEX_CALL_Ev_Jv_STEP_1 4'd4
232
+ `define CMDEX_IRET_task_switch_STEP_1 4'd6
233
+ `define CMDEX_IRET_task_switch_STEP_0 4'd5
234
+ `define CMD_INC_DEC 7'd14
235
+ `define CMDEX_POP_modregrm_STEP_1 4'd2
236
+ `define CMDEX_Arith_modregrm 4'd1
237
+ `define CMD_BSR 7'd117
238
+ `define CMDEX_CALL_2_call_gate_STEP_1 4'd6
239
+ `define CMDEX_CALL_2_call_gate_STEP_0 4'd5
240
+ `define CMD_BSF 7'd116
241
+ `define CMDEX_CALL_2_call_gate_STEP_2 4'd7
242
+ `define CMDEX_WBINVD_STEP_1 4'd1
243
+ `define CMDEX_int_2_int_trap_gate_same_STEP_5 4'd5
244
+ `define CMDEX_WBINVD_STEP_0 4'd0
245
+ `define CMDEX_int_2_int_trap_gate_same_STEP_4 4'd4
246
+ `define CMDEX_int_2_int_trap_gate_same_STEP_3 4'd3
247
+ `define CMDEX_WBINVD_STEP_2 4'd2
248
+ `define CMDEX_STOS_STEP_0 4'd0
249
+ `define CMDEX_int_2_int_trap_gate_same_STEP_2 4'd2
250
+ `define CMD_STOS 7'd83
251
+ `define CMDEX_int_2_int_trap_gate_same_STEP_1 4'd1
252
+ `define CMDEX_LOOP 4'd2
253
+ `define CMDEX_int_2_int_trap_gate_same_STEP_0 4'd0
254
+ `define CMDEX_INC_DEC_decrement_modregrm 4'd3
255
+ `define CMDEX_POP_modregrm_STEP_0 4'd1
256
+ `define CMDEX_Shift_modregrm 4'd1
257
+ `define CMDEX_POPA_STEP_7 4'd7
258
+ `define CMDEX_POPA_STEP_6 4'd6
259
+ `define CMDEX_PUSH_implicit 4'd0
260
+ `define CMD_IRET 7'd35
261
+ `define CMDEX_IRET_2_protected_to_v86_STEP_6 4'd10
262
+ `define CMDEX_RET_far_real_STEP_3 4'd3
263
+ `define CMDEX_task_switch_3_STEP_0 4'd0
264
+ `define CMDEX_task_switch_3_STEP_7 4'd7
265
+ `define CMDEX_task_switch_3_STEP_8 4'd8
266
+ `define CMD_int 7'd28
267
+ `define CMDEX_io_allow_2 4'd1
268
+ `define CMDEX_io_allow_1 4'd0
269
+ `define CMDEX_PUSH_MOV_SEG_implicit_SS 4'd2
270
+ `define CMDEX_IMUL_modregrm 4'd0
271
+ `define CMDEX_load_seg_STEP_2 4'd1
272
+ `define CMDEX_CALL_2_task_gate_STEP_1 4'd4
273
+ `define CMDEX_IMUL_modregrm_imm 4'd1
274
+ `define CMDEX_CALL_2_task_gate_STEP_0 4'd3
275
+ `define CMD_IMUL 7'd54
276
+ `define CMDEX_int_3_int_trap_gate_more_STEP_5 4'd5
277
+ `define CMDEX_int_3_int_trap_gate_more_STEP_6 4'd6
278
+ `define CMDEX_PUSH_MOV_SEG_implicit_TR 4'd7
279
+ `define CMD_LSL 7'd80
280
+ `define CMDEX_int_3_int_trap_gate_more_STEP_3 4'd3
281
+ `define CMDEX_INVLPG_STEP_1 4'd1
282
+ `define CMDEX_int_3_int_trap_gate_more_STEP_4 4'd4
283
+ `define CMDEX_INVLPG_STEP_0 4'd0
284
+ `define CMD_POPF 7'd94
285
+ `define CMDEX_int_3_int_trap_gate_more_STEP_1 4'd1
286
+ `define CMDEX_int_3_int_trap_gate_more_STEP_2 4'd2
287
+ `define CMDEX_INVLPG_STEP_2 4'd2
288
+ `define CMDEX_int_3_int_trap_gate_more_STEP_0 4'd0
289
+ `define CMD_POPA 7'd109
290
+ `define CMDEX_load_seg_STEP_1 4'd0
291
+ `define CMDEX_INC_DEC_modregrm 4'd2
292
+ `define CMDEX_IRET_2_protected_outer_STEP_4 4'd7
293
+ `define CMDEX_RET_far_STEP_2 4'd2
294
+ `define CMDEX_IRET_2_protected_outer_STEP_5 4'd8
295
+ `define CMDEX_RET_far_STEP_1 4'd1
296
+ `define CMDEX_IRET_2_protected_outer_STEP_6 4'd9
297
+ `define CMDEX_IRET_2_protected_outer_STEP_0 4'd3
298
+ `define CMDEX_IRET_2_protected_outer_STEP_1 4'd4
299
+ `define CMDEX_IRET_2_protected_outer_STEP_2 4'd5
300
+ `define CMDEX_CMPS_LAST 4'd1
301
+ `define CMDEX_IRET_2_protected_outer_STEP_3 4'd6
302
+ `define CMD_OUTS 7'd85
303
+ `define CMDEX_MOV_immediate 4'd0
304
+ `define CMDEX_JMP_task_switch_STEP_0 4'd13
305
+ `define CMDEX_MOV_modregrm 4'd1
306
+ `define CMDEX_int_real_STEP_4 4'd6
307
+ `define CMD_LTR 7'd21
308
+ `define CMDEX_int_real_STEP_5 4'd7
309
+ `define TASK_SWITCH_SOURCE_BITS 17:16
310
+ `define CMDEX_debug_reg_MOV_load_STEP_0 4'd1
311
+ `define CMDEX_debug_reg_MOV_load_STEP_1 4'd2
312
+ `define CMDEX_INC_DEC_increment_implicit 4'd0
313
+ `define CMDEX_JMP_Ap_STEP_1 4'd6
314
+ `define CMDEX_JMP_Ap_STEP_0 4'd3
315
+ `define CMD_SUB 7'd69
316
+ `define CMDEX_JMP_task_gate_STEP_1 4'd15
317
+ `define CMDEX_JMP_task_gate_STEP_0 4'd14
318
+ `define CMD_SHRD 7'd57
319
+ `define CMDEX_OUT_dx 4'd1
320
+ `define CMDEX_PUSH_MOV_SEG_modregrm_TR 4'd15
321
+ `define CMD_CALL_2 7'd4
322
+ `define CMD_CALL_3 7'd5
323
+ `define CMD_CWD 7'd93
324
+ `define CMDEX_JMP_2_call_gate_STEP_3 4'd3
325
+ `define CMDEX_JMP_2_call_gate_STEP_2 4'd2
326
+ `define CMD_STI 7'd96
327
+ `define CMD_LEAVE 7'd55
328
+ `define CMDEX_JMP_2_call_gate_STEP_1 4'd1
329
+ `define CMDEX_JMP_2_call_gate_STEP_0 4'd0
330
+ `define CMD_INS 7'd84
331
+ `define CMD_STC 7'd25
332
+ `define CMDEX_IRET_2_protected_same_STEP_1 4'd2
333
+ `define CMD_STD 7'd26
334
+ `define CMD_LOOP 7'd60
335
+ `define CMD_XLAT 7'd111
336
+ `define CMDEX_ENTER_PUSH 4'd2
337
+ `define CMDEX_IRET_2_protected_same_STEP_0 4'd1
338
+ `define CMDEX_CALL_2_task_switch_STEP_0 4'd2
339
+ `define CMDEX_MOV_memoffset 4'd3
340
+ `define CMD_BTx 7'd36
341
+ `define CMDEX_PUSH_MOV_SEG_modregrm_SS 4'd10
342
+ `define CMD_AND 7'd68
343
+ `define CMDEX_int_task_gate_STEP_1 4'd12
344
+ `define CMDEX_int_task_gate_STEP_0 4'd11
345
+ `define CMDEX_CALL_Ev_STEP_0 4'd0
346
+ `define CMDEX_Shift_modregrm_imm 4'd2
347
+ `define CMDEX_INC_DEC_decrement_implicit 4'd1
348
+ `define CMD_POP_seg 7'd34
349
+ `define CMD_CALL 7'd3
350
+ `define CMDEX_XCHG_implicit 4'd0
351
+ `define CMDEX_JMP_protected_seg_STEP_1 4'd12
352
+ `define CMDEX_JMP_protected_seg_STEP_0 4'd11
353
+ `define CMDEX_POPA_STEP_3 4'd3
354
+ `define CMDEX_POPA_STEP_2 4'd2
355
+ `define CMDEX_POPA_STEP_5 4'd5
356
+ `define CMDEX_POPA_STEP_4 4'd4
357
+ `define CMD_BSx 7'd116
358
+ `define CMD_NEG 7'd7
359
+ `define CMDEX_POPA_STEP_1 4'd1
360
+ `define CMDEX_POPA_STEP_0 4'd0
361
+ `define CMDEX_Shift_implicit 4'd0
362
+ `define CMDEX_MOV_to_seg_LLDT_LTR_STEP_LAST 4'd1
363
+ `define CMDEX_task_switch_2_STEP_0 4'd0
364
+ `define CMD_BTS 7'd37
365
+ `define CMDEX_XADD_FIRST 4'd0
366
+ `define CMD_BTR 7'd38
367
+ `define CMD_SHxD 7'd56
368
+ `define CMD_BTC 7'd39
369
+ `define CMD_OR 7'd65
370
+ `define CMDEX_task_switch_2_STEP_7 4'd7
371
+ `define CMD_task_switch_2 7'd100
372
+ `define CMD_task_switch_3 7'd101
373
+ `define CMD_task_switch_4 7'd102
374
+ `define CMD_CLTS 7'd62
375
+ `define CMDEX_RET_near 4'd0
376
+ `define CMD_JMP 7'd87
377
+ `define CMD_POP 7'd41
378
+ `define CMDEX_RET_near_LAST 4'd2
379
+ `define CMD_BOUND 7'd97
380
+ `define CMDEX_int_STEP_0 4'd0
381
+ `define CMD_XOR 7'd70
382
+ `define CMD_JCXZ 7'd2
383
+ `define CMDEX_ENTER_LAST 4'd1
384
+ `define CMDEX_task_switch_3_STEP_15 4'd15
385
+ `define CMDEX_OUT_imm 4'd0
386
+ `define CMD_JMP_2 7'd88
387
+ `define CMDEX_PUSH_MOV_SEG_modregrm_GS 4'd13
388
+ `define CMD_CMPXCHG 7'd52
389
+ `define CMDEX_task_switch_3_STEP_12 4'd12
390
+ `define CMDEX_OUTS_first 4'd0
391
+ `define CMDEX_control_reg_MOV_store_STEP_0 4'd3
392
+ `define CMD_XADD 7'd1
393
+ `define CMDEX_LAR_LSL_VERR_VERW_STEP_LAST 4'd2
394
+ `define CMD_RET_far 7'd63
395
+ `define CMD_SHLD 7'd56
396
+ `define CMD_CMC 7'd24
397
+ `define CMDEX_BOUND_STEP_LAST 4'd1
398
+ `define CMDEX_SHxD_modregrm_imm 4'd1
399
+ `define CMD_HLT 7'd12
400
+ `define CMDEX_LxS_STEP_LAST 4'd3
401
+ `define CMD_ARPL 7'd16
402
+ `define CMDEX_JMP_Ev_Jv_STEP_1 4'd4
403
+ `define CMD_ENTER 7'd53
404
+ `define CMD_SALC 7'd98
405
+ `define CMD_CLD 7'd23
406
+ `define CMD_CLC 7'd22
407
+ `define CMDEX_INT_INTO_INT_STEP_0 4'd0
408
+ `define CMD_CLI 7'd95
409
+ `define CMD_LLDT 7'd20
410
+ `define CMDEX_INT_INTO_INT1_STEP_0 4'd3
411
+ `define CMD_RET_near 7'd15
412
+ `define CMD_VERW 7'd82
413
+ `define CMDEX_JMP_Ev_STEP_0 4'd0
414
+ `define CMD_VERR 7'd81
415
+ `define CMDEX_IRET_protected_to_v86_STEP_0 4'd10
416
+ `define CMDEX_IRET_protected_to_v86_STEP_1 4'd11
417
+ `define CMDEX_IRET_protected_to_v86_STEP_4 4'd14
418
+ `define CMDEX_IRET_protected_to_v86_STEP_5 4'd15
419
+ `define CMDEX_IRET_protected_to_v86_STEP_2 4'd12
420
+ `define CMD_IN 7'd77
421
+ `define CMDEX_IRET_protected_to_v86_STEP_3 4'd13
422
+ `define CMD_CMP 7'd71
423
+ `define CMDEX_SALC_STEP_0 4'd0
424
+ `define CMDEX_LxS_STEP_3 4'd2
425
+ `define CMDEX_CALL_3_call_gate_more_STEP_8 4'd4
426
+ `define CMDEX_CALL_3_call_gate_more_STEP_7 4'd3
427
+ `define CMDEX_LxS_STEP_1 4'd0
428
+ `define CMDEX_LxS_STEP_2 4'd1
429
+ `define CMDEX_CALL_3_call_gate_more_STEP_9 4'd5
430
+ `define CMDEX_CALL_3_call_gate_more_STEP_5 4'd1
431
+ `define TASK_SWITCH_FROM_JUMP 2'd3
432
+ `define CMDEX_CALL_3_call_gate_more_STEP_6 4'd2
433
+ `define CMDEX_CALL_3_call_gate_more_STEP_4 4'd0
434
+ `define TASK_SWITCH_FROM_CALL 2'd2
435
+ `define CMDEX_TEST_modregrm_imm 4'd2
436
+ `define CMD_XCHG 7'd73
437
+ `define CMD_debug_reg 7'd110
438
+ `define CMDEX_CALL_protected_STEP_1 4'd12
439
+ `define CMDEX_POP_seg_STEP_LAST 4'd1
440
+ `define CMDEX_CALL_protected_STEP_0 4'd11
441
+ `define CMDEX_RET_far_outer_STEP_7 4'd10
442
+ `define CMDEX_RET_far_outer_STEP_3 4'd6
443
+ `define CMDEX_RET_far_outer_STEP_4 4'd7
444
+ `define CMDEX_RET_far_outer_STEP_5 4'd8
445
+ `define CMDEX_RET_far_outer_STEP_6 4'd9
446
+ `define CMDEX_CALL_Ap_STEP_1 4'd6
447
+ `define CMDEX_CALL_Ap_STEP_0 4'd3
448
+ `define CMD_INVD 7'd9
449
+ `define CMDEX_PUSH_immediate_se 4'd1
snapshots/MiSTer-devel_ao486_MiSTer_pr72/rtl/ao486/autogen/exception.v ADDED
@@ -0,0 +1,95 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ //======================================================== conditions
2
+ wire cond_0 = exception_init || wr_debug_init;
3
+ wire cond_1 = ~(class_trap) && ~(class_abort);
4
+ wire cond_2 = wr_is_esp_speculative;
5
+ wire cond_3 = vector != `EXCEPTION_DB;
6
+ wire cond_4 = vector == `EXCEPTION_DB;
7
+ wire cond_5 = wr_debug_init && ~(wr_string_in_progress_final);
8
+ wire cond_6 = wr_debug_init && wr_string_in_progress_final;
9
+ wire cond_7 = shutdown_start == `FALSE && count > 2'd0 && exception_type != `EXCEPTION_TYPE_DOUBLE_FAULT && (
10
+ (last_type == `EXCEPTION_TYPE_CONTRIBUTORY && exception_type == `EXCEPTION_TYPE_CONTRIBUTORY) ||
11
+ (last_type == `EXCEPTION_TYPE_PAGE_FAULT && exception_type == `EXCEPTION_TYPE_CONTRIBUTORY) ||
12
+ (last_type == `EXCEPTION_TYPE_PAGE_FAULT && exception_type == `EXCEPTION_TYPE_PAGE_FAULT));
13
+ wire cond_8 = shutdown_start == `FALSE;
14
+ wire cond_9 = shutdown_start;
15
+ wire cond_10 = shutdown;
16
+ wire cond_11 = interrupt_done;
17
+ //======================================================== saves
18
+ assign exc_soft_int_to_reg =
19
+ (cond_0 && ~cond_7 && cond_8)? ( `FALSE) :
20
+ (cond_11)? ( `FALSE) :
21
+ exc_soft_int;
22
+ assign exc_push_error_to_reg =
23
+ (cond_0 && ~cond_7 && cond_8)? ( push_error) :
24
+ (cond_11)? ( `FALSE) :
25
+ exc_push_error;
26
+ assign count_to_reg =
27
+ (cond_0 && ~cond_7 && cond_8)? ( count + 2'd1) :
28
+ count;
29
+ assign exc_eip_to_reg =
30
+ (cond_0 && ~cond_1)? ( trap_eip) :
31
+ (cond_0 && cond_4 && cond_5)? ( wr_eip) :
32
+ (cond_0 && cond_4 && cond_6)? ( exception_eip_from_wr) :
33
+ (cond_11)? ( (interrupt_string_in_progress)? exception_eip_from_wr : wr_eip) :
34
+ exc_eip;
35
+ assign external_to_reg =
36
+ (cond_0)? ( `TRUE) :
37
+ (cond_11)? ( `TRUE) :
38
+ external;
39
+ assign last_type_to_reg =
40
+ (cond_0 && ~cond_7 && cond_8)? ( exception_type) :
41
+ last_type;
42
+ assign exc_vector_full_to_reg =
43
+ (cond_0 && cond_7)? ( { 1'b1, `EXCEPTION_DF }) :
44
+ (cond_0 && ~cond_7 && cond_8)? ( { 1'b0, vector }) :
45
+ (cond_0 && cond_9)? ( { 1'b0, vector }) :
46
+ (cond_11)? ( { 1'b0, interrupt_vector }) :
47
+ exc_vector_full;
48
+ assign exc_error_code_to_reg =
49
+ (cond_0 && cond_7)? ( 16'd0) :
50
+ (cond_0 && ~cond_7 && cond_8)? ( error_code) :
51
+ (cond_11)? ( 16'd0) :
52
+ exc_error_code;
53
+ assign exc_soft_int_ib_to_reg =
54
+ (cond_0 && ~cond_7 && cond_8)? ( `FALSE) :
55
+ (cond_11)? ( `FALSE) :
56
+ exc_soft_int_ib;
57
+ assign shutdown_to_reg =
58
+ (cond_0 && cond_9)? ( `TRUE) :
59
+ shutdown;
60
+ //======================================================== always
61
+ //======================================================== sets
62
+ assign exc_set_rflag =
63
+ (cond_0 && cond_1 && cond_3)? (`TRUE) :
64
+ 1'd0;
65
+ assign exc_dec_reset =
66
+ (cond_0)? (`TRUE) :
67
+ (cond_10)? (`TRUE) :
68
+ (cond_11)? (`TRUE) :
69
+ 1'd0;
70
+ assign exc_restore_esp =
71
+ (cond_0 && cond_1 && cond_2)? (`TRUE) :
72
+ 1'd0;
73
+ assign exc_micro_reset =
74
+ (cond_0)? (`TRUE) :
75
+ (cond_10)? (`TRUE) :
76
+ (cond_11)? (`TRUE) :
77
+ 1'd0;
78
+ assign exc_wr_reset =
79
+ (cond_0)? (`TRUE) :
80
+ (cond_10)? (`TRUE) :
81
+ (cond_11)? (`TRUE) :
82
+ 1'd0;
83
+ assign exc_rd_reset =
84
+ (cond_0)? (`TRUE) :
85
+ (cond_10)? (`TRUE) :
86
+ (cond_11)? (`TRUE) :
87
+ 1'd0;
88
+ assign exc_exe_reset =
89
+ (cond_0)? (`TRUE) :
90
+ (cond_10)? (`TRUE) :
91
+ (cond_11)? (`TRUE) :
92
+ 1'd0;
93
+ assign exception_start =
94
+ (cond_0 && ~cond_7 && cond_8)? (`TRUE) :
95
+ 1'd0;
snapshots/MiSTer-devel_ao486_MiSTer_pr72/rtl/ao486/autogen/execute_commands.v ADDED
@@ -0,0 +1,1157 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ wire exe_jecxz_condition;
2
+ assign exe_jecxz_condition = (exe_address_16bit)? ecx[15:0] == 16'd0 : ecx == 32'd0;
3
+
4
+ reg e_invd_code_done;
5
+ reg e_invd_data_done;
6
+ always @(posedge clk) begin if(rst_n == 1'b0) e_invd_code_done <= `FALSE; else if(exe_reset) e_invd_code_done <= `FALSE; else if(exe_ready) e_invd_code_done <= `FALSE; else if(invdcode_done) e_invd_code_done <= `TRUE;
7
+ end
8
+ always @(posedge clk) begin if(rst_n == 1'b0) e_invd_data_done <= `FALSE; else if(exe_reset) e_invd_data_done <= `FALSE; else if(exe_ready) e_invd_data_done <= `FALSE; else if(invddata_done) e_invd_data_done <= `TRUE;
9
+ end
10
+
11
+ wire [3:0] e_io_allow_bits;
12
+ assign e_io_allow_bits = (glob_param_1[2:0] == 3'd0)? src[3:0] : (glob_param_1[2:0] == 3'd1)? src[4:1] : (glob_param_1[2:0] == 3'd2)? src[5:2] : (glob_param_1[2:0] == 3'd3)? src[6:3] : (glob_param_1[2:0] == 3'd4)? src[7:4] : (glob_param_1[2:0] == 3'd5)? src[8:5] : (glob_param_1[2:0] == 3'd6)? src[9:6] : src[10:7];
13
+
14
+ wire exe_int_2_int_trap_same_exception;
15
+ assign exe_int_2_int_trap_same_exception = (v8086_mode && (`DESC_IS_CODE_CONFORMING(exe_descriptor) || exe_descriptor[`DESC_BITS_DPL] != 2'd0));
16
+
17
+ wire [7:0] e_aad_result;
18
+ assign e_aad_result = mult_result[7:0] + dst[7:0];
19
+
20
+ wire [1:0] e_cpl_current;
21
+ assign e_cpl_current = (glob_param_1[`MC_PARAM_1_FLAG_CPL_FROM_PARAM_3_BIT])? glob_param_3[`SELECTOR_BITS_RPL] : cpl;
22
+ assign exe_load_seg_gp_fault = exe_cmd == `CMD_load_seg && exe_cmdex == `CMDEX_load_seg_STEP_2 && ( (exe_segment < `SEGMENT_LDT && exe_segment != `SEGMENT_CS) && ( exe_descriptor[`DESC_BIT_SEG] == `FALSE || (exe_segment == `SEGMENT_SS && ( exe_selector[`SELECTOR_BITS_RPL] != e_cpl_current || `DESC_IS_CODE(exe_descriptor) || `DESC_IS_DATA_RO(exe_descriptor) || exe_descriptor[`DESC_BITS_DPL] != e_cpl_current )) || (exe_segment != `SEGMENT_SS && ( `DESC_IS_CODE_EO(exe_descriptor) || ((`DESC_IS_DATA(exe_descriptor) || `DESC_IS_CODE_NON_CONFORMING(exe_descriptor)) && exe_privilege_not_accepted) )) ) || (exe_segment == `SEGMENT_LDT && (exe_descriptor[`DESC_BIT_SEG] || exe_descriptor[`DESC_BITS_TYPE] != `DESC_LDT) ) || (exe_segment == `SEGMENT_TR && (exe_descriptor[`DESC_BIT_SEG] || (exe_descriptor[`DESC_BITS_TYPE] != `DESC_TSS_AVAIL_386 && exe_descriptor[`DESC_BITS_TYPE] != `DESC_TSS_AVAIL_286)) ) || (exe_segment == `SEGMENT_CS && ( exe_selector[`SELECTOR_BITS_RPL] < cpl || exe_descriptor[`DESC_BIT_SEG] == `FALSE || `DESC_IS_DATA(exe_descriptor) || (`DESC_IS_CODE_NON_CONFORMING(exe_descriptor) && exe_descriptor[`DESC_BITS_DPL] != exe_selector[`SELECTOR_BITS_RPL]) || (`DESC_IS_CODE_CONFORMING(exe_descriptor) && exe_descriptor[`DESC_BITS_DPL] > exe_selector[`SELECTOR_BITS_RPL]) )) );
23
+ assign exe_load_seg_ss_fault = exe_cmd == `CMD_load_seg && exe_cmdex == `CMDEX_load_seg_STEP_2 && ~(glob_param_1[`MC_PARAM_1_FLAG_NP_NOT_SS_BIT]) && exe_segment == `SEGMENT_SS && exe_descriptor[`DESC_BIT_P] == `FALSE;
24
+ assign exe_load_seg_np_fault = exe_cmd == `CMD_load_seg && exe_cmdex == `CMDEX_load_seg_STEP_2 && (glob_param_1[`MC_PARAM_1_FLAG_NP_NOT_SS_BIT] || exe_segment != `SEGMENT_SS) && exe_descriptor[`DESC_BIT_P] == `FALSE;
25
+
26
+ wire [4:0] e_bit_selector;
27
+ wire e_bit_selected;
28
+ wire e_bit_value;
29
+ wire [31:0] e_bit_result;
30
+ assign e_bit_selector = (exe_operand_16bit)? { 1'b0, src[3:0] } : src[4:0];
31
+ assign e_bit_selected = (e_bit_selector == 5'd0)? dst[0] : (e_bit_selector == 5'd1)? dst[1] : (e_bit_selector == 5'd2)? dst[2] : (e_bit_selector == 5'd3)? dst[3] : (e_bit_selector == 5'd4)? dst[4] : (e_bit_selector == 5'd5)? dst[5] : (e_bit_selector == 5'd6)? dst[6] : (e_bit_selector == 5'd7)? dst[7] : (e_bit_selector == 5'd8)? dst[8] : (e_bit_selector == 5'd9)? dst[9] : (e_bit_selector == 5'd10)? dst[10] : (e_bit_selector == 5'd11)? dst[11] : (e_bit_selector == 5'd12)? dst[12] : (e_bit_selector == 5'd13)? dst[13] : (e_bit_selector == 5'd14)? dst[14] : (e_bit_selector == 5'd15)? dst[15] : (e_bit_selector == 5'd16)? dst[16] : (e_bit_selector == 5'd17)? dst[17] : (e_bit_selector == 5'd18)? dst[18] : (e_bit_selector == 5'd19)? dst[19] : (e_bit_selector == 5'd20)? dst[20] : (e_bit_selector == 5'd21)? dst[21] : (e_bit_selector == 5'd22)? dst[22] : (e_bit_selector == 5'd23)? dst[23] : (e_bit_selector == 5'd24)? dst[24] : (e_bit_selector == 5'd25)? dst[25] : (e_bit_selector == 5'd26)? dst[26] : (e_bit_selector == 5'd27)? dst[27] : (e_bit_selector == 5'd28)? dst[28] : (e_bit_selector == 5'd29)? dst[29] : (e_bit_selector == 5'd30)? dst[30] : dst[31];
32
+ assign e_bit_value = (exe_cmd == `CMD_BTC)? ~e_bit_selected : (exe_cmd == `CMD_BTR)? 1'b0 : 1'b1;
33
+ assign e_bit_result = (e_bit_selector == 5'd0)? { dst[31:1], e_bit_value } : (e_bit_selector == 5'd1)? { dst[31:2], e_bit_value, dst[0] } : (e_bit_selector == 5'd2)? { dst[31:3], e_bit_value, dst[1:0] } : (e_bit_selector == 5'd3)? { dst[31:4], e_bit_value, dst[2:0] } : (e_bit_selector == 5'd4)? { dst[31:5], e_bit_value, dst[3:0] } : (e_bit_selector == 5'd5)? { dst[31:6], e_bit_value, dst[4:0] } : (e_bit_selector == 5'd6)? { dst[31:7], e_bit_value, dst[5:0] } : (e_bit_selector == 5'd7)? { dst[31:8], e_bit_value, dst[6:0] } : (e_bit_selector == 5'd8)? { dst[31:9], e_bit_value, dst[7:0] } : (e_bit_selector == 5'd9)? { dst[31:10], e_bit_value, dst[8:0] } : (e_bit_selector == 5'd10)? { dst[31:11], e_bit_value, dst[9:0] } : (e_bit_selector == 5'd11)? { dst[31:12], e_bit_value, dst[10:0] } : (e_bit_selector == 5'd12)? { dst[31:13], e_bit_value, dst[11:0] } : (e_bit_selector == 5'd13)? { dst[31:14], e_bit_value, dst[12:0] } : (e_bit_selector == 5'd14)? { dst[31:15], e_bit_value, dst[13:0] } : (e_bit_selector == 5'd15)? { dst[31:16], e_bit_value, dst[14:0] } : (e_bit_selector == 5'd16)? { dst[31:17], e_bit_value, dst[15:0] } : (e_bit_selector == 5'd17)? { dst[31:18], e_bit_value, dst[16:0] } : (e_bit_selector == 5'd18)? { dst[31:19], e_bit_value, dst[17:0] } : (e_bit_selector == 5'd19)? { dst[31:20], e_bit_value, dst[18:0] } : (e_bit_selector == 5'd20)? { dst[31:21], e_bit_value, dst[19:0] } : (e_bit_selector == 5'd21)? { dst[31:22], e_bit_value, dst[20:0] } : (e_bit_selector == 5'd22)? { dst[31:23], e_bit_value, dst[21:0] } : (e_bit_selector == 5'd23)? { dst[31:24], e_bit_value, dst[22:0] } : (e_bit_selector == 5'd24)? { dst[31:25], e_bit_value, dst[23:0] } : (e_bit_selector == 5'd25)? { dst[31:26], e_bit_value, dst[24:0] } : (e_bit_selector == 5'd26)? { dst[31:27], e_bit_value, dst[25:0] } : (e_bit_selector == 5'd27)? { dst[31:28], e_bit_value, dst[26:0] } : (e_bit_selector == 5'd28)? { dst[31:29], e_bit_value, dst[27:0] } : (e_bit_selector == 5'd29)? { dst[31:30], e_bit_value, dst[28:0] } : (e_bit_selector == 5'd30)? { dst[31], e_bit_value, dst[29:0] } : { e_bit_value, dst[30:0] };
34
+
35
+ wire [31:0] e_cr0_reg;
36
+ assign e_cr0_reg = { cr0_pg, cr0_cd, cr0_nw, 10'b0, cr0_am, 1'b0, cr0_wp, 10'b0, cr0_ne, 1'b1, cr0_ts, cr0_em, cr0_mp, cr0_pe };
37
+
38
+ wire e_cmpxchg_eq;
39
+ wire [32:0] e_cmpxchg_sub;
40
+ wire [31:0] e_cmpxchg_result;
41
+ assign e_cmpxchg_eq = (exe_is_8bit && eax[7:0] == dst[7:0]) || (exe_operand_16bit && eax[15:0] == dst[15:0]) || (exe_operand_32bit && eax[31:0] == dst[31:0]);
42
+ assign e_cmpxchg_sub = eax - dst;
43
+ assign e_cmpxchg_result = (e_cmpxchg_eq)? src : e_cmpxchg_sub[31:0];
44
+
45
+ reg e_wbinvd_code_done;
46
+ reg e_wbinvd_data_done;
47
+ always @(posedge clk) begin if(rst_n == 1'b0) e_wbinvd_code_done <= `FALSE; else if(exe_reset) e_wbinvd_code_done <= `FALSE; else if(exe_ready) e_wbinvd_code_done <= `FALSE; else if(invdcode_done) e_wbinvd_code_done <= `TRUE;
48
+ end
49
+ always @(posedge clk) begin if(rst_n == 1'b0) e_wbinvd_data_done <= `FALSE; else if(exe_reset) e_wbinvd_data_done <= `FALSE; else if(exe_ready) e_wbinvd_data_done <= `FALSE; else if(wbinvddata_done) e_wbinvd_data_done <= `TRUE;
50
+ end
51
+
52
+ wire exe_cmd_loop_ecx;
53
+ wire exe_cmd_loop_condition;
54
+ assign exe_cmd_loop_ecx = (exe_address_16bit)? ecx[15:0] != 16'd1 : ecx != 32'd1;
55
+ assign exe_cmd_loop_condition = (exe_cmdex == `CMDEX_LOOP_NE)? exe_cmd_loop_ecx && zflag == `FALSE : (exe_cmdex == `CMDEX_LOOP_E)? exe_cmd_loop_ecx && zflag == `TRUE : exe_cmd_loop_ecx;
56
+
57
+ wire exe_cmd_lar_desc_invalid;
58
+ wire exe_cmd_lsl_desc_invalid;
59
+ wire exe_cmd_verr_desc_invalid;
60
+ wire exe_cmd_verw_desc_invalid;
61
+ assign exe_cmd_lar_desc_invalid = (~(exe_descriptor[`DESC_BIT_SEG]) && (exe_descriptor[`DESC_BITS_TYPE] == 4'd0 || exe_descriptor[`DESC_BITS_TYPE] == 4'd8 || exe_descriptor[`DESC_BITS_TYPE] == 4'd10 || exe_descriptor[`DESC_BITS_TYPE] == 4'd13) ) || (exe_descriptor[`DESC_BIT_SEG] && (`DESC_IS_DATA(exe_descriptor) || `DESC_IS_CODE_NON_CONFORMING(exe_descriptor)) && exe_privilege_not_accepted ) || (~(exe_descriptor[`DESC_BIT_SEG]) && (exe_descriptor[`DESC_BITS_TYPE] == `DESC_INTERRUPT_GATE_386 || exe_descriptor[`DESC_BITS_TYPE] == `DESC_INTERRUPT_GATE_286 || exe_descriptor[`DESC_BITS_TYPE] == `DESC_TRAP_GATE_386 || exe_descriptor[`DESC_BITS_TYPE] == `DESC_TRAP_GATE_286) ) || (~(exe_descriptor[`DESC_BIT_SEG]) && exe_privilege_not_accepted );
62
+ assign exe_cmd_lsl_desc_invalid = (~(exe_descriptor[`DESC_BIT_SEG]) && (exe_descriptor[`DESC_BITS_TYPE] != `DESC_TSS_AVAIL_386 && exe_descriptor[`DESC_BITS_TYPE] != `DESC_TSS_BUSY_386 && exe_descriptor[`DESC_BITS_TYPE] != `DESC_TSS_AVAIL_286 && exe_descriptor[`DESC_BITS_TYPE] != `DESC_TSS_BUSY_286 && exe_descriptor[`DESC_BITS_TYPE] != `DESC_LDT) ) || (~(exe_descriptor[`DESC_BIT_SEG]) && exe_privilege_not_accepted ) || (exe_descriptor[`DESC_BIT_SEG] && (`DESC_IS_DATA(exe_descriptor) || `DESC_IS_CODE_NON_CONFORMING(exe_descriptor)) && exe_privilege_not_accepted );
63
+ assign exe_cmd_verr_desc_invalid = (~(exe_descriptor[`DESC_BIT_SEG]) ) || (`DESC_IS_CODE_EO(exe_descriptor) || (`DESC_IS_CODE_NON_CONFORMING(exe_descriptor) && exe_privilege_not_accepted) ) || (`DESC_IS_DATA(exe_descriptor) && exe_privilege_not_accepted );
64
+ assign exe_cmd_verw_desc_invalid = (~(exe_descriptor[`DESC_BIT_SEG]) ) || (`DESC_IS_CODE(exe_descriptor) ) || (`DESC_IS_DATA_RO(exe_descriptor) || exe_privilege_not_accepted );
65
+
66
+ wire signed [31:0] e_bound_min;
67
+ wire signed [31:0] e_bound_max;
68
+ wire signed [31:0] e_bound_dst;
69
+ assign e_bound_min = (exe_operand_16bit)? { {16{exe_buffer[15]}}, exe_buffer[15:0] } : exe_buffer;
70
+ assign e_bound_max = (exe_operand_16bit)? { {16{src[15]}}, src[15:0] } : src;
71
+ assign e_bound_dst = (exe_operand_16bit)? { {16{dst[15]}}, dst[15:0] } : dst;
72
+ assign exe_bound_fault = exe_cmd == `CMD_BOUND && exe_cmdex == `CMDEX_BOUND_STEP_LAST && (e_bound_dst < e_bound_min || e_bound_dst > e_bound_max);
73
+
74
+ wire [31:0] exe_new_tss_max;
75
+ assign exe_new_tss_max = (glob_descriptor[`DESC_BITS_TYPE] <= 4'd3)? 32'h2B : 32'h67;
76
+
77
+ wire e_bcd_condition_cf;
78
+ wire exe_bcd_condition_af;
79
+ wire exe_bcd_condition_cf;
80
+ wire [15:0] e_aaa_result;
81
+ wire [15:0] e_aas_result;
82
+ wire [7:0] e_daa_sum_low;
83
+ wire [7:0] e_daa_step1;
84
+ wire [7:0] e_daa_sum_high;
85
+ wire [7:0] e_daa_result;
86
+ wire [7:0] e_das_sub_low;
87
+ wire [7:0] e_das_step1;
88
+ wire [7:0] e_das_sub_high;
89
+ wire [7:0] e_das_result;
90
+ assign e_bcd_condition_cf = (dst[7:0] > 8'h99 || cflag);
91
+ assign exe_bcd_condition_af = dst[3:0] > 4'd9 || aflag;
92
+ assign exe_bcd_condition_cf = e_bcd_condition_cf || (exe_bcd_condition_af && (cflag || (exe_cmd == `CMD_DAA)? dst[7:0] > 8'hF9 : dst[7:0] < 8'h06));
93
+ assign e_aaa_sum_ax = dst[15:0] + 16'h0106;
94
+ assign e_aaa_result = (exe_bcd_condition_af)? { e_aaa_sum_ax[15:8], 4'b0, e_aaa_sum_ax[3:0] } : { dst[15:8], 4'd0, dst[3:0] };
95
+ assign e_aas_sub_ax = dst[15:0] - 16'h0106;
96
+ assign e_aas_result = (exe_bcd_condition_af)? { e_aas_sub_ax[15:8], 4'b0, e_aas_sub_ax[3:0] } : { dst[15:8], 4'b0, dst[3:0] };
97
+ assign e_daa_sum_low = dst[7:0] + 8'h06;
98
+ assign e_daa_step1 = (exe_bcd_condition_af)? e_daa_sum_low : dst[7:0];
99
+ assign e_daa_sum_high = e_daa_step1 + 8'h60;
100
+ assign e_daa_result = (e_bcd_condition_cf)? e_daa_sum_high : e_daa_step1;
101
+ assign e_das_sub_low = dst[7:0] - 8'h06;
102
+ assign e_das_step1 = (exe_bcd_condition_af)? e_das_sub_low : dst[7:0];
103
+ assign e_das_sub_high = e_das_step1 - 8'h60;
104
+ assign e_das_result = (e_bcd_condition_cf)? e_das_sub_high : e_das_step1;
105
+
106
+ wire [4:0] e_bit_scan_forward;
107
+ wire e_bit_scan_zero;
108
+ wire [31:0] e_src_ze;
109
+ wire [4:0] e_bit_scan_reverse;
110
+ assign e_bit_scan_forward = (src[0])? 5'd0 : (src[1])? 5'd1 : (src[2])? 5'd2 : (src[3])? 5'd3 : (src[4])? 5'd4 : (src[5])? 5'd5 : (src[6])? 5'd6 : (src[7])? 5'd7 : (src[8])? 5'd8 : (src[9])? 5'd9 : (src[10])? 5'd10 : (src[11])? 5'd11 : (src[12])? 5'd12 : (src[13])? 5'd13 : (src[14])? 5'd14 : (src[15])? 5'd15 : (src[16])? 5'd16 : (src[17])? 5'd17 : (src[18])? 5'd18 : (src[19])? 5'd19 : (src[20])? 5'd20 : (src[21])? 5'd21 : (src[22])? 5'd22 : (src[23])? 5'd23 : (src[24])? 5'd24 : (src[25])? 5'd25 : (src[26])? 5'd26 : (src[27])? 5'd27 : (src[28])? 5'd28 : (src[29])? 5'd29 : (src[30])? 5'd30 : (src[31])? 5'd31 : 5'd0;
111
+ assign e_src_ze = (exe_operand_16bit)? { 16'd0, src[15:0] } : src;
112
+ assign e_bit_scan_reverse = (e_src_ze[31])? 5'd31 : (e_src_ze[30])? 5'd30 : (e_src_ze[29])? 5'd29 : (e_src_ze[28])? 5'd28 : (e_src_ze[27])? 5'd27 : (e_src_ze[26])? 5'd26 : (e_src_ze[25])? 5'd25 : (e_src_ze[24])? 5'd24 : (e_src_ze[23])? 5'd23 : (e_src_ze[22])? 5'd22 : (e_src_ze[21])? 5'd21 : (e_src_ze[20])? 5'd20 : (e_src_ze[19])? 5'd19 : (e_src_ze[18])? 5'd18 : (e_src_ze[17])? 5'd17 : (e_src_ze[16])? 5'd16 : (e_src_ze[15])? 5'd15 : (e_src_ze[14])? 5'd14 : (e_src_ze[13])? 5'd13 : (e_src_ze[12])? 5'd12 : (e_src_ze[11])? 5'd11 : (e_src_ze[10])? 5'd10 : (e_src_ze[9])? 5'd9 : (e_src_ze[8])? 5'd8 : (e_src_ze[7])? 5'd7 : (e_src_ze[6])? 5'd6 : (e_src_ze[5])? 5'd5 : (e_src_ze[4])? 5'd4 : (e_src_ze[3])? 5'd3 : (e_src_ze[2])? 5'd2 : (e_src_ze[1])? 5'd1 : (e_src_ze[0])? 5'd0 : 5'd0;
113
+ assign e_bit_scan_zero = (exe_operand_16bit)? src[15:0] == 16'd0 : src[31:0] == 32'd0;
114
+
115
+ //======================================================== conditions
116
+ wire cond_0 = exe_cmd == `CMD_XADD && exe_cmdex == `CMDEX_XADD_FIRST;
117
+ wire cond_1 = exe_cmd == `CMD_XADD && exe_cmdex == `CMDEX_XADD_LAST;
118
+ wire cond_2 = exe_cmd == `CMD_JCXZ;
119
+ wire cond_3 = exe_mutex_current[`MUTEX_ECX_BIT];
120
+ wire cond_4 = exe_jecxz_condition && exe_branch_eip > cs_limit;
121
+ wire cond_5 = exe_cmd == `CMD_CALL && exe_cmdex == `CMDEX_CALL_protected_STEP_1;
122
+ wire cond_6 = exe_cmd == `CMD_CALL_2 && exe_cmdex == `CMDEX_CALL_2_protected_seg_STEP_3;
123
+ wire cond_7 = glob_param_2 > glob_desc_limit;
124
+ wire cond_8 = exe_cmd == `CMD_CALL && (exe_cmdex == `CMDEX_CALL_Ev_STEP_0 || exe_cmdex == `CMDEX_CALL_Ep_STEP_0 || exe_cmdex == `CMDEX_CALL_Ap_STEP_0);
125
+ wire cond_9 = exe_cmdex == `CMDEX_CALL_Ev_STEP_0;
126
+ wire cond_10 = exe_mutex_current[`MUTEX_ESP_BIT];
127
+ wire cond_11 = exe_operand_32bit;
128
+ wire cond_12 = exe_cmd == `CMD_CALL && exe_cmdex == `CMDEX_CALL_Jv_STEP_0;
129
+ wire cond_13 = exe_cmd == `CMD_CALL && exe_cmdex == `CMDEX_CALL_Ev_Jv_STEP_1;
130
+ wire cond_14 = glob_param_2 > cs_limit;
131
+ wire cond_15 = exe_cmd == `CMD_CALL && exe_cmdex == `CMDEX_CALL_Ep_STEP_1;
132
+ wire cond_16 = exe_cmd == `CMD_CALL && exe_cmdex == `CMDEX_CALL_Ap_STEP_1;
133
+ wire cond_17 = exe_cmd == `CMD_CALL && exe_cmdex == `CMDEX_CALL_real_v8086_STEP_0;
134
+ wire cond_18 = exe_operand_32bit && glob_param_2 > cs_limit;
135
+ wire cond_19 = exe_cmd == `CMD_CALL && exe_cmdex == `CMDEX_CALL_real_v8086_STEP_1;
136
+ wire cond_20 = exe_mutex_current[`MUTEX_ACTIVE_BIT];
137
+ wire cond_21 = exe_cmd == `CMD_CALL && exe_cmdex == `CMDEX_CALL_real_v8086_STEP_2;
138
+ wire cond_22 = exe_operand_16bit && glob_param_2 > cs_limit;
139
+ wire cond_23 = exe_cmd == `CMD_CALL && exe_cmdex == `CMDEX_CALL_real_v8086_STEP_3;
140
+ wire cond_24 = exe_cmd == `CMD_CALL && exe_cmdex == `CMDEX_CALL_protected_seg_STEP_0;
141
+ wire cond_25 = exe_cmd == `CMD_CALL && exe_cmdex == `CMDEX_CALL_protected_seg_STEP_1;
142
+ wire cond_26 = exe_cmd == `CMD_CALL && exe_cmdex == `CMDEX_CALL_protected_seg_STEP_2;
143
+ wire cond_27 = exe_cmd == `CMD_CALL_2 && exe_cmdex == `CMDEX_CALL_2_protected_seg_STEP_4;
144
+ wire cond_28 = exe_cmd == `CMD_CALL_2 && exe_cmdex == `CMDEX_CALL_2_call_gate_STEP_0;
145
+ wire cond_29 = exe_cmd == `CMD_CALL_2 && exe_cmdex == `CMDEX_CALL_2_call_gate_same_STEP_0;
146
+ wire cond_30 = exe_cmd == `CMD_CALL_2 && exe_cmdex == `CMDEX_CALL_2_call_gate_same_STEP_1;
147
+ wire cond_31 = exe_cmd == `CMD_CALL_2 && exe_cmdex == `CMDEX_CALL_2_call_gate_same_STEP_2;
148
+ wire cond_32 = exe_cmd == `CMD_CALL_2 && exe_cmdex == `CMDEX_CALL_2_protected_seg_STEP_3;
149
+ wire cond_33 = exe_cmd == `CMD_CALL_2 && exe_cmdex == `CMDEX_CALL_2_call_gate_same_STEP_3;
150
+ wire cond_34 = exe_cmd == `CMD_CALL_2 && exe_cmdex == `CMDEX_CALL_2_call_gate_more_STEP_1;
151
+ wire cond_35 = glob_param_3[15:2] == 14'd0;
152
+ wire cond_36 = exe_ready;
153
+ wire cond_37 = exe_cmd == `CMD_CALL_2 && exe_cmdex == `CMDEX_CALL_2_call_gate_more_STEP_3;
154
+ wire cond_38 = ss_cache[`DESC_BIT_D_B];
155
+ wire cond_39 = exe_cmd == `CMD_CALL_3 && (exe_cmdex == `CMDEX_CALL_3_call_gate_more_STEP_4 || exe_cmdex == `CMDEX_CALL_3_call_gate_more_STEP_5);
156
+ wire cond_40 = exe_cmd == `CMD_CALL_3 && exe_cmdex == `CMDEX_CALL_3_call_gate_more_STEP_6;
157
+ wire cond_41 = exe_cmd == `CMD_CALL_3 && exe_cmdex == `CMDEX_CALL_3_call_gate_more_STEP_7;
158
+ wire cond_42 = glob_descriptor_2[`DESC_BIT_D_B];
159
+ wire cond_43 = exe_cmd == `CMD_CALL_3 && exe_cmdex == `CMDEX_CALL_3_call_gate_more_STEP_8;
160
+ wire cond_44 = glob_param_2 > glob_desc_2_limit;
161
+ wire cond_45 = exe_cmd == `CMD_CALL_3 && exe_cmdex == `CMDEX_CALL_3_call_gate_more_STEP_9;
162
+ wire cond_46 = exe_cmd == `CMD_CALL_3 && exe_cmdex == `CMDEX_CALL_3_call_gate_more_STEP_10;
163
+ wire cond_47 = exe_cmd == `CMD_PUSH_MOV_SEG && { exe_cmdex[3], 3'b0 } == `CMDEX_PUSH_MOV_SEG_implicit;
164
+ wire cond_48 = exe_cmd == `CMD_PUSH_MOV_SEG && { exe_cmdex[3], 3'b0 } == `CMDEX_PUSH_MOV_SEG_modregrm;
165
+ wire cond_49 = exe_cmd == `CMD_NEG;
166
+ wire cond_50 = exe_cmd == `CMD_Jcc;
167
+ wire cond_51 = exe_mutex_current[`MUTEX_EFLAGS_BIT];
168
+ wire cond_52 = exe_condition && exe_branch_eip > cs_limit;
169
+ wire cond_53 = exe_cmd == `CMD_INVD && exe_cmdex == `CMDEX_INVD_STEP_0;
170
+ wire cond_54 = cpl > 2'd0;
171
+ wire cond_55 = exe_cmd == `CMD_INVD && exe_cmdex == `CMDEX_INVD_STEP_1;
172
+ wire cond_56 = ~(e_invd_code_done && e_invd_data_done);
173
+ wire cond_57 = exe_cmd == `CMD_INVLPG && exe_cmdex == `CMDEX_INVLPG_STEP_0;
174
+ wire cond_58 = exe_cmd == `CMD_INVLPG && exe_cmdex == `CMDEX_INVLPG_STEP_1;
175
+ wire cond_59 = ~(tlbflushsingle_done);
176
+ wire cond_60 = exe_cmd == `CMD_io_allow && exe_cmdex == `CMDEX_io_allow_2;
177
+ wire cond_61 = ( exe_is_8bit && e_io_allow_bits[0] != 1'd0) || (~(exe_is_8bit) && exe_operand_16bit && e_io_allow_bits[1:0] != 2'd0) || (~(exe_is_8bit) && exe_operand_32bit && e_io_allow_bits[3:0] != 4'd0);
178
+ wire cond_62 = exe_cmd == `CMD_HLT && exe_cmdex == `CMDEX_HLT_STEP_0;
179
+ wire cond_63 = exe_cmd == `CMD_SCAS;
180
+ wire cond_64 = exe_cmd == `CMD_INC_DEC;
181
+ wire cond_65 = exe_cmd == `CMD_RET_near && exe_cmdex != `CMDEX_RET_near_LAST;
182
+ wire cond_66 = exe_cmdex == `CMDEX_RET_near;
183
+ wire cond_67 = exe_cmdex == `CMDEX_RET_near_imm;
184
+ wire cond_68 = exe_cmd == `CMD_ARPL;
185
+ wire cond_69 = exe_cmd == `CMD_BSWAP;
186
+ wire cond_70 = exe_cmd == `CMD_LxS;
187
+ wire cond_71 = (exe_cmd == `CMD_LLDT || exe_cmd == `CMD_LTR) && exe_cmdex == `CMDEX_MOV_to_seg_LLDT_LTR_STEP_1;
188
+ wire cond_72 = cpl != 2'd0;
189
+ wire cond_73 = exe_cmd == `CMD_int && exe_cmdex == `CMDEX_int_int_trap_gate_STEP_0;
190
+ wire cond_74 = exe_cmd == `CMD_int_2 && exe_cmdex == `CMDEX_int_2_int_trap_gate_more_STEP_1;
191
+ wire cond_75 = v8086_mode && exe_descriptor[`DESC_BITS_DPL] != 2'd0;
192
+ wire cond_76 = ~(exe_trigger_gp_fault) && glob_param_3[15:2] == 14'd0;
193
+ wire cond_77 = exe_cmd == `CMD_int_2 && exe_cmdex == `CMDEX_int_2_int_trap_gate_more_STEP_3;
194
+ wire cond_78 = exe_cmd == `CMD_int_2 && exe_cmdex == `CMDEX_int_2_int_trap_gate_same_STEP_5;
195
+ wire cond_79 = exe_cmd == `CMD_int_3 && (exe_cmdex == `CMDEX_int_3_int_trap_gate_more_STEP_4 || exe_cmdex == `CMDEX_int_3_int_trap_gate_more_STEP_5);
196
+ wire cond_80 = ~(exe_mutex_current[`MUTEX_ACTIVE_BIT]) && exe_ready;
197
+ wire cond_81 = exe_cmd == `CMD_int_3 && exe_cmdex == `CMDEX_int_3_int_trap_gate_more_STEP_6;
198
+ wire cond_82 = exe_cmd == `CMD_int && exe_cmdex == `CMDEX_int_STEP_0;
199
+ wire cond_83 = exe_cmd == `CMD_int && exe_cmdex == `CMDEX_int_STEP_1;
200
+ wire cond_84 = exc_soft_int_ib && v8086_mode && iopl < 2'd3;
201
+ wire cond_85 = exe_cmd == `CMD_int && exe_cmdex == `CMDEX_int_real_STEP_0;
202
+ wire cond_86 = { 6'd0, exc_vector[7:0], 2'b11 } > idtr_limit;
203
+ wire cond_87 = exe_cmd == `CMD_int && exe_cmdex == `CMDEX_int_real_STEP_1;
204
+ wire cond_88 = exe_cmd == `CMD_int && exe_cmdex == `CMDEX_int_real_STEP_2;
205
+ wire cond_89 = exe_cmd == `CMD_int && exe_cmdex == `CMDEX_int_real_STEP_3;
206
+ wire cond_90 = exe_cmd == `CMD_int && exe_cmdex == `CMDEX_int_real_STEP_5;
207
+ wire cond_91 = exe_cmd == `CMD_int && exe_cmdex == `CMDEX_int_protected_STEP_0;
208
+ wire cond_92 = { 5'd0, exc_vector[7:0], 3'b111 } > idtr_limit;
209
+ wire cond_93 = exe_cmd == `CMD_int && exe_cmdex == `CMDEX_int_protected_STEP_1;
210
+ wire cond_94 = exe_descriptor[`DESC_BIT_SEG] || ( ( exe_descriptor[`DESC_BITS_TYPE] != `DESC_TASK_GATE && exe_descriptor[`DESC_BITS_TYPE] != `DESC_INTERRUPT_GATE_386 && exe_descriptor[`DESC_BITS_TYPE] != `DESC_INTERRUPT_GATE_286 && exe_descriptor[`DESC_BITS_TYPE] != `DESC_TRAP_GATE_386 && exe_descriptor[`DESC_BITS_TYPE] != `DESC_TRAP_GATE_286 ) || (exc_soft_int && exe_descriptor[`DESC_BITS_DPL] < cpl) );
211
+ wire cond_95 = ~(exe_trigger_gp_fault) && exe_descriptor[`DESC_BIT_P] == `FALSE;
212
+ wire cond_96 = exe_cmd == `CMD_int_2 && exe_cmdex == `CMDEX_int_2_int_trap_gate_same_STEP_0;
213
+ wire cond_97 = exe_int_2_int_trap_same_exception || (glob_param_2 > glob_desc_limit);
214
+ wire cond_98 = exe_cmd == `CMD_int_2 && exe_cmdex == `CMDEX_int_2_int_trap_gate_same_STEP_1;
215
+ wire cond_99 = exe_cmd == `CMD_int_2 && exe_cmdex == `CMDEX_int_2_int_trap_gate_same_STEP_2;
216
+ wire cond_100 = exe_cmd == `CMD_int_2 && exe_cmdex == `CMDEX_int_2_int_trap_gate_same_STEP_3;
217
+ wire cond_101 = exe_cmd == `CMD_int_2 && exe_cmdex >= `CMDEX_int_2_int_trap_gate_more_STEP_4;
218
+ wire cond_102 = exe_cmd == `CMD_int_3 && exe_cmdex == `CMDEX_int_3_int_trap_gate_more_STEP_0;
219
+ wire cond_103 = exe_cmd == `CMD_int_3 && exe_cmdex == `CMDEX_int_3_int_trap_gate_more_STEP_1;
220
+ wire cond_104 = exe_cmd == `CMD_int_3 && exe_cmdex == `CMDEX_int_3_int_trap_gate_more_STEP_2;
221
+ wire cond_105 = exe_cmd == `CMD_int_3 && exe_cmdex == `CMDEX_int_3_int_trap_gate_more_STEP_3;
222
+ wire cond_106 = exe_cmd == `CMD_AAD;
223
+ wire cond_107 = mult_busy;
224
+ wire cond_108 = exe_cmd == `CMD_AAM;
225
+ wire cond_109 = exe_div_exception || div_busy;
226
+ wire cond_110 = exe_cmd == `CMD_load_seg && exe_cmdex == `CMDEX_load_seg_STEP_1;
227
+ wire cond_111 = protected_mode;
228
+ wire cond_112 = ((glob_param_1[18:16] == `SEGMENT_SS || glob_param_1[18:16] == `SEGMENT_TR || glob_param_1[18:16] == `SEGMENT_CS) && glob_param_1[15:2] == 14'd0) || ((glob_param_1[18:16] == `SEGMENT_LDT || glob_param_1[18:16] == `SEGMENT_TR) && glob_param_1[`SELECTOR_BIT_TI] == 1'b1);
229
+ wire cond_113 = exe_cmd == `CMD_load_seg && exe_cmdex == `CMDEX_load_seg_STEP_2;
230
+ wire cond_114 = ~(protected_mode && glob_param_1[15:2] == 14'd0);
231
+ wire cond_115 = exe_load_seg_gp_fault || exe_load_seg_ss_fault || exe_load_seg_np_fault;
232
+ wire cond_116 = exe_cmd == `CMD_POP_seg;
233
+ wire cond_117 = { exe_cmd[6:2], 2'd0 } == `CMD_BTx;
234
+ wire cond_118 = exe_cmd == `CMD_IRET_2 && exe_cmdex == `CMDEX_IRET_2_protected_same_STEP_0;
235
+ wire cond_119 = exe_cmd == `CMD_IRET_2 && exe_cmdex == `CMDEX_IRET_2_protected_same_STEP_1;
236
+ wire cond_120 = exe_cmd == `CMD_IRET_2 && exe_cmdex == `CMDEX_IRET_2_protected_outer_STEP_3;
237
+ wire cond_121 = exe_cmd == `CMD_IRET_2 && exe_cmdex == `CMDEX_IRET_2_protected_outer_STEP_5;
238
+ wire cond_122 = exe_cmd == `CMD_IRET_2 && exe_cmdex == `CMDEX_IRET_2_protected_outer_STEP_6;
239
+ wire cond_123 = exe_cmd == `CMD_IRET && exe_cmdex == `CMDEX_IRET_real_v86_STEP_0;
240
+ wire cond_124 = v8086_mode && iopl < 2'd3;
241
+ wire cond_125 = exe_cmd == `CMD_IRET && exe_cmdex == `CMDEX_IRET_real_v86_STEP_1;
242
+ wire cond_126 = exe_cmd == `CMD_IRET && exe_cmdex == `CMDEX_IRET_real_v86_STEP_2;
243
+ wire cond_127 = ~(v8086_mode) && glob_param_2 > cs_limit;
244
+ wire cond_128 = exe_cmd == `CMD_IRET && exe_cmdex == `CMDEX_IRET_real_v86_STEP_3;
245
+ wire cond_129 = exe_cmd == `CMD_IRET && exe_cmdex == `CMDEX_IRET_task_switch_STEP_0;
246
+ wire cond_130 = glob_param_1[`SELECTOR_BIT_TI];
247
+ wire cond_131 = exe_cmd == `CMD_IRET && exe_cmdex == `CMDEX_IRET_task_switch_STEP_1;
248
+ wire cond_132 = glob_param_2[1] || exe_descriptor[`DESC_BIT_SEG] || (exe_descriptor[`DESC_BITS_TYPE] != `DESC_TSS_BUSY_386 && exe_descriptor[`DESC_BITS_TYPE] != `DESC_TSS_BUSY_286);
249
+ wire cond_133 = glob_param_2[1] == 1'b0 && ~(exe_trigger_ts_fault) && ~(exe_descriptor[`DESC_BIT_P]);
250
+ wire cond_134 = exe_cmd == `CMD_IRET && exe_cmdex >= `CMDEX_IRET_protected_to_v86_STEP_0;
251
+ wire cond_135 = exe_cmd == `CMD_IRET_2 && exe_cmdex == `CMDEX_IRET_2_protected_to_v86_STEP_6;
252
+ wire cond_136 = exe_cmd == `CMD_IRET_2 && exe_cmdex == `CMDEX_IRET_2_protected_outer_STEP_0;
253
+ wire cond_137 = glob_param_1[`SELECTOR_BITS_RPL] != glob_param_3[`SELECTOR_BITS_RPL];
254
+ wire cond_138 = exe_cmd == `CMD_POP && exe_cmdex == `CMDEX_POP_implicit;
255
+ wire cond_139 = exe_cmd == `CMD_POP && exe_cmdex == `CMDEX_POP_modregrm_STEP_0;
256
+ wire cond_140 = exe_cmd == `CMD_POP && exe_cmdex == `CMDEX_POP_modregrm_STEP_1;
257
+ wire cond_141 = exe_cmd == `CMD_IDIV || exe_cmd == `CMD_DIV;
258
+ wire cond_142 = exe_cmd == `CMD_Shift && exe_decoder[13:12] == 2'b01;
259
+ wire cond_143 = exe_cmd == `CMD_Shift && exe_decoder[13:12] != 2'b01;
260
+ wire cond_144 = exe_cmd == `CMD_CMPS;
261
+ wire cond_145 = exe_cmd == `CMD_control_reg && exe_cmdex == `CMDEX_control_reg_LMSW_STEP_0;
262
+ wire cond_146 = exe_cmd == `CMD_control_reg && exe_cmdex == `CMDEX_control_reg_MOV_store_STEP_0;
263
+ wire cond_147 = exe_modregrm_reg == 3'd0;
264
+ wire cond_148 = exe_modregrm_reg == 3'd2;
265
+ wire cond_149 = exe_modregrm_reg == 3'd3;
266
+ wire cond_150 = exe_cmd == `CMD_control_reg && exe_cmdex == `CMDEX_control_reg_MOV_load_STEP_0;
267
+ wire cond_151 = cpl > 2'd0 || (exe_modregrm_reg == 3'd0 && ((src[31] && ~(src[0])) || (src[29] && ~(src[30]))));
268
+ wire cond_152 = exe_cmd == `CMD_control_reg && exe_cmdex == `CMDEX_control_reg_SMSW_STEP_0;
269
+ wire cond_153 = exe_cmd == `CMD_LGDT || exe_cmd == `CMD_LIDT;
270
+ wire cond_154 = exe_cmd == `CMD_PUSHA;
271
+ wire cond_155 = exe_cmdex[2:0] == 3'd4;
272
+ wire cond_156 = exe_cmd == `CMD_fpu && exe_cmdex == `CMDEX_ESC_STEP_0;
273
+ wire cond_157 = cr0_em || cr0_ts;
274
+ wire cond_158 = exe_cmd == `CMD_SETcc;
275
+ wire cond_159 = exe_condition;
276
+ wire cond_160 = exe_cmd == `CMD_CMPXCHG;
277
+ wire cond_161 = exe_mutex_current[`MUTEX_EAX_BIT];
278
+ wire cond_162 = exe_cmd == `CMD_ENTER && exe_cmdex == `CMDEX_ENTER_FIRST;
279
+ wire cond_163 = exe_cmd == `CMD_ENTER && exe_cmdex == `CMDEX_ENTER_LAST;
280
+ wire cond_164 = exe_cmd == `CMD_ENTER && (exe_cmdex == `CMDEX_ENTER_PUSH || exe_cmdex == `CMDEX_ENTER_LOOP);
281
+ wire cond_165 = exe_cmdex == `CMDEX_ENTER_PUSH;
282
+ wire cond_166 = exe_cmd == `CMD_IMUL;
283
+ wire cond_167 = exe_cmd == `CMD_LEAVE;
284
+ wire cond_168 = { exe_cmd[6:1], 1'd0 } == `CMD_SHxD;
285
+ wire cond_169 = exe_cmd == `CMD_WBINVD && exe_cmdex == `CMDEX_WBINVD_STEP_0;
286
+ wire cond_170 = exe_cmd == `CMD_WBINVD && exe_cmdex == `CMDEX_WBINVD_STEP_1;
287
+ wire cond_171 = ~(e_wbinvd_code_done && e_wbinvd_data_done);
288
+ wire cond_172 = { exe_cmd[6:3], 3'd0 } == `CMD_Arith;
289
+ wire cond_173 = exe_cmd[2:1] == 2'b01 && exe_mutex_current[`MUTEX_EFLAGS_BIT];
290
+ wire cond_174 = exe_cmd == `CMD_MUL;
291
+ wire cond_175 = exe_cmd == `CMD_LOOP;
292
+ wire cond_176 = exe_mutex_current[`MUTEX_ECX_BIT] || (exe_mutex_current[`MUTEX_EFLAGS_BIT] && (exe_cmdex == `CMDEX_LOOP_NE || exe_cmdex == `CMDEX_LOOP_E));
293
+ wire cond_177 = exe_cmd_loop_condition && exe_branch_eip > cs_limit;
294
+ wire cond_178 = exe_cmd == `CMD_TEST;
295
+ wire cond_179 = exe_cmd == `CMD_CLTS;
296
+ wire cond_180 = exe_cmd == `CMD_RET_far && exe_cmdex == `CMDEX_RET_far_STEP_1;
297
+ wire cond_181 = exe_cmd == `CMD_RET_far && exe_cmdex == `CMDEX_RET_far_STEP_2;
298
+ wire cond_182 = (v8086_mode || real_mode) && glob_param_2 > cs_limit;
299
+ wire cond_183 = exe_cmd == `CMD_RET_far && exe_cmdex == `CMDEX_RET_far_same_STEP_3;
300
+ wire cond_184 = exe_cmd == `CMD_RET_far && exe_cmdex == `CMDEX_RET_far_outer_STEP_5;
301
+ wire cond_185 = exe_cmd == `CMD_RET_far && exe_cmdex == `CMDEX_RET_far_outer_STEP_6;
302
+ wire cond_186 = exe_cmd == `CMD_RET_far && exe_cmdex == `CMDEX_RET_far_outer_STEP_7;
303
+ wire cond_187 = exe_cmd == `CMD_RET_far && (exe_cmdex == `CMDEX_RET_far_real_STEP_3 || exe_cmdex == `CMDEX_RET_far_same_STEP_4);
304
+ wire cond_188 = exe_cmdex == `CMDEX_RET_far_real_STEP_3;
305
+ wire cond_189 = exe_cmd == `CMD_LODS;
306
+ wire cond_190 = exe_cmd == `CMD_XCHG && exe_cmdex == `CMDEX_XCHG_implicit;
307
+ wire cond_191 = exe_cmd == `CMD_XCHG && exe_cmdex == `CMDEX_XCHG_modregrm;
308
+ wire cond_192 = exe_cmd == `CMD_XCHG && exe_cmdex == `CMDEX_XCHG_modregrm_LAST;
309
+ wire cond_193 = exe_cmd == `CMD_PUSH;
310
+ wire cond_194 = exe_cmdex == `CMDEX_PUSH_immediate_se;
311
+ wire cond_195 = exe_cmd == `CMD_IN && exe_cmdex == `CMDEX_IN_protected;
312
+ wire cond_196 = exe_cmd == `CMD_IN && (exe_cmdex == `CMDEX_IN_dx || exe_cmdex == `CMDEX_IN_imm);
313
+ wire cond_197 = exe_cmdex == `CMDEX_IN_dx && exe_mutex_current[`MUTEX_EDX_BIT];
314
+ wire cond_198 = exe_cmd == `CMD_NOT;
315
+ wire cond_199 = (exe_cmd == `CMD_LAR || exe_cmd == `CMD_LSL) && exe_cmdex == `CMDEX_LAR_LSL_VERR_VERW_STEP_LAST;
316
+ wire cond_200 = (exe_cmd == `CMD_LAR || exe_cmd == `CMD_LSL || exe_cmd == `CMD_VERR || exe_cmd == `CMD_VERW) && exe_cmdex == `CMDEX_LAR_LSL_VERR_VERW_STEP_2;
317
+ wire cond_201 = (exe_cmd == `CMD_CALL && exe_cmdex == `CMDEX_CALL_protected_STEP_0) || (exe_cmd == `CMD_JMP && exe_cmdex == `CMDEX_JMP_protected_STEP_0);
318
+ wire cond_202 = glob_param_1[15:2] == 14'd0 || (exe_descriptor[`DESC_BIT_SEG] == `FALSE && ( exe_descriptor[`DESC_BITS_DPL] < cpl || exe_descriptor[`DESC_BITS_DPL] < exe_selector[`SELECTOR_BITS_RPL] || ((exe_descriptor[`DESC_BITS_TYPE] == 4'd1 || exe_descriptor[`DESC_BITS_TYPE] == 4'd9) && exe_selector[`SELECTOR_BIT_TI]) || exe_descriptor[`DESC_BITS_TYPE] == 4'd0 || exe_descriptor[`DESC_BITS_TYPE] == 4'd8 || exe_descriptor[`DESC_BITS_TYPE] == 4'd10 || exe_descriptor[`DESC_BITS_TYPE] == 4'd13 || exe_descriptor[`DESC_BITS_TYPE] == 4'd2 || exe_descriptor[`DESC_BITS_TYPE] == 4'd3 || exe_descriptor[`DESC_BITS_TYPE] == 4'd6 || exe_descriptor[`DESC_BITS_TYPE] == 4'd7 || exe_descriptor[`DESC_BITS_TYPE] == 4'd11 || exe_descriptor[`DESC_BITS_TYPE] == 4'd14 || exe_descriptor[`DESC_BITS_TYPE] == 4'd15) ) || (exe_descriptor[`DESC_BIT_SEG] && ( `DESC_IS_DATA(exe_descriptor) || (`DESC_IS_CODE_NON_CONFORMING(exe_descriptor) && (exe_descriptor[`DESC_BITS_DPL] != cpl || exe_selector[`SELECTOR_BITS_RPL] > cpl)) || (`DESC_IS_CODE_CONFORMING(exe_descriptor) && exe_descriptor[`DESC_BITS_DPL] > cpl)) ) ;
319
+ wire cond_203 = ~(exe_trigger_gp_fault) && exe_descriptor[`DESC_BIT_P] == `FALSE && (exe_descriptor[`DESC_BIT_SEG] || exe_descriptor[`DESC_BITS_TYPE] == 4'd1 || exe_descriptor[`DESC_BITS_TYPE] == 4'd9 || exe_descriptor[`DESC_BITS_TYPE] == 4'd4 || exe_descriptor[`DESC_BITS_TYPE] == 4'd12 || exe_descriptor[`DESC_BITS_TYPE] == 4'd5) ;
320
+ wire cond_204 = (exe_cmd == `CMD_CALL_2 && exe_cmdex == `CMDEX_CALL_2_task_switch_STEP_0) || (exe_cmd == `CMD_JMP && exe_cmdex == `CMDEX_JMP_task_switch_STEP_0);
321
+ wire cond_205 = exe_cmd == `CMD_CALL_2;
322
+ wire cond_206 = exe_cmd == `CMD_JMP;
323
+ wire cond_207 = (exe_cmd == `CMD_CALL_2 && exe_cmdex == `CMDEX_CALL_2_task_gate_STEP_1) || (exe_cmd == `CMD_JMP && exe_cmdex == `CMDEX_JMP_task_gate_STEP_1) || (exe_cmd == `CMD_int && exe_cmdex == `CMDEX_int_task_gate_STEP_1);
324
+ wire cond_208 = glob_param_1[`SELECTOR_BIT_TI] || glob_descriptor[`DESC_BIT_SEG] || (glob_descriptor[`DESC_BITS_TYPE] != `DESC_TSS_AVAIL_386 && glob_descriptor[`DESC_BITS_TYPE] != `DESC_TSS_AVAIL_286);
325
+ wire cond_209 = exe_cmd == `CMD_int;
326
+ wire cond_210 = exe_cmd != `CMD_int;
327
+ wire cond_211 = (exe_cmd == `CMD_CALL_2 && exe_cmdex == `CMDEX_CALL_2_call_gate_STEP_1) || (exe_cmd == `CMD_int && exe_cmdex == `CMDEX_int_int_trap_gate_STEP_1);
328
+ wire cond_212 = glob_param_1[15:2] == 14'd0 || glob_descriptor[`DESC_BIT_SEG] == `FALSE || `DESC_IS_DATA(glob_descriptor) || glob_descriptor[`DESC_BITS_DPL] > cpl;
329
+ wire cond_213 = (exe_cmd == `CMD_CALL_2 && exe_cmdex == `CMDEX_CALL_2_call_gate_more_STEP_2) || (exe_cmd == `CMD_int_2 && exe_cmdex == `CMDEX_int_2_int_trap_gate_more_STEP_2);
330
+ wire cond_214 = glob_param_5[0] || glob_param_1[`SELECTOR_BITS_RPL] != glob_descriptor_2[`DESC_BITS_DPL] || glob_descriptor[`DESC_BITS_DPL] != glob_descriptor_2[`DESC_BITS_DPL] || glob_descriptor[`DESC_BIT_SEG] == `FALSE || `DESC_IS_CODE(glob_descriptor) || `DESC_IS_DATA_RO(glob_descriptor);
331
+ wire cond_215 = glob_param_5[0] == 1'b0 && ~(exe_trigger_ts_fault) && ~(glob_descriptor[`DESC_BIT_P]);
332
+ wire cond_216 = exe_cmd == `CMD_STOS;
333
+ wire cond_217 = exe_cmd == `CMD_INS;
334
+ wire cond_218 = exe_mutex_current[`MUTEX_EDX_BIT];
335
+ wire cond_219 = exe_cmd == `CMD_OUTS;
336
+ wire cond_220 = exe_cmd == `CMD_PUSHF;
337
+ wire cond_221 = exe_mutex_current[`MUTEX_ESP_BIT] || exe_mutex_current[`MUTEX_EFLAGS_BIT];
338
+ wire cond_222 = exe_cmd == `CMD_JMP && (exe_cmdex == `CMDEX_JMP_Ev_STEP_0 || exe_cmdex == `CMDEX_JMP_Ep_STEP_0 || exe_cmdex == `CMDEX_JMP_Ap_STEP_0);
339
+ wire cond_223 = exe_cmd == `CMD_JMP && exe_cmdex == `CMDEX_JMP_Jv_STEP_0;
340
+ wire cond_224 = exe_cmd == `CMD_CALL && exe_mutex_current[`MUTEX_ESP_BIT];
341
+ wire cond_225 = exe_cmd == `CMD_JMP && exe_cmdex == `CMDEX_JMP_Ev_Jv_STEP_1;
342
+ wire cond_226 = exe_cmd == `CMD_JMP && exe_cmdex == `CMDEX_JMP_Ep_STEP_1;
343
+ wire cond_227 = exe_cmd == `CMD_JMP && exe_cmdex == `CMDEX_JMP_Ap_STEP_1;
344
+ wire cond_228 = exe_cmd == `CMD_JMP && exe_cmdex == `CMDEX_JMP_real_v8086_STEP_0;
345
+ wire cond_229 = exe_cmd == `CMD_JMP && exe_cmdex == `CMDEX_JMP_real_v8086_STEP_1;
346
+ wire cond_230 = exe_cmd == `CMD_JMP && exe_cmdex == `CMDEX_JMP_protected_seg_STEP_0;
347
+ wire cond_231 = exe_cmd == `CMD_JMP && exe_cmdex == `CMDEX_JMP_protected_seg_STEP_1;
348
+ wire cond_232 = exe_cmd == `CMD_JMP_2 && exe_cmdex == `CMDEX_JMP_2_call_gate_STEP_1;
349
+ wire cond_233 = glob_param_1[15:2] == 14'd0 || glob_descriptor[`DESC_BIT_SEG] == `FALSE || `DESC_IS_DATA(glob_descriptor) || (`DESC_IS_CODE_NON_CONFORMING(exe_descriptor) && exe_descriptor[`DESC_BITS_DPL] != cpl) || (`DESC_IS_CODE_CONFORMING(exe_descriptor) && exe_descriptor[`DESC_BITS_DPL] > cpl);
350
+ wire cond_234 = exe_cmd == `CMD_JMP_2 && exe_cmdex == `CMDEX_JMP_2_call_gate_STEP_2;
351
+ wire cond_235 = exe_cmd == `CMD_JMP_2 && exe_cmdex == `CMDEX_JMP_2_call_gate_STEP_3;
352
+ wire cond_236 = exe_cmd == `CMD_OUT && (exe_cmdex == `CMDEX_OUT_dx || exe_cmdex == `CMDEX_OUT_imm);
353
+ wire cond_237 = exe_cmdex == `CMDEX_OUT_dx && exe_mutex_current[`MUTEX_EDX_BIT];
354
+ wire cond_238 = exe_cmd == `CMD_OUT && exe_cmdex == `CMDEX_OUT_protected;
355
+ wire cond_239 = exe_cmd == `CMD_MOV;
356
+ wire cond_240 = exe_cmd == `CMD_POPF && exe_cmdex == `CMDEX_POPF_STEP_0;
357
+ wire cond_241 = exe_cmd == `CMD_CLI || exe_cmd == `CMD_STI;
358
+ wire cond_242 = (protected_mode && iopl < cpl) || (v8086_mode && iopl != 2'd3);
359
+ wire cond_243 = exe_cmd == `CMD_BOUND && exe_cmdex == `CMDEX_BOUND_STEP_FIRST;
360
+ wire cond_244 = exe_cmd == `CMD_BOUND && exe_cmdex == `CMDEX_BOUND_STEP_LAST;
361
+ wire cond_245 = exe_bound_fault;
362
+ wire cond_246 = exe_cmd == `CMD_task_switch && exe_cmdex == `CMDEX_task_switch_STEP_1;
363
+ wire cond_247 = glob_desc_limit < exe_new_tss_max;
364
+ wire cond_248 = tr_limit < ((tr_cache[`DESC_BITS_TYPE] <= 4'd3)? 32'h29 : 32'h5F);
365
+ wire cond_249 = exe_cmd == `CMD_task_switch && exe_cmdex == `CMDEX_task_switch_STEP_2;
366
+ wire cond_250 = ~(tlbcheck_done) && ~(tlbcheck_page_fault);
367
+ wire cond_251 = tlbcheck_page_fault;
368
+ wire cond_252 = exe_cmd == `CMD_task_switch && exe_cmdex == `CMDEX_task_switch_STEP_3;
369
+ wire cond_253 = exe_cmd == `CMD_task_switch && exe_cmdex == `CMDEX_task_switch_STEP_4;
370
+ wire cond_254 = exe_cmd == `CMD_task_switch && exe_cmdex == `CMDEX_task_switch_STEP_5;
371
+ wire cond_255 = exe_cmd == `CMD_task_switch && exe_cmdex == `CMDEX_task_switch_STEP_7;
372
+ wire cond_256 = exe_cmd == `CMD_task_switch && exe_cmdex == `CMDEX_task_switch_STEP_8;
373
+ wire cond_257 = exe_cmd == `CMD_task_switch && exe_cmdex == `CMDEX_task_switch_STEP_10;
374
+ wire cond_258 = exe_cmd == `CMD_task_switch && exe_cmdex >= `CMDEX_task_switch_STEP_12 && exe_cmdex <= `CMDEX_task_switch_STEP_14;
375
+ wire cond_259 = exe_cmd == `CMD_task_switch_2;
376
+ wire cond_260 = exe_cmdex <= `CMDEX_task_switch_2_STEP_7;
377
+ wire cond_261 = exe_cmdex > `CMDEX_task_switch_2_STEP_7;
378
+ wire cond_262 = exe_cmd == `CMD_task_switch_3;
379
+ wire cond_263 = exe_cmd == `CMD_task_switch_4 && exe_cmdex == `CMDEX_task_switch_4_STEP_0;
380
+ wire cond_264 = exe_cmd == `CMD_task_switch_4 && exe_cmdex == `CMDEX_task_switch_4_STEP_2;
381
+ wire cond_265 = glob_param_2[2] || glob_param_2[2:0] == 3'b010 || ( glob_param_2[2:0] == 3'b000 && ( exe_descriptor[`DESC_BIT_SEG] || exe_descriptor[`DESC_BITS_TYPE] != `DESC_LDT || exe_descriptor[`DESC_BIT_P] == `FALSE ) );
382
+ wire cond_266 = exe_cmd == `CMD_task_switch_4 && exe_cmdex == `CMDEX_task_switch_4_STEP_3;
383
+ wire cond_267 = ~(v8086_mode);
384
+ wire cond_268 = glob_param_2[1:0] != 2'b00 || ( exe_descriptor[`DESC_BIT_SEG] == 1'b0 || `DESC_IS_CODE(exe_descriptor) || `DESC_IS_DATA_RO(exe_descriptor) || (exe_descriptor[`DESC_BIT_P] && ( exe_descriptor[`DESC_BITS_DPL] != wr_task_rpl || exe_descriptor[`DESC_BITS_DPL] != exe_selector[`SELECTOR_BITS_RPL] ) ) );
385
+ wire cond_269 = glob_param_2[1:0] == 2'b00 && exe_descriptor[`DESC_BIT_SEG] && `DESC_IS_DATA_RW(exe_descriptor) && ~(exe_descriptor[`DESC_BIT_P]);
386
+ wire cond_270 = exe_cmd == `CMD_task_switch_4 && exe_cmdex >= `CMDEX_task_switch_4_STEP_4 && exe_cmdex <= `CMDEX_task_switch_4_STEP_7;
387
+ wire cond_271 = glob_param_2[1:0] == 2'b10 || (glob_param_2[1:0] == 2'b00 && ( exe_descriptor[`DESC_BIT_SEG] == 1'b0 || `DESC_IS_CODE_EO(exe_descriptor) || ((`DESC_IS_DATA(exe_descriptor) || `DESC_IS_CODE_NON_CONFORMING(exe_descriptor)) && exe_privilege_not_accepted) ));
388
+ wire cond_272 = glob_param_2[1:0] == 2'b00 && ~(exe_trigger_ts_fault) && ~(exe_descriptor[`DESC_BIT_P]);
389
+ wire cond_273 = exe_cmd == `CMD_task_switch_4 && exe_cmdex == `CMDEX_task_switch_4_STEP_8;
390
+ wire cond_274 = glob_param_2[1:0] != 2'b00 || ( exe_descriptor[`DESC_BIT_SEG] == 1'b0 || `DESC_IS_DATA(exe_descriptor) || (`DESC_IS_CODE_NON_CONFORMING(exe_descriptor) && exe_descriptor[`DESC_BITS_DPL] != exe_selector[`SELECTOR_BITS_RPL]) || (`DESC_IS_CODE_CONFORMING(exe_descriptor) && exe_descriptor[`DESC_BITS_DPL] > exe_selector[`SELECTOR_BITS_RPL]) );
391
+ wire cond_275 = exe_cmd == `CMD_task_switch_4 && exe_cmdex == `CMDEX_task_switch_4_STEP_9;
392
+ wire cond_276 = exe_cmd == `CMD_task_switch_4 && exe_cmdex == `CMDEX_task_switch_4_STEP_10;
393
+ wire cond_277 = exe_eip > cs_limit;
394
+ wire cond_278 = exe_cmd == `CMD_LEA;
395
+ wire cond_279 = exe_cmd == `CMD_SGDT;
396
+ wire cond_280 = exe_cmdex == `CMDEX_SGDT_SIDT_STEP_1;
397
+ wire cond_281 = exe_cmdex == `CMDEX_SGDT_SIDT_STEP_2;
398
+ wire cond_282 = exe_cmd == `CMD_SIDT;
399
+ wire cond_283 = exe_cmd == `CMD_MOVS;
400
+ wire cond_284 = exe_cmd == `CMD_MOVSX || exe_cmd == `CMD_MOVZX;
401
+ wire cond_285 = exe_cmd == `CMD_POPA;
402
+ wire cond_286 = exe_cmd == `CMD_debug_reg && (exe_cmdex == `CMDEX_debug_reg_MOV_store_STEP_0 || exe_cmdex == `CMDEX_debug_reg_MOV_load_STEP_0);
403
+ wire cond_287 = exe_cmdex == `CMDEX_debug_reg_MOV_load_STEP_0;
404
+ wire cond_288 = exe_cmdex == `CMDEX_debug_reg_MOV_store_STEP_0 && exe_modregrm_reg == 3'd0;
405
+ wire cond_289 = exe_cmdex == `CMDEX_debug_reg_MOV_store_STEP_0 && exe_modregrm_reg == 3'd1;
406
+ wire cond_290 = exe_cmdex == `CMDEX_debug_reg_MOV_store_STEP_0 && exe_modregrm_reg == 3'd2;
407
+ wire cond_291 = exe_cmdex == `CMDEX_debug_reg_MOV_store_STEP_0 && exe_modregrm_reg == 3'd3;
408
+ wire cond_292 = exe_cmdex == `CMDEX_debug_reg_MOV_store_STEP_0 && (exe_modregrm_reg == 3'd4 || exe_modregrm_reg == 3'd6);
409
+ wire cond_293 = exe_cmdex == `CMDEX_debug_reg_MOV_store_STEP_0 && (exe_modregrm_reg == 3'd5 || exe_modregrm_reg == 3'd7);
410
+ wire cond_294 = dr7[`DR7_BIT_GD];
411
+ wire cond_295 = exe_cmd == `CMD_XLAT;
412
+ wire cond_296 = exe_cmd == `CMD_AAA || exe_cmd == `CMD_AAS || exe_cmd == `CMD_DAA || exe_cmd == `CMD_DAS;
413
+ wire cond_297 = { exe_cmd[6:1], 1'd0 } == `CMD_BSx;
414
+ wire cond_298 = exe_cmd == `CMD_BSF;
415
+ wire cond_299 = exe_cmd == `CMD_BSR;
416
+ //======================================================== saves
417
+ wire [31:0] exe_buffer_to_reg =
418
+ (cond_0)? ( dst) :
419
+ (cond_134 && cond_36)? ( src) :
420
+ (cond_139)? ( src) :
421
+ (cond_162 && ~cond_10)? ( exe_enter_offset) :
422
+ (cond_191)? ( dst) :
423
+ (cond_243)? ( src) :
424
+ (cond_258 && cond_36)? ( src) :
425
+ (cond_262 && cond_36)? ( (exe_cmdex == `CMDEX_task_switch_3_STEP_15 && glob_descriptor[`DESC_BITS_TYPE] <= 4'd3)? 32'd0 : src) :
426
+ (cond_285 && cond_36)? ( src) :
427
+ exe_buffer;
428
+ //======================================================== always
429
+ always @(posedge clk) begin
430
+ if(rst_n == 1'b0) exe_buffer <= 32'd0;
431
+ else exe_buffer <= exe_buffer_to_reg;
432
+ end
433
+ //======================================================== sets
434
+ assign tlbcheck_rw =
435
+ (cond_249)? ( `FALSE) :
436
+ (cond_252)? ( `FALSE) :
437
+ (cond_253)? ( `TRUE) :
438
+ (cond_254)? ( `TRUE) :
439
+ (cond_255)? ( `TRUE) :
440
+ (cond_256)? ( `TRUE) :
441
+ 1'd0;
442
+ assign exe_cmpxchg_switch =
443
+ (cond_160)? (`TRUE) :
444
+ 1'd0;
445
+ assign wbinvddata_do =
446
+ (cond_170)? ( ~(e_wbinvd_data_done)) :
447
+ 1'd0;
448
+ assign exe_trigger_ss_fault =
449
+ (cond_213 && cond_215)? (`TRUE) :
450
+ (cond_266 && cond_267 && cond_269)? (`TRUE) :
451
+ 1'd0;
452
+ assign offset_ret =
453
+ (cond_65 && cond_67)? (`TRUE) :
454
+ (cond_183)? ( exe_decoder[0] == 1'b0) :
455
+ (cond_187 && cond_188)? ( exe_decoder[0] == 1'b0) :
456
+ 1'd0;
457
+ assign exe_buffer_shift_word =
458
+ (cond_262 && cond_36)? ( exe_cmdex > `CMDEX_task_switch_3_STEP_8) :
459
+ 1'd0;
460
+ assign exe_buffer_shift =
461
+ (cond_134 && cond_36)? (`TRUE) :
462
+ (cond_258 && cond_36)? (`TRUE) :
463
+ (cond_262 && cond_36)? ( exe_cmdex <= `CMDEX_task_switch_3_STEP_8) :
464
+ (cond_285 && cond_36)? (`TRUE) :
465
+ 1'd0;
466
+ assign offset_ret_far_se =
467
+ (cond_187 && cond_188)? (`TRUE) :
468
+ 1'd0;
469
+ assign exe_eip_from_glob_param_2 =
470
+ (cond_13)? (`TRUE) :
471
+ (cond_23)? (`TRUE) :
472
+ (cond_27)? (`TRUE) :
473
+ (cond_33)? (`TRUE) :
474
+ (cond_46)? (`TRUE) :
475
+ (cond_65)? (`TRUE) :
476
+ (cond_78)? (`TRUE) :
477
+ (cond_81)? (`TRUE) :
478
+ (cond_90)? (`TRUE) :
479
+ (cond_119)? (`TRUE) :
480
+ (cond_122)? (`TRUE) :
481
+ (cond_128)? (`TRUE) :
482
+ (cond_186)? (`TRUE) :
483
+ (cond_187)? (`TRUE) :
484
+ (cond_225)? (`TRUE) :
485
+ (cond_229)? (`TRUE) :
486
+ (cond_231)? (`TRUE) :
487
+ (cond_235)? (`TRUE) :
488
+ (cond_276)? (`TRUE) :
489
+ 1'd0;
490
+ assign exe_task_switch_finished =
491
+ (cond_276)? (`TRUE) :
492
+ 1'd0;
493
+ assign offset_esp =
494
+ (cond_5)? (`TRUE) :
495
+ 1'd0;
496
+ assign exe_trigger_np_fault =
497
+ (cond_93 && cond_95)? (`TRUE) :
498
+ (cond_131 && cond_133)? (`TRUE) :
499
+ (cond_201 && cond_203)? (`TRUE) :
500
+ (cond_207 && cond_95)? (`TRUE) :
501
+ (cond_211 && cond_95)? (`TRUE) :
502
+ (cond_232 && cond_95)? (`TRUE) :
503
+ (cond_270 && cond_267 && cond_272)? (`TRUE) :
504
+ (cond_273 && cond_267 && cond_272)? (`TRUE) :
505
+ 1'd0;
506
+ assign offset_iret =
507
+ (cond_118)? (`TRUE) :
508
+ 1'd0;
509
+ assign exe_eip_from_glob_param_2_16bit =
510
+ (cond_135)? (`TRUE) :
511
+ 1'd0;
512
+ assign exe_trigger_gp_fault =
513
+ (cond_2 && ~cond_3 && cond_4)? (`TRUE) :
514
+ (cond_6 && cond_7)? (`TRUE) :
515
+ (cond_13 && cond_14)? (`TRUE) :
516
+ (cond_17 && cond_18)? (`TRUE) :
517
+ (cond_21 && cond_22)? (`TRUE) :
518
+ (cond_31 && cond_7)? (`TRUE) :
519
+ (cond_43 && cond_44)? (`TRUE) :
520
+ (cond_50 && ~cond_51 && cond_52)? (`TRUE) :
521
+ (cond_53 && cond_54)? (`TRUE) :
522
+ (cond_57 && cond_54)? (`TRUE) :
523
+ (cond_60 && cond_61)? (`TRUE) :
524
+ (cond_62 && cond_54)? (`TRUE) :
525
+ (cond_65 && cond_14)? (`TRUE) :
526
+ (cond_71 && cond_72)? (`TRUE) :
527
+ (cond_74 && cond_75)? (`TRUE) :
528
+ (cond_77 && cond_44)? (`TRUE) :
529
+ (cond_83 && cond_84)? (`TRUE) :
530
+ (cond_85 && cond_86)? (`TRUE) :
531
+ (cond_89 && cond_14)? (`TRUE) :
532
+ (cond_91 && cond_92)? (`TRUE) :
533
+ (cond_93 && cond_94)? (`TRUE) :
534
+ (cond_96 && cond_97)? (`TRUE) :
535
+ (cond_110 && cond_111 && cond_112)? (`TRUE) :
536
+ (cond_118 && cond_7)? (`TRUE) :
537
+ (cond_120 && cond_44)? (`TRUE) :
538
+ (cond_123 && cond_124)? (`TRUE) :
539
+ (cond_126 && cond_127)? (`TRUE) :
540
+ (cond_136 && cond_137)? (`TRUE) :
541
+ (cond_145 && cond_54)? (`TRUE) :
542
+ (cond_146 && cond_54)? (`TRUE) :
543
+ (cond_150 && cond_151)? (`TRUE) :
544
+ (cond_153 && cond_72)? (`TRUE) :
545
+ (cond_169 && cond_54)? (`TRUE) :
546
+ (cond_175 && ~cond_176 && cond_177)? (`TRUE) :
547
+ (cond_179 && cond_54)? (`TRUE) :
548
+ (cond_181 && cond_182)? (`TRUE) :
549
+ (cond_183 && cond_7)? (`TRUE) :
550
+ (cond_184 && cond_44)? (`TRUE) :
551
+ (cond_201 && cond_202)? (`TRUE) :
552
+ (cond_207 && cond_208)? (`TRUE) :
553
+ (cond_211 && cond_212)? (`TRUE) :
554
+ (cond_220 && ~cond_221 && cond_124)? (`TRUE) :
555
+ (cond_225 && cond_14)? (`TRUE) :
556
+ (cond_228 && cond_14)? (`TRUE) :
557
+ (cond_230 && cond_7)? (`TRUE) :
558
+ (cond_232 && cond_233)? (`TRUE) :
559
+ (cond_234 && cond_7)? (`TRUE) :
560
+ (cond_240 && ~cond_51 && cond_124)? (`TRUE) :
561
+ (cond_241 && ~cond_51 && cond_242)? (`TRUE) :
562
+ (cond_276 && cond_277)? (`TRUE) :
563
+ (cond_286 && ~cond_294 && cond_54)? (`TRUE) :
564
+ 1'd0;
565
+ assign exe_glob_descriptor_value =
566
+ (cond_24)? ( ss_cache) :
567
+ (cond_26 && ~cond_20)? ( glob_descriptor_2) :
568
+ (cond_45 && cond_36)? ( glob_descriptor_2) :
569
+ (cond_79 && cond_80)? ( glob_descriptor_2) :
570
+ (cond_120 && ~cond_44)? ( glob_descriptor_2) :
571
+ (cond_121)? ( glob_descriptor_2) :
572
+ (cond_184 && ~cond_44)? ( glob_descriptor_2) :
573
+ (cond_185)? ( glob_descriptor_2) :
574
+ 64'd0;
575
+ assign offset_task =
576
+ (cond_275)? (`TRUE) :
577
+ 1'd0;
578
+ assign exe_glob_param_2_set =
579
+ (cond_8 && cond_11)? (`TRUE) :
580
+ (cond_8 && ~cond_11)? (`TRUE) :
581
+ (cond_12 && cond_11)? (`TRUE) :
582
+ (cond_12 && ~cond_11)? (`TRUE) :
583
+ (cond_28)? (`TRUE) :
584
+ (cond_73)? (`TRUE) :
585
+ (cond_200)? (`TRUE) :
586
+ (cond_222 && cond_11)? (`TRUE) :
587
+ (cond_222 && ~cond_11)? (`TRUE) :
588
+ (cond_223 && cond_11)? (`TRUE) :
589
+ (cond_223 && ~cond_11)? (`TRUE) :
590
+ (cond_276)? (`TRUE) :
591
+ 1'd0;
592
+ assign offset_pop =
593
+ (cond_65 && cond_66)? (`TRUE) :
594
+ (cond_116)? (`TRUE) :
595
+ (cond_123)? (`TRUE) :
596
+ (cond_125)? (`TRUE) :
597
+ (cond_126)? (`TRUE) :
598
+ (cond_138)? (`TRUE) :
599
+ (cond_139)? (`TRUE) :
600
+ (cond_140)? (`TRUE) :
601
+ (cond_180)? (`TRUE) :
602
+ (cond_183)? ( exe_decoder[0] == 1'b1) :
603
+ (cond_187 && cond_188)? ( exe_decoder[0] == 1'b1) :
604
+ (cond_240)? (`TRUE) :
605
+ (cond_285)? (`TRUE) :
606
+ 1'd0;
607
+ assign exe_result2 =
608
+ (cond_106)? ( mult_result[63:32]) :
609
+ (cond_108)? ( div_result_remainder) :
610
+ (cond_141)? ( div_result_remainder) :
611
+ (cond_145)? ( src) :
612
+ (cond_150)? ( src) :
613
+ (cond_153)? ( src) :
614
+ (cond_160)? ( dst) :
615
+ (cond_166)? ( mult_result[63:32]) :
616
+ (cond_174)? ( mult_result[63:32]) :
617
+ (cond_189)? ( src) :
618
+ (cond_190)? ( dst) :
619
+ (cond_195)? ( src) :
620
+ (cond_196)? ( src) :
621
+ (cond_239)? ( dst) :
622
+ (cond_240)? ( src) :
623
+ (cond_259 && cond_260)? ( src) :
624
+ (cond_259 && cond_261)? ( { 16'd0, e_seg_by_cmdex }) :
625
+ (cond_263)? ( src) :
626
+ (cond_286 && cond_287)? ( src) :
627
+ (cond_295)? ( dst) :
628
+ 32'd0;
629
+ assign offset_new_stack_continue =
630
+ (cond_37)? (`TRUE) :
631
+ (cond_39)? (`TRUE) :
632
+ (cond_40)? (`TRUE) :
633
+ (cond_41)? (`TRUE) :
634
+ (cond_101)? (`TRUE) :
635
+ (cond_102)? (`TRUE) :
636
+ (cond_103)? (`TRUE) :
637
+ (cond_104)? (`TRUE) :
638
+ (cond_105)? (`TRUE) :
639
+ 1'd0;
640
+ assign tlbflushsingle_do =
641
+ (cond_58)? (`TRUE) :
642
+ 1'd0;
643
+ assign tlbflushsingle_address =
644
+ (cond_58)? ( exe_linear) :
645
+ 32'd0;
646
+ assign exe_result_signals =
647
+ (cond_2 && ~cond_3)? ( { 4'd0, exe_jecxz_condition }) :
648
+ (cond_50 && ~cond_51)? ( { 4'd0, exe_condition }) :
649
+ (cond_68)? ( { 4'd0, dst[1:0] < src[1:0] }) :
650
+ (cond_117)? ( { 4'd0, e_bit_selected }) :
651
+ (cond_142)? ( { e_shift_no_write, e_shift_oszapc_update, e_shift_cf_of_update, e_shift_oflag, e_shift_cflag }) :
652
+ (cond_143)? ( { e_shift_no_write, e_shift_oszapc_update, e_shift_cf_of_update, e_shift_oflag, e_shift_cflag }) :
653
+ (cond_160)? ( { 4'd0, e_cmpxchg_eq }) :
654
+ (cond_168)? ( { e_shift_no_write, e_shift_oszapc_update, e_shift_cf_of_update, e_shift_oflag, e_shift_cflag }) :
655
+ (cond_175 && ~cond_176)? ( { 4'd0, exe_cmd_loop_condition }) :
656
+ (cond_296)? ( { 3'b0, exe_bcd_condition_af, exe_bcd_condition_cf }) :
657
+ (cond_297)? ( { 4'd0, e_bit_scan_zero }) :
658
+ 5'd0;
659
+ assign exe_result_push =
660
+ (cond_8 && cond_9)? ( exe_eip) :
661
+ (cond_12)? ( exe_eip) :
662
+ (cond_17)? ( { 16'd0, cs[15:0] }) :
663
+ (cond_19)? ( exe_eip) :
664
+ (cond_24)? ( { 16'd0, cs[15:0] }) :
665
+ (cond_25)? ( exe_eip) :
666
+ (cond_29)? ( { 16'd0, cs[15:0] }) :
667
+ (cond_30)? ( exe_eip) :
668
+ (cond_37 && cond_38)? ( esp) :
669
+ (cond_37 && ~cond_38)? ( { 16'd0, esp[15:0] }) :
670
+ (cond_39)? ( glob_param_5) :
671
+ (cond_40)? ( { 16'd0, cs[15:0] }) :
672
+ (cond_41 && cond_42)? ( exe_eip) :
673
+ (cond_41 && ~cond_42)? ( { 16'd0, exe_eip[15:0] }) :
674
+ (cond_47)? ( { 16'd0, e_seg_by_cmdex }) :
675
+ (cond_85)? ( exe_push_eflags) :
676
+ (cond_87)? ( { 16'd0, cs[15:0] }) :
677
+ (cond_88)? ( exe_eip) :
678
+ (cond_96)? ( exe_push_eflags) :
679
+ (cond_98)? ( { 16'd0, cs[15:0] }) :
680
+ (cond_99)? ( exe_eip) :
681
+ (cond_100)? ( { 16'd0, exc_error_code[15:0] }) :
682
+ (cond_101)? ( (exe_cmdex == `CMDEX_int_2_int_trap_gate_more_STEP_4)? { 16'd0, gs } : (exe_cmdex == `CMDEX_int_2_int_trap_gate_more_STEP_5)? { 16'd0, fs } : (exe_cmdex == `CMDEX_int_2_int_trap_gate_more_STEP_6)? { 16'd0, ds } : (exe_cmdex == `CMDEX_int_2_int_trap_gate_more_STEP_7)? { 16'd0, es } : (exe_cmdex == `CMDEX_int_2_int_trap_gate_more_STEP_8)? { 16'd0, ss } : esp) :
683
+ (cond_102)? ( exe_push_eflags) :
684
+ (cond_103)? ( { 16'd0, cs[15:0] }) :
685
+ (cond_104)? ( exe_eip) :
686
+ (cond_105)? ( { 16'd0, exc_error_code[15:0] }) :
687
+ (cond_154 && cond_155)? ( wr_esp_prev) :
688
+ (cond_154 && ~cond_155)? ( src) :
689
+ (cond_162)? ( ebp) :
690
+ (cond_164 && cond_165)? ( exe_buffer) :
691
+ (cond_164 && ~cond_165)? ( src) :
692
+ (cond_167)? ( src) :
693
+ (cond_193 && cond_194)? ( { {24{src[7]}}, src[7:0] }) :
694
+ (cond_193 && ~cond_194)? ( src) :
695
+ (cond_213 && cond_205)? ( { 16'd0, ss[15:0] }) :
696
+ (cond_216)? ( src) :
697
+ (cond_217)? ( src) :
698
+ (cond_219)? ( src) :
699
+ (cond_220)? ( exe_pushf_eflags) :
700
+ (cond_236)? ( src) :
701
+ (cond_238)? ( src) :
702
+ (cond_257)? ( exe_push_eflags) :
703
+ (cond_275)? ( { 16'd0, glob_param_3[15:0] }) :
704
+ (cond_283)? ( src) :
705
+ 32'd0;
706
+ assign exe_error_code =
707
+ (cond_74 && cond_75)? ( `SELECTOR_FOR_CODE(glob_param_1)) :
708
+ (cond_91 && cond_92)? ( { 5'd0, exc_vector[7:0], 3'b010 }) :
709
+ (cond_93 && cond_94)? ( { 5'd0, exc_vector[7:0], 3'b010 }) :
710
+ (cond_93 && cond_95)? ( { 5'd0, exc_vector[7:0], 3'b010 }) :
711
+ (cond_96 && cond_97)? ( (exe_int_2_int_trap_same_exception)? `SELECTOR_FOR_CODE(glob_param_1) : 16'd0) :
712
+ (cond_110 && cond_111 && cond_112)? ( { glob_param_1[15:2], 2'd0 }) :
713
+ (cond_113 && cond_114)? ( { glob_param_1[15:2], 2'd0 }) :
714
+ (cond_129 && cond_130)? ( `SELECTOR_FOR_CODE(glob_param_1)) :
715
+ (cond_131 && cond_132)? ( `SELECTOR_FOR_CODE(glob_param_1)) :
716
+ (cond_131 && cond_133)? ( `SELECTOR_FOR_CODE(glob_param_1)) :
717
+ (cond_136 && cond_137)? ( { glob_param_1[15:2], 2'd0 }) :
718
+ (cond_201 && cond_202)? ( `SELECTOR_FOR_CODE(glob_param_1)) :
719
+ (cond_201 && cond_203)? ( `SELECTOR_FOR_CODE(glob_param_1)) :
720
+ (cond_207 && cond_208)? ( `SELECTOR_FOR_CODE(glob_param_1)) :
721
+ (cond_207 && cond_95)? ( `SELECTOR_FOR_CODE(glob_param_1)) :
722
+ (cond_211 && cond_212)? ( `SELECTOR_FOR_CODE(glob_param_1)) :
723
+ (cond_211 && cond_95)? ( `SELECTOR_FOR_CODE(glob_param_1)) :
724
+ (cond_213 && cond_214)? ( `SELECTOR_FOR_CODE(glob_param_1)) :
725
+ (cond_213 && cond_215)? ( `SELECTOR_FOR_CODE(glob_param_1)) :
726
+ (cond_232 && cond_233)? ( `SELECTOR_FOR_CODE(glob_param_1)) :
727
+ (cond_232 && cond_95)? ( `SELECTOR_FOR_CODE(glob_param_1)) :
728
+ (cond_246 && cond_247)? ( `SELECTOR_FOR_CODE(glob_param_1)) :
729
+ (cond_246 && cond_248)? ( `SELECTOR_FOR_CODE(tr)) :
730
+ (cond_264 && cond_265)? ( `SELECTOR_FOR_CODE(glob_param_1)) :
731
+ (cond_266 && cond_267 && cond_268)? ( `SELECTOR_FOR_CODE(glob_param_1)) :
732
+ (cond_266 && cond_267 && cond_269)? ( `SELECTOR_FOR_CODE(glob_param_1)) :
733
+ (cond_270 && cond_267 && cond_271)? ( `SELECTOR_FOR_CODE(glob_param_1)) :
734
+ (cond_270 && cond_267 && cond_272)? ( `SELECTOR_FOR_CODE(glob_param_1)) :
735
+ (cond_273 && cond_267 && cond_274)? ( `SELECTOR_FOR_CODE(glob_param_1)) :
736
+ (cond_273 && cond_267 && cond_272)? ( `SELECTOR_FOR_CODE(glob_param_1)) :
737
+ 16'd0;
738
+ assign exe_waiting =
739
+ (cond_2 && cond_3)? (`TRUE) :
740
+ (cond_2 && ~cond_3 && cond_4)? (`TRUE) :
741
+ (cond_6 && cond_7)? (`TRUE) :
742
+ (cond_8 && cond_9 && cond_10)? (`TRUE) :
743
+ (cond_12 && cond_10)? (`TRUE) :
744
+ (cond_13 && cond_14)? (`TRUE) :
745
+ (cond_17 && cond_18)? (`TRUE) :
746
+ (cond_19 && cond_20)? (`TRUE) :
747
+ (cond_21 && cond_22)? (`TRUE) :
748
+ (cond_26 && cond_20)? (`TRUE) :
749
+ (cond_31 && cond_7)? (`TRUE) :
750
+ (cond_34 && cond_35)? (`TRUE) :
751
+ (cond_43 && cond_44)? (`TRUE) :
752
+ (cond_47 && cond_10)? (`TRUE) :
753
+ (cond_50 && cond_51)? (`TRUE) :
754
+ (cond_50 && ~cond_51 && cond_52)? (`TRUE) :
755
+ (cond_53 && cond_54)? (`TRUE) :
756
+ (cond_55 && cond_56)? (`TRUE) :
757
+ (cond_57 && cond_54)? (`TRUE) :
758
+ (cond_58 && cond_59)? (`TRUE) :
759
+ (cond_60 && cond_61)? (`TRUE) :
760
+ (cond_62 && cond_54)? (`TRUE) :
761
+ (cond_65 && cond_14)? (`TRUE) :
762
+ (cond_71 && cond_72)? (`TRUE) :
763
+ (cond_74 && cond_75)? (`TRUE) :
764
+ (cond_74 && cond_76)? (`TRUE) :
765
+ (cond_77 && cond_44)? (`TRUE) :
766
+ (cond_79 && cond_20)? (`TRUE) :
767
+ (cond_82 && cond_20)? (`TRUE) :
768
+ (cond_83 && cond_84)? (`TRUE) :
769
+ (cond_85 && cond_86)? (`TRUE) :
770
+ (cond_89 && cond_14)? (`TRUE) :
771
+ (cond_91 && cond_92)? (`TRUE) :
772
+ (cond_93 && cond_94)? (`TRUE) :
773
+ (cond_93 && cond_95)? (`TRUE) :
774
+ (cond_96 && cond_97)? (`TRUE) :
775
+ (cond_106 && cond_107)? (`TRUE) :
776
+ (cond_108 && cond_109)? (`TRUE) :
777
+ (cond_110 && cond_111 && cond_112)? (`TRUE) :
778
+ (cond_113 && cond_114 && cond_115)? (`TRUE) :
779
+ (cond_118 && cond_7)? (`TRUE) :
780
+ (cond_120 && cond_44)? (`TRUE) :
781
+ (cond_123 && cond_124)? (`TRUE) :
782
+ (cond_126 && cond_127)? (`TRUE) :
783
+ (cond_129 && cond_130)? (`TRUE) :
784
+ (cond_131 && cond_132)? (`TRUE) :
785
+ (cond_131 && cond_133)? (`TRUE) :
786
+ (cond_136 && cond_137)? (`TRUE) :
787
+ (cond_141 && cond_109)? (`TRUE) :
788
+ (cond_142 && cond_51)? (`TRUE) :
789
+ (cond_145 && cond_54)? (`TRUE) :
790
+ (cond_146 && cond_54)? (`TRUE) :
791
+ (cond_150 && cond_151)? (`TRUE) :
792
+ (cond_153 && cond_72)? (`TRUE) :
793
+ (cond_154 && cond_10)? (`TRUE) :
794
+ (cond_156 && cond_157)? (`TRUE) :
795
+ (cond_158 && cond_51)? (`TRUE) :
796
+ (cond_160 && cond_161)? (`TRUE) :
797
+ (cond_162 && cond_10)? (`TRUE) :
798
+ (cond_164 && cond_10)? (`TRUE) :
799
+ (cond_166 && cond_107)? (`TRUE) :
800
+ (cond_169 && cond_54)? (`TRUE) :
801
+ (cond_170 && cond_171)? (`TRUE) :
802
+ (cond_172 && cond_173)? (`TRUE) :
803
+ (cond_174 && cond_107)? (`TRUE) :
804
+ (cond_175 && cond_176)? (`TRUE) :
805
+ (cond_175 && ~cond_176 && cond_177)? (`TRUE) :
806
+ (cond_179 && cond_54)? (`TRUE) :
807
+ (cond_181 && cond_182)? (`TRUE) :
808
+ (cond_183 && cond_7)? (`TRUE) :
809
+ (cond_184 && cond_44)? (`TRUE) :
810
+ (cond_186 && cond_20)? (`TRUE) :
811
+ (cond_193 && cond_10)? (`TRUE) :
812
+ (cond_196 && cond_197)? (`TRUE) :
813
+ (cond_201 && cond_202)? (`TRUE) :
814
+ (cond_201 && cond_203)? (`TRUE) :
815
+ (cond_207 && cond_208)? (`TRUE) :
816
+ (cond_207 && cond_95)? (`TRUE) :
817
+ (cond_211 && cond_212)? (`TRUE) :
818
+ (cond_211 && cond_95)? (`TRUE) :
819
+ (cond_213 && cond_214)? (`TRUE) :
820
+ (cond_213 && cond_215)? (`TRUE) :
821
+ (cond_217 && cond_218)? (`TRUE) :
822
+ (cond_219 && cond_218)? (`TRUE) :
823
+ (cond_220 && cond_221)? (`TRUE) :
824
+ (cond_220 && ~cond_221 && cond_124)? (`TRUE) :
825
+ (cond_223 && cond_224)? (`TRUE) :
826
+ (cond_225 && cond_14)? (`TRUE) :
827
+ (cond_228 && cond_14)? (`TRUE) :
828
+ (cond_230 && cond_7)? (`TRUE) :
829
+ (cond_232 && cond_233)? (`TRUE) :
830
+ (cond_232 && cond_95)? (`TRUE) :
831
+ (cond_234 && cond_7)? (`TRUE) :
832
+ (cond_236 && cond_237)? (`TRUE) :
833
+ (cond_240 && cond_51)? (`TRUE) :
834
+ (cond_240 && ~cond_51 && cond_124)? (`TRUE) :
835
+ (cond_241 && cond_51)? (`TRUE) :
836
+ (cond_241 && ~cond_51 && cond_242)? (`TRUE) :
837
+ (cond_244 && cond_245)? (`TRUE) :
838
+ (cond_246 && cond_247)? (`TRUE) :
839
+ (cond_246 && cond_248)? (`TRUE) :
840
+ (cond_249 && cond_250)? (`TRUE) :
841
+ (cond_249 && cond_251)? (`TRUE) :
842
+ (cond_252 && cond_250)? (`TRUE) :
843
+ (cond_252 && cond_251)? (`TRUE) :
844
+ (cond_253 && cond_250)? (`TRUE) :
845
+ (cond_253 && cond_251)? (`TRUE) :
846
+ (cond_254 && cond_250)? (`TRUE) :
847
+ (cond_254 && cond_251)? (`TRUE) :
848
+ (cond_255 && cond_250)? (`TRUE) :
849
+ (cond_255 && cond_251)? (`TRUE) :
850
+ (cond_256 && cond_250)? (`TRUE) :
851
+ (cond_256 && cond_251)? (`TRUE) :
852
+ (cond_264 && cond_265)? (`TRUE) :
853
+ (cond_266 && cond_267 && cond_268)? (`TRUE) :
854
+ (cond_266 && cond_267 && cond_269)? (`TRUE) :
855
+ (cond_270 && cond_267 && cond_271)? (`TRUE) :
856
+ (cond_270 && cond_267 && cond_272)? (`TRUE) :
857
+ (cond_273 && cond_267 && cond_274)? (`TRUE) :
858
+ (cond_273 && cond_267 && cond_272)? (`TRUE) :
859
+ (cond_276 && cond_277)? (`TRUE) :
860
+ (cond_286 && cond_294)? (`TRUE) :
861
+ (cond_286 && ~cond_294 && cond_54)? (`TRUE) :
862
+ (cond_296 && cond_51)? (`TRUE) :
863
+ 1'd0;
864
+ assign exe_trigger_pf_fault =
865
+ (cond_249 && cond_251)? (`TRUE) :
866
+ (cond_252 && cond_251)? (`TRUE) :
867
+ (cond_253 && cond_251)? (`TRUE) :
868
+ (cond_254 && cond_251)? (`TRUE) :
869
+ (cond_255 && cond_251)? (`TRUE) :
870
+ (cond_256 && cond_251)? (`TRUE) :
871
+ 1'd0;
872
+ assign exe_branch =
873
+ (cond_2 && ~cond_3)? ( exe_jecxz_condition) :
874
+ (cond_50 && ~cond_51)? ( exe_condition) :
875
+ (cond_175 && ~cond_176)? ( exe_cmd_loop_condition) :
876
+ 1'd0;
877
+ assign offset_call =
878
+ (cond_24)? (`TRUE) :
879
+ (cond_25)? (`TRUE) :
880
+ 1'd0;
881
+ assign invddata_do =
882
+ (cond_55)? ( ~(e_invd_data_done)) :
883
+ 1'd0;
884
+ assign offset_int_real =
885
+ (cond_85)? (`TRUE) :
886
+ 1'd0;
887
+ assign offset_iret_glob_param_4 =
888
+ (cond_122)? (`TRUE) :
889
+ (cond_186)? ( exe_decoder[0] == 1'b1) :
890
+ 1'd0;
891
+ assign offset_leave =
892
+ (cond_167)? (`TRUE) :
893
+ 1'd0;
894
+ assign offset_new_stack_minus =
895
+ (cond_213 && cond_205)? (`TRUE) :
896
+ 1'd0;
897
+ assign offset_call_int_same_first =
898
+ (cond_29)? (`TRUE) :
899
+ (cond_96)? (`TRUE) :
900
+ 1'd0;
901
+ assign exe_trigger_db_fault =
902
+ (cond_286 && cond_294)? (`TRUE) :
903
+ 1'd0;
904
+ assign exe_glob_descriptor_2_set =
905
+ (cond_24)? (`TRUE) :
906
+ (cond_34 && cond_36)? (`TRUE) :
907
+ (cond_74 && cond_36)? (`TRUE) :
908
+ (cond_79 && cond_80)? (`TRUE) :
909
+ (cond_120 && ~cond_44)? (`TRUE) :
910
+ (cond_121)? (`TRUE) :
911
+ (cond_184 && ~cond_44)? (`TRUE) :
912
+ (cond_185)? ( exe_ready) :
913
+ 1'd0;
914
+ assign exe_glob_param_1_value =
915
+ (cond_15)? ( { 13'd0, `SEGMENT_CS, src[15:0] }) :
916
+ (cond_16 && cond_11)? ( { 13'd0, `SEGMENT_CS, exe_extra[31:16] }) :
917
+ (cond_16 && ~cond_11)? ( { 13'd0, `SEGMENT_CS, exe_extra[15:0] }) :
918
+ (cond_28)? ( { 7'd0, glob_descriptor[36:32], glob_descriptor[`DESC_BITS_TYPE] == `DESC_CALL_GATE_386, `SEGMENT_CS, glob_descriptor[31:16] }) :
919
+ (cond_34 && cond_36)? ( { 13'd0, `SEGMENT_SS, glob_param_3[15:0] }) :
920
+ (cond_45 && cond_36)? ( glob_param_3) :
921
+ (cond_73)? ( { 11'd0, glob_descriptor[`DESC_BIT_TYPE_BIT_0], glob_descriptor[`DESC_BITS_TYPE] >= `DESC_INTERRUPT_GATE_386, `SEGMENT_CS, glob_descriptor[31:16] }) :
922
+ (cond_74 && cond_36)? ( { 13'd0, `SEGMENT_SS, glob_param_3[15:0] }) :
923
+ (cond_79 && cond_80)? ( glob_param_3) :
924
+ (cond_120 && ~cond_44)? ( glob_param_3) :
925
+ (cond_121)? ( glob_param_3) :
926
+ (cond_184 && ~cond_44)? ( glob_param_3) :
927
+ (cond_185)? ( glob_param_3) :
928
+ (cond_196 && ~cond_197)? ( (exe_cmdex == `CMDEX_IN_dx)? { 16'd0, edx[15:0] } : { 24'd0, exe_decoder[15:8] }) :
929
+ (cond_204 && cond_205)? ( { 14'd0, `TASK_SWITCH_FROM_CALL, glob_param_1[15:0] }) :
930
+ (cond_204 && cond_206)? ( { 14'd0, `TASK_SWITCH_FROM_JUMP, glob_param_1[15:0] }) :
931
+ (cond_207 && cond_205)? ( { 14'd0, `TASK_SWITCH_FROM_CALL, glob_param_1[15:0] }) :
932
+ (cond_207 && cond_206)? ( { 14'd0, `TASK_SWITCH_FROM_JUMP, glob_param_1[15:0] }) :
933
+ (cond_207 && cond_209)? ( { 14'd0, `TASK_SWITCH_FROM_INT, glob_param_1[15:0] }) :
934
+ (cond_217 && ~cond_218)? ( { 16'd0, edx[15:0] }) :
935
+ (cond_219 && ~cond_218)? ( { 16'd0, edx[15:0] }) :
936
+ (cond_226)? ( { 13'd0, `SEGMENT_CS, src[15:0] }) :
937
+ (cond_227 && cond_11)? ( { 13'd0, `SEGMENT_CS, exe_extra[31:16] }) :
938
+ (cond_227 && ~cond_11)? ( { 13'd0, `SEGMENT_CS, exe_extra[15:0] }) :
939
+ (cond_236 && ~cond_237)? ( (exe_cmdex == `CMDEX_OUT_dx)? { 16'd0, edx[15:0] } : { 24'd0, exe_decoder[15:8] }) :
940
+ 32'd0;
941
+ assign exe_glob_param_1_set =
942
+ (cond_15)? (`TRUE) :
943
+ (cond_16 && cond_11)? (`TRUE) :
944
+ (cond_16 && ~cond_11)? (`TRUE) :
945
+ (cond_28)? (`TRUE) :
946
+ (cond_34 && cond_36)? (`TRUE) :
947
+ (cond_45 && cond_36)? (`TRUE) :
948
+ (cond_73)? (`TRUE) :
949
+ (cond_74 && cond_36)? (`TRUE) :
950
+ (cond_79 && cond_80)? (`TRUE) :
951
+ (cond_120 && ~cond_44)? (`TRUE) :
952
+ (cond_121)? (`TRUE) :
953
+ (cond_184 && ~cond_44)? (`TRUE) :
954
+ (cond_185)? ( exe_ready) :
955
+ (cond_196 && ~cond_197)? (`TRUE) :
956
+ (cond_204 && cond_205)? (`TRUE) :
957
+ (cond_204 && cond_206)? (`TRUE) :
958
+ (cond_207 && cond_205)? (`TRUE) :
959
+ (cond_207 && cond_206)? (`TRUE) :
960
+ (cond_207 && cond_209)? (`TRUE) :
961
+ (cond_217 && ~cond_218)? (`TRUE) :
962
+ (cond_219 && ~cond_218)? (`TRUE) :
963
+ (cond_226)? (`TRUE) :
964
+ (cond_227 && cond_11)? (`TRUE) :
965
+ (cond_227 && ~cond_11)? (`TRUE) :
966
+ (cond_236 && ~cond_237)? (`TRUE) :
967
+ 1'd0;
968
+ assign offset_call_int_same_next =
969
+ (cond_30)? (`TRUE) :
970
+ (cond_98)? (`TRUE) :
971
+ (cond_99)? (`TRUE) :
972
+ (cond_100)? (`TRUE) :
973
+ 1'd0;
974
+ assign offset_call_keep =
975
+ (cond_26)? (`TRUE) :
976
+ (cond_31)? (`TRUE) :
977
+ (cond_32)? (`TRUE) :
978
+ 1'd0;
979
+ assign invdcode_do =
980
+ (cond_55)? ( ~(e_invd_code_done)) :
981
+ (cond_170)? ( ~(e_wbinvd_code_done)) :
982
+ 1'd0;
983
+ assign exe_is_8bit_clear =
984
+ (cond_284)? ( exe_is_8bit) :
985
+ 1'd0;
986
+ assign exe_glob_param_3_value =
987
+ (cond_34 && cond_36)? ( glob_param_1) :
988
+ (cond_74 && cond_36)? ( glob_param_1) :
989
+ (cond_79 && cond_80)? ( glob_param_1) :
990
+ (cond_120 && ~cond_44)? ( glob_param_1) :
991
+ (cond_121)? ( glob_param_1) :
992
+ (cond_184 && ~cond_44)? ( glob_param_1) :
993
+ (cond_185)? ( glob_param_1) :
994
+ (cond_204)? ( { 10'd0, exe_consumed, 1'd0, 1'd0, 16'd0 }) :
995
+ (cond_207 && cond_210)? ( { 10'd0, exe_consumed, 1'd0, 1'd0, 16'd0 }) :
996
+ (cond_207 && cond_209)? ( { 10'd0, exe_consumed, 1'd0, exc_push_error, exc_error_code[15:0] }) :
997
+ 32'd0;
998
+ assign tlbcheck_do =
999
+ (cond_249)? (`TRUE) :
1000
+ (cond_252)? (`TRUE) :
1001
+ (cond_253)? (`TRUE) :
1002
+ (cond_254)? (`TRUE) :
1003
+ (cond_255)? (`TRUE) :
1004
+ (cond_256)? (`TRUE) :
1005
+ 1'd0;
1006
+ assign offset_int_real_next =
1007
+ (cond_87)? (`TRUE) :
1008
+ (cond_88)? (`TRUE) :
1009
+ 1'd0;
1010
+ assign tlbcheck_address =
1011
+ (cond_249)? ( glob_desc_base) :
1012
+ (cond_252)? ( glob_desc_base + exe_new_tss_max) :
1013
+ (cond_253)? ( glob_desc_base) :
1014
+ (cond_254)? ( glob_desc_base + 32'd1) :
1015
+ (cond_255)? ( (tr_cache[`DESC_BITS_TYPE] <= 4'd3)? tr_base + 32'd14 : tr_base + 32'h20) :
1016
+ (cond_256)? ( (tr_cache[`DESC_BITS_TYPE] <= 4'd3)? tr_base + 32'd41 : tr_base + 32'h5D) :
1017
+ 32'd0;
1018
+ assign exe_glob_param_2_value =
1019
+ (cond_8 && cond_11)? ( src) :
1020
+ (cond_8 && ~cond_11)? ( { 16'd0, src[15:0] }) :
1021
+ (cond_12 && cond_11)? ( exe_arith_add[31:0]) :
1022
+ (cond_12 && ~cond_11)? ( { 16'd0, exe_arith_add[15:0] }) :
1023
+ (cond_28)? ( (glob_descriptor[`DESC_BITS_TYPE] == `DESC_CALL_GATE_386)? { glob_descriptor[63:48], glob_descriptor[15:0] } : { 16'd0, glob_descriptor[15:0] }) :
1024
+ (cond_73)? ( (glob_descriptor[`DESC_BITS_TYPE] >= `DESC_INTERRUPT_GATE_386)? { glob_descriptor[63:48], glob_descriptor[15:0] } : { 16'd0, glob_descriptor[15:0] }) :
1025
+ (cond_200)? ( { 26'd0, exe_cmd_verw_desc_invalid, exe_cmd_verr_desc_invalid, exe_cmd_lsl_desc_invalid, exe_cmd_lar_desc_invalid, glob_param_2[1:0] }) :
1026
+ (cond_222 && cond_11)? ( src) :
1027
+ (cond_222 && ~cond_11)? ( { 16'd0, src[15:0] }) :
1028
+ (cond_223 && cond_11)? ( exe_arith_add[31:0]) :
1029
+ (cond_223 && ~cond_11)? ( { 16'd0, exe_arith_add[15:0] }) :
1030
+ (cond_276)? ( exe_eip) :
1031
+ 32'd0;
1032
+ assign exe_cmpxchg_switch_carry =
1033
+ (cond_160)? ( e_cmpxchg_sub[32]) :
1034
+ 1'd0;
1035
+ assign exe_trigger_nm_fault =
1036
+ (cond_156 && cond_157)? (`TRUE) :
1037
+ 1'd0;
1038
+ assign exe_arith_index =
1039
+ (cond_0)? ( (`ARITH_VALID | `ARITH_ADD)) :
1040
+ (cond_49)? ( (`ARITH_VALID | `ARITH_SUB)) :
1041
+ (cond_63)? ( (`ARITH_VALID | `ARITH_SUB)) :
1042
+ (cond_64)? ( (exe_cmdex[0] == `FALSE)? (`ARITH_VALID | `ARITH_ADD) : (`ARITH_VALID | `ARITH_SUB)) :
1043
+ (cond_144)? ( (`ARITH_VALID | `ARITH_SUB)) :
1044
+ (cond_160)? ( (`ARITH_VALID | `ARITH_SUB)) :
1045
+ (cond_172)? ( {`TRUE, exe_cmd[2:0]}) :
1046
+ (cond_178)? ( (`ARITH_VALID | `ARITH_AND)) :
1047
+ 4'd0;
1048
+ assign exe_glob_descriptor_set =
1049
+ (cond_24)? (`TRUE) :
1050
+ (cond_26 && ~cond_20)? (`TRUE) :
1051
+ (cond_45 && cond_36)? (`TRUE) :
1052
+ (cond_79 && cond_80)? (`TRUE) :
1053
+ (cond_120 && ~cond_44)? (`TRUE) :
1054
+ (cond_121)? (`TRUE) :
1055
+ (cond_184 && ~cond_44)? (`TRUE) :
1056
+ (cond_185)? ( exe_ready) :
1057
+ 1'd0;
1058
+ assign exe_result =
1059
+ (cond_0)? ( exe_arith_add[31:0]) :
1060
+ (cond_1)? ( exe_buffer) :
1061
+ (cond_48)? ( { 16'd0, e_seg_by_cmdex }) :
1062
+ (cond_49)? ( exe_arith_sub[31:0]) :
1063
+ (cond_63)? ( exe_arith_sub[31:0]) :
1064
+ (cond_64)? ( (exe_cmdex[0] == `FALSE)? exe_arith_add[31:0] : exe_arith_sub[31:0]) :
1065
+ (cond_68)? ( { 16'd0, dst[15:2], src[1:0] }) :
1066
+ (cond_69 && cond_11)? ( { dst[7:0], dst[15:8], dst[23:16], dst[31:24] }) :
1067
+ (cond_70)? ( glob_param_2) :
1068
+ (cond_106)? ( { 24'd0, e_aad_result }) :
1069
+ (cond_108)? ( { 16'd0, div_result_quotient[7:0], div_result_remainder[7:0] }) :
1070
+ (cond_117)? ( e_bit_result) :
1071
+ (cond_138)? ( src) :
1072
+ (cond_140)? ( exe_buffer) :
1073
+ (cond_141)? ( (exe_is_8bit)? { 16'd0, div_result_remainder[7:0], div_result_quotient[7:0] } : (exe_operand_16bit)? { div_result_remainder[15:0], div_result_quotient[15:0] } : div_result_quotient) :
1074
+ (cond_142)? ( e_shift_result) :
1075
+ (cond_143)? ( e_shift_result) :
1076
+ (cond_144)? ( exe_arith_sub[31:0]) :
1077
+ (cond_146 && cond_147)? ( e_cr0_reg) :
1078
+ (cond_146 && cond_148)? ( cr2) :
1079
+ (cond_146 && cond_149)? ( cr3) :
1080
+ (cond_152)? ( e_cr0_reg) :
1081
+ (cond_158 && cond_159)? ( 32'd1) :
1082
+ (cond_160)? ( e_cmpxchg_result) :
1083
+ (cond_166)? ( mult_result[31:0]) :
1084
+ (cond_168)? ( e_shift_result) :
1085
+ (cond_172)? ( ({ 1'b0, exe_cmd[2:0] } == `ARITH_ADD)? exe_arith_add[31:0] : ({ 1'b0, exe_cmd[2:0] } == `ARITH_OR)? exe_arith_or : ({ 1'b0, exe_cmd[2:0] } == `ARITH_ADC)? exe_arith_adc[31:0] : ({ 1'b0, exe_cmd[2:0] } == `ARITH_SBB)? exe_arith_sbb[31:0] : ({ 1'b0, exe_cmd[2:0] } == `ARITH_AND)? exe_arith_and : ({ 1'b0, exe_cmd[2:0] } == `ARITH_XOR)? exe_arith_xor : exe_arith_sub[31:0]) :
1086
+ (cond_174)? ( mult_result[31:0]) :
1087
+ (cond_178)? ( exe_arith_and) :
1088
+ (cond_190)? ( src) :
1089
+ (cond_191)? ( src) :
1090
+ (cond_192)? ( exe_buffer) :
1091
+ (cond_198)? ( exe_arith_not) :
1092
+ (cond_199)? ( exe_extra) :
1093
+ (cond_239)? ( src) :
1094
+ (cond_278)? ( exe_address_effective) :
1095
+ (cond_279 && cond_280)? ( { 16'd0, gdtr_limit }) :
1096
+ (cond_279 && cond_281)? ( gdtr_base) :
1097
+ (cond_282 && cond_280)? ( { 16'd0, idtr_limit }) :
1098
+ (cond_282 && cond_281)? ( idtr_base) :
1099
+ (cond_284)? ( (exe_cmd == `CMD_MOVSX && exe_is_8bit)? { {24{src[7]}}, src[7:0] } : (exe_cmd == `CMD_MOVSX)? { {16{src[15]}}, src[15:0] } : (exe_cmd == `CMD_MOVZX && exe_is_8bit)? { 24'd0, src[7:0] } : { 16'd0, src[15:0] }) :
1100
+ (cond_286 && cond_288)? ( dr0) :
1101
+ (cond_286 && cond_289)? ( dr1) :
1102
+ (cond_286 && cond_290)? ( dr2) :
1103
+ (cond_286 && cond_291)? ( dr3) :
1104
+ (cond_286 && cond_292)? ( { 16'hFFFF, dr6_bt, dr6_bs, dr6_bd, dr6_b12, 8'hFF, dr6_breakpoints }) :
1105
+ (cond_286 && cond_293)? ( dr7) :
1106
+ (cond_295)? ( src) :
1107
+ (cond_296)? ( (exe_cmd == `CMD_AAA)? { 16'd0, e_aaa_result } : (exe_cmd == `CMD_AAS)? { 16'd0, e_aas_result } : (exe_cmd == `CMD_DAA)? { 16'd0, dst[15:8], e_daa_result } : { 16'd0, dst[15:8], e_das_result }) :
1108
+ (cond_297 && cond_298)? ( { 27'd0, e_bit_scan_forward }) :
1109
+ (cond_297 && cond_299)? ( { 27'd0, e_bit_scan_reverse }) :
1110
+ 32'd0;
1111
+ assign exe_trigger_ts_fault =
1112
+ (cond_34 && cond_35)? (`TRUE) :
1113
+ (cond_74 && cond_76)? (`TRUE) :
1114
+ (cond_129 && cond_130)? (`TRUE) :
1115
+ (cond_131 && cond_132)? (`TRUE) :
1116
+ (cond_213 && cond_214)? (`TRUE) :
1117
+ (cond_246 && cond_247)? (`TRUE) :
1118
+ (cond_246 && cond_248)? (`TRUE) :
1119
+ (cond_264 && cond_265)? (`TRUE) :
1120
+ (cond_266 && cond_267 && cond_268)? (`TRUE) :
1121
+ (cond_270 && cond_267 && cond_271)? (`TRUE) :
1122
+ (cond_273 && cond_267 && cond_274)? (`TRUE) :
1123
+ 1'd0;
1124
+ assign exe_glob_param_3_set =
1125
+ (cond_34 && cond_36)? (`TRUE) :
1126
+ (cond_74 && cond_36)? (`TRUE) :
1127
+ (cond_79 && cond_80)? (`TRUE) :
1128
+ (cond_120 && ~cond_44)? (`TRUE) :
1129
+ (cond_121)? (`TRUE) :
1130
+ (cond_184 && ~cond_44)? (`TRUE) :
1131
+ (cond_185)? ( exe_ready) :
1132
+ (cond_204)? (`TRUE) :
1133
+ (cond_207 && cond_210)? (`TRUE) :
1134
+ (cond_207 && cond_209)? (`TRUE) :
1135
+ 1'd0;
1136
+ assign exe_glob_descriptor_2_value =
1137
+ (cond_24)? ( glob_descriptor) :
1138
+ (cond_34 && cond_36)? ( glob_descriptor) :
1139
+ (cond_74 && cond_36)? ( glob_descriptor) :
1140
+ (cond_79 && cond_80)? ( glob_descriptor) :
1141
+ (cond_120 && ~cond_44)? ( glob_descriptor) :
1142
+ (cond_121)? ( glob_descriptor) :
1143
+ (cond_184 && ~cond_44)? ( glob_descriptor) :
1144
+ (cond_185)? ( glob_descriptor) :
1145
+ 64'd0;
1146
+ assign dr6_bd_set =
1147
+ (cond_286 && cond_294)? ( `TRUE) :
1148
+ 1'd0;
1149
+ assign offset_enter_last =
1150
+ (cond_163)? (`TRUE) :
1151
+ 1'd0;
1152
+ assign offset_new_stack =
1153
+ (cond_77)? (`TRUE) :
1154
+ 1'd0;
1155
+ assign offset_ret_imm =
1156
+ (cond_186)? ( exe_decoder[0] == 1'b0) :
1157
+ 1'd0;
snapshots/MiSTer-devel_ao486_MiSTer_pr72/rtl/ao486/autogen/memory_write.v ADDED
@@ -0,0 +1,74 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ //======================================================== conditions
2
+ wire cond_0 = state == STATE_IDLE;
3
+ wire cond_1 = length_1 == 3'd1;
4
+ wire cond_2 = length_1 == 3'd2;
5
+ wire cond_3 = write_do && ~(wr_reset) && ~(write_page_fault) && ~(write_ac_fault);
6
+ wire cond_4 = state == STATE_FIRST_WAIT;
7
+ wire cond_5 = tlbwrite_page_fault || tlbwrite_ac_fault;
8
+ wire cond_6 = tlbwrite_done && length_2_reg != 3'd0;
9
+ wire cond_7 = tlbwrite_done;
10
+ wire cond_8 = reset_waiting == `FALSE;
11
+ wire cond_9 = state == STATE_SECOND;
12
+ wire cond_10 = tlbwrite_page_fault || tlbwrite_ac_fault || tlbwrite_done;
13
+ wire cond_11 = tlbwrite_done && reset_waiting == `FALSE;
14
+ //======================================================== saves
15
+ wire [23:0] buffer_to_reg =
16
+ (cond_0 && cond_1)? ( write_data[31:8]) :
17
+ (cond_0 && ~cond_1 && cond_2)? ( { 8'd0, write_data[31:16] }) :
18
+ (cond_0 && ~cond_1 && ~cond_2)? ( { 16'd0, write_data[31:24] }) :
19
+ buffer;
20
+ wire [31:0] address_2_reg_to_reg =
21
+ (cond_0)? ( { address_2[31:4], 4'd0 }) :
22
+ address_2_reg;
23
+ wire [2:0] length_2_reg_to_reg =
24
+ (cond_0)? ( length_2) :
25
+ length_2_reg;
26
+ wire [1:0] state_to_reg =
27
+ (cond_0 && cond_3)? ( STATE_FIRST_WAIT) :
28
+ (cond_4 && cond_5)? ( STATE_IDLE) :
29
+ (cond_4 && ~cond_5 && cond_6)? ( STATE_SECOND) :
30
+ (cond_4 && ~cond_5 && ~cond_6 && cond_7)? ( STATE_IDLE) :
31
+ (cond_9 && cond_10)? ( STATE_IDLE) :
32
+ state;
33
+ //======================================================== always
34
+ always @(posedge clk) begin
35
+ if(rst_n == 1'b0) buffer <= 24'd0;
36
+ else buffer <= buffer_to_reg;
37
+ end
38
+ always @(posedge clk) begin
39
+ if(rst_n == 1'b0) address_2_reg <= 32'd0;
40
+ else address_2_reg <= address_2_reg_to_reg;
41
+ end
42
+ always @(posedge clk) begin
43
+ if(rst_n == 1'b0) length_2_reg <= 3'd0;
44
+ else length_2_reg <= length_2_reg_to_reg;
45
+ end
46
+ always @(posedge clk) begin
47
+ if(rst_n == 1'b0) state <= 2'd0;
48
+ else state <= state_to_reg;
49
+ end
50
+ //======================================================== sets
51
+ assign write_done =
52
+ (cond_4 && ~cond_5 && ~cond_6 && cond_7 && cond_8)? (`TRUE) :
53
+ (cond_9 && cond_11)? (`TRUE) :
54
+ 1'd0;
55
+ assign tlbwrite_do =
56
+ (cond_0 && cond_3)? (`TRUE) :
57
+ (cond_4)? (`TRUE) :
58
+ (cond_9)? (`TRUE) :
59
+ 1'd0;
60
+ assign tlbwrite_address =
61
+ (cond_0)? ( write_address) :
62
+ (cond_4)? ( write_address) :
63
+ (cond_9)? ( address_2_reg) :
64
+ 32'd0;
65
+ assign tlbwrite_length =
66
+ (cond_0)? ( length_1) :
67
+ (cond_4)? ( length_1) :
68
+ (cond_9)? ( length_2_reg) :
69
+ 3'd0;
70
+ assign tlbwrite_data =
71
+ (cond_0)? ( write_data) :
72
+ (cond_4)? ( write_data) :
73
+ (cond_9)? ( { 8'd0, buffer }) :
74
+ 32'd0;
snapshots/MiSTer-devel_ao486_MiSTer_pr72/rtl/ao486/autogen/microcode_commands.v ADDED
@@ -0,0 +1,926 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ //======================================================== conditions
2
+ wire cond_0 = mc_cmd == `CMD_XADD && mc_cmdex_last == `CMDEX_XADD_FIRST;
3
+ wire cond_1 = mc_cmd == `CMD_CALL && mc_cmdex_last == `CMDEX_CALL_Ev_STEP_0;
4
+ wire cond_2 = mc_cmd == `CMD_CALL && mc_cmdex_last == `CMDEX_CALL_Jv_STEP_0;
5
+ wire cond_3 = mc_cmd == `CMD_CALL && mc_cmdex_last == `CMDEX_CALL_Ep_STEP_0;
6
+ wire cond_4 = mc_cmd == `CMD_CALL && mc_cmdex_last == `CMDEX_CALL_Ap_STEP_0;
7
+ wire cond_5 = mc_cmd == `CMD_CALL && (mc_cmdex_last == `CMDEX_CALL_Ep_STEP_1 || mc_cmdex_last == `CMDEX_CALL_Ap_STEP_1) && (real_mode || v8086_mode);
8
+ wire cond_6 = mc_cmd == `CMD_CALL && mc_cmdex_last == `CMDEX_CALL_real_v8086_STEP_0;
9
+ wire cond_7 = mc_cmd == `CMD_CALL && mc_cmdex_last == `CMDEX_CALL_real_v8086_STEP_1;
10
+ wire cond_8 = mc_cmd == `CMD_CALL && mc_cmdex_last == `CMDEX_CALL_real_v8086_STEP_2;
11
+ wire cond_9 = mc_cmd == `CMD_CALL && (mc_cmdex_last == `CMDEX_CALL_Ep_STEP_1 || mc_cmdex_last == `CMDEX_CALL_Ap_STEP_1) && (protected_mode);
12
+ wire cond_10 = mc_cmd == `CMD_CALL && mc_cmdex_last == `CMDEX_CALL_protected_STEP_0;
13
+ wire cond_11 = mc_cmd == `CMD_CALL && mc_cmdex_last == `CMDEX_CALL_protected_STEP_1 && glob_descriptor[`DESC_BIT_SEG];
14
+ wire cond_12 = mc_cmd == `CMD_CALL && mc_cmdex_last == `CMDEX_CALL_protected_seg_STEP_0;
15
+ wire cond_13 = mc_cmd == `CMD_CALL && mc_cmdex_last == `CMDEX_CALL_protected_seg_STEP_1;
16
+ wire cond_14 = mc_cmd == `CMD_CALL && mc_cmdex_last == `CMDEX_CALL_protected_seg_STEP_2;
17
+ wire cond_15 = mc_cmd == `CMD_CALL_2 && mc_cmdex_last == `CMDEX_CALL_2_protected_seg_STEP_3;
18
+ wire cond_16 = mc_cmd == `CMD_CALL && mc_cmdex_last == `CMDEX_CALL_protected_STEP_1 && glob_descriptor[`DESC_BIT_SEG] == `FALSE && (glob_descriptor[`DESC_BITS_TYPE] == `DESC_TSS_AVAIL_386 || glob_descriptor[`DESC_BITS_TYPE] == `DESC_TSS_AVAIL_286);
19
+ wire cond_17 = mc_cmd == `CMD_CALL_2 && mc_cmdex_last == `CMDEX_CALL_2_task_switch_STEP_0 && glob_param_3[21:18] == 4'd0;
20
+ wire cond_18 = mc_cmd == `CMD_CALL_2 && mc_cmdex_last == `CMDEX_CALL_2_task_switch_STEP_0 && glob_param_3[21:18] != 4'd0;
21
+ wire cond_19 = mc_cmd == `CMD_CALL && mc_cmdex_last == `CMDEX_CALL_protected_STEP_1 && glob_descriptor[`DESC_BIT_SEG] == `FALSE && glob_descriptor[`DESC_BITS_TYPE] == `DESC_TASK_GATE;
22
+ wire cond_20 = mc_cmd == `CMD_CALL_2 && mc_cmdex_last == `CMDEX_CALL_2_task_gate_STEP_0;
23
+ wire cond_21 = mc_cmd == `CMD_CALL_2 && mc_cmdex_last == `CMDEX_CALL_2_task_gate_STEP_1;
24
+ wire cond_22 = mc_cmd == `CMD_CALL && mc_cmdex_last == `CMDEX_CALL_protected_STEP_1 && glob_descriptor[`DESC_BIT_SEG] == `FALSE && (glob_descriptor[`DESC_BITS_TYPE] == `DESC_CALL_GATE_386 || glob_descriptor[`DESC_BITS_TYPE] == `DESC_CALL_GATE_286);
25
+ wire cond_23 = mc_cmd == `CMD_CALL_2 && mc_cmdex_last == `CMDEX_CALL_2_call_gate_STEP_0;
26
+ wire cond_24 = mc_cmd == `CMD_CALL_2 && mc_cmdex_last == `CMDEX_CALL_2_call_gate_STEP_1;
27
+ wire cond_25 = mc_cmd == `CMD_CALL_2 && mc_cmdex_last == `CMDEX_CALL_2_call_gate_STEP_2 && `DESC_IS_CODE_NON_CONFORMING(glob_descriptor) && glob_descriptor[`DESC_BITS_DPL] < cpl;
28
+ wire cond_26 = mc_cmd == `CMD_CALL_2 && mc_cmdex_last == `CMDEX_CALL_2_call_gate_more_STEP_0;
29
+ wire cond_27 = mc_cmd == `CMD_CALL_2 && mc_cmdex_last == `CMDEX_CALL_2_call_gate_more_STEP_1;
30
+ wire cond_28 = mc_cmd == `CMD_CALL_2 && mc_cmdex_last == `CMDEX_CALL_2_call_gate_more_STEP_2;
31
+ wire cond_29 = mc_cmd == `CMD_CALL_2 && mc_cmdex_last == `CMDEX_CALL_2_call_gate_more_STEP_3 && glob_param_3[24:20] != 5'd0;
32
+ wire cond_30 = mc_cmd == `CMD_CALL_3 && mc_cmdex_last == `CMDEX_CALL_3_call_gate_more_STEP_4 && glob_param_3[24:20] == 5'd1;
33
+ wire cond_31 = mc_cmd == `CMD_CALL_3 && mc_cmdex_last == `CMDEX_CALL_3_call_gate_more_STEP_4 && glob_param_3[24:20] != 5'd1;
34
+ wire cond_32 = mc_cmd == `CMD_CALL_3 && mc_cmdex_last == `CMDEX_CALL_3_call_gate_more_STEP_5 && glob_param_3[24:20] == 5'd1;
35
+ wire cond_33 = mc_cmd == `CMD_CALL_3 && mc_cmdex_last == `CMDEX_CALL_3_call_gate_more_STEP_5 && glob_param_3[24:20] != 5'd1;
36
+ wire cond_34 = mc_cmd == `CMD_CALL_2 && mc_cmdex_last == `CMDEX_CALL_2_call_gate_more_STEP_3 && glob_param_3[24:20] == 5'd0;
37
+ wire cond_35 = mc_cmd == `CMD_CALL_3 && mc_cmdex_last == `CMDEX_CALL_3_call_gate_more_STEP_6;
38
+ wire cond_36 = mc_cmd == `CMD_CALL_3 && mc_cmdex_last == `CMDEX_CALL_3_call_gate_more_STEP_7;
39
+ wire cond_37 = mc_cmd == `CMD_CALL_3 && mc_cmdex_last == `CMDEX_CALL_3_call_gate_more_STEP_8;
40
+ wire cond_38 = mc_cmd == `CMD_CALL_3 && mc_cmdex_last == `CMDEX_CALL_3_call_gate_more_STEP_9;
41
+ wire cond_39 = mc_cmd == `CMD_CALL_2 && mc_cmdex_last == `CMDEX_CALL_2_call_gate_STEP_2 && ~(`DESC_IS_CODE_NON_CONFORMING(glob_descriptor) && glob_descriptor[`DESC_BITS_DPL] < cpl);
42
+ wire cond_40 = mc_cmd == `CMD_CALL_2 && mc_cmdex_last == `CMDEX_CALL_2_call_gate_same_STEP_0;
43
+ wire cond_41 = mc_cmd == `CMD_CALL_2 && mc_cmdex_last == `CMDEX_CALL_2_call_gate_same_STEP_1;
44
+ wire cond_42 = mc_cmd == `CMD_CALL_2 && mc_cmdex_last == `CMDEX_CALL_2_call_gate_same_STEP_2;
45
+ wire cond_43 = mc_cmd == `CMD_INVD && mc_cmdex_last == `CMDEX_INVD_STEP_0;
46
+ wire cond_44 = mc_cmd == `CMD_INVD && mc_cmdex_last == `CMDEX_INVD_STEP_1;
47
+ wire cond_45 = mc_cmd == `CMD_INVLPG && mc_cmdex_last == `CMDEX_INVLPG_STEP_0;
48
+ wire cond_46 = mc_cmd == `CMD_INVLPG && mc_cmdex_last == `CMDEX_INVLPG_STEP_1;
49
+ wire cond_47 = mc_cmd == `CMD_io_allow && mc_cmdex_last == `CMDEX_io_allow_1;
50
+ wire cond_48 = mc_cmd == `CMD_io_allow && mc_cmdex_last == `CMDEX_io_allow_2;
51
+ wire cond_49 = mc_cmd == `CMD_RET_near && mc_cmdex_last == `CMDEX_RET_near_imm;
52
+ wire cond_50 = mc_cmd == `CMD_RET_near && mc_cmdex_last == `CMDEX_RET_near;
53
+ wire cond_51 = mc_cmd == `CMD_LxS && mc_cmdex_last == `CMDEX_LxS_STEP_1;
54
+ wire cond_52 = mc_cmd == `CMD_LxS && mc_cmdex_last == `CMDEX_LxS_STEP_2;
55
+ wire cond_53 = mc_cmd == `CMD_LxS && mc_cmdex_last == `CMDEX_LxS_STEP_3;
56
+ wire cond_54 = (mc_cmd == `CMD_MOV_to_seg || mc_cmd == `CMD_LLDT || mc_cmd == `CMD_LTR) && mc_cmdex_last != `CMDEX_MOV_to_seg_LLDT_LTR_STEP_LAST;
57
+ wire cond_55 = (mc_cmd == `CMD_MOV_to_seg || mc_cmd == `CMD_LLDT || mc_cmd == `CMD_LTR) && mc_cmdex_last == `CMDEX_MOV_to_seg_LLDT_LTR_STEP_LAST;
58
+ wire cond_56 = mc_cmd == `CMD_int && mc_cmdex_last == `CMDEX_int_STEP_0;
59
+ wire cond_57 = mc_cmd == `CMD_int && mc_cmdex_last == `CMDEX_int_STEP_1 && real_mode;
60
+ wire cond_58 = mc_cmd == `CMD_int && mc_cmdex_last == `CMDEX_int_real_STEP_0;
61
+ wire cond_59 = mc_cmd == `CMD_int && mc_cmdex_last == `CMDEX_int_real_STEP_1;
62
+ wire cond_60 = mc_cmd == `CMD_int && mc_cmdex_last == `CMDEX_int_real_STEP_2;
63
+ wire cond_61 = mc_cmd == `CMD_int && mc_cmdex_last == `CMDEX_int_real_STEP_3;
64
+ wire cond_62 = mc_cmd == `CMD_int && mc_cmdex_last == `CMDEX_int_real_STEP_4;
65
+ wire cond_63 = mc_cmd == `CMD_int && mc_cmdex_last == `CMDEX_int_STEP_1 && ~(real_mode);
66
+ wire cond_64 = mc_cmd == `CMD_int && mc_cmdex_last == `CMDEX_int_protected_STEP_0;
67
+ wire cond_65 = mc_cmd == `CMD_int && mc_cmdex_last == `CMDEX_int_protected_STEP_1;
68
+ wire cond_66 = mc_cmd == `CMD_int && mc_cmdex_last == `CMDEX_int_protected_STEP_2 && glob_descriptor[`DESC_BITS_TYPE] == `DESC_TASK_GATE;
69
+ wire cond_67 = mc_cmd == `CMD_int && mc_cmdex_last == `CMDEX_int_task_gate_STEP_0;
70
+ wire cond_68 = mc_cmd == `CMD_int && mc_cmdex_last == `CMDEX_int_task_gate_STEP_1;
71
+ wire cond_69 = mc_cmd == `CMD_int && mc_cmdex_last == `CMDEX_int_protected_STEP_2 && glob_descriptor[`DESC_BITS_TYPE] != `DESC_TASK_GATE;
72
+ wire cond_70 = mc_cmd == `CMD_int && mc_cmdex_last == `CMDEX_int_int_trap_gate_STEP_0;
73
+ wire cond_71 = mc_cmd == `CMD_int && mc_cmdex_last == `CMDEX_int_int_trap_gate_STEP_1;
74
+ wire cond_72 = mc_cmd == `CMD_int && mc_cmdex_last == `CMDEX_int_int_trap_gate_STEP_2 && `DESC_IS_CODE_NON_CONFORMING(glob_descriptor) && glob_descriptor[`DESC_BITS_DPL] < cpl;
75
+ wire cond_73 = mc_cmd == `CMD_int_2 && mc_cmdex_last == `CMDEX_int_2_int_trap_gate_more_STEP_0;
76
+ wire cond_74 = mc_cmd == `CMD_int_2 && mc_cmdex_last == `CMDEX_int_2_int_trap_gate_more_STEP_1;
77
+ wire cond_75 = mc_cmd == `CMD_int_2 && mc_cmdex_last == `CMDEX_int_2_int_trap_gate_more_STEP_2;
78
+ wire cond_76 = mc_cmd == `CMD_int_2 && mc_cmdex_last == `CMDEX_int_2_int_trap_gate_more_STEP_3 && v8086_mode;
79
+ wire cond_77 = mc_cmd == `CMD_int_2 && mc_cmdex_last == `CMDEX_int_2_int_trap_gate_more_STEP_4;
80
+ wire cond_78 = mc_cmd == `CMD_int_2 && mc_cmdex_last == `CMDEX_int_2_int_trap_gate_more_STEP_5;
81
+ wire cond_79 = mc_cmd == `CMD_int_2 && mc_cmdex_last == `CMDEX_int_2_int_trap_gate_more_STEP_6;
82
+ wire cond_80 = mc_cmd == `CMD_int_2 && mc_cmdex_last == `CMDEX_int_2_int_trap_gate_more_STEP_7;
83
+ wire cond_81 = mc_cmd == `CMD_int_2 && mc_cmdex_last == `CMDEX_int_2_int_trap_gate_more_STEP_3 && ~(v8086_mode);
84
+ wire cond_82 = mc_cmd == `CMD_int_2 && mc_cmdex_last == `CMDEX_int_2_int_trap_gate_more_STEP_8;
85
+ wire cond_83 = mc_cmd == `CMD_int_2 && mc_cmdex_last == `CMDEX_int_2_int_trap_gate_more_STEP_9;
86
+ wire cond_84 = mc_cmd == `CMD_int_3 && mc_cmdex_last == `CMDEX_int_3_int_trap_gate_more_STEP_0;
87
+ wire cond_85 = mc_cmd == `CMD_int_3 && mc_cmdex_last == `CMDEX_int_3_int_trap_gate_more_STEP_1;
88
+ wire cond_86 = mc_cmd == `CMD_int_3 && mc_cmdex_last == `CMDEX_int_3_int_trap_gate_more_STEP_2 && exc_push_error;
89
+ wire cond_87 = mc_cmd == `CMD_int_3 && mc_cmdex_last == `CMDEX_int_3_int_trap_gate_more_STEP_3;
90
+ wire cond_88 = mc_cmd == `CMD_int_3 && mc_cmdex_last == `CMDEX_int_3_int_trap_gate_more_STEP_2 && ~(exc_push_error);
91
+ wire cond_89 = mc_cmd == `CMD_int_3 && mc_cmdex_last == `CMDEX_int_3_int_trap_gate_more_STEP_4;
92
+ wire cond_90 = mc_cmd == `CMD_int_3 && mc_cmdex_last == `CMDEX_int_3_int_trap_gate_more_STEP_5;
93
+ wire cond_91 = mc_cmd == `CMD_int && mc_cmdex_last == `CMDEX_int_int_trap_gate_STEP_2 && ~(`DESC_IS_CODE_NON_CONFORMING(glob_descriptor) && glob_descriptor[`DESC_BITS_DPL] < cpl);
94
+ wire cond_92 = mc_cmd == `CMD_int_2 && mc_cmdex_last == `CMDEX_int_2_int_trap_gate_same_STEP_0;
95
+ wire cond_93 = mc_cmd == `CMD_int_2 && mc_cmdex_last == `CMDEX_int_2_int_trap_gate_same_STEP_1;
96
+ wire cond_94 = mc_cmd == `CMD_int_2 && mc_cmdex_last == `CMDEX_int_2_int_trap_gate_same_STEP_2 && exc_push_error;
97
+ wire cond_95 = mc_cmd == `CMD_int_2 && mc_cmdex_last == `CMDEX_int_2_int_trap_gate_same_STEP_3;
98
+ wire cond_96 = mc_cmd == `CMD_int_2 && mc_cmdex_last == `CMDEX_int_2_int_trap_gate_same_STEP_2 && ~(exc_push_error);
99
+ wire cond_97 = mc_cmd == `CMD_int_2 && mc_cmdex_last == `CMDEX_int_2_int_trap_gate_same_STEP_4;
100
+ wire cond_98 = mc_cmd == `CMD_load_seg && (~(protected_mode) || (protected_mode && mc_cmdex_last == `CMDEX_load_seg_STEP_2));
101
+ wire cond_99 = mc_cmd == `CMD_load_seg && protected_mode && mc_cmdex_last == `CMDEX_load_seg_STEP_1;
102
+ wire cond_100 = mc_cmd == `CMD_POP_seg && mc_cmdex_last == `CMDEX_POP_seg_STEP_1;
103
+ wire cond_101 = mc_cmd == `CMD_IRET && mc_cmdex_last == `CMDEX_IRET_real_v86_STEP_0;
104
+ wire cond_102 = mc_cmd == `CMD_IRET && mc_cmdex_last == `CMDEX_IRET_real_v86_STEP_1;
105
+ wire cond_103 = mc_cmd == `CMD_IRET && mc_cmdex_last == `CMDEX_IRET_real_v86_STEP_2;
106
+ wire cond_104 = mc_cmd == `CMD_IRET && mc_cmdex_last == `CMDEX_IRET_protected_STEP_0 && ntflag;
107
+ wire cond_105 = mc_cmd == `CMD_IRET && mc_cmdex_last == `CMDEX_IRET_task_switch_STEP_0;
108
+ wire cond_106 = mc_cmd == `CMD_IRET && mc_cmdex_last == `CMDEX_IRET_task_switch_STEP_1;
109
+ wire cond_107 = mc_cmd == `CMD_IRET && mc_cmdex_last == `CMDEX_IRET_protected_STEP_0 && ~(ntflag);
110
+ wire cond_108 = mc_cmd == `CMD_IRET && mc_cmdex_last == `CMDEX_IRET_protected_STEP_1;
111
+ wire cond_109 = mc_cmd == `CMD_IRET && mc_cmdex_last == `CMDEX_IRET_protected_STEP_2;
112
+ wire cond_110 = mc_cmd == `CMD_IRET && mc_cmdex_last == `CMDEX_IRET_protected_STEP_3 && mc_operand_32bit && glob_param_3[`EFLAGS_BIT_VM] && cpl == 2'd0;
113
+ wire cond_111 = mc_cmd == `CMD_IRET && mc_cmdex_last >= `CMDEX_IRET_protected_to_v86_STEP_0 && mc_cmdex_last < `CMDEX_IRET_protected_to_v86_STEP_5;
114
+ wire cond_112 = mc_cmd == `CMD_IRET && mc_cmdex_last == `CMDEX_IRET_protected_to_v86_STEP_5;
115
+ wire cond_113 = mc_cmd == `CMD_IRET_2 && mc_cmdex_last == `CMDEX_IRET_2_protected_to_v86_STEP_6;
116
+ wire cond_114 = mc_cmd == `CMD_IRET && mc_cmdex_last == `CMDEX_IRET_protected_STEP_3 && ~(mc_operand_32bit && glob_param_3[`EFLAGS_BIT_VM] && cpl == 2'd0);
117
+ wire cond_115 = mc_cmd == `CMD_IRET_2 && mc_cmdex_last == `CMDEX_IRET_2_protected_same_STEP_0;
118
+ wire cond_116 = mc_cmd == `CMD_IRET_2 && mc_cmdex_last == `CMDEX_IRET_2_protected_same_STEP_1;
119
+ wire cond_117 = mc_cmd == `CMD_IRET_2 && mc_cmdex_last == `CMDEX_IRET_2_protected_outer_STEP_0;
120
+ wire cond_118 = mc_cmd == `CMD_IRET_2 && mc_cmdex_last >= `CMDEX_IRET_2_protected_outer_STEP_1 && mc_cmdex_last < `CMDEX_IRET_2_protected_outer_STEP_6;
121
+ wire cond_119 = mc_cmd == `CMD_IRET_2 && mc_cmdex_last == `CMDEX_IRET_2_protected_outer_STEP_6;
122
+ wire cond_120 = mc_cmd == `CMD_POP && mc_cmdex_last == `CMDEX_POP_modregrm_STEP_0;
123
+ wire cond_121 = mc_cmd == `CMD_CMPS && mc_cmdex_last == `CMDEX_CMPS_FIRST;
124
+ wire cond_122 = mc_cmd == `CMD_CMPS && mc_cmdex_last == `CMDEX_CMPS_LAST;
125
+ wire cond_123 = mc_cmd == `CMD_control_reg && mc_cmdex_last == `CMDEX_control_reg_LMSW_STEP_0;
126
+ wire cond_124 = mc_cmd == `CMD_control_reg && mc_cmdex_last == `CMDEX_control_reg_MOV_load_STEP_0;
127
+ wire cond_125 = (mc_cmd == `CMD_LGDT || mc_cmd == `CMD_LIDT) && mc_cmdex_last == `CMDEX_LGDT_LIDT_STEP_1;
128
+ wire cond_126 = (mc_cmd == `CMD_LGDT || mc_cmd == `CMD_LIDT) && mc_cmdex_last == `CMDEX_LGDT_LIDT_STEP_2;
129
+ wire cond_127 = (mc_cmd == `CMD_LGDT || mc_cmd == `CMD_LIDT) && mc_cmdex_last == `CMDEX_LGDT_LIDT_STEP_LAST;
130
+ wire cond_128 = mc_cmd == `CMD_PUSHA && mc_step < 6'd7;
131
+ wire cond_129 = mc_cmd == `CMD_PUSHA && mc_step == 6'd7;
132
+ wire cond_130 = mc_cmd == `CMD_ENTER && ((mc_step == 6'd1 && mc_decoder[28:24] == 5'd0) || (mc_step == 6'd2 && mc_decoder[28:24] == 5'd1) || (mc_step > { 1'b0, mc_decoder[28:24] } && mc_decoder[28:24] > 5'd1));
133
+ wire cond_131 = mc_cmd == `CMD_ENTER && ((mc_step == 6'd1 && mc_decoder[28:24] == 5'd1) || (mc_step == { 1'b0, mc_decoder[28:24] } && mc_decoder[28:24] > 5'd1));
134
+ wire cond_132 = mc_cmd == `CMD_ENTER && (mc_step < { 1'b0, mc_decoder[28:24] } && mc_decoder[28:24] > 5'd1);
135
+ wire cond_133 = mc_cmd == `CMD_WBINVD && mc_cmdex_last == `CMDEX_WBINVD_STEP_0;
136
+ wire cond_134 = mc_cmd == `CMD_WBINVD && mc_cmdex_last == `CMDEX_WBINVD_STEP_1;
137
+ wire cond_135 = mc_cmd == `CMD_CLTS && mc_cmdex_last == `CMDEX_CLTS_STEP_FIRST;
138
+ wire cond_136 = mc_cmd == `CMD_RET_far && mc_cmdex_last == `CMDEX_RET_far_STEP_1;
139
+ wire cond_137 = mc_cmd == `CMD_RET_far && mc_cmdex_last == `CMDEX_RET_far_STEP_2;
140
+ wire cond_138 = mc_cmd == `CMD_RET_far && mc_cmdex_last == `CMDEX_RET_far_real_STEP_3;
141
+ wire cond_139 = mc_cmd == `CMD_RET_far && mc_cmdex_last == `CMDEX_RET_far_same_STEP_3;
142
+ wire cond_140 = mc_cmd == `CMD_RET_far && mc_cmdex_last == `CMDEX_RET_far_outer_STEP_3;
143
+ wire cond_141 = mc_cmd == `CMD_RET_far && mc_cmdex_last == `CMDEX_RET_far_outer_STEP_4;
144
+ wire cond_142 = mc_cmd == `CMD_RET_far && mc_cmdex_last == `CMDEX_RET_far_outer_STEP_5;
145
+ wire cond_143 = mc_cmd == `CMD_RET_far && mc_cmdex_last == `CMDEX_RET_far_outer_STEP_6;
146
+ wire cond_144 = mc_cmd == `CMD_XCHG && mc_cmdex_last == `CMDEX_XCHG_modregrm;
147
+ wire cond_145 = mc_cmd == `CMD_INT_INTO && (mc_cmdex_last == `CMDEX_INT_INTO_INT_STEP_0 || mc_cmdex_last == `CMDEX_INT_INTO_INT3_STEP_0 || mc_cmdex_last == `CMDEX_INT_INTO_INT1_STEP_0);
148
+ wire cond_146 = mc_cmd == `CMD_INT_INTO && mc_cmdex_last == `CMDEX_INT_INTO_INTO_STEP_0 && oflag;
149
+ wire cond_147 = mc_cmd == `CMD_INT_INTO && mc_cmdex_last == `CMDEX_INT_INTO_INTO_STEP_0 && ~(oflag);
150
+ wire cond_148 = mc_cmd == `CMD_IN && (mc_cmdex_last == `CMDEX_IN_imm || mc_cmdex_last == `CMDEX_IN_dx) && ~(io_allow_check_needed);
151
+ wire cond_149 = mc_cmd == `CMD_IN && (mc_cmdex_last == `CMDEX_IN_imm || mc_cmdex_last == `CMDEX_IN_dx) && io_allow_check_needed;
152
+ wire cond_150 = mc_cmd == `CMD_IN && mc_cmdex_last == `CMDEX_IN_protected;
153
+ wire cond_151 = (mc_cmd == `CMD_LAR || mc_cmd == `CMD_LSL || mc_cmd == `CMD_VERR || mc_cmd == `CMD_VERW) && mc_cmdex_last == `CMDEX_LAR_LSL_VERR_VERW_STEP_1;
154
+ wire cond_152 = (mc_cmd == `CMD_LAR || mc_cmd == `CMD_LSL || mc_cmd == `CMD_VERR || mc_cmd == `CMD_VERW) && mc_cmdex_last == `CMDEX_LAR_LSL_VERR_VERW_STEP_2;
155
+ wire cond_153 = mc_cmd == `CMD_INS && mc_cmdex_last == `CMDEX_INS_real_1 && ~(io_allow_check_needed);
156
+ wire cond_154 = mc_cmd == `CMD_INS && mc_cmdex_last == `CMDEX_INS_real_2;
157
+ wire cond_155 = mc_cmd == `CMD_INS && mc_cmdex_last == `CMDEX_INS_real_1 && io_allow_check_needed;
158
+ wire cond_156 = mc_cmd == `CMD_INS && mc_cmdex_last == `CMDEX_INS_protected_1;
159
+ wire cond_157 = mc_cmd == `CMD_INS && mc_cmdex_last == `CMDEX_INS_protected_2;
160
+ wire cond_158 = mc_cmd == `CMD_OUTS && mc_cmdex_last == `CMDEX_OUTS_first && ~(io_allow_check_needed);
161
+ wire cond_159 = mc_cmd == `CMD_OUTS && mc_cmdex_last == `CMDEX_OUTS_first && io_allow_check_needed;
162
+ wire cond_160 = mc_cmd == `CMD_JMP && mc_cmdex_last == `CMDEX_JMP_Jv_STEP_0;
163
+ wire cond_161 = mc_cmd == `CMD_JMP && mc_cmdex_last == `CMDEX_JMP_Ev_STEP_0;
164
+ wire cond_162 = mc_cmd == `CMD_JMP && mc_cmdex_last == `CMDEX_JMP_Ep_STEP_0;
165
+ wire cond_163 = mc_cmd == `CMD_JMP && mc_cmdex_last == `CMDEX_JMP_Ap_STEP_0;
166
+ wire cond_164 = mc_cmd == `CMD_JMP && (mc_cmdex_last == `CMDEX_JMP_Ep_STEP_1 || mc_cmdex_last == `CMDEX_JMP_Ap_STEP_1) && (real_mode || v8086_mode);
167
+ wire cond_165 = mc_cmd == `CMD_JMP && mc_cmdex_last == `CMDEX_JMP_real_v8086_STEP_0;
168
+ wire cond_166 = mc_cmd == `CMD_JMP && (mc_cmdex_last == `CMDEX_JMP_Ep_STEP_1 || mc_cmdex_last == `CMDEX_JMP_Ap_STEP_1) && (protected_mode);
169
+ wire cond_167 = mc_cmd == `CMD_JMP && mc_cmdex_last == `CMDEX_JMP_protected_STEP_0;
170
+ wire cond_168 = mc_cmd == `CMD_JMP && mc_cmdex_last == `CMDEX_JMP_protected_STEP_1 && glob_descriptor[`DESC_BIT_SEG];
171
+ wire cond_169 = mc_cmd == `CMD_JMP && mc_cmdex_last == `CMDEX_JMP_protected_seg_STEP_0;
172
+ wire cond_170 = mc_cmd == `CMD_JMP && mc_cmdex_last == `CMDEX_JMP_protected_STEP_1 && glob_descriptor[`DESC_BIT_SEG] == `FALSE && (glob_descriptor[`DESC_BITS_TYPE] == `DESC_TSS_AVAIL_386 || glob_descriptor[`DESC_BITS_TYPE] == `DESC_TSS_AVAIL_286);
173
+ wire cond_171 = mc_cmd == `CMD_JMP && mc_cmdex_last == `CMDEX_JMP_task_switch_STEP_0 && glob_param_3[21:18] == 4'd0;
174
+ wire cond_172 = mc_cmd == `CMD_JMP && mc_cmdex_last == `CMDEX_JMP_task_switch_STEP_0 && glob_param_3[21:18] != 4'd0;
175
+ wire cond_173 = mc_cmd == `CMD_JMP && mc_cmdex_last == `CMDEX_JMP_protected_STEP_1 && glob_descriptor[`DESC_BIT_SEG] == `FALSE && glob_descriptor[`DESC_BITS_TYPE] == `DESC_TASK_GATE;
176
+ wire cond_174 = mc_cmd == `CMD_JMP && mc_cmdex_last == `CMDEX_JMP_task_gate_STEP_0;
177
+ wire cond_175 = mc_cmd == `CMD_JMP && mc_cmdex_last == `CMDEX_JMP_task_gate_STEP_1;
178
+ wire cond_176 = mc_cmd == `CMD_JMP && mc_cmdex_last == `CMDEX_JMP_protected_STEP_1 && glob_descriptor[`DESC_BIT_SEG] == `FALSE && (glob_descriptor[`DESC_BITS_TYPE] == `DESC_CALL_GATE_386 || glob_descriptor[`DESC_BITS_TYPE] == `DESC_CALL_GATE_286);
179
+ wire cond_177 = mc_cmd == `CMD_JMP_2 && mc_cmdex_last == `CMDEX_JMP_2_call_gate_STEP_0;
180
+ wire cond_178 = mc_cmd == `CMD_JMP_2 && mc_cmdex_last == `CMDEX_JMP_2_call_gate_STEP_1;
181
+ wire cond_179 = mc_cmd == `CMD_JMP_2 && mc_cmdex_last == `CMDEX_JMP_2_call_gate_STEP_2;
182
+ wire cond_180 = mc_cmd == `CMD_OUT && (mc_cmdex_last == `CMDEX_OUT_imm || mc_cmdex_last == `CMDEX_OUT_dx) && ~(io_allow_check_needed);
183
+ wire cond_181 = mc_cmd == `CMD_OUT && (mc_cmdex_last == `CMDEX_OUT_imm || mc_cmdex_last == `CMDEX_OUT_dx) && io_allow_check_needed;
184
+ wire cond_182 = mc_cmd == `CMD_OUT && mc_cmdex_last == `CMDEX_OUT_protected;
185
+ wire cond_183 = mc_cmd == `CMD_POPF && mc_cmdex_last == `CMDEX_POPF_STEP_0;
186
+ wire cond_184 = mc_cmd == `CMD_BOUND && mc_cmdex_last == `CMDEX_BOUND_STEP_FIRST;
187
+ wire cond_185 = mc_cmd == `CMD_task_switch && mc_cmdex_last == `CMDEX_task_switch_STEP_1 && cr0_pg;
188
+ wire cond_186 = mc_cmd == `CMD_task_switch && mc_cmdex_last == `CMDEX_task_switch_STEP_2;
189
+ wire cond_187 = mc_cmd == `CMD_task_switch && mc_cmdex_last == `CMDEX_task_switch_STEP_3 && (glob_param_1[`TASK_SWITCH_SOURCE_BITS] == `TASK_SWITCH_FROM_CALL || glob_param_1[`TASK_SWITCH_SOURCE_BITS] == `TASK_SWITCH_FROM_INT);
190
+ wire cond_188 = mc_cmd == `CMD_task_switch && mc_cmdex_last == `CMDEX_task_switch_STEP_4;
191
+ wire cond_189 = mc_cmd == `CMD_task_switch && mc_cmdex_last == `CMDEX_task_switch_STEP_5;
192
+ wire cond_190 = mc_cmd == `CMD_task_switch && mc_cmdex_last == `CMDEX_task_switch_STEP_3 && ~(glob_param_1[`TASK_SWITCH_SOURCE_BITS] == `TASK_SWITCH_FROM_CALL || glob_param_1[`TASK_SWITCH_SOURCE_BITS] == `TASK_SWITCH_FROM_INT);
193
+ wire cond_191 = mc_cmd == `CMD_task_switch && mc_cmdex_last == `CMDEX_task_switch_STEP_1 && ~(cr0_pg);
194
+ wire cond_192 = mc_cmd == `CMD_task_switch && mc_cmdex_last == `CMDEX_task_switch_STEP_6 && cr0_pg;
195
+ wire cond_193 = mc_cmd == `CMD_task_switch && mc_cmdex_last == `CMDEX_task_switch_STEP_7;
196
+ wire cond_194 = mc_cmd == `CMD_task_switch && mc_cmdex_last == `CMDEX_task_switch_STEP_8;
197
+ wire cond_195 = mc_cmd == `CMD_task_switch && mc_cmdex_last == `CMDEX_task_switch_STEP_6 && ~(cr0_pg);
198
+ wire cond_196 = mc_cmd == `CMD_task_switch && mc_cmdex_last == `CMDEX_task_switch_STEP_9;
199
+ wire cond_197 = mc_cmd == `CMD_task_switch && mc_cmdex_last == `CMDEX_task_switch_STEP_10;
200
+ wire cond_198 = mc_cmd == `CMD_task_switch_2 && mc_cmdex_last < `CMDEX_task_switch_2_STEP_13;
201
+ wire cond_199 = mc_cmd == `CMD_task_switch_2 && mc_cmdex_last == `CMDEX_task_switch_2_STEP_13;
202
+ wire cond_200 = mc_cmd == `CMD_task_switch && mc_cmdex_last == `CMDEX_task_switch_STEP_11;
203
+ wire cond_201 = mc_cmd == `CMD_task_switch && mc_cmdex_last == `CMDEX_task_switch_STEP_12;
204
+ wire cond_202 = mc_cmd == `CMD_task_switch && mc_cmdex_last == `CMDEX_task_switch_STEP_13;
205
+ wire cond_203 = mc_cmd == `CMD_task_switch && mc_cmdex_last == `CMDEX_task_switch_STEP_14;
206
+ wire cond_204 = mc_cmd == `CMD_task_switch_3;
207
+ wire cond_205 = mc_cmd == `CMD_task_switch_3 && mc_cmdex_last == `CMDEX_task_switch_3_STEP_15;
208
+ wire cond_206 = mc_cmd == `CMD_task_switch_4 && mc_cmdex_last < `CMDEX_task_switch_4_STEP_10;
209
+ wire cond_207 = mc_cmd == `CMD_SGDT || mc_cmd == `CMD_SIDT;
210
+ wire cond_208 = mc_cmd == `CMD_POPA && mc_step < 6'd7;
211
+ wire cond_209 = mc_cmd == `CMD_POPA && mc_step == 6'd7;
212
+ wire cond_210 = mc_cmd == `CMD_debug_reg && mc_cmdex_last == `CMDEX_debug_reg_MOV_load_STEP_0;
213
+ wire cond_211 =
214
+ (mc_cmd == `CMD_CALL && mc_cmdex_last == `CMDEX_CALL_Ev_Jv_STEP_1) ||
215
+ (mc_cmd == `CMD_CALL && mc_cmdex_last == `CMDEX_CALL_real_v8086_STEP_3) ||
216
+ (mc_cmd == `CMD_CALL_2 && mc_cmdex_last == `CMDEX_CALL_2_protected_seg_STEP_4) ||
217
+ (mc_cmd == `CMD_CALL_3 && mc_cmdex_last == `CMDEX_CALL_3_call_gate_more_STEP_10) ||
218
+ (mc_cmd == `CMD_CALL_2 && mc_cmdex_last == `CMDEX_CALL_2_call_gate_same_STEP_3) ||
219
+ (mc_cmd == `CMD_INVD && mc_cmdex_last == `CMDEX_INVD_STEP_2) ||
220
+ (mc_cmd == `CMD_INVLPG && mc_cmdex_last == `CMDEX_INVLPG_STEP_2) ||
221
+ (mc_cmd == `CMD_HLT && mc_cmdex_last == `CMDEX_HLT_STEP_0) ||
222
+ (mc_cmd == `CMD_SCAS && mc_cmdex_last == `CMDEX_SCAS_STEP_0) ||
223
+ (mc_cmd == `CMD_LxS && mc_cmdex_last == `CMDEX_LxS_STEP_LAST) ||
224
+ (mc_cmd == `CMD_int && mc_cmdex_last == `CMDEX_int_real_STEP_5) ||
225
+ (mc_cmd == `CMD_int_3 && mc_cmdex_last == `CMDEX_int_3_int_trap_gate_more_STEP_6) ||
226
+ (mc_cmd == `CMD_int_2 && mc_cmdex_last == `CMDEX_int_2_int_trap_gate_same_STEP_5) ||
227
+ (mc_cmd == `CMD_POP_seg && mc_cmdex_last == `CMDEX_POP_seg_STEP_LAST) ||
228
+ (mc_cmd == `CMD_IRET && mc_cmdex_last == `CMDEX_IRET_real_v86_STEP_3) ||
229
+ (mc_cmd == `CMD_IRET_2 && mc_cmdex_last == `CMDEX_IRET_2_idle) ||
230
+ (mc_cmd == `CMD_control_reg && mc_cmdex_last == `CMDEX_control_reg_LMSW_STEP_1) ||
231
+ (mc_cmd == `CMD_control_reg && mc_cmdex_last == `CMDEX_control_reg_MOV_load_STEP_1) ||
232
+ (mc_cmd == `CMD_WBINVD && mc_cmdex_last == `CMDEX_WBINVD_STEP_2) ||
233
+ (mc_cmd == `CMD_CLTS && mc_cmdex_last == `CMDEX_CLTS_STEP_LAST) ||
234
+ (mc_cmd == `CMD_RET_far && mc_cmdex_last == `CMDEX_RET_far_real_STEP_3) ||
235
+ (mc_cmd == `CMD_RET_far && mc_cmdex_last == `CMDEX_RET_far_same_STEP_4) ||
236
+ (mc_cmd == `CMD_RET_far && mc_cmdex_last == `CMDEX_RET_far_outer_STEP_7) ||
237
+ (mc_cmd == `CMD_LODS && mc_cmdex_last == `CMDEX_LODS_STEP_0) ||
238
+ (mc_cmd == `CMD_CPUID && mc_cmdex_last == `CMDEX_CPUID_STEP_LAST) ||
239
+ (mc_cmd == `CMD_IN && mc_cmdex_last == `CMDEX_IN_idle) ||
240
+ (mc_cmd == `CMD_STOS && mc_cmdex_last == `CMDEX_STOS_STEP_0) ||
241
+ (mc_cmd == `CMD_OUTS && mc_cmdex_last == `CMDEX_OUTS_protected) ||
242
+ (mc_cmd == `CMD_JMP && mc_cmdex_last == `CMDEX_JMP_Ev_Jv_STEP_1) ||
243
+ (mc_cmd == `CMD_JMP && mc_cmdex_last == `CMDEX_JMP_real_v8086_STEP_1) ||
244
+ (mc_cmd == `CMD_JMP && mc_cmdex_last == `CMDEX_JMP_protected_seg_STEP_1) ||
245
+ (mc_cmd == `CMD_JMP_2 && mc_cmdex_last == `CMDEX_JMP_2_call_gate_STEP_3) ||
246
+ (mc_cmd == `CMD_OUT && mc_cmdex_last == `CMDEX_OUT_idle) ||
247
+ (mc_cmd == `CMD_POPF && mc_cmdex_last == `CMDEX_POPF_STEP_1) ||
248
+ (mc_cmd == `CMD_MOVS && mc_cmdex_last == `CMDEX_MOVS_STEP_0) ||
249
+ (mc_cmd == `CMD_debug_reg && mc_cmdex_last == `CMDEX_debug_reg_MOV_load_STEP_1)
250
+ ;
251
+ //======================================================== saves
252
+ wire [6:0] mc_saved_command_to_reg =
253
+ (cond_8)? ( `CMD_CALL) :
254
+ (cond_53)? ( `CMD_LxS) :
255
+ (cond_54)? ( `CMD_MOV_to_seg) :
256
+ (cond_62)? ( `CMD_int) :
257
+ (cond_100)? ( `CMD_POP_seg) :
258
+ (cond_103)? ( `CMD_IRET) :
259
+ (cond_114)? ( `CMD_IRET_2) :
260
+ (cond_117)? ( `CMD_IRET_2) :
261
+ (cond_137)? ( `CMD_RET_far) :
262
+ (cond_141)? ( `CMD_RET_far) :
263
+ (cond_149)? ( `CMD_IN) :
264
+ (cond_155)? ( `CMD_INS) :
265
+ (cond_159)? ( `CMD_OUTS) :
266
+ (cond_165)? ( `CMD_JMP) :
267
+ (cond_181)? ( `CMD_OUT) :
268
+ mc_saved_command;
269
+ wire [3:0] mc_saved_cmdex_to_reg =
270
+ (cond_8)? ( `CMDEX_CALL_real_v8086_STEP_3) :
271
+ (cond_53)? ( `CMDEX_LxS_STEP_LAST) :
272
+ (cond_54)? ( `CMDEX_MOV_to_seg_LLDT_LTR_STEP_LAST) :
273
+ (cond_62)? ( `CMDEX_int_real_STEP_5) :
274
+ (cond_100)? ( `CMDEX_POP_seg_STEP_LAST) :
275
+ (cond_103)? ( `CMDEX_IRET_real_v86_STEP_3) :
276
+ (cond_114)? ( (glob_param_1[`SELECTOR_BITS_RPL] == cpl)? `CMDEX_IRET_2_protected_same_STEP_0 : `CMDEX_IRET_2_protected_outer_STEP_0) :
277
+ (cond_117)? ( `CMDEX_IRET_2_protected_outer_STEP_1) :
278
+ (cond_137)? ( (real_mode || v8086_mode)? `CMDEX_RET_far_real_STEP_3 : (glob_param_1[`SELECTOR_BITS_RPL] == cpl)? `CMDEX_RET_far_same_STEP_3 : `CMDEX_RET_far_outer_STEP_3) :
279
+ (cond_141)? ( `CMDEX_RET_far_outer_STEP_5) :
280
+ (cond_149)? ( `CMDEX_IN_protected) :
281
+ (cond_155)? ( `CMDEX_INS_protected_1) :
282
+ (cond_159)? ( `CMDEX_OUTS_protected) :
283
+ (cond_165)? ( `CMDEX_JMP_real_v8086_STEP_1) :
284
+ (cond_181)? ( `CMDEX_OUT_protected) :
285
+ mc_saved_cmdex;
286
+ //======================================================== always
287
+ always @(posedge clk) begin
288
+ if(rst_n == 1'b0) mc_saved_command <= 7'd0;
289
+ else mc_saved_command <= mc_saved_command_to_reg;
290
+ end
291
+ always @(posedge clk) begin
292
+ if(rst_n == 1'b0) mc_saved_cmdex <= 4'd0;
293
+ else mc_saved_cmdex <= mc_saved_cmdex_to_reg;
294
+ end
295
+ //======================================================== sets
296
+ assign mc_cmd_next =
297
+ (cond_1)? ( `CMD_CALL) :
298
+ (cond_2)? ( `CMD_CALL) :
299
+ (cond_3)? ( `CMD_CALL) :
300
+ (cond_4)? ( `CMD_CALL) :
301
+ (cond_5)? ( `CMD_CALL) :
302
+ (cond_6)? ( `CMD_CALL) :
303
+ (cond_7)? ( `CMD_CALL) :
304
+ (cond_8)? ( `CMD_load_seg) :
305
+ (cond_9)? ( `CMD_CALL) :
306
+ (cond_10)? ( `CMD_CALL) :
307
+ (cond_11)? ( `CMD_CALL) :
308
+ (cond_12)? ( `CMD_CALL) :
309
+ (cond_13)? ( `CMD_CALL) :
310
+ (cond_14)? ( `CMD_CALL_2) :
311
+ (cond_15)? ( `CMD_CALL_2) :
312
+ (cond_16)? ( `CMD_CALL_2) :
313
+ (cond_17)? ( `CMD_CALL_2) :
314
+ (cond_18)? ( `CMD_task_switch) :
315
+ (cond_19)? ( `CMD_CALL_2) :
316
+ (cond_20)? ( `CMD_CALL_2) :
317
+ (cond_21)? ( `CMD_task_switch) :
318
+ (cond_22)? ( `CMD_CALL_2) :
319
+ (cond_23)? ( `CMD_CALL_2) :
320
+ (cond_24)? ( `CMD_CALL_2) :
321
+ (cond_25)? ( `CMD_CALL_2) :
322
+ (cond_26)? ( `CMD_CALL_2) :
323
+ (cond_27)? ( `CMD_CALL_2) :
324
+ (cond_28)? ( `CMD_CALL_2) :
325
+ (cond_29)? ( `CMD_CALL_3) :
326
+ (cond_30)? ( `CMD_CALL_3) :
327
+ (cond_31)? ( `CMD_CALL_3) :
328
+ (cond_32)? ( `CMD_CALL_3) :
329
+ (cond_33)? ( `CMD_CALL_3) :
330
+ (cond_34)? ( `CMD_CALL_3) :
331
+ (cond_35)? ( `CMD_CALL_3) :
332
+ (cond_36)? ( `CMD_CALL_3) :
333
+ (cond_37)? ( `CMD_CALL_3) :
334
+ (cond_38)? ( `CMD_CALL_3) :
335
+ (cond_39)? ( `CMD_CALL_2) :
336
+ (cond_40)? ( `CMD_CALL_2) :
337
+ (cond_41)? ( `CMD_CALL_2) :
338
+ (cond_42)? ( `CMD_CALL_2) :
339
+ (cond_43)? ( `CMD_INVD) :
340
+ (cond_44)? ( `CMD_INVD) :
341
+ (cond_45)? ( `CMD_INVLPG) :
342
+ (cond_46)? ( `CMD_INVLPG) :
343
+ (cond_47)? ( `CMD_io_allow) :
344
+ (cond_48)? ( mc_saved_command) :
345
+ (cond_51)? ( `CMD_LxS) :
346
+ (cond_52)? ( `CMD_LxS) :
347
+ (cond_53)? ( `CMD_load_seg) :
348
+ (cond_54)? ( `CMD_load_seg) :
349
+ (cond_55)? ( `CMD_MOV_to_seg) :
350
+ (cond_56)? ( `CMD_int) :
351
+ (cond_57)? ( `CMD_int) :
352
+ (cond_58)? ( `CMD_int) :
353
+ (cond_59)? ( `CMD_int) :
354
+ (cond_60)? ( `CMD_int) :
355
+ (cond_61)? ( `CMD_int) :
356
+ (cond_62)? ( `CMD_load_seg) :
357
+ (cond_63)? ( `CMD_int) :
358
+ (cond_64)? ( `CMD_int) :
359
+ (cond_65)? ( `CMD_int) :
360
+ (cond_66)? ( `CMD_int) :
361
+ (cond_67)? ( `CMD_int) :
362
+ (cond_68)? ( `CMD_task_switch) :
363
+ (cond_69)? ( `CMD_int) :
364
+ (cond_70)? ( `CMD_int) :
365
+ (cond_71)? ( `CMD_int) :
366
+ (cond_72)? ( `CMD_int_2) :
367
+ (cond_73)? ( `CMD_int_2) :
368
+ (cond_74)? ( `CMD_int_2) :
369
+ (cond_75)? ( `CMD_int_2) :
370
+ (cond_76)? ( `CMD_int_2) :
371
+ (cond_77)? ( `CMD_int_2) :
372
+ (cond_78)? ( `CMD_int_2) :
373
+ (cond_79)? ( `CMD_int_2) :
374
+ (cond_80)? ( `CMD_int_2) :
375
+ (cond_81)? ( `CMD_int_2) :
376
+ (cond_82)? ( `CMD_int_2) :
377
+ (cond_83)? ( `CMD_int_3) :
378
+ (cond_84)? ( `CMD_int_3) :
379
+ (cond_85)? ( `CMD_int_3) :
380
+ (cond_86)? ( `CMD_int_3) :
381
+ (cond_87)? ( `CMD_int_3) :
382
+ (cond_88)? ( `CMD_int_3) :
383
+ (cond_89)? ( `CMD_int_3) :
384
+ (cond_90)? ( `CMD_int_3) :
385
+ (cond_91)? ( `CMD_int_2) :
386
+ (cond_92)? ( `CMD_int_2) :
387
+ (cond_93)? ( `CMD_int_2) :
388
+ (cond_94)? ( `CMD_int_2) :
389
+ (cond_95)? ( `CMD_int_2) :
390
+ (cond_96)? ( `CMD_int_2) :
391
+ (cond_97)? ( `CMD_int_2) :
392
+ (cond_98)? ( mc_saved_command) :
393
+ (cond_99)? ( `CMD_load_seg) :
394
+ (cond_100)? ( `CMD_load_seg) :
395
+ (cond_101)? ( `CMD_IRET) :
396
+ (cond_102)? ( `CMD_IRET) :
397
+ (cond_103)? ( `CMD_load_seg) :
398
+ (cond_104)? ( `CMD_IRET) :
399
+ (cond_105)? ( `CMD_IRET) :
400
+ (cond_106)? ( `CMD_task_switch) :
401
+ (cond_107)? ( `CMD_IRET) :
402
+ (cond_108)? ( `CMD_IRET) :
403
+ (cond_109)? ( `CMD_IRET) :
404
+ (cond_110)? ( `CMD_IRET) :
405
+ (cond_111)? ( `CMD_IRET) :
406
+ (cond_112)? ( `CMD_IRET_2) :
407
+ (cond_113)? ( `CMD_IRET_2) :
408
+ (cond_114)? ( `CMD_load_seg) :
409
+ (cond_115)? ( `CMD_IRET_2) :
410
+ (cond_116)? ( `CMD_IRET_2) :
411
+ (cond_117)? ( `CMD_load_seg) :
412
+ (cond_118)? ( `CMD_IRET_2) :
413
+ (cond_119)? ( `CMD_IRET_2) :
414
+ (cond_121)? ( `CMD_CMPS) :
415
+ (cond_122)? ( `CMD_CMPS) :
416
+ (cond_123)? ( `CMD_control_reg) :
417
+ (cond_124)? ( `CMD_control_reg) :
418
+ (cond_125)? ( mc_cmd) :
419
+ (cond_126)? ( mc_cmd) :
420
+ (cond_127)? ( mc_cmd) :
421
+ (cond_128)? ( mc_cmd) :
422
+ (cond_131)? ( `CMD_ENTER) :
423
+ (cond_132)? ( `CMD_ENTER) :
424
+ (cond_133)? ( `CMD_WBINVD) :
425
+ (cond_134)? ( `CMD_WBINVD) :
426
+ (cond_135)? ( `CMD_CLTS) :
427
+ (cond_136)? ( `CMD_RET_far) :
428
+ (cond_137)? ( `CMD_load_seg) :
429
+ (cond_138)? ( `CMD_RET_far) :
430
+ (cond_139)? ( `CMD_RET_far) :
431
+ (cond_140)? ( `CMD_RET_far) :
432
+ (cond_141)? ( `CMD_load_seg) :
433
+ (cond_142)? ( `CMD_RET_far) :
434
+ (cond_143)? ( `CMD_RET_far) :
435
+ (cond_145)? ( `CMD_int) :
436
+ (cond_146)? ( `CMD_int) :
437
+ (cond_147)? ( `CMD_INT_INTO) :
438
+ (cond_148)? ( `CMD_IN) :
439
+ (cond_149)? ( `CMD_io_allow) :
440
+ (cond_150)? ( `CMD_IN) :
441
+ (cond_151)? ( mc_cmd) :
442
+ (cond_153)? ( `CMD_INS) :
443
+ (cond_154)? ( `CMD_INS) :
444
+ (cond_155)? ( `CMD_io_allow) :
445
+ (cond_156)? ( `CMD_INS) :
446
+ (cond_157)? ( `CMD_INS) :
447
+ (cond_158)? ( `CMD_OUTS) :
448
+ (cond_159)? ( `CMD_io_allow) :
449
+ (cond_160)? ( `CMD_JMP) :
450
+ (cond_161)? ( `CMD_JMP) :
451
+ (cond_162)? ( `CMD_JMP) :
452
+ (cond_163)? ( `CMD_JMP) :
453
+ (cond_164)? ( `CMD_JMP) :
454
+ (cond_165)? ( `CMD_load_seg) :
455
+ (cond_166)? ( `CMD_JMP) :
456
+ (cond_167)? ( `CMD_JMP) :
457
+ (cond_168)? ( `CMD_JMP) :
458
+ (cond_169)? ( `CMD_JMP) :
459
+ (cond_170)? ( `CMD_JMP) :
460
+ (cond_171)? ( `CMD_JMP) :
461
+ (cond_172)? ( `CMD_task_switch) :
462
+ (cond_173)? ( `CMD_JMP) :
463
+ (cond_174)? ( `CMD_JMP) :
464
+ (cond_175)? ( `CMD_task_switch) :
465
+ (cond_176)? ( `CMD_JMP_2) :
466
+ (cond_177)? ( `CMD_JMP_2) :
467
+ (cond_178)? ( `CMD_JMP_2) :
468
+ (cond_179)? ( `CMD_JMP_2) :
469
+ (cond_180)? ( `CMD_OUT) :
470
+ (cond_181)? ( `CMD_io_allow) :
471
+ (cond_182)? ( `CMD_OUT) :
472
+ (cond_183)? ( `CMD_POPF) :
473
+ (cond_185)? ( `CMD_task_switch) :
474
+ (cond_186)? ( `CMD_task_switch) :
475
+ (cond_187)? ( `CMD_task_switch) :
476
+ (cond_188)? ( `CMD_task_switch) :
477
+ (cond_189)? ( `CMD_task_switch) :
478
+ (cond_190)? ( `CMD_task_switch) :
479
+ (cond_191)? ( `CMD_task_switch) :
480
+ (cond_192)? ( `CMD_task_switch) :
481
+ (cond_193)? ( `CMD_task_switch) :
482
+ (cond_194)? ( `CMD_task_switch) :
483
+ (cond_195)? ( `CMD_task_switch) :
484
+ (cond_196)? ( `CMD_task_switch) :
485
+ (cond_197)? ( `CMD_task_switch_2) :
486
+ (cond_198)? ( mc_cmd) :
487
+ (cond_199)? ( `CMD_task_switch) :
488
+ (cond_200)? ( `CMD_task_switch) :
489
+ (cond_201)? ( `CMD_task_switch) :
490
+ (cond_202)? ( `CMD_task_switch) :
491
+ (cond_203)? ( `CMD_task_switch_3) :
492
+ (cond_204)? ( mc_cmd) :
493
+ (cond_205)? ( `CMD_task_switch_4) :
494
+ (cond_206)? ( mc_cmd) :
495
+ (cond_208)? ( mc_cmd) :
496
+ (cond_210)? ( `CMD_debug_reg) :
497
+ (cond_211)? ( mc_cmd) :
498
+ 7'd0;
499
+ assign mc_cmdex_current =
500
+ (cond_0)? ( `CMDEX_XADD_LAST) :
501
+ (cond_1)? ( `CMDEX_CALL_Ev_Jv_STEP_1) :
502
+ (cond_2)? ( `CMDEX_CALL_Ev_Jv_STEP_1) :
503
+ (cond_3)? ( `CMDEX_CALL_Ep_STEP_1) :
504
+ (cond_4)? ( `CMDEX_CALL_Ap_STEP_1) :
505
+ (cond_5)? ( `CMDEX_CALL_real_v8086_STEP_0) :
506
+ (cond_6)? ( `CMDEX_CALL_real_v8086_STEP_1) :
507
+ (cond_7)? ( `CMDEX_CALL_real_v8086_STEP_2) :
508
+ (cond_8)? ( `CMDEX_load_seg_STEP_1) :
509
+ (cond_9)? ( `CMDEX_CALL_protected_STEP_0) :
510
+ (cond_10)? ( `CMDEX_CALL_protected_STEP_1) :
511
+ (cond_11)? ( `CMDEX_CALL_protected_seg_STEP_0) :
512
+ (cond_12)? ( `CMDEX_CALL_protected_seg_STEP_1) :
513
+ (cond_13)? ( `CMDEX_CALL_protected_seg_STEP_2) :
514
+ (cond_14)? ( `CMDEX_CALL_2_protected_seg_STEP_3) :
515
+ (cond_15)? ( `CMDEX_CALL_2_protected_seg_STEP_4) :
516
+ (cond_16)? ( `CMDEX_CALL_2_task_switch_STEP_0) :
517
+ (cond_17)? ( `CMDEX_CALL_2_task_switch_STEP_0) :
518
+ (cond_18)? ( `CMDEX_task_switch_STEP_1) :
519
+ (cond_19)? ( `CMDEX_CALL_2_task_gate_STEP_0) :
520
+ (cond_20)? ( `CMDEX_CALL_2_task_gate_STEP_1) :
521
+ (cond_21)? ( `CMDEX_task_switch_STEP_1) :
522
+ (cond_22)? ( `CMDEX_CALL_2_call_gate_STEP_0) :
523
+ (cond_23)? ( `CMDEX_CALL_2_call_gate_STEP_1) :
524
+ (cond_24)? ( `CMDEX_CALL_2_call_gate_STEP_2) :
525
+ (cond_25)? ( `CMDEX_CALL_2_call_gate_more_STEP_0) :
526
+ (cond_26)? ( `CMDEX_CALL_2_call_gate_more_STEP_1) :
527
+ (cond_27)? ( `CMDEX_CALL_2_call_gate_more_STEP_2) :
528
+ (cond_28)? ( `CMDEX_CALL_2_call_gate_more_STEP_3) :
529
+ (cond_29)? ( `CMDEX_CALL_3_call_gate_more_STEP_4) :
530
+ (cond_30)? ( `CMDEX_CALL_3_call_gate_more_STEP_6) :
531
+ (cond_31)? ( `CMDEX_CALL_3_call_gate_more_STEP_5) :
532
+ (cond_32)? ( `CMDEX_CALL_3_call_gate_more_STEP_6) :
533
+ (cond_33)? ( `CMDEX_CALL_3_call_gate_more_STEP_5) :
534
+ (cond_34)? ( `CMDEX_CALL_3_call_gate_more_STEP_6) :
535
+ (cond_35)? ( `CMDEX_CALL_3_call_gate_more_STEP_7) :
536
+ (cond_36)? ( `CMDEX_CALL_3_call_gate_more_STEP_8) :
537
+ (cond_37)? ( `CMDEX_CALL_3_call_gate_more_STEP_9) :
538
+ (cond_38)? ( `CMDEX_CALL_3_call_gate_more_STEP_10) :
539
+ (cond_39)? ( `CMDEX_CALL_2_call_gate_same_STEP_0) :
540
+ (cond_40)? ( `CMDEX_CALL_2_call_gate_same_STEP_1) :
541
+ (cond_41)? ( `CMDEX_CALL_2_call_gate_same_STEP_2) :
542
+ (cond_42)? ( `CMDEX_CALL_2_call_gate_same_STEP_3) :
543
+ (cond_43)? ( `CMDEX_INVD_STEP_1) :
544
+ (cond_44)? ( `CMDEX_INVD_STEP_2) :
545
+ (cond_45)? ( `CMDEX_INVLPG_STEP_1) :
546
+ (cond_46)? ( `CMDEX_INVLPG_STEP_2) :
547
+ (cond_47)? ( `CMDEX_io_allow_2) :
548
+ (cond_48)? ( mc_saved_cmdex) :
549
+ (cond_49)? ( `CMDEX_RET_near_LAST) :
550
+ (cond_50)? ( `CMDEX_RET_near_LAST) :
551
+ (cond_51)? ( `CMDEX_LxS_STEP_2) :
552
+ (cond_52)? ( `CMDEX_LxS_STEP_3) :
553
+ (cond_53)? ( `CMDEX_load_seg_STEP_1) :
554
+ (cond_54)? ( `CMDEX_load_seg_STEP_1) :
555
+ (cond_55)? ( `CMDEX_MOV_to_seg_LLDT_LTR_STEP_LAST) :
556
+ (cond_56)? ( `CMDEX_int_STEP_1) :
557
+ (cond_57)? ( `CMDEX_int_real_STEP_0) :
558
+ (cond_58)? ( `CMDEX_int_real_STEP_1) :
559
+ (cond_59)? ( `CMDEX_int_real_STEP_2) :
560
+ (cond_60)? ( `CMDEX_int_real_STEP_3) :
561
+ (cond_61)? ( `CMDEX_int_real_STEP_4) :
562
+ (cond_62)? ( `CMDEX_load_seg_STEP_1) :
563
+ (cond_63)? ( `CMDEX_int_protected_STEP_0) :
564
+ (cond_64)? ( `CMDEX_int_protected_STEP_1) :
565
+ (cond_65)? ( `CMDEX_int_protected_STEP_2) :
566
+ (cond_66)? ( `CMDEX_int_task_gate_STEP_0) :
567
+ (cond_67)? ( `CMDEX_int_task_gate_STEP_1) :
568
+ (cond_68)? ( `CMDEX_task_switch_STEP_1) :
569
+ (cond_69)? ( `CMDEX_int_int_trap_gate_STEP_0) :
570
+ (cond_70)? ( `CMDEX_int_int_trap_gate_STEP_1) :
571
+ (cond_71)? ( `CMDEX_int_int_trap_gate_STEP_2) :
572
+ (cond_72)? ( `CMDEX_int_2_int_trap_gate_more_STEP_0) :
573
+ (cond_73)? ( `CMDEX_int_2_int_trap_gate_more_STEP_1) :
574
+ (cond_74)? ( `CMDEX_int_2_int_trap_gate_more_STEP_2) :
575
+ (cond_75)? ( `CMDEX_int_2_int_trap_gate_more_STEP_3) :
576
+ (cond_76)? ( `CMDEX_int_2_int_trap_gate_more_STEP_4) :
577
+ (cond_77)? ( `CMDEX_int_2_int_trap_gate_more_STEP_5) :
578
+ (cond_78)? ( `CMDEX_int_2_int_trap_gate_more_STEP_6) :
579
+ (cond_79)? ( `CMDEX_int_2_int_trap_gate_more_STEP_7) :
580
+ (cond_80)? ( `CMDEX_int_2_int_trap_gate_more_STEP_8) :
581
+ (cond_81)? ( `CMDEX_int_2_int_trap_gate_more_STEP_8) :
582
+ (cond_82)? ( `CMDEX_int_2_int_trap_gate_more_STEP_9) :
583
+ (cond_83)? ( `CMDEX_int_3_int_trap_gate_more_STEP_0) :
584
+ (cond_84)? ( `CMDEX_int_3_int_trap_gate_more_STEP_1) :
585
+ (cond_85)? ( `CMDEX_int_3_int_trap_gate_more_STEP_2) :
586
+ (cond_86)? ( `CMDEX_int_3_int_trap_gate_more_STEP_3) :
587
+ (cond_87)? ( `CMDEX_int_3_int_trap_gate_more_STEP_4) :
588
+ (cond_88)? ( `CMDEX_int_3_int_trap_gate_more_STEP_4) :
589
+ (cond_89)? ( `CMDEX_int_3_int_trap_gate_more_STEP_5) :
590
+ (cond_90)? ( `CMDEX_int_3_int_trap_gate_more_STEP_6) :
591
+ (cond_91)? ( `CMDEX_int_2_int_trap_gate_same_STEP_0) :
592
+ (cond_92)? ( `CMDEX_int_2_int_trap_gate_same_STEP_1) :
593
+ (cond_93)? ( `CMDEX_int_2_int_trap_gate_same_STEP_2) :
594
+ (cond_94)? ( `CMDEX_int_2_int_trap_gate_same_STEP_3) :
595
+ (cond_95)? ( `CMDEX_int_2_int_trap_gate_same_STEP_4) :
596
+ (cond_96)? ( `CMDEX_int_2_int_trap_gate_same_STEP_4) :
597
+ (cond_97)? ( `CMDEX_int_2_int_trap_gate_same_STEP_5) :
598
+ (cond_98)? ( mc_saved_cmdex) :
599
+ (cond_99)? ( `CMDEX_load_seg_STEP_2) :
600
+ (cond_100)? ( `CMDEX_load_seg_STEP_1) :
601
+ (cond_101)? ( `CMDEX_IRET_real_v86_STEP_1) :
602
+ (cond_102)? ( `CMDEX_IRET_real_v86_STEP_2) :
603
+ (cond_103)? ( `CMDEX_load_seg_STEP_1) :
604
+ (cond_104)? ( `CMDEX_IRET_task_switch_STEP_0) :
605
+ (cond_105)? ( `CMDEX_IRET_task_switch_STEP_1) :
606
+ (cond_106)? ( `CMDEX_task_switch_STEP_1) :
607
+ (cond_107)? ( `CMDEX_IRET_protected_STEP_1) :
608
+ (cond_108)? ( `CMDEX_IRET_protected_STEP_2) :
609
+ (cond_109)? ( `CMDEX_IRET_protected_STEP_3) :
610
+ (cond_110)? ( `CMDEX_IRET_protected_to_v86_STEP_0) :
611
+ (cond_111)? ( mc_cmdex_last + 4'd1) :
612
+ (cond_112)? ( `CMDEX_IRET_2_protected_to_v86_STEP_6) :
613
+ (cond_113)? ( `CMDEX_IRET_2_idle) :
614
+ (cond_114)? ( `CMDEX_load_seg_STEP_1) :
615
+ (cond_115)? ( `CMDEX_IRET_2_protected_same_STEP_1) :
616
+ (cond_116)? ( `CMDEX_IRET_2_idle) :
617
+ (cond_117)? ( `CMDEX_load_seg_STEP_1) :
618
+ (cond_118)? ( mc_cmdex_last + 4'd1) :
619
+ (cond_119)? ( `CMDEX_IRET_2_idle) :
620
+ (cond_120)? ( `CMDEX_POP_modregrm_STEP_1) :
621
+ (cond_121)? ( `CMDEX_CMPS_LAST) :
622
+ (cond_122)? ( `CMDEX_CMPS_FIRST) :
623
+ (cond_123)? ( `CMDEX_control_reg_LMSW_STEP_1) :
624
+ (cond_124)? ( `CMDEX_control_reg_MOV_load_STEP_1) :
625
+ (cond_125)? ( `CMDEX_LGDT_LIDT_STEP_2) :
626
+ (cond_126)? ( `CMDEX_LGDT_LIDT_STEP_LAST) :
627
+ (cond_127)? ( `CMDEX_LGDT_LIDT_STEP_LAST) :
628
+ (cond_128)? ( mc_step[3:0]) :
629
+ (cond_129)? ( `CMDEX_PUSHA_STEP_7) :
630
+ (cond_130)? ( `CMDEX_ENTER_LAST) :
631
+ (cond_131)? ( `CMDEX_ENTER_PUSH) :
632
+ (cond_132)? ( `CMDEX_ENTER_LOOP) :
633
+ (cond_133)? ( `CMDEX_WBINVD_STEP_1) :
634
+ (cond_134)? ( `CMDEX_WBINVD_STEP_2) :
635
+ (cond_135)? ( `CMDEX_CLTS_STEP_LAST) :
636
+ (cond_136)? ( `CMDEX_RET_far_STEP_2) :
637
+ (cond_137)? ( `CMDEX_load_seg_STEP_1) :
638
+ (cond_138)? ( `CMDEX_RET_far_real_STEP_3) :
639
+ (cond_139)? ( `CMDEX_RET_far_same_STEP_4) :
640
+ (cond_140)? ( `CMDEX_RET_far_outer_STEP_4) :
641
+ (cond_141)? ( `CMDEX_load_seg_STEP_1) :
642
+ (cond_142)? ( `CMDEX_RET_far_outer_STEP_6) :
643
+ (cond_143)? ( `CMDEX_RET_far_outer_STEP_7) :
644
+ (cond_144)? ( `CMDEX_XCHG_modregrm_LAST) :
645
+ (cond_145)? ( `CMDEX_int_STEP_0) :
646
+ (cond_146)? ( `CMDEX_int_STEP_0) :
647
+ (cond_147)? ( `CMDEX_INT_INTO_INTO_STEP_0) :
648
+ (cond_148)? ( `CMDEX_IN_idle) :
649
+ (cond_149)? ( `CMDEX_io_allow_1) :
650
+ (cond_150)? ( `CMDEX_IN_idle) :
651
+ (cond_151)? ( `CMDEX_LAR_LSL_VERR_VERW_STEP_2) :
652
+ (cond_152)? ( `CMDEX_LAR_LSL_VERR_VERW_STEP_LAST) :
653
+ (cond_153)? ( `CMDEX_INS_real_2) :
654
+ (cond_154)? ( `CMDEX_INS_real_1) :
655
+ (cond_155)? ( `CMDEX_io_allow_1) :
656
+ (cond_156)? ( `CMDEX_INS_protected_2) :
657
+ (cond_157)? ( `CMDEX_INS_protected_1) :
658
+ (cond_158)? ( `CMDEX_OUTS_first) :
659
+ (cond_159)? ( `CMDEX_io_allow_1) :
660
+ (cond_160)? ( `CMDEX_JMP_Ev_Jv_STEP_1) :
661
+ (cond_161)? ( `CMDEX_JMP_Ev_Jv_STEP_1) :
662
+ (cond_162)? ( `CMDEX_JMP_Ep_STEP_1) :
663
+ (cond_163)? ( `CMDEX_JMP_Ap_STEP_1) :
664
+ (cond_164)? ( `CMDEX_JMP_real_v8086_STEP_0) :
665
+ (cond_165)? ( `CMDEX_load_seg_STEP_1) :
666
+ (cond_166)? ( `CMDEX_JMP_protected_STEP_0) :
667
+ (cond_167)? ( `CMDEX_JMP_protected_STEP_1) :
668
+ (cond_168)? ( `CMDEX_JMP_protected_seg_STEP_0) :
669
+ (cond_169)? ( `CMDEX_JMP_protected_seg_STEP_1) :
670
+ (cond_170)? ( `CMDEX_JMP_task_switch_STEP_0) :
671
+ (cond_171)? ( `CMDEX_JMP_task_switch_STEP_0) :
672
+ (cond_172)? ( `CMDEX_task_switch_STEP_1) :
673
+ (cond_173)? ( `CMDEX_JMP_task_gate_STEP_0) :
674
+ (cond_174)? ( `CMDEX_JMP_task_gate_STEP_1) :
675
+ (cond_175)? ( `CMDEX_task_switch_STEP_1) :
676
+ (cond_176)? ( `CMDEX_JMP_2_call_gate_STEP_0) :
677
+ (cond_177)? ( `CMDEX_JMP_2_call_gate_STEP_1) :
678
+ (cond_178)? ( `CMDEX_JMP_2_call_gate_STEP_2) :
679
+ (cond_179)? ( `CMDEX_JMP_2_call_gate_STEP_3) :
680
+ (cond_180)? ( `CMDEX_OUT_idle) :
681
+ (cond_181)? ( `CMDEX_io_allow_1) :
682
+ (cond_182)? ( `CMDEX_OUT_idle) :
683
+ (cond_183)? ( `CMDEX_POPF_STEP_1) :
684
+ (cond_184)? ( `CMDEX_BOUND_STEP_LAST) :
685
+ (cond_185)? ( `CMDEX_task_switch_STEP_2) :
686
+ (cond_186)? ( `CMDEX_task_switch_STEP_3) :
687
+ (cond_187)? ( `CMDEX_task_switch_STEP_4) :
688
+ (cond_188)? ( `CMDEX_task_switch_STEP_5) :
689
+ (cond_189)? ( `CMDEX_task_switch_STEP_6) :
690
+ (cond_190)? ( `CMDEX_task_switch_STEP_6) :
691
+ (cond_191)? ( `CMDEX_task_switch_STEP_6) :
692
+ (cond_192)? ( `CMDEX_task_switch_STEP_7) :
693
+ (cond_193)? ( `CMDEX_task_switch_STEP_8) :
694
+ (cond_194)? ( `CMDEX_task_switch_STEP_9) :
695
+ (cond_195)? ( `CMDEX_task_switch_STEP_9) :
696
+ (cond_196)? ( `CMDEX_task_switch_STEP_10) :
697
+ (cond_197)? ( `CMDEX_task_switch_2_STEP_0) :
698
+ (cond_198)? ( mc_cmdex_last + 4'd1) :
699
+ (cond_199)? ( `CMDEX_task_switch_STEP_11) :
700
+ (cond_200)? ( `CMDEX_task_switch_STEP_12) :
701
+ (cond_201)? ( `CMDEX_task_switch_STEP_13) :
702
+ (cond_202)? ( `CMDEX_task_switch_STEP_14) :
703
+ (cond_203)? ( `CMDEX_task_switch_3_STEP_0) :
704
+ (cond_204)? ( mc_cmdex_last + 4'd1) :
705
+ (cond_205)? ( `CMDEX_task_switch_4_STEP_0) :
706
+ (cond_206)? ( mc_cmdex_last + 4'd1) :
707
+ (cond_207)? ( `CMDEX_SGDT_SIDT_STEP_2) :
708
+ (cond_208)? ( mc_step[3:0]) :
709
+ (cond_209)? ( `CMDEX_POPA_STEP_7) :
710
+ (cond_210)? ( `CMDEX_debug_reg_MOV_load_STEP_1) :
711
+ (cond_211)? ( mc_cmdex_last) :
712
+ 4'd0;
713
+ assign mc_cmd_current =
714
+ (cond_0)? ( `CMD_XADD) :
715
+ (cond_1)? ( `CMD_CALL) :
716
+ (cond_2)? ( `CMD_CALL) :
717
+ (cond_3)? ( `CMD_CALL) :
718
+ (cond_4)? ( `CMD_CALL) :
719
+ (cond_5)? ( `CMD_CALL) :
720
+ (cond_6)? ( `CMD_CALL) :
721
+ (cond_7)? ( `CMD_CALL) :
722
+ (cond_8)? ( `CMD_load_seg) :
723
+ (cond_9)? ( `CMD_CALL) :
724
+ (cond_10)? ( `CMD_CALL) :
725
+ (cond_11)? ( `CMD_CALL) :
726
+ (cond_12)? ( `CMD_CALL) :
727
+ (cond_13)? ( `CMD_CALL) :
728
+ (cond_14)? ( `CMD_CALL_2) :
729
+ (cond_15)? ( `CMD_CALL_2) :
730
+ (cond_16)? ( `CMD_CALL_2) :
731
+ (cond_17)? ( `CMD_CALL_2) :
732
+ (cond_18)? ( `CMD_task_switch) :
733
+ (cond_19)? ( `CMD_CALL_2) :
734
+ (cond_20)? ( `CMD_CALL_2) :
735
+ (cond_21)? ( `CMD_task_switch) :
736
+ (cond_22)? ( `CMD_CALL_2) :
737
+ (cond_23)? ( `CMD_CALL_2) :
738
+ (cond_24)? ( `CMD_CALL_2) :
739
+ (cond_25)? ( `CMD_CALL_2) :
740
+ (cond_26)? ( `CMD_CALL_2) :
741
+ (cond_27)? ( `CMD_CALL_2) :
742
+ (cond_28)? ( `CMD_CALL_2) :
743
+ (cond_29)? ( `CMD_CALL_3) :
744
+ (cond_30)? ( `CMD_CALL_3) :
745
+ (cond_31)? ( `CMD_CALL_3) :
746
+ (cond_32)? ( `CMD_CALL_3) :
747
+ (cond_33)? ( `CMD_CALL_3) :
748
+ (cond_34)? ( `CMD_CALL_3) :
749
+ (cond_35)? ( `CMD_CALL_3) :
750
+ (cond_36)? ( `CMD_CALL_3) :
751
+ (cond_37)? ( `CMD_CALL_3) :
752
+ (cond_38)? ( `CMD_CALL_3) :
753
+ (cond_39)? ( `CMD_CALL_2) :
754
+ (cond_40)? ( `CMD_CALL_2) :
755
+ (cond_41)? ( `CMD_CALL_2) :
756
+ (cond_42)? ( `CMD_CALL_2) :
757
+ (cond_43)? ( `CMD_INVD) :
758
+ (cond_44)? ( `CMD_INVD) :
759
+ (cond_45)? ( `CMD_INVLPG) :
760
+ (cond_46)? ( `CMD_INVLPG) :
761
+ (cond_47)? ( `CMD_io_allow) :
762
+ (cond_48)? ( mc_saved_command) :
763
+ (cond_49)? ( `CMD_RET_near) :
764
+ (cond_50)? ( `CMD_RET_near) :
765
+ (cond_51)? ( `CMD_LxS) :
766
+ (cond_52)? ( `CMD_LxS) :
767
+ (cond_53)? ( `CMD_load_seg) :
768
+ (cond_54)? ( `CMD_load_seg) :
769
+ (cond_55)? ( `CMD_MOV_to_seg) :
770
+ (cond_56)? ( `CMD_int) :
771
+ (cond_57)? ( `CMD_int) :
772
+ (cond_58)? ( `CMD_int) :
773
+ (cond_59)? ( `CMD_int) :
774
+ (cond_60)? ( `CMD_int) :
775
+ (cond_61)? ( `CMD_int) :
776
+ (cond_62)? ( `CMD_load_seg) :
777
+ (cond_63)? ( `CMD_int) :
778
+ (cond_64)? ( `CMD_int) :
779
+ (cond_65)? ( `CMD_int) :
780
+ (cond_66)? ( `CMD_int) :
781
+ (cond_67)? ( `CMD_int) :
782
+ (cond_68)? ( `CMD_task_switch) :
783
+ (cond_69)? ( `CMD_int) :
784
+ (cond_70)? ( `CMD_int) :
785
+ (cond_71)? ( `CMD_int) :
786
+ (cond_72)? ( `CMD_int_2) :
787
+ (cond_73)? ( `CMD_int_2) :
788
+ (cond_74)? ( `CMD_int_2) :
789
+ (cond_75)? ( `CMD_int_2) :
790
+ (cond_76)? ( `CMD_int_2) :
791
+ (cond_77)? ( `CMD_int_2) :
792
+ (cond_78)? ( `CMD_int_2) :
793
+ (cond_79)? ( `CMD_int_2) :
794
+ (cond_80)? ( `CMD_int_2) :
795
+ (cond_81)? ( `CMD_int_2) :
796
+ (cond_82)? ( `CMD_int_2) :
797
+ (cond_83)? ( `CMD_int_3) :
798
+ (cond_84)? ( `CMD_int_3) :
799
+ (cond_85)? ( `CMD_int_3) :
800
+ (cond_86)? ( `CMD_int_3) :
801
+ (cond_87)? ( `CMD_int_3) :
802
+ (cond_88)? ( `CMD_int_3) :
803
+ (cond_89)? ( `CMD_int_3) :
804
+ (cond_90)? ( `CMD_int_3) :
805
+ (cond_91)? ( `CMD_int_2) :
806
+ (cond_92)? ( `CMD_int_2) :
807
+ (cond_93)? ( `CMD_int_2) :
808
+ (cond_94)? ( `CMD_int_2) :
809
+ (cond_95)? ( `CMD_int_2) :
810
+ (cond_96)? ( `CMD_int_2) :
811
+ (cond_97)? ( `CMD_int_2) :
812
+ (cond_98)? ( mc_saved_command) :
813
+ (cond_99)? ( `CMD_load_seg) :
814
+ (cond_100)? ( `CMD_load_seg) :
815
+ (cond_101)? ( `CMD_IRET) :
816
+ (cond_102)? ( `CMD_IRET) :
817
+ (cond_103)? ( `CMD_load_seg) :
818
+ (cond_104)? ( `CMD_IRET) :
819
+ (cond_105)? ( `CMD_IRET) :
820
+ (cond_106)? ( `CMD_task_switch) :
821
+ (cond_107)? ( `CMD_IRET) :
822
+ (cond_108)? ( `CMD_IRET) :
823
+ (cond_109)? ( `CMD_IRET) :
824
+ (cond_110)? ( `CMD_IRET) :
825
+ (cond_111)? ( `CMD_IRET) :
826
+ (cond_112)? ( `CMD_IRET_2) :
827
+ (cond_113)? ( `CMD_IRET_2) :
828
+ (cond_114)? ( `CMD_load_seg) :
829
+ (cond_115)? ( `CMD_IRET_2) :
830
+ (cond_116)? ( `CMD_IRET_2) :
831
+ (cond_117)? ( `CMD_load_seg) :
832
+ (cond_118)? ( `CMD_IRET_2) :
833
+ (cond_119)? ( `CMD_IRET_2) :
834
+ (cond_120)? ( `CMD_POP) :
835
+ (cond_121)? ( `CMD_CMPS) :
836
+ (cond_122)? ( `CMD_CMPS) :
837
+ (cond_123)? ( `CMD_control_reg) :
838
+ (cond_124)? ( `CMD_control_reg) :
839
+ (cond_125)? ( mc_cmd) :
840
+ (cond_126)? ( mc_cmd) :
841
+ (cond_127)? ( mc_cmd) :
842
+ (cond_128)? ( mc_cmd) :
843
+ (cond_129)? ( `CMD_PUSHA) :
844
+ (cond_130)? ( `CMD_ENTER) :
845
+ (cond_131)? ( `CMD_ENTER) :
846
+ (cond_132)? ( `CMD_ENTER) :
847
+ (cond_133)? ( `CMD_WBINVD) :
848
+ (cond_134)? ( `CMD_WBINVD) :
849
+ (cond_135)? ( `CMD_CLTS) :
850
+ (cond_136)? ( `CMD_RET_far) :
851
+ (cond_137)? ( `CMD_load_seg) :
852
+ (cond_138)? ( `CMD_RET_far) :
853
+ (cond_139)? ( `CMD_RET_far) :
854
+ (cond_140)? ( `CMD_RET_far) :
855
+ (cond_141)? ( `CMD_load_seg) :
856
+ (cond_142)? ( `CMD_RET_far) :
857
+ (cond_143)? ( `CMD_RET_far) :
858
+ (cond_144)? ( `CMD_XCHG) :
859
+ (cond_145)? ( `CMD_int) :
860
+ (cond_146)? ( `CMD_int) :
861
+ (cond_147)? ( `CMD_INT_INTO) :
862
+ (cond_148)? ( `CMD_IN) :
863
+ (cond_149)? ( `CMD_io_allow) :
864
+ (cond_150)? ( `CMD_IN) :
865
+ (cond_151)? ( mc_cmd) :
866
+ (cond_152)? ( mc_cmd) :
867
+ (cond_153)? ( `CMD_INS) :
868
+ (cond_154)? ( `CMD_INS) :
869
+ (cond_155)? ( `CMD_io_allow) :
870
+ (cond_156)? ( `CMD_INS) :
871
+ (cond_157)? ( `CMD_INS) :
872
+ (cond_158)? ( `CMD_OUTS) :
873
+ (cond_159)? ( `CMD_io_allow) :
874
+ (cond_160)? ( `CMD_JMP) :
875
+ (cond_161)? ( `CMD_JMP) :
876
+ (cond_162)? ( `CMD_JMP) :
877
+ (cond_163)? ( `CMD_JMP) :
878
+ (cond_164)? ( `CMD_JMP) :
879
+ (cond_165)? ( `CMD_load_seg) :
880
+ (cond_166)? ( `CMD_JMP) :
881
+ (cond_167)? ( `CMD_JMP) :
882
+ (cond_168)? ( `CMD_JMP) :
883
+ (cond_169)? ( `CMD_JMP) :
884
+ (cond_170)? ( `CMD_JMP) :
885
+ (cond_171)? ( `CMD_JMP) :
886
+ (cond_172)? ( `CMD_task_switch) :
887
+ (cond_173)? ( `CMD_JMP) :
888
+ (cond_174)? ( `CMD_JMP) :
889
+ (cond_175)? ( `CMD_task_switch) :
890
+ (cond_176)? ( `CMD_JMP_2) :
891
+ (cond_177)? ( `CMD_JMP_2) :
892
+ (cond_178)? ( `CMD_JMP_2) :
893
+ (cond_179)? ( `CMD_JMP_2) :
894
+ (cond_180)? ( `CMD_OUT) :
895
+ (cond_181)? ( `CMD_io_allow) :
896
+ (cond_182)? ( `CMD_OUT) :
897
+ (cond_183)? ( `CMD_POPF) :
898
+ (cond_184)? ( `CMD_BOUND) :
899
+ (cond_185)? ( `CMD_task_switch) :
900
+ (cond_186)? ( `CMD_task_switch) :
901
+ (cond_187)? ( `CMD_task_switch) :
902
+ (cond_188)? ( `CMD_task_switch) :
903
+ (cond_189)? ( `CMD_task_switch) :
904
+ (cond_190)? ( `CMD_task_switch) :
905
+ (cond_191)? ( `CMD_task_switch) :
906
+ (cond_192)? ( `CMD_task_switch) :
907
+ (cond_193)? ( `CMD_task_switch) :
908
+ (cond_194)? ( `CMD_task_switch) :
909
+ (cond_195)? ( `CMD_task_switch) :
910
+ (cond_196)? ( `CMD_task_switch) :
911
+ (cond_197)? ( `CMD_task_switch_2) :
912
+ (cond_198)? ( mc_cmd) :
913
+ (cond_199)? ( `CMD_task_switch) :
914
+ (cond_200)? ( `CMD_task_switch) :
915
+ (cond_201)? ( `CMD_task_switch) :
916
+ (cond_202)? ( `CMD_task_switch) :
917
+ (cond_203)? ( `CMD_task_switch_3) :
918
+ (cond_204)? ( mc_cmd) :
919
+ (cond_205)? ( `CMD_task_switch_4) :
920
+ (cond_206)? ( mc_cmd) :
921
+ (cond_207)? ( mc_cmd) :
922
+ (cond_208)? ( mc_cmd) :
923
+ (cond_209)? ( `CMD_POPA) :
924
+ (cond_210)? ( `CMD_debug_reg) :
925
+ (cond_211)? ( mc_cmd) :
926
+ 7'd0;
snapshots/MiSTer-devel_ao486_MiSTer_pr72/rtl/ao486/autogen/prefetch_control.v ADDED
@@ -0,0 +1,60 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ //======================================================== conditions
2
+ wire cond_0 = state == STATE_TLB_REQUEST;
3
+ wire cond_1 = ~(pr_reset) && prefetch_length > 5'd0 && prefetchfifo_used < 5'd3;
4
+ wire cond_2 = tlbcode_do;
5
+ wire cond_3 = state == STATE_ICACHE;
6
+ wire cond_4 = page_cross || pr_reset || prefetchfifo_used >= 5'd8;
7
+ wire cond_5 = offset_update;
8
+ //======================================================== saves
9
+ wire [31:0] physical_to_reg =
10
+ (cond_0 && cond_1 && cond_2)? ( tlbcode_physical) :
11
+ (cond_3 && cond_5)? ( { physical[31:12], prefetch_address[11:0] }) :
12
+ physical;
13
+ wire [31:0] linear_to_reg =
14
+ (cond_0 && cond_1 && cond_2)? ( tlbcode_linear) :
15
+ (cond_3 && cond_5)? ( { linear[31:12], prefetch_address[11:0] }) :
16
+ linear;
17
+ wire [1:0] state_to_reg =
18
+ (cond_0 && cond_1 && cond_2)? ( STATE_ICACHE) :
19
+ (cond_3 && cond_4)? ( STATE_TLB_REQUEST) :
20
+ state;
21
+ wire cache_disable_to_reg =
22
+ (cond_0 && cond_1 && cond_2)? ( tlbcode_cache_disable) :
23
+ cache_disable;
24
+ //======================================================== always
25
+ always @(posedge clk) begin
26
+ if(rst_n == 1'b0) physical <= 32'd0;
27
+ else physical <= physical_to_reg;
28
+ end
29
+ always @(posedge clk) begin
30
+ if(rst_n == 1'b0) linear <= 32'd0;
31
+ else linear <= linear_to_reg;
32
+ end
33
+ always @(posedge clk) begin
34
+ if(rst_n == 1'b0) state <= 2'd0;
35
+ else state <= state_to_reg;
36
+ end
37
+ always @(posedge clk) begin
38
+ if(rst_n == 1'b0) cache_disable <= 1'd0;
39
+ else cache_disable <= cache_disable_to_reg;
40
+ end
41
+ //======================================================== sets
42
+ assign icacheread_length =
43
+ (cond_0 && cond_1 && cond_2)? ( length) :
44
+ (cond_3)? ( length) :
45
+ 5'd0;
46
+ assign tlbcoderequest_do =
47
+ (cond_0 && cond_1)? (`TRUE) :
48
+ 1'd0;
49
+ assign icacheread_do =
50
+ (cond_0 && cond_1 && cond_2)? (`TRUE) :
51
+ (cond_3 && ~cond_4)? (`TRUE) :
52
+ 1'd0;
53
+ assign icacheread_cache_disable =
54
+ (cond_0 && cond_1 && cond_2)? ( tlbcode_cache_disable) :
55
+ (cond_3)? ( cache_disable) :
56
+ 1'd0;
57
+ assign icacheread_address =
58
+ (cond_0 && cond_1 && cond_2)? ( tlbcode_physical) :
59
+ (cond_3)? ( (offset_update)? { physical[31:12], prefetch_address[11:0] } : physical) :
60
+ 32'd0;
snapshots/MiSTer-devel_ao486_MiSTer_pr72/rtl/ao486/autogen/read_commands.v ADDED
@@ -0,0 +1,1440 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ wire [4:0] rd_call_gate_param;
2
+ assign rd_call_gate_param = glob_param_3[24:20] - 5'd1;
3
+
4
+ wire rd_io_allow_1_fault;
5
+ wire rd_io_allow_2_fault;
6
+ assign rd_io_allow_1_fault = rd_cmd == `CMD_io_allow && rd_cmdex == `CMDEX_io_allow_1 && ( ~(tr_cache_valid) || (tr_cache[`DESC_BITS_TYPE] != `DESC_TSS_AVAIL_386 && tr_cache[`DESC_BITS_TYPE] != `DESC_TSS_BUSY_386) || tr_limit < 32'd103 );
7
+ assign rd_io_allow_2_fault = rd_cmd == `CMD_io_allow && rd_cmdex == `CMDEX_io_allow_2 && ({ 16'd0, rd_memory_last[15:0] } + { 16'd0, 3'd0, glob_param_1[15:3] }) >= tr_limit;
8
+ assign rd_io_allow_fault = rd_io_allow_1_fault || rd_io_allow_2_fault;
9
+
10
+ wire rd_imul_modregrm_mutex_busy;
11
+ assign rd_imul_modregrm_mutex_busy = ( rd_decoder[3] && rd_mutex_busy_modregrm_reg) || (~(rd_decoder[3]) && rd_mutex_busy_eax);
12
+
13
+ wire rd_arith_modregrm_to_rm;
14
+ wire rd_arith_modregrm_to_reg;
15
+ assign rd_arith_modregrm_to_rm = ~(rd_decoder[1]);
16
+ assign rd_arith_modregrm_to_reg= rd_decoder[1];
17
+
18
+ wire rd_in_condition;
19
+ assign rd_in_condition = (rd_mutex_busy_active && (rd_cmdex == `CMDEX_IN_imm || rd_cmdex == `CMDEX_IN_dx) && ~(io_allow_check_needed)) || (rd_cmdex == `CMDEX_IN_dx && rd_mutex_busy_edx);
20
+
21
+ wire [31:0] rd_offset_for_esp_from_tss;
22
+ wire [31:0] rd_offset_for_ss_from_tss;
23
+ wire [31:0] r_limit_for_ss_esp_from_tss;
24
+ wire rd_ss_esp_from_tss_386;
25
+ assign rd_ss_esp_from_tss_386 = tr_cache[`DESC_BITS_TYPE] == `DESC_TSS_AVAIL_386 || tr_cache[`DESC_BITS_TYPE] == `DESC_TSS_BUSY_386;
26
+ assign r_limit_for_ss_esp_from_tss = (rd_ss_esp_from_tss_386)? { 27'd0, glob_descriptor[`DESC_BITS_DPL], 3'd0 } + 32'd11 : { 28'd0, glob_descriptor[`DESC_BITS_DPL], 2'd0 } + 32'd5;
27
+ assign rd_offset_for_ss_from_tss = (rd_ss_esp_from_tss_386)? { 27'd0, glob_descriptor[`DESC_BITS_DPL], 3'd0 } + 32'd8 : { 28'd0, glob_descriptor[`DESC_BITS_DPL], 2'd0 } + 32'd4;
28
+ assign rd_offset_for_esp_from_tss = (rd_ss_esp_from_tss_386)? { 27'd0, glob_descriptor[`DESC_BITS_DPL], 3'd0 } + 32'd4 : { 28'd0, glob_descriptor[`DESC_BITS_DPL], 2'd0 } + 32'd2;
29
+ assign rd_ss_esp_from_tss_fault = ( (rd_cmd == `CMD_CALL_2 && rd_cmdex == `CMDEX_CALL_2_call_gate_more_STEP_0) || (rd_cmd == `CMD_int_2 && rd_cmdex == `CMDEX_int_2_int_trap_gate_more_STEP_0) ) && r_limit_for_ss_esp_from_tss > tr_limit;
30
+
31
+ wire [31:0] rd_task_switch_linear_next;
32
+ reg [31:0] rd_task_switch_linear_reg;
33
+ assign rd_task_switch_linear_next = (glob_descriptor[`DESC_BITS_TYPE] <= 4'd3)? rd_task_switch_linear_reg + 32'd2 : rd_task_switch_linear_reg + 32'd4;
34
+ always @(posedge clk) begin if(rst_n == 1'b0) rd_task_switch_linear_reg <= 32'd0; else if(rd_cmd == `CMD_task_switch && rd_cmdex == `CMDEX_task_switch_STEP_12) rd_task_switch_linear_reg <= rd_system_linear; else if(rd_ready) rd_task_switch_linear_reg <= rd_task_switch_linear_next;
35
+ end
36
+
37
+ //======================================================== conditions
38
+ wire cond_0 = rd_cmd == `CMD_XADD && rd_cmdex == `CMDEX_XADD_FIRST;
39
+ wire cond_1 = rd_modregrm_mod == 2'b11;
40
+ wire cond_2 = rd_mutex_busy_modregrm_reg || rd_mutex_busy_modregrm_rm;
41
+ wire cond_3 = rd_modregrm_mod != 2'b11;
42
+ wire cond_4 = rd_mutex_busy_modregrm_reg || rd_mutex_busy_memory;
43
+ wire cond_5 = ~(read_for_rd_ready);
44
+ wire cond_6 = rd_cmd == `CMD_XADD && rd_cmdex == `CMDEX_XADD_LAST;
45
+ wire cond_7 = rd_cmd == `CMD_CALL && rd_cmdex == `CMDEX_CALL_Ev_STEP_0;
46
+ wire cond_8 = rd_mutex_busy_modregrm_rm;
47
+ wire cond_9 = rd_mutex_busy_memory;
48
+ wire cond_10 = rd_cmd == `CMD_CALL && rd_cmdex == `CMDEX_CALL_Jv_STEP_0;
49
+ wire cond_11 = rd_cmd == `CMD_CALL && (rd_cmdex == `CMDEX_CALL_Ep_STEP_0 || rd_cmdex == `CMDEX_CALL_Ep_STEP_1);
50
+ wire cond_12 = rd_cmdex == `CMDEX_CALL_Ep_STEP_1;
51
+ wire cond_13 = rd_cmd == `CMD_CALL && rd_cmdex == `CMDEX_CALL_Ap_STEP_0;
52
+ wire cond_14 = rd_cmd == `CMD_CALL && rd_cmdex == `CMDEX_CALL_Ap_STEP_1;
53
+ wire cond_15 = rd_cmd == `CMD_CALL && rd_cmdex == `CMDEX_CALL_protected_STEP_0;
54
+ wire cond_16 = rd_mutex_busy_active;
55
+ wire cond_17 = glob_param_1[15:2] != 14'd0;
56
+ wire cond_18 = rd_cmd == `CMD_CALL_2 && rd_cmdex == `CMDEX_CALL_2_task_gate_STEP_0;
57
+ wire cond_19 = rd_cmd == `CMD_CALL_2 && rd_cmdex == `CMDEX_CALL_2_task_gate_STEP_1;
58
+ wire cond_20 = glob_param_1[`SELECTOR_BIT_TI] == 1'b0;
59
+ wire cond_21 = rd_cmd == `CMD_CALL_2 && rd_cmdex == `CMDEX_CALL_2_call_gate_STEP_1;
60
+ wire cond_22 = rd_cmd == `CMD_CALL_3 && (rd_cmdex == `CMDEX_CALL_3_call_gate_more_STEP_4 || rd_cmdex == `CMDEX_CALL_3_call_gate_more_STEP_5);
61
+ wire cond_23 = ~(glob_param_3[19]);
62
+ wire cond_24 = glob_param_3[19];
63
+ wire cond_25 = rd_ready;
64
+ wire cond_26 = rd_cmdex == `CMDEX_CALL_3_call_gate_more_STEP_4;
65
+ wire cond_27 = rd_cmd == `CMD_PUSH_MOV_SEG && { rd_cmdex[3], 3'b0 } == `CMDEX_PUSH_MOV_SEG_implicit;
66
+ wire cond_28 = rd_cmd == `CMD_PUSH_MOV_SEG && { rd_cmdex[3], 3'b0 } == `CMDEX_PUSH_MOV_SEG_modregrm;
67
+ wire cond_29 = ~(write_virtual_check_ready);
68
+ wire cond_30 = rd_cmd == `CMD_NEG;
69
+ wire cond_31 = rd_cmd == `CMD_INVLPG && rd_cmdex == `CMDEX_INVLPG_STEP_1;
70
+ wire cond_32 = ~(rd_address_effective_ready);
71
+ wire cond_33 = rd_cmd == `CMD_io_allow && rd_cmdex == `CMDEX_io_allow_1;
72
+ wire cond_34 = rd_io_allow_1_fault || rd_mutex_busy_active;
73
+ wire cond_35 = rd_cmd == `CMD_io_allow && rd_cmdex == `CMDEX_io_allow_2;
74
+ wire cond_36 = rd_io_allow_2_fault;
75
+ wire cond_37 = rd_cmd == `CMD_SCAS;
76
+ wire cond_38 = rd_mutex_busy_memory || (rd_mutex_busy_ecx && rd_prefix_group_1_rep != 2'd0);
77
+ wire cond_39 = ~(rd_string_ignore);
78
+ wire cond_40 = rd_cmd == `CMD_INC_DEC && { rd_cmdex[3:1], 1'b0 } == `CMDEX_INC_DEC_modregrm;
79
+ wire cond_41 = rd_cmd == `CMD_INC_DEC && { rd_cmdex[3:1], 1'b0 } == `CMDEX_INC_DEC_implicit;
80
+ wire cond_42 = rd_mutex_busy_implicit_reg;
81
+ wire cond_43 = rd_cmd == `CMD_RET_near && rd_cmdex != `CMDEX_RET_near_LAST;
82
+ wire cond_44 = rd_cmd == `CMD_ARPL;
83
+ wire cond_45 = rd_mutex_busy_modregrm_rm || rd_mutex_busy_modregrm_reg;
84
+ wire cond_46 = rd_mutex_busy_memory || rd_mutex_busy_modregrm_reg;
85
+ wire cond_47 = rd_cmd == `CMD_BSWAP;
86
+ wire cond_48 = rd_cmd == `CMD_LxS && rd_cmdex == `CMDEX_LxS_STEP_1;
87
+ wire cond_49 = ~(rd_address_effective_ready) || rd_mutex_busy_memory;
88
+ wire cond_50 = rd_operand_16bit;
89
+ wire cond_51 = rd_cmd == `CMD_LxS && rd_cmdex == `CMDEX_LxS_STEP_2;
90
+ wire cond_52 = rd_operand_32bit;
91
+ wire cond_53 = rd_cmd == `CMD_LxS && rd_cmdex == `CMDEX_LxS_STEP_3;
92
+ wire cond_54 = rd_cmd == `CMD_LxS && rd_cmdex == `CMDEX_LxS_STEP_LAST;
93
+ wire cond_55 = (rd_cmd == `CMD_MOV_to_seg || rd_cmd == `CMD_LLDT || rd_cmd == `CMD_LTR) && rd_cmdex == `CMDEX_MOV_to_seg_LLDT_LTR_STEP_1;
94
+ wire cond_56 = rd_cmd == `CMD_MOV_to_seg || cpl == 2'd0;
95
+ wire cond_57 = rd_cmd == `CMD_MOV_to_seg;
96
+ wire cond_58 = rd_cmd == `CMD_LLDT;
97
+ wire cond_59 = rd_cmd == `CMD_LTR;
98
+ wire cond_60 = rd_cmd == `CMD_CLC || rd_cmd == `CMD_CMC || rd_cmd == `CMD_CLD || rd_cmd == `CMD_STC || rd_cmd == `CMD_STD || rd_cmd == `CMD_SAHF;
99
+ wire cond_61 = rd_cmd == `CMD_int && rd_cmdex == `CMDEX_int_task_gate_STEP_0;
100
+ wire cond_62 = rd_cmd == `CMD_int && rd_cmdex == `CMDEX_int_task_gate_STEP_1;
101
+ wire cond_63 = rd_cmd == `CMD_int && rd_cmdex == `CMDEX_int_int_trap_gate_STEP_1;
102
+ wire cond_64 = rd_cmd == `CMD_int && rd_cmdex == `CMDEX_int_real_STEP_3;
103
+ wire cond_65 = rd_cmd == `CMD_int && rd_cmdex == `CMDEX_int_real_STEP_4;
104
+ wire cond_66 = rd_cmd == `CMD_int && rd_cmdex == `CMDEX_int_protected_STEP_1;
105
+ wire cond_67 = rd_cmd == `CMD_AAM || rd_cmd == `CMD_AAD;
106
+ wire cond_68 = rd_mutex_busy_eax;
107
+ wire cond_69 = rd_cmd == `CMD_load_seg && rd_cmdex == `CMDEX_load_seg_STEP_1;
108
+ wire cond_70 = v8086_mode;
109
+ wire cond_71 = real_mode;
110
+ wire cond_72 = protected_mode;
111
+ wire cond_73 = rd_cmd == `CMD_load_seg && rd_cmdex == `CMDEX_load_seg_STEP_2;
112
+ wire cond_74 = ~(protected_mode && glob_param_1[15:2] == 14'd0);
113
+ wire cond_75 = rd_cmd == `CMD_POP_seg && rd_cmdex == `CMDEX_POP_seg_STEP_1;
114
+ wire cond_76 = { rd_cmd[6:2], 2'd0 } == `CMD_BTx;
115
+ wire cond_77 = rd_mutex_busy_modregrm_rm || (rd_cmdex == `CMDEX_BTx_modregrm && rd_mutex_busy_modregrm_reg);
116
+ wire cond_78 = rd_mutex_busy_memory || (rd_cmdex == `CMDEX_BTx_modregrm && rd_mutex_busy_modregrm_reg);
117
+ wire cond_79 = rd_cmd == `CMD_IRET && rd_cmdex <= `CMDEX_IRET_real_v86_STEP_2;
118
+ wire cond_80 = rd_cmdex >`CMDEX_IRET_real_v86_STEP_0;
119
+ wire cond_81 = rd_cmdex == `CMDEX_IRET_real_v86_STEP_0;
120
+ wire cond_82 = rd_cmdex == `CMDEX_IRET_real_v86_STEP_1;
121
+ wire cond_83 = rd_cmdex == `CMDEX_IRET_real_v86_STEP_2;
122
+ wire cond_84 = rd_mutex_busy_memory || (rd_mutex_busy_eflags && v8086_mode);
123
+ wire cond_85 = ~(v8086_mode) || iopl == 2'd3;
124
+ wire cond_86 = rd_cmd == `CMD_IRET && rd_cmdex == `CMDEX_IRET_protected_STEP_0;
125
+ wire cond_87 = rd_mutex_busy_memory || rd_mutex_busy_eflags;
126
+ wire cond_88 = rd_cmd == `CMD_IRET && rd_cmdex == `CMDEX_IRET_task_switch_STEP_0;
127
+ wire cond_89 = rd_cmd == `CMD_IRET && rd_cmdex == `CMDEX_IRET_task_switch_STEP_1;
128
+ wire cond_90 = ~(rd_descriptor_not_in_limits);
129
+ wire cond_91 = rd_cmd == `CMD_IRET && rd_cmdex >= `CMDEX_IRET_protected_STEP_1 && rd_cmdex <= `CMDEX_IRET_protected_STEP_3;
130
+ wire cond_92 = rd_cmdex == `CMDEX_IRET_protected_STEP_1;
131
+ wire cond_93 = rd_cmdex == `CMDEX_IRET_protected_STEP_2;
132
+ wire cond_94 = rd_cmdex == `CMDEX_IRET_protected_STEP_3;
133
+ wire cond_95 = rd_cmd == `CMD_IRET && rd_cmdex >= `CMDEX_IRET_protected_to_v86_STEP_0;
134
+ wire cond_96 = rd_cmdex == `CMDEX_IRET_protected_to_v86_STEP_0;
135
+ wire cond_97 = rd_cmd == `CMD_IRET_2 && rd_cmdex == `CMDEX_IRET_2_protected_outer_STEP_0;
136
+ wire cond_98 = rd_cmd == `CMD_IRET_2 && rd_cmdex >= `CMDEX_IRET_2_protected_outer_STEP_1 && rd_cmdex <= `CMDEX_IRET_2_protected_outer_STEP_3;
137
+ wire cond_99 = rd_cmdex == `CMDEX_IRET_2_protected_outer_STEP_1;
138
+ wire cond_100 = rd_cmdex == `CMDEX_IRET_2_protected_outer_STEP_2;
139
+ wire cond_101 = rd_cmdex == `CMDEX_IRET_2_protected_outer_STEP_3;
140
+ wire cond_102 = rd_cmd == `CMD_IRET_2 && rd_cmdex >= `CMDEX_IRET_2_protected_outer_STEP_6;
141
+ wire cond_103 = rd_cmd == `CMD_POP && rd_cmdex == `CMDEX_POP_implicit;
142
+ wire cond_104 = rd_mutex_busy_memory || rd_mutex_busy_esp;
143
+ wire cond_105 = rd_cmd == `CMD_POP && rd_cmdex == `CMDEX_POP_modregrm_STEP_0;
144
+ wire cond_106 = rd_cmd == `CMD_POP && rd_cmdex == `CMDEX_POP_modregrm_STEP_1;
145
+ wire cond_107 = rd_cmd == `CMD_IDIV || rd_cmd == `CMD_DIV;
146
+ wire cond_108 = rd_mutex_busy_eax || (rd_decoder[0] && rd_mutex_busy_edx) || rd_mutex_busy_modregrm_rm;
147
+ wire cond_109 = rd_mutex_busy_eax || (rd_decoder[0] && rd_mutex_busy_edx) || rd_mutex_busy_memory;
148
+ wire cond_110 = rd_cmd == `CMD_Shift && rd_cmdex != `CMDEX_Shift_implicit;
149
+ wire cond_111 = rd_cmd == `CMD_Shift && rd_cmdex == `CMDEX_Shift_implicit;
150
+ wire cond_112 = rd_mutex_busy_modregrm_rm || rd_mutex_busy_ecx;
151
+ wire cond_113 = rd_mutex_busy_memory || rd_mutex_busy_ecx;
152
+ wire cond_114 = rd_cmd == `CMD_CMPS && rd_cmdex == `CMDEX_CMPS_FIRST;
153
+ wire cond_115 = rd_cmd == `CMD_CMPS && rd_cmdex == `CMDEX_CMPS_LAST;
154
+ wire cond_116 = rd_cmd == `CMD_control_reg && rd_cmdex == `CMDEX_control_reg_SMSW_STEP_0;
155
+ wire cond_117 = rd_cmd == `CMD_control_reg && rd_cmdex == `CMDEX_control_reg_LMSW_STEP_0;
156
+ wire cond_118 = cpl == 2'd0;
157
+ wire cond_119 = rd_cmd == `CMD_control_reg && rd_cmdex == `CMDEX_control_reg_MOV_load_STEP_0;
158
+ wire cond_120 = rd_cmd == `CMD_control_reg && rd_cmdex == `CMDEX_control_reg_MOV_store_STEP_0;
159
+ wire cond_121 = (rd_cmd == `CMD_LGDT || rd_cmd == `CMD_LIDT) && (rd_cmdex == `CMDEX_LGDT_LIDT_STEP_1 || rd_cmdex == `CMDEX_LGDT_LIDT_STEP_2);
160
+ wire cond_122 = rd_cmdex == `CMDEX_LGDT_LIDT_STEP_1;
161
+ wire cond_123 = rd_cmdex == `CMDEX_LGDT_LIDT_STEP_2;
162
+ wire cond_124 = rd_cmd == `CMD_PUSHA;
163
+ wire cond_125 = (rd_cmdex == `CMDEX_PUSHA_STEP_0 && rd_mutex_busy_eax) || (rd_cmdex == `CMDEX_PUSHA_STEP_1 && rd_mutex_busy_ecx) || (rd_cmdex == `CMDEX_PUSHA_STEP_2 && rd_mutex_busy_edx);
164
+ wire cond_126 = rd_cmd == `CMD_SETcc;
165
+ wire cond_127 = rd_cmd == `CMD_CMPXCHG;
166
+ wire cond_128 = rd_cmd == `CMD_ENTER && rd_cmdex == `CMDEX_ENTER_FIRST;
167
+ wire cond_129 = rd_mutex_busy_ebp;
168
+ wire cond_130 = rd_cmd == `CMD_ENTER && rd_cmdex == `CMDEX_ENTER_LAST;
169
+ wire cond_131 = rd_cmd == `CMD_ENTER && rd_cmdex == `CMDEX_ENTER_PUSH;
170
+ wire cond_132 = rd_cmd == `CMD_ENTER && rd_cmdex == `CMDEX_ENTER_LOOP;
171
+ wire cond_133 = rd_cmd == `CMD_IMUL && rd_cmdex == `CMDEX_IMUL_modregrm_imm;
172
+ wire cond_134 = rd_decoder[1:0] == 2'b11;
173
+ wire cond_135 = rd_cmd == `CMD_IMUL && rd_cmdex == `CMDEX_IMUL_modregrm;
174
+ wire cond_136 = rd_imul_modregrm_mutex_busy || rd_mutex_busy_modregrm_rm;
175
+ wire cond_137 = rd_imul_modregrm_mutex_busy || rd_mutex_busy_memory;
176
+ wire cond_138 = rd_cmd == `CMD_LEAVE;
177
+ wire cond_139 = { rd_cmd[6:1], 1'd0 } == `CMD_SHxD && rd_cmdex != `CMDEX_SHxD_implicit;
178
+ wire cond_140 = { rd_cmd[6:1], 1'd0 } == `CMD_SHxD && rd_cmdex == `CMDEX_SHxD_implicit;
179
+ wire cond_141 = rd_mutex_busy_modregrm_rm || rd_mutex_busy_ecx || rd_mutex_busy_modregrm_reg;
180
+ wire cond_142 = rd_mutex_busy_memory || rd_mutex_busy_ecx || rd_mutex_busy_modregrm_reg;
181
+ wire cond_143 = { rd_cmd[6:3], 3'd0 } == `CMD_Arith && rd_cmdex == `CMDEX_Arith_modregrm;
182
+ wire cond_144 = rd_decoder[5:3] != 3'b111;
183
+ wire cond_145 = rd_decoder[5:3] != 3'b111 && rd_arith_modregrm_to_rm;
184
+ wire cond_146 = rd_decoder[5:3] != 3'b111 && rd_arith_modregrm_to_reg;
185
+ wire cond_147 = { rd_cmd[6:3], 3'd0 } == `CMD_Arith && rd_cmdex == `CMDEX_Arith_modregrm_imm;
186
+ wire cond_148 = rd_decoder[13:11] != 3'b111;
187
+ wire cond_149 = { rd_cmd[6:3], 3'd0 } == `CMD_Arith && rd_cmdex == `CMDEX_Arith_immediate;
188
+ wire cond_150 = rd_cmd == `CMD_MUL;
189
+ wire cond_151 = rd_mutex_busy_eax || rd_mutex_busy_modregrm_rm;
190
+ wire cond_152 = rd_mutex_busy_eax || rd_mutex_busy_memory;
191
+ wire cond_153 = rd_cmd == `CMD_LOOP;
192
+ wire cond_154 = rd_cmd == `CMD_TEST && rd_cmdex == `CMDEX_TEST_modregrm;
193
+ wire cond_155 = rd_cmd == `CMD_TEST && rd_cmdex == `CMDEX_TEST_modregrm_imm;
194
+ wire cond_156 = rd_cmd == `CMD_TEST && rd_cmdex == `CMDEX_TEST_immediate;
195
+ wire cond_157 = rd_cmd == `CMD_RET_far && rd_cmdex == `CMDEX_RET_far_outer_STEP_3;
196
+ wire cond_158 = rd_cmd == `CMD_RET_far && rd_cmdex == `CMDEX_RET_far_STEP_1;
197
+ wire cond_159 = real_mode || v8086_mode;
198
+ wire cond_160 = rd_cmd == `CMD_RET_far && rd_cmdex == `CMDEX_RET_far_STEP_2;
199
+ wire cond_161 = rd_cmd == `CMD_RET_far && rd_cmdex == `CMDEX_RET_far_outer_STEP_4;
200
+ wire cond_162 = rd_cmd == `CMD_LODS;
201
+ wire cond_163 = rd_cmd == `CMD_XCHG && rd_cmdex == `CMDEX_XCHG_implicit;
202
+ wire cond_164 = rd_mutex_busy_implicit_reg || rd_mutex_busy_eax;
203
+ wire cond_165 = rd_cmd == `CMD_XCHG && rd_cmdex == `CMDEX_XCHG_modregrm;
204
+ wire cond_166 = rd_cmd == `CMD_XCHG && rd_cmdex == `CMDEX_XCHG_modregrm_LAST;
205
+ wire cond_167 = rd_cmd == `CMD_PUSH && (rd_cmdex == `CMDEX_PUSH_immediate || rd_cmdex == `CMDEX_PUSH_immediate_se);
206
+ wire cond_168 = rd_cmd == `CMD_PUSH && rd_cmdex == `CMDEX_PUSH_implicit;
207
+ wire cond_169 = rd_cmd == `CMD_PUSH && rd_cmdex == `CMDEX_PUSH_modregrm;
208
+ wire cond_170 = rd_cmd == `CMD_INT_INTO && rd_cmdex == `CMDEX_INT_INTO_INTO_STEP_0;
209
+ wire cond_171 = rd_mutex_busy_eflags;
210
+ wire cond_172 = rd_cmd == `CMD_CPUID;
211
+ wire cond_173 = rd_cmd == `CMD_IN && rd_cmdex != `CMDEX_IN_idle;
212
+ wire cond_174 = rd_in_condition;
213
+ wire cond_175 = ~(io_allow_check_needed) || rd_cmdex == `CMDEX_IN_protected;
214
+ wire cond_176 = ~(rd_io_ready);
215
+ wire cond_177 = rd_cmd == `CMD_NOT;
216
+ wire cond_178 = (rd_cmd == `CMD_LAR || rd_cmd == `CMD_LSL || rd_cmd == `CMD_VERR || rd_cmd == `CMD_VERW) && rd_cmdex == `CMDEX_LAR_LSL_VERR_VERW_STEP_1;
217
+ wire cond_179 = (rd_cmd == `CMD_LAR || rd_cmd == `CMD_LSL || rd_cmd == `CMD_VERR || rd_cmd == `CMD_VERW) && rd_cmdex == `CMDEX_LAR_LSL_VERR_VERW_STEP_2;
218
+ wire cond_180 = ~(glob_param_1[15:2] == 14'd0) && ~(rd_descriptor_not_in_limits);
219
+ wire cond_181 = (rd_cmd == `CMD_LAR || rd_cmd == `CMD_LSL) && rd_cmdex == `CMDEX_LAR_LSL_VERR_VERW_STEP_LAST;
220
+ wire cond_182 = rd_cmd == `CMD_LAR;
221
+ wire cond_183 = exe_mutex[`MUTEX_ACTIVE_BIT];
222
+ wire cond_184 = glob_param_2[1:0] == 2'd0 && ((glob_param_2[2] == 1'd0 && rd_cmd == `CMD_LAR) || (glob_param_2[3] == 1'd0 && rd_cmd == `CMD_LSL));
223
+ wire cond_185 = (rd_cmd == `CMD_VERR || rd_cmd == `CMD_VERW) && rd_cmdex == `CMDEX_LAR_LSL_VERR_VERW_STEP_LAST;
224
+ wire cond_186 = glob_param_2[1:0] == 2'd0 && ((glob_param_2[4] == 1'd0 && rd_cmd == `CMD_VERR) || (glob_param_2[5] == 1'd0 && rd_cmd == `CMD_VERW));
225
+ wire cond_187 = (rd_cmd == `CMD_int_2 && rd_cmdex == `CMDEX_int_2_int_trap_gate_more_STEP_0) || (rd_cmd == `CMD_CALL_2 && rd_cmdex == `CMDEX_CALL_2_call_gate_more_STEP_0) ;
226
+ wire cond_188 = rd_ss_esp_from_tss_fault;
227
+ wire cond_189 = (rd_cmd == `CMD_int_2 && rd_cmdex == `CMDEX_int_2_int_trap_gate_more_STEP_1) || (rd_cmd == `CMD_CALL_2 && rd_cmdex == `CMDEX_CALL_2_call_gate_more_STEP_1) ;
228
+ wire cond_190 = (rd_cmd == `CMD_int_2 && rd_cmdex == `CMDEX_int_2_int_trap_gate_more_STEP_2) || (rd_cmd == `CMD_CALL_2 && rd_cmdex == `CMDEX_CALL_2_call_gate_more_STEP_2) ;
229
+ wire cond_191 = rd_cmd == `CMD_STOS;
230
+ wire cond_192 = rd_mutex_busy_eax || (rd_mutex_busy_ecx && rd_prefix_group_1_rep != 2'd0);
231
+ wire cond_193 = rd_cmd == `CMD_INS && (rd_cmdex == `CMDEX_INS_real_1 || rd_cmdex == `CMDEX_INS_protected_1);
232
+ wire cond_194 = rd_mutex_busy_ecx && rd_prefix_group_1_rep != 2'd0;
233
+ wire cond_195 = ~(rd_string_ignore) && ~(io_allow_check_needed && rd_cmdex == `CMDEX_INS_real_1);
234
+ wire cond_196 = rd_cmd == `CMD_INS && (rd_cmdex == `CMDEX_INS_real_2 || rd_cmdex == `CMDEX_INS_protected_2);
235
+ wire cond_197 = rd_mutex_busy_edx || (rd_mutex_busy_ecx && rd_prefix_group_1_rep != 2'd0);
236
+ wire cond_198 = rd_cmd == `CMD_OUTS;
237
+ wire cond_199 = ~(rd_string_ignore) && ~(io_allow_check_needed && rd_cmdex == `CMDEX_OUTS_first);
238
+ wire cond_200 = rd_cmd == `CMD_PUSHF;
239
+ wire cond_201 = rd_cmd == `CMD_JMP && rd_cmdex == `CMDEX_JMP_Jv_STEP_0;
240
+ wire cond_202 = rd_cmd == `CMD_JMP && rd_cmdex == `CMDEX_JMP_Ap_STEP_1;
241
+ wire cond_203 = rd_cmd == `CMD_JMP_2 && rd_cmdex == `CMDEX_JMP_2_call_gate_STEP_0;
242
+ wire cond_204 = rd_cmd == `CMD_JMP_2 && rd_cmdex == `CMDEX_JMP_2_call_gate_STEP_1;
243
+ wire cond_205 = rd_cmd == `CMD_JMP && rd_cmdex == `CMDEX_JMP_Ev_STEP_0;
244
+ wire cond_206 = rd_cmd == `CMD_JMP && (rd_cmdex == `CMDEX_JMP_Ep_STEP_0 || rd_cmdex == `CMDEX_JMP_Ep_STEP_1);
245
+ wire cond_207 = rd_cmdex == `CMDEX_JMP_Ep_STEP_1;
246
+ wire cond_208 = rd_cmd == `CMD_JMP && rd_cmdex == `CMDEX_JMP_Ap_STEP_0;
247
+ wire cond_209 = rd_cmd == `CMD_JMP && rd_cmdex == `CMDEX_JMP_protected_STEP_0;
248
+ wire cond_210 = rd_cmd == `CMD_JMP && rd_cmdex == `CMDEX_JMP_task_gate_STEP_0;
249
+ wire cond_211 = rd_cmd == `CMD_JMP && rd_cmdex == `CMDEX_JMP_task_gate_STEP_1;
250
+ wire cond_212 = rd_cmd == `CMD_OUT;
251
+ wire cond_213 = rd_cmd == `CMD_MOV && rd_cmdex == `CMDEX_MOV_memoffset;
252
+ wire cond_214 = ~(rd_decoder[1]);
253
+ wire cond_215 = rd_mutex_busy_eax || ~(write_virtual_check_ready);
254
+ wire cond_216 = rd_cmd == `CMD_MOV && rd_cmdex == `CMDEX_MOV_modregrm && rd_decoder[1];
255
+ wire cond_217 = rd_cmd == `CMD_MOV && rd_cmdex == `CMDEX_MOV_modregrm && ~(rd_decoder[1]);
256
+ wire cond_218 = rd_mutex_busy_modregrm_reg;
257
+ wire cond_219 = rd_cmd == `CMD_MOV && rd_cmdex == `CMDEX_MOV_modregrm_imm;
258
+ wire cond_220 = rd_cmd == `CMD_MOV && rd_cmdex == `CMDEX_MOV_immediate;
259
+ wire cond_221 = rd_cmd == `CMD_LAHF || rd_cmd == `CMD_CBW || rd_cmd == `CMD_CWD;
260
+ wire cond_222 = rd_cmd == `CMD_POPF && rd_cmdex == `CMDEX_POPF_STEP_0;
261
+ wire cond_223 = rd_cmd == `CMD_CLI || rd_cmd == `CMD_STI;
262
+ wire cond_224 = rd_cmd == `CMD_BOUND && rd_cmdex == `CMDEX_BOUND_STEP_FIRST;
263
+ wire cond_225 = rd_cmd == `CMD_BOUND && rd_cmdex == `CMDEX_BOUND_STEP_LAST;
264
+ wire cond_226 = rd_cmd == `CMD_SALC && rd_cmdex == `CMDEX_SALC_STEP_0;
265
+ wire cond_227 = rd_cmd == `CMD_task_switch && rd_cmdex == `CMDEX_task_switch_STEP_6;
266
+ wire cond_228 = glob_param_1[`TASK_SWITCH_SOURCE_BITS] == `TASK_SWITCH_FROM_JUMP || glob_param_1[`TASK_SWITCH_SOURCE_BITS] == `TASK_SWITCH_FROM_IRET;
267
+ wire cond_229 = rd_cmd == `CMD_task_switch && rd_cmdex == `CMDEX_task_switch_STEP_9;
268
+ wire cond_230 = rd_cmd == `CMD_task_switch_2 && rd_cmdex <= `CMDEX_task_switch_2_STEP_7;
269
+ wire cond_231 = rd_cmd == `CMD_task_switch_2 && rd_cmdex == `CMDEX_task_switch_2_STEP_13;
270
+ wire cond_232 = rd_cmd == `CMD_task_switch && rd_cmdex >= `CMDEX_task_switch_STEP_12 && rd_cmdex <= `CMDEX_task_switch_STEP_14;
271
+ wire cond_233 = rd_cmdex == `CMDEX_task_switch_STEP_12 && glob_descriptor[`DESC_BITS_TYPE] <= 4'd3;
272
+ wire cond_234 = rd_cmdex == `CMDEX_task_switch_STEP_12 && glob_descriptor[`DESC_BITS_TYPE] > 4'd3;
273
+ wire cond_235 = rd_cmdex == `CMDEX_task_switch_STEP_13 || rd_cmdex == `CMDEX_task_switch_STEP_14;
274
+ wire cond_236 = rd_cmdex != `CMDEX_task_switch_STEP_12 || (glob_descriptor[`DESC_BITS_TYPE] > 4'd3 && cr0_pg);
275
+ wire cond_237 = rd_cmd == `CMD_task_switch_3;
276
+ wire cond_238 = rd_cmdex <= `CMDEX_task_switch_3_STEP_12 || glob_descriptor[`DESC_BITS_TYPE] > 4'd3;
277
+ wire cond_239 = rd_cmd == `CMD_task_switch_4 && rd_cmdex == `CMDEX_task_switch_4_STEP_0;
278
+ wire cond_240 = glob_param_1[`TASK_SWITCH_SOURCE_BITS] != `TASK_SWITCH_FROM_IRET;
279
+ wire cond_241 = rd_cmd == `CMD_task_switch_4 && rd_cmdex == `CMDEX_task_switch_4_STEP_2;
280
+ wire cond_242 = glob_param_1[`SELECTOR_BIT_TI] == 1'b0 && glob_param_1[15:2] != 14'd0 && ~(rd_descriptor_not_in_limits);
281
+ wire cond_243 = rd_cmd == `CMD_task_switch_4 && rd_cmdex >= `CMDEX_task_switch_4_STEP_3 && rd_cmdex <= `CMDEX_task_switch_4_STEP_8;
282
+ wire cond_244 = glob_param_1[15:2] != 14'd0 && ~(rd_descriptor_not_in_limits);
283
+ wire cond_245 = rd_cmd == `CMD_LEA;
284
+ wire cond_246 = (rd_cmd == `CMD_SGDT || rd_cmd == `CMD_SIDT);
285
+ wire cond_247 = rd_cmdex == `CMDEX_SGDT_SIDT_STEP_1;
286
+ wire cond_248 = rd_cmdex == `CMDEX_SGDT_SIDT_STEP_2;
287
+ wire cond_249 = rd_cmd == `CMD_MOVS;
288
+ wire cond_250 = rd_cmd == `CMD_MOVSX || rd_cmd == `CMD_MOVZX;
289
+ wire cond_251 = rd_cmd == `CMD_POPA;
290
+ wire cond_252 = rd_cmdex[2:0] > 3'd0;
291
+ wire cond_253 = rd_cmdex[2:0] == 3'd7;
292
+ wire cond_254 = rd_cmd == `CMD_debug_reg && rd_cmdex == `CMDEX_debug_reg_MOV_store_STEP_0;
293
+ wire cond_255 = rd_cmd == `CMD_debug_reg && rd_cmdex == `CMDEX_debug_reg_MOV_load_STEP_0;
294
+ wire cond_256 = rd_cmd == `CMD_XLAT;
295
+ wire cond_257 = rd_cmd == `CMD_AAA || rd_cmd == `CMD_AAS || rd_cmd == `CMD_DAA || rd_cmd == `CMD_DAS;
296
+ wire cond_258 = { rd_cmd[6:1], 1'd0 } == `CMD_BSx;
297
+ //======================================================== saves
298
+ //======================================================== always
299
+ //======================================================== sets
300
+ assign rd_glob_param_5_set =
301
+ (cond_22 && ~cond_16)? (`TRUE) :
302
+ (cond_98 && cond_100)? (`TRUE) :
303
+ (cond_190 && ~cond_16 && cond_90)? (`TRUE) :
304
+ (cond_190 && ~cond_16 && ~cond_90)? (`TRUE) :
305
+ 1'd0;
306
+ assign rd_glob_param_2_set =
307
+ (cond_43)? (`TRUE) :
308
+ (cond_48 && ~cond_49 && cond_50)? (`TRUE) :
309
+ (cond_53 && ~cond_50)? (`TRUE) :
310
+ (cond_64)? (`TRUE) :
311
+ (cond_79 && cond_81)? (`TRUE) :
312
+ (cond_89 && ~cond_16 && cond_90)? (`TRUE) :
313
+ (cond_89 && ~cond_16 && ~cond_90)? (`TRUE) :
314
+ (cond_91 && cond_94)? (`TRUE) :
315
+ (cond_98 && cond_101)? (`TRUE) :
316
+ (cond_158 && ~cond_9 && cond_159)? (`TRUE) :
317
+ (cond_160 && ~cond_9 && cond_72)? (`TRUE) :
318
+ (cond_179 && cond_180 && ~cond_9)? (`TRUE) :
319
+ (cond_179 && ~cond_180)? (`TRUE) :
320
+ (cond_203 && ~cond_16)? (`TRUE) :
321
+ (cond_227 && ~cond_16 && cond_228)? (`TRUE) :
322
+ (cond_241 && ~cond_16 && cond_242)? (`TRUE) :
323
+ (cond_241 && ~cond_16 && ~cond_242)? (`TRUE) :
324
+ (cond_243 && ~cond_16 && cond_70)? (`TRUE) :
325
+ (cond_243 && ~cond_16 && ~cond_70 && cond_244)? (`TRUE) :
326
+ (cond_243 && ~cond_16 && ~cond_70 && ~cond_244)? (`TRUE) :
327
+ 1'd0;
328
+ assign rd_req_all =
329
+ (cond_251 && cond_253)? (`TRUE) :
330
+ 1'd0;
331
+ assign rd_req_esp =
332
+ (cond_27)? (`TRUE) :
333
+ (cond_43)? (`TRUE) :
334
+ (cond_75)? (`TRUE) :
335
+ (cond_103)? (`TRUE) :
336
+ (cond_105)? (`TRUE) :
337
+ (cond_124)? (`TRUE) :
338
+ (cond_128)? (`TRUE) :
339
+ (cond_130)? (`TRUE) :
340
+ (cond_131)? (`TRUE) :
341
+ (cond_132)? (`TRUE) :
342
+ (cond_138 && ~cond_9)? (`TRUE) :
343
+ (cond_167)? (`TRUE) :
344
+ (cond_168)? (`TRUE) :
345
+ (cond_169)? (`TRUE) :
346
+ (cond_200)? (`TRUE) :
347
+ (cond_222)? (`TRUE) :
348
+ 1'd0;
349
+ assign rd_src_is_cmdex =
350
+ (cond_124)? (`TRUE) :
351
+ (cond_128)? (`TRUE) :
352
+ (cond_230)? (`TRUE) :
353
+ 1'd0;
354
+ assign rd_req_implicit_reg =
355
+ (cond_41)? (`TRUE) :
356
+ (cond_47)? (`TRUE) :
357
+ (cond_103)? (`TRUE) :
358
+ (cond_163)? (`TRUE) :
359
+ (cond_220)? (`TRUE) :
360
+ 1'd0;
361
+ assign rd_req_reg =
362
+ (cond_6)? (`TRUE) :
363
+ (cond_54)? (`TRUE) :
364
+ (cond_133)? (`TRUE) :
365
+ (cond_135)? ( rd_decoder[3]) :
366
+ (cond_143 && cond_1 && cond_144)? ( rd_arith_modregrm_to_reg) :
367
+ (cond_143 && cond_3 && cond_146)? (`TRUE) :
368
+ (cond_166)? (`TRUE) :
369
+ (cond_181 && ~cond_183 && cond_184)? (`TRUE) :
370
+ (cond_216)? (`TRUE) :
371
+ (cond_245)? (`TRUE) :
372
+ (cond_258)? (`TRUE) :
373
+ 1'd0;
374
+ assign rd_dst_is_0 =
375
+ (cond_30)? (`TRUE) :
376
+ 1'd0;
377
+ assign address_esi =
378
+ (cond_114)? (`TRUE) :
379
+ (cond_162)? (`TRUE) :
380
+ (cond_198)? (`TRUE) :
381
+ (cond_249)? (`TRUE) :
382
+ 1'd0;
383
+ assign address_stack_save =
384
+ (cond_22 && cond_26)? (`TRUE) :
385
+ (cond_91 && cond_92)? (`TRUE) :
386
+ (cond_95 && cond_96)? (`TRUE) :
387
+ (cond_98 && cond_99)? (`TRUE) :
388
+ (cond_158)? (`TRUE) :
389
+ (cond_157)? (`TRUE) :
390
+ 1'd0;
391
+ assign read_rmw_virtual =
392
+ (cond_0 && cond_3 && ~cond_4)? (`TRUE) :
393
+ (cond_30 && cond_3 && ~cond_9)? (`TRUE) :
394
+ (cond_40 && cond_3 && ~cond_9)? (`TRUE) :
395
+ (cond_44 && cond_3 && ~cond_46)? (`TRUE) :
396
+ (cond_76 && cond_3 && ~cond_78)? ( rd_cmd[1:0] != 2'd0) :
397
+ (cond_110 && cond_3 && ~cond_9)? (`TRUE) :
398
+ (cond_111 && cond_3 && ~cond_113)? (`TRUE) :
399
+ (cond_127 && cond_3 && ~cond_4)? (`TRUE) :
400
+ (cond_130)? (`TRUE) :
401
+ (cond_139 && cond_3 && ~cond_46)? (`TRUE) :
402
+ (cond_140 && cond_3 && ~cond_142)? (`TRUE) :
403
+ (cond_143 && cond_3 && ~cond_46 && cond_145)? (`TRUE) :
404
+ (cond_147 && cond_3 && ~cond_9 && cond_148)? (`TRUE) :
405
+ (cond_165 && cond_3 && ~cond_4)? (`TRUE) :
406
+ (cond_177 && cond_3 && ~cond_9)? (`TRUE) :
407
+ (cond_193 && ~cond_194 && cond_195)? (`TRUE) :
408
+ 1'd0;
409
+ assign address_stack_pop_speedup =
410
+ (cond_79 && cond_80)? (`TRUE) :
411
+ (cond_160)? ( real_mode || v8086_mode) :
412
+ (cond_251 && cond_252)? (`TRUE) :
413
+ 1'd0;
414
+ assign io_read =
415
+ (cond_173 && ~cond_174 && cond_175)? (`TRUE) :
416
+ (cond_196 && ~cond_197 && cond_195)? (`TRUE) :
417
+ 1'd0;
418
+ assign address_leave =
419
+ (cond_138)? (`TRUE) :
420
+ 1'd0;
421
+ assign rd_dst_is_eax =
422
+ (cond_37 && ~cond_38 && cond_39)? (`TRUE) :
423
+ (cond_67)? (`TRUE) :
424
+ (cond_149)? (`TRUE) :
425
+ (cond_156)? (`TRUE) :
426
+ (cond_213 && cond_214)? (`TRUE) :
427
+ (cond_256)? (`TRUE) :
428
+ (cond_257)? (`TRUE) :
429
+ 1'd0;
430
+ assign rd_src_is_imm =
431
+ (cond_10)? (`TRUE) :
432
+ (cond_13)? (`TRUE) :
433
+ (cond_67)? (`TRUE) :
434
+ (cond_149)? (`TRUE) :
435
+ (cond_156)? (`TRUE) :
436
+ (cond_167)? (`TRUE) :
437
+ (cond_208)? (`TRUE) :
438
+ (cond_220)? (`TRUE) :
439
+ 1'd0;
440
+ assign address_bits_transform =
441
+ (cond_76)? ( rd_cmdex == `CMDEX_BTx_modregrm) :
442
+ 1'd0;
443
+ assign rd_src_is_1 =
444
+ (cond_40)? (`TRUE) :
445
+ (cond_41)? (`TRUE) :
446
+ (cond_110)? ( rd_cmdex == `CMDEX_Shift_modregrm) :
447
+ 1'd0;
448
+ assign read_system_dword =
449
+ (cond_189)? ( rd_ss_esp_from_tss_386) :
450
+ (cond_232 && cond_236 && ~cond_9)? ( glob_descriptor[`DESC_BITS_TYPE] > 4'd3) :
451
+ (cond_237 && cond_238)? ( glob_descriptor[`DESC_BITS_TYPE] > 4'd3 && rd_cmdex <= `CMDEX_task_switch_3_STEP_7) :
452
+ 1'd0;
453
+ assign address_stack_for_ret_first =
454
+ (cond_158)? (`TRUE) :
455
+ 1'd0;
456
+ assign rd_req_eax =
457
+ (cond_67)? (`TRUE) :
458
+ (cond_107)? (`TRUE) :
459
+ (cond_127)? (`TRUE) :
460
+ (cond_135)? ( ~(rd_decoder[3])) :
461
+ (cond_149 && cond_144)? (`TRUE) :
462
+ (cond_150)? (`TRUE) :
463
+ (cond_162 && ~cond_38 && cond_39)? (`TRUE) :
464
+ (cond_163)? (`TRUE) :
465
+ (cond_172)? (`TRUE) :
466
+ (cond_213 && cond_214)? (`TRUE) :
467
+ (cond_221)? ( rd_cmd != `CMD_CWD) :
468
+ (cond_226)? (`TRUE) :
469
+ (cond_256)? (`TRUE) :
470
+ (cond_257)? (`TRUE) :
471
+ 1'd0;
472
+ assign address_stack_for_iret_last =
473
+ (cond_98 && cond_101)? (`TRUE) :
474
+ 1'd0;
475
+ assign rd_glob_param_3_value =
476
+ (cond_15 && ~cond_16 && cond_17)? ( 32'd0) :
477
+ (cond_22 && cond_25)? ( { 7'd0, rd_call_gate_param, glob_param_3[19:0] }) :
478
+ (cond_79 && cond_83)? ( (rd_operand_16bit)? { 16'd0, read_4[15:0] } : read_4) :
479
+ (cond_89)? ( { 10'd0, rd_consumed, 18'd0 }) :
480
+ (cond_91 && cond_92)? ( (rd_operand_16bit)? { 16'd0, read_4[15:0] } : read_4) :
481
+ (cond_97)? ( glob_param_1) :
482
+ (cond_157)? ( glob_param_1) :
483
+ (cond_187 && ~cond_188)? ( { 16'd0, read_4[15:0] }) :
484
+ (cond_209 && ~cond_16 && cond_17)? ( 32'd0) :
485
+ 32'd0;
486
+ assign read_virtual =
487
+ (cond_7 && cond_3 && ~cond_9)? (`TRUE) :
488
+ (cond_11 && ~cond_9)? (`TRUE) :
489
+ (cond_22 && ~cond_16)? (`TRUE) :
490
+ (cond_37 && ~cond_38 && cond_39)? (`TRUE) :
491
+ (cond_43 && ~cond_9)? (`TRUE) :
492
+ (cond_48 && ~cond_49 && cond_50)? (`TRUE) :
493
+ (cond_51 && cond_52)? (`TRUE) :
494
+ (cond_53)? (`TRUE) :
495
+ (cond_55 && cond_56 && cond_3 && ~cond_9)? (`TRUE) :
496
+ (cond_75 && ~cond_9)? (`TRUE) :
497
+ (cond_76 && cond_3 && ~cond_78)? ( rd_cmd[1:0] == 2'd0) :
498
+ (cond_79 && ~cond_84 && cond_85)? (`TRUE) :
499
+ (cond_91)? (`TRUE) :
500
+ (cond_95)? (`TRUE) :
501
+ (cond_97)? (`TRUE) :
502
+ (cond_98)? (`TRUE) :
503
+ (cond_103 && ~cond_104)? (`TRUE) :
504
+ (cond_105 && ~cond_104)? (`TRUE) :
505
+ (cond_107 && cond_3 && ~cond_109)? (`TRUE) :
506
+ (cond_114 && ~cond_38 && cond_39)? (`TRUE) :
507
+ (cond_115 && cond_39)? (`TRUE) :
508
+ (cond_117 && cond_118 && cond_3 && ~cond_9)? (`TRUE) :
509
+ (cond_121 && cond_118 && ~cond_9)? (`TRUE) :
510
+ (cond_132)? (`TRUE) :
511
+ (cond_133 && cond_3 && ~cond_9)? (`TRUE) :
512
+ (cond_135 && cond_3 && ~cond_137)? (`TRUE) :
513
+ (cond_138 && ~cond_9)? (`TRUE) :
514
+ (cond_143 && cond_3 && ~cond_46 && ~cond_145)? (`TRUE) :
515
+ (cond_147 && cond_3 && ~cond_9 && ~cond_148)? (`TRUE) :
516
+ (cond_150 && cond_3 && ~cond_152)? (`TRUE) :
517
+ (cond_154 && cond_3 && ~cond_46)? (`TRUE) :
518
+ (cond_155 && cond_3 && ~cond_9)? (`TRUE) :
519
+ (cond_157)? (`TRUE) :
520
+ (cond_158 && ~cond_9)? (`TRUE) :
521
+ (cond_160 && ~cond_9)? (`TRUE) :
522
+ (cond_161)? (`TRUE) :
523
+ (cond_162 && ~cond_38 && cond_39)? (`TRUE) :
524
+ (cond_169 && cond_3 && ~cond_9)? (`TRUE) :
525
+ (cond_178 && cond_3 && ~cond_9)? (`TRUE) :
526
+ (cond_198 && ~cond_38 && cond_199)? (`TRUE) :
527
+ (cond_205 && cond_3 && ~cond_9)? (`TRUE) :
528
+ (cond_206 && ~cond_9)? (`TRUE) :
529
+ (cond_213 && cond_214 && ~cond_9)? (`TRUE) :
530
+ (cond_216 && cond_3 && ~cond_9)? (`TRUE) :
531
+ (cond_222 && ~cond_9)? (`TRUE) :
532
+ (cond_224 && ~cond_9)? (`TRUE) :
533
+ (cond_225 && ~cond_9)? (`TRUE) :
534
+ (cond_249 && ~cond_38 && cond_39)? (`TRUE) :
535
+ (cond_250 && cond_3 && ~cond_9)? (`TRUE) :
536
+ (cond_251 && ~cond_104)? (`TRUE) :
537
+ (cond_256 && ~cond_9)? (`TRUE) :
538
+ (cond_258 && cond_3 && ~cond_9)? (`TRUE) :
539
+ 1'd0;
540
+ assign rd_glob_param_4_value =
541
+ (cond_98 && cond_99)? ( (rd_operand_16bit)? { 16'd0, read_4[15:0] } : read_4) :
542
+ (cond_161)? ( (rd_operand_16bit)? { 16'd0, read_4[15:0] } : read_4) :
543
+ (cond_189)? ( (rd_ss_esp_from_tss_386)? read_4 : { 16'd0, read_4[15:0] }) :
544
+ 32'd0;
545
+ assign address_stack_pop_for_call =
546
+ (cond_22)? (`TRUE) :
547
+ 1'd0;
548
+ assign rd_glob_param_5_value =
549
+ (cond_22 && ~cond_16)? ( read_4) :
550
+ (cond_98 && cond_100)? ( (rd_operand_16bit)? { 16'd0, read_4[15:0] } : read_4) :
551
+ (cond_190 && ~cond_16 && cond_90)? ( 32'd0) :
552
+ (cond_190 && ~cond_16 && ~cond_90)? ( { 31'd0, rd_descriptor_not_in_limits }) :
553
+ 32'd0;
554
+ assign write_virtual_check =
555
+ (cond_28 && cond_3 && ~cond_9)? (`TRUE) :
556
+ (cond_106 && cond_3)? (`TRUE) :
557
+ (cond_116 && cond_3)? (`TRUE) :
558
+ (cond_126 && cond_3)? (`TRUE) :
559
+ (cond_213 && ~cond_214)? (`TRUE) :
560
+ (cond_217 && cond_3 && ~cond_218)? (`TRUE) :
561
+ (cond_219 && cond_3 && ~cond_218)? (`TRUE) :
562
+ (cond_246)? (`TRUE) :
563
+ 1'd0;
564
+ assign rd_req_esi =
565
+ (cond_114 && ~cond_38 && cond_39)? (`TRUE) :
566
+ (cond_115 && cond_39)? (`TRUE) :
567
+ (cond_162 && ~cond_38 && cond_39)? (`TRUE) :
568
+ (cond_198 && ~cond_38 && cond_199 && ~cond_5)? (`TRUE) :
569
+ (cond_249 && ~cond_38 && cond_39)? (`TRUE) :
570
+ 1'd0;
571
+ assign rd_dst_is_implicit_reg =
572
+ (cond_41)? (`TRUE) :
573
+ (cond_47)? (`TRUE) :
574
+ (cond_103)? (`TRUE) :
575
+ (cond_163)? (`TRUE) :
576
+ (cond_220)? (`TRUE) :
577
+ 1'd0;
578
+ assign rd_req_eflags =
579
+ (cond_6)? (`TRUE) :
580
+ (cond_30)? (`TRUE) :
581
+ (cond_37 && ~cond_38 && cond_39 && ~cond_5)? (`TRUE) :
582
+ (cond_40)? (`TRUE) :
583
+ (cond_41)? (`TRUE) :
584
+ (cond_44 && cond_1)? (`TRUE) :
585
+ (cond_60)? (`TRUE) :
586
+ (cond_67)? (`TRUE) :
587
+ (cond_76)? (`TRUE) :
588
+ (cond_110)? (`TRUE) :
589
+ (cond_111)? (`TRUE) :
590
+ (cond_114 && ~cond_38 && cond_39)? (`TRUE) :
591
+ (cond_115 && cond_39)? (`TRUE) :
592
+ (cond_127)? (`TRUE) :
593
+ (cond_133)? (`TRUE) :
594
+ (cond_135)? (`TRUE) :
595
+ (cond_139)? (`TRUE) :
596
+ (cond_140)? (`TRUE) :
597
+ (cond_143)? (`TRUE) :
598
+ (cond_147)? (`TRUE) :
599
+ (cond_149)? (`TRUE) :
600
+ (cond_150)? (`TRUE) :
601
+ (cond_154)? (`TRUE) :
602
+ (cond_155)? (`TRUE) :
603
+ (cond_156)? (`TRUE) :
604
+ (cond_181)? (`TRUE) :
605
+ (cond_185)? (`TRUE) :
606
+ (cond_222)? (`TRUE) :
607
+ (cond_223)? (`TRUE) :
608
+ (cond_257)? (`TRUE) :
609
+ (cond_258)? (`TRUE) :
610
+ 1'd0;
611
+ assign rd_extra_wire =
612
+ (cond_14)? ( rd_decoder[55:24]) :
613
+ (cond_181 && cond_182)? ( { 8'd0, glob_descriptor[55:40], 8'd0 }) :
614
+ (cond_181 && ~cond_182)? ( glob_desc_limit) :
615
+ (cond_202)? ( rd_decoder[55:24]) :
616
+ 32'd0;
617
+ assign address_memoffset =
618
+ (cond_213)? (`TRUE) :
619
+ 1'd0;
620
+ assign rd_src_is_reg =
621
+ (cond_0)? (`TRUE) :
622
+ (cond_44 && cond_1)? (`TRUE) :
623
+ (cond_76)? ( rd_cmdex == `CMDEX_BTx_modregrm) :
624
+ (cond_127)? (`TRUE) :
625
+ (cond_139)? (`TRUE) :
626
+ (cond_140)? (`TRUE) :
627
+ (cond_143)? ( rd_arith_modregrm_to_rm) :
628
+ (cond_154)? (`TRUE) :
629
+ (cond_165)? (`TRUE) :
630
+ (cond_217)? (`TRUE) :
631
+ 1'd0;
632
+ assign io_read_address =
633
+ (cond_173)? ( (rd_cmdex == `CMDEX_IN_imm)? { 8'd0, rd_decoder[15:8] } : (rd_cmdex == `CMDEX_IN_protected)? glob_param_1[15:0] : edx[15:0]) :
634
+ (cond_196)? ( edx[15:0]) :
635
+ 16'd0;
636
+ assign rd_req_memory =
637
+ (cond_6)? ( rd_modregrm_mod != 2'b11) :
638
+ (cond_27)? (`TRUE) :
639
+ (cond_28 && cond_3)? (`TRUE) :
640
+ (cond_30 && cond_3 && ~cond_9)? (`TRUE) :
641
+ (cond_40 && cond_3)? (`TRUE) :
642
+ (cond_44 && cond_3)? (`TRUE) :
643
+ (cond_76 && cond_3)? ( rd_cmd[1:0] != 2'd0) :
644
+ (cond_106 && cond_3)? (`TRUE) :
645
+ (cond_110 && cond_3)? (`TRUE) :
646
+ (cond_111 && cond_3)? (`TRUE) :
647
+ (cond_116 && cond_3)? (`TRUE) :
648
+ (cond_124)? (`TRUE) :
649
+ (cond_126 && cond_3)? (`TRUE) :
650
+ (cond_127 && cond_3 && ~cond_4)? (`TRUE) :
651
+ (cond_128)? (`TRUE) :
652
+ (cond_131)? (`TRUE) :
653
+ (cond_132)? (`TRUE) :
654
+ (cond_139 && cond_3)? (`TRUE) :
655
+ (cond_140 && cond_3)? (`TRUE) :
656
+ (cond_143 && cond_3 && cond_145)? (`TRUE) :
657
+ (cond_147 && cond_3 && cond_148)? (`TRUE) :
658
+ (cond_166 && cond_3)? (`TRUE) :
659
+ (cond_167)? (`TRUE) :
660
+ (cond_168)? (`TRUE) :
661
+ (cond_169)? (`TRUE) :
662
+ (cond_177 && cond_3)? (`TRUE) :
663
+ (cond_191 && ~cond_192 && cond_39)? (`TRUE) :
664
+ (cond_196 && ~cond_197 && cond_195)? (`TRUE) :
665
+ (cond_200)? (`TRUE) :
666
+ (cond_213 && ~cond_214)? (`TRUE) :
667
+ (cond_217 && cond_3)? (`TRUE) :
668
+ (cond_219 && cond_3)? (`TRUE) :
669
+ (cond_227 && ~cond_16 && cond_228)? (`TRUE) :
670
+ (cond_231)? (`TRUE) :
671
+ (cond_246)? (`TRUE) :
672
+ (cond_249 && ~cond_38 && cond_39)? (`TRUE) :
673
+ 1'd0;
674
+ assign rd_glob_param_3_set =
675
+ (cond_15 && ~cond_16 && cond_17)? (`TRUE) :
676
+ (cond_22 && cond_25)? (`TRUE) :
677
+ (cond_79 && cond_83)? (`TRUE) :
678
+ (cond_89)? (`TRUE) :
679
+ (cond_91 && cond_92)? (`TRUE) :
680
+ (cond_97)? (`TRUE) :
681
+ (cond_157)? (`TRUE) :
682
+ (cond_187 && ~cond_188)? (`TRUE) :
683
+ (cond_209 && ~cond_16 && cond_17)? (`TRUE) :
684
+ 1'd0;
685
+ assign rd_glob_descriptor_value =
686
+ (cond_15 && ~cond_16 && cond_17)? ( read_8) :
687
+ (cond_19 && cond_20)? ( read_8) :
688
+ (cond_21 && ~cond_16 && cond_17)? ( read_8) :
689
+ (cond_62 && cond_20)? ( read_8) :
690
+ (cond_63 && ~cond_16 && cond_17)? ( read_8) :
691
+ (cond_66)? ( read_8) :
692
+ (cond_69 && cond_70)? ( `DESC_MASK_P | `DESC_MASK_DPL | `DESC_MASK_SEG | `DESC_MASK_DATA_RWA | { 24'd0, 4'd0, glob_param_1[15:12], glob_param_1[11:0], 4'd0, 16'hFFFF }) :
693
+ (cond_69 && cond_71)? ( `DESC_MASK_P | `DESC_MASK_SEG | { 24'd0, 4'd0, glob_param_1[15:12], glob_param_1[11:0], 4'd0, 16'd0 }) :
694
+ (cond_69 && cond_72)? ( `DESC_MASK_SEG | { 24'd0, 24'd0, 16'd0 }) :
695
+ (cond_73 && cond_74)? ( read_8) :
696
+ (cond_89 && ~cond_16 && cond_90)? ( read_8) :
697
+ (cond_179 && cond_180 && ~cond_9)? ( read_8) :
698
+ (cond_190 && ~cond_16 && cond_90)? ( read_8) :
699
+ (cond_204 && cond_17)? ( read_8) :
700
+ (cond_209 && ~cond_16 && cond_17)? ( read_8) :
701
+ (cond_211 && cond_20)? ( read_8) :
702
+ (cond_241 && ~cond_16 && cond_242)? ( read_8) :
703
+ (cond_243 && ~cond_16 && cond_70)? ( `DESC_MASK_P | `DESC_MASK_DPL | `DESC_MASK_SEG | `DESC_MASK_DATA_RWA | { 24'd0, 4'd0,glob_param_1[15:12], glob_param_1[11:0],4'd0, 16'hFFFF }) :
704
+ (cond_243 && ~cond_16 && ~cond_70 && cond_244)? ( read_8) :
705
+ 64'd0;
706
+ assign address_stack_add_4_to_saved =
707
+ (cond_95)? (`TRUE) :
708
+ 1'd0;
709
+ assign rd_dst_is_eip =
710
+ (cond_10)? (`TRUE) :
711
+ (cond_201)? (`TRUE) :
712
+ 1'd0;
713
+ assign rd_src_is_memory =
714
+ (cond_7 && cond_3)? (`TRUE) :
715
+ (cond_11)? (`TRUE) :
716
+ (cond_30 && cond_3 && ~cond_9)? (`TRUE) :
717
+ (cond_35 && ~cond_36)? (`TRUE) :
718
+ (cond_37 && ~cond_38 && cond_39)? (`TRUE) :
719
+ (cond_95)? (`TRUE) :
720
+ (cond_103)? (`TRUE) :
721
+ (cond_105)? (`TRUE) :
722
+ (cond_107 && cond_3 && ~cond_109)? (`TRUE) :
723
+ (cond_114 && ~cond_38 && cond_39)? (`TRUE) :
724
+ (cond_115 && cond_39)? (`TRUE) :
725
+ (cond_117 && cond_118 && cond_3)? (`TRUE) :
726
+ (cond_121 && cond_118)? (`TRUE) :
727
+ (cond_132)? (`TRUE) :
728
+ (cond_133 && cond_3)? (`TRUE) :
729
+ (cond_135 && cond_3 && ~cond_137)? (`TRUE) :
730
+ (cond_138 && ~cond_9)? (`TRUE) :
731
+ (cond_143 && cond_3)? ( rd_arith_modregrm_to_reg) :
732
+ (cond_150 && cond_3)? (`TRUE) :
733
+ (cond_162 && ~cond_38 && cond_39)? (`TRUE) :
734
+ (cond_169 && cond_3)? (`TRUE) :
735
+ (cond_198 && ~cond_38 && cond_199)? (`TRUE) :
736
+ (cond_205 && cond_3)? (`TRUE) :
737
+ (cond_206)? (`TRUE) :
738
+ (cond_213 && cond_214)? (`TRUE) :
739
+ (cond_216 && cond_3)? (`TRUE) :
740
+ (cond_222)? (`TRUE) :
741
+ (cond_224)? (`TRUE) :
742
+ (cond_225)? (`TRUE) :
743
+ (cond_232 && cond_236 && ~cond_9)? (`TRUE) :
744
+ (cond_237 && cond_238)? (`TRUE) :
745
+ (cond_239 && ~cond_16 && cond_240)? (`TRUE) :
746
+ (cond_249 && ~cond_38 && cond_39)? (`TRUE) :
747
+ (cond_250 && cond_3)? (`TRUE) :
748
+ (cond_251 && ~cond_104)? (`TRUE) :
749
+ (cond_256)? (`TRUE) :
750
+ (cond_258 && cond_3)? (`TRUE) :
751
+ 1'd0;
752
+ assign read_system_qword =
753
+ (cond_66 && ~cond_16)? (`TRUE) :
754
+ 1'd0;
755
+ assign rd_dst_is_modregrm_imm =
756
+ (cond_133 && ~cond_134)? (`TRUE) :
757
+ 1'd0;
758
+ assign address_stack_pop =
759
+ (cond_43)? (`TRUE) :
760
+ (cond_75)? (`TRUE) :
761
+ (cond_79)? (`TRUE) :
762
+ (cond_103)? (`TRUE) :
763
+ (cond_105)? (`TRUE) :
764
+ (cond_158)? ( real_mode || v8086_mode) :
765
+ (cond_160)? ( real_mode || v8086_mode) :
766
+ (cond_222)? (`TRUE) :
767
+ (cond_251)? (`TRUE) :
768
+ 1'd0;
769
+ assign rd_req_reg_not_8bit =
770
+ (cond_250)? (`TRUE) :
771
+ 1'd0;
772
+ assign rd_dst_is_rm =
773
+ (cond_0 && cond_1)? (`TRUE) :
774
+ (cond_28 && cond_1)? (`TRUE) :
775
+ (cond_30 && cond_1)? (`TRUE) :
776
+ (cond_40 && cond_1 && ~cond_8)? (`TRUE) :
777
+ (cond_44 && cond_1)? (`TRUE) :
778
+ (cond_55 && cond_56 && cond_1)? (`TRUE) :
779
+ (cond_76 && cond_1)? (`TRUE) :
780
+ (cond_106 && cond_1)? (`TRUE) :
781
+ (cond_110 && cond_1)? (`TRUE) :
782
+ (cond_111 && cond_1)? (`TRUE) :
783
+ (cond_116 && cond_1)? (`TRUE) :
784
+ (cond_120)? (`TRUE) :
785
+ (cond_126 && cond_1)? (`TRUE) :
786
+ (cond_127 && cond_1 && ~cond_2)? (`TRUE) :
787
+ (cond_139 && cond_1)? (`TRUE) :
788
+ (cond_140 && cond_1)? (`TRUE) :
789
+ (cond_143 && cond_1)? ( rd_arith_modregrm_to_rm) :
790
+ (cond_147 && cond_1)? (`TRUE) :
791
+ (cond_154 && cond_1)? (`TRUE) :
792
+ (cond_155 && cond_1)? (`TRUE) :
793
+ (cond_165 && cond_1)? (`TRUE) :
794
+ (cond_177 && cond_1)? (`TRUE) :
795
+ (cond_178 && cond_1 && ~cond_8)? (`TRUE) :
796
+ (cond_217 && cond_1)? (`TRUE) :
797
+ (cond_219 && cond_1)? (`TRUE) :
798
+ (cond_254)? (`TRUE) :
799
+ 1'd0;
800
+ assign rd_req_edx =
801
+ (cond_172)? (`TRUE) :
802
+ (cond_221)? ( rd_cmd == `CMD_CWD) :
803
+ 1'd0;
804
+ assign rd_src_is_io =
805
+ (cond_173 && ~cond_174 && cond_175)? (`TRUE) :
806
+ (cond_196 && ~cond_197 && cond_195)? (`TRUE) :
807
+ 1'd0;
808
+ assign rd_src_is_eax =
809
+ (cond_163)? (`TRUE) :
810
+ (cond_191 && ~cond_192 && cond_39)? (`TRUE) :
811
+ (cond_212)? (`TRUE) :
812
+ (cond_213 && ~cond_214)? (`TRUE) :
813
+ 1'd0;
814
+ assign address_stack_for_ret_second =
815
+ (cond_157)? (`TRUE) :
816
+ 1'd0;
817
+ assign rd_glob_param_1_set =
818
+ (cond_18 && ~cond_16)? (`TRUE) :
819
+ (cond_51 && cond_52)? (`TRUE) :
820
+ (cond_53 && cond_50)? (`TRUE) :
821
+ (cond_55 && cond_56 && cond_1 && cond_57)? (`TRUE) :
822
+ (cond_55 && cond_56 && cond_1 && cond_58)? (`TRUE) :
823
+ (cond_55 && cond_56 && cond_1 && cond_59)? (`TRUE) :
824
+ (cond_55 && cond_56 && cond_3 && ~cond_9 && cond_57)? (`TRUE) :
825
+ (cond_55 && cond_56 && cond_3 && ~cond_9 && cond_58)? (`TRUE) :
826
+ (cond_55 && cond_56 && cond_3 && ~cond_9 && cond_59)? (`TRUE) :
827
+ (cond_61 && ~cond_16)? (`TRUE) :
828
+ (cond_65)? (`TRUE) :
829
+ (cond_75)? (`TRUE) :
830
+ (cond_79 && cond_82)? (`TRUE) :
831
+ (cond_88)? (`TRUE) :
832
+ (cond_91 && cond_93)? (`TRUE) :
833
+ (cond_97)? ( rd_ready) :
834
+ (cond_157)? ( rd_ready) :
835
+ (cond_158 && ~cond_9 && cond_72)? (`TRUE) :
836
+ (cond_160 && ~cond_9 && cond_159)? (`TRUE) :
837
+ (cond_178 && cond_1 && ~cond_8)? (`TRUE) :
838
+ (cond_178 && cond_3 && ~cond_9)? (`TRUE) :
839
+ (cond_203 && ~cond_16)? (`TRUE) :
840
+ (cond_210 && ~cond_16)? (`TRUE) :
841
+ 1'd0;
842
+ assign rd_glob_param_4_set =
843
+ (cond_98 && cond_99)? (`TRUE) :
844
+ (cond_161)? (`TRUE) :
845
+ (cond_189)? (`TRUE) :
846
+ 1'd0;
847
+ assign address_stack_pop_next =
848
+ (cond_22)? (`TRUE) :
849
+ (cond_91)? (`TRUE) :
850
+ (cond_95)? (`TRUE) :
851
+ (cond_97)? (`TRUE) :
852
+ (cond_98)? (`TRUE) :
853
+ (cond_157)? (`TRUE) :
854
+ (cond_158)? ( protected_mode) :
855
+ (cond_160)? ( protected_mode) :
856
+ (cond_161)? (`TRUE) :
857
+ 1'd0;
858
+ assign rd_req_edi =
859
+ (cond_37 && ~cond_38 && cond_39 && ~cond_5)? (`TRUE) :
860
+ (cond_114 && ~cond_38 && cond_39)? (`TRUE) :
861
+ (cond_115 && cond_39)? (`TRUE) :
862
+ (cond_191 && ~cond_192 && cond_39)? (`TRUE) :
863
+ (cond_196 && ~cond_197 && cond_195)? (`TRUE) :
864
+ (cond_249 && ~cond_38 && cond_39)? (`TRUE) :
865
+ 1'd0;
866
+ assign rd_glob_descriptor_set =
867
+ (cond_15 && ~cond_16 && cond_17)? (`TRUE) :
868
+ (cond_19 && cond_20)? (`TRUE) :
869
+ (cond_21 && ~cond_16 && cond_17)? (`TRUE) :
870
+ (cond_62 && cond_20)? (`TRUE) :
871
+ (cond_63 && ~cond_16 && cond_17)? (`TRUE) :
872
+ (cond_66)? (`TRUE) :
873
+ (cond_69 && cond_70)? (`TRUE) :
874
+ (cond_69 && cond_71)? (`TRUE) :
875
+ (cond_69 && cond_72)? (`TRUE) :
876
+ (cond_73 && cond_74)? (`TRUE) :
877
+ (cond_89 && ~cond_16 && cond_90)? (`TRUE) :
878
+ (cond_179 && cond_180 && ~cond_9)? (`TRUE) :
879
+ (cond_190 && ~cond_16 && cond_90)? (`TRUE) :
880
+ (cond_204 && cond_17)? (`TRUE) :
881
+ (cond_209 && ~cond_16 && cond_17)? (`TRUE) :
882
+ (cond_211 && cond_20)? (`TRUE) :
883
+ (cond_241 && ~cond_16 && cond_242)? (`TRUE) :
884
+ (cond_243 && ~cond_16 && cond_70)? (`TRUE) :
885
+ (cond_243 && ~cond_16 && ~cond_70 && cond_244)? (`TRUE) :
886
+ 1'd0;
887
+ assign read_system_word =
888
+ (cond_33 && ~cond_34)? (`TRUE) :
889
+ (cond_35 && ~cond_36)? (`TRUE) :
890
+ (cond_64 && ~cond_16)? (`TRUE) :
891
+ (cond_65 && ~cond_16)? (`TRUE) :
892
+ (cond_88)? (`TRUE) :
893
+ (cond_187 && ~cond_188)? (`TRUE) :
894
+ (cond_189)? ( ~(rd_ss_esp_from_tss_386)) :
895
+ (cond_232 && cond_236 && ~cond_9)? ( glob_descriptor[`DESC_BITS_TYPE] <= 4'd3) :
896
+ (cond_237 && cond_238)? ( glob_descriptor[`DESC_BITS_TYPE] <= 4'd3 || rd_cmdex > `CMDEX_task_switch_3_STEP_7) :
897
+ 1'd0;
898
+ assign address_enter_last =
899
+ (cond_130)? (`TRUE) :
900
+ 1'd0;
901
+ assign rd_dst_is_memory_last =
902
+ (cond_115 && cond_39)? (`TRUE) :
903
+ 1'd0;
904
+ assign read_system_descriptor =
905
+ (cond_15 && ~cond_16 && cond_17)? (`TRUE) :
906
+ (cond_19 && cond_20)? (`TRUE) :
907
+ (cond_21 && ~cond_16 && cond_17)? (`TRUE) :
908
+ (cond_62 && cond_20)? (`TRUE) :
909
+ (cond_63 && ~cond_16 && cond_17)? (`TRUE) :
910
+ (cond_73 && cond_74 && ~cond_16)? (`TRUE) :
911
+ (cond_89 && ~cond_16 && cond_90)? (`TRUE) :
912
+ (cond_179 && cond_180 && ~cond_9)? (`TRUE) :
913
+ (cond_190 && ~cond_16 && cond_90)? (`TRUE) :
914
+ (cond_204 && cond_17)? (`TRUE) :
915
+ (cond_209 && ~cond_16 && cond_17)? (`TRUE) :
916
+ (cond_211 && cond_20)? (`TRUE) :
917
+ (cond_241 && ~cond_16 && cond_242)? (`TRUE) :
918
+ (cond_243 && ~cond_16 && ~cond_70 && cond_244)? (`TRUE) :
919
+ 1'd0;
920
+ assign address_edi =
921
+ (cond_37)? (`TRUE) :
922
+ (cond_115)? (`TRUE) :
923
+ (cond_193)? (`TRUE) :
924
+ 1'd0;
925
+ assign rd_waiting =
926
+ (cond_0 && cond_1 && cond_2)? (`TRUE) :
927
+ (cond_0 && cond_3 && cond_4)? (`TRUE) :
928
+ (cond_0 && cond_3 && ~cond_4 && cond_5)? (`TRUE) :
929
+ (cond_7 && cond_1 && cond_8)? (`TRUE) :
930
+ (cond_7 && cond_3 && cond_9)? (`TRUE) :
931
+ (cond_7 && cond_3 && ~cond_9 && cond_5)? (`TRUE) :
932
+ (cond_11 && cond_9)? (`TRUE) :
933
+ (cond_11 && ~cond_9 && cond_5)? (`TRUE) :
934
+ (cond_15 && cond_16)? (`TRUE) :
935
+ (cond_15 && ~cond_16 && cond_17 && cond_5)? (`TRUE) :
936
+ (cond_18 && cond_16)? (`TRUE) :
937
+ (cond_19 && cond_20 && cond_5)? (`TRUE) :
938
+ (cond_21 && cond_16)? (`TRUE) :
939
+ (cond_21 && ~cond_16 && cond_17 && cond_5)? (`TRUE) :
940
+ (cond_22 && cond_16)? (`TRUE) :
941
+ (cond_22 && ~cond_16 && cond_5)? (`TRUE) :
942
+ (cond_28 && cond_3 && cond_9)? (`TRUE) :
943
+ (cond_28 && cond_3 && ~cond_9 && cond_29)? (`TRUE) :
944
+ (cond_30 && cond_1 && cond_8)? (`TRUE) :
945
+ (cond_30 && cond_3 && cond_9)? (`TRUE) :
946
+ (cond_30 && cond_3 && ~cond_9 && cond_5)? (`TRUE) :
947
+ (cond_31 && cond_32)? (`TRUE) :
948
+ (cond_33 && cond_34)? (`TRUE) :
949
+ (cond_33 && ~cond_34 && cond_5)? (`TRUE) :
950
+ (cond_35 && cond_36)? (`TRUE) :
951
+ (cond_35 && ~cond_36 && cond_5)? (`TRUE) :
952
+ (cond_37 && cond_38)? (`TRUE) :
953
+ (cond_37 && ~cond_38 && cond_39 && cond_5)? (`TRUE) :
954
+ (cond_40 && cond_1 && cond_8)? (`TRUE) :
955
+ (cond_40 && cond_3 && cond_9)? (`TRUE) :
956
+ (cond_40 && cond_3 && ~cond_9 && cond_5)? (`TRUE) :
957
+ (cond_41 && cond_42)? (`TRUE) :
958
+ (cond_43 && cond_9)? (`TRUE) :
959
+ (cond_43 && ~cond_9 && cond_5)? (`TRUE) :
960
+ (cond_44 && cond_1 && cond_45)? (`TRUE) :
961
+ (cond_44 && cond_3 && cond_46)? (`TRUE) :
962
+ (cond_44 && cond_3 && ~cond_46 && cond_5)? (`TRUE) :
963
+ (cond_47 && cond_42)? (`TRUE) :
964
+ (cond_48 && cond_49)? (`TRUE) :
965
+ (cond_48 && ~cond_49 && cond_50 && cond_5)? (`TRUE) :
966
+ (cond_51 && cond_52 && cond_5)? (`TRUE) :
967
+ (cond_53 && cond_5)? (`TRUE) :
968
+ (cond_55 && cond_56 && cond_1 && cond_8)? (`TRUE) :
969
+ (cond_55 && cond_56 && cond_3 && cond_9)? (`TRUE) :
970
+ (cond_55 && cond_56 && cond_3 && ~cond_9 && cond_5)? (`TRUE) :
971
+ (cond_61 && cond_16)? (`TRUE) :
972
+ (cond_62 && cond_20 && cond_5)? (`TRUE) :
973
+ (cond_63 && cond_16)? (`TRUE) :
974
+ (cond_63 && ~cond_16 && cond_17 && cond_5)? (`TRUE) :
975
+ (cond_64 && cond_16)? (`TRUE) :
976
+ (cond_64 && ~cond_16 && cond_5)? (`TRUE) :
977
+ (cond_65 && cond_16)? (`TRUE) :
978
+ (cond_65 && ~cond_16 && cond_5)? (`TRUE) :
979
+ (cond_66 && cond_16)? (`TRUE) :
980
+ (cond_66 && ~cond_16 && cond_5)? (`TRUE) :
981
+ (cond_67 && cond_68)? (`TRUE) :
982
+ (cond_73 && cond_74 && cond_16)? (`TRUE) :
983
+ (cond_73 && cond_74 && ~cond_16 && cond_5)? (`TRUE) :
984
+ (cond_75 && cond_9)? (`TRUE) :
985
+ (cond_75 && ~cond_9 && cond_5)? (`TRUE) :
986
+ (cond_76 && cond_1 && cond_77)? (`TRUE) :
987
+ (cond_76 && cond_3 && cond_78)? (`TRUE) :
988
+ (cond_76 && cond_3 && ~cond_78 && cond_5)? (`TRUE) :
989
+ (cond_79 && cond_84)? (`TRUE) :
990
+ (cond_79 && ~cond_84 && cond_85 && cond_5)? (`TRUE) :
991
+ (cond_86 && cond_87)? (`TRUE) :
992
+ (cond_88 && cond_5)? (`TRUE) :
993
+ (cond_89 && cond_16)? (`TRUE) :
994
+ (cond_89 && ~cond_16 && cond_90 && cond_5)? (`TRUE) :
995
+ (cond_91 && cond_5)? (`TRUE) :
996
+ (cond_95 && cond_5)? (`TRUE) :
997
+ (cond_97 && cond_5)? (`TRUE) :
998
+ (cond_98 && cond_5)? (`TRUE) :
999
+ (cond_102 && cond_16)? (`TRUE) :
1000
+ (cond_103 && cond_104)? (`TRUE) :
1001
+ (cond_103 && ~cond_104 && cond_5)? (`TRUE) :
1002
+ (cond_105 && cond_104)? (`TRUE) :
1003
+ (cond_105 && ~cond_104 && cond_5)? (`TRUE) :
1004
+ (cond_106 && cond_3 && cond_29)? (`TRUE) :
1005
+ (cond_107 && cond_1 && cond_108)? (`TRUE) :
1006
+ (cond_107 && cond_3 && cond_109)? (`TRUE) :
1007
+ (cond_107 && cond_3 && ~cond_109 && cond_5)? (`TRUE) :
1008
+ (cond_110 && cond_1 && cond_8)? (`TRUE) :
1009
+ (cond_110 && cond_3 && cond_9)? (`TRUE) :
1010
+ (cond_110 && cond_3 && ~cond_9 && cond_5)? (`TRUE) :
1011
+ (cond_111 && cond_1 && cond_112)? (`TRUE) :
1012
+ (cond_111 && cond_3 && cond_113)? (`TRUE) :
1013
+ (cond_111 && cond_3 && ~cond_113 && cond_5)? (`TRUE) :
1014
+ (cond_114 && cond_38)? (`TRUE) :
1015
+ (cond_114 && ~cond_38 && cond_39 && cond_5)? (`TRUE) :
1016
+ (cond_115 && cond_39 && cond_5)? (`TRUE) :
1017
+ (cond_116 && cond_3 && cond_29)? (`TRUE) :
1018
+ (cond_117 && cond_118 && cond_1 && cond_8)? (`TRUE) :
1019
+ (cond_117 && cond_118 && cond_3 && cond_9)? (`TRUE) :
1020
+ (cond_117 && cond_118 && cond_3 && ~cond_9 && cond_5)? (`TRUE) :
1021
+ (cond_119 && cond_8)? (`TRUE) :
1022
+ (cond_121 && cond_118 && cond_9)? (`TRUE) :
1023
+ (cond_121 && cond_118 && ~cond_9 && cond_5)? (`TRUE) :
1024
+ (cond_124 && cond_125)? (`TRUE) :
1025
+ (cond_126 && cond_3 && cond_29)? (`TRUE) :
1026
+ (cond_127 && cond_1 && cond_2)? (`TRUE) :
1027
+ (cond_127 && cond_3 && cond_4)? (`TRUE) :
1028
+ (cond_127 && cond_3 && ~cond_4 && cond_5)? (`TRUE) :
1029
+ (cond_128 && cond_129)? (`TRUE) :
1030
+ (cond_130 && cond_5)? (`TRUE) :
1031
+ (cond_132 && cond_5)? (`TRUE) :
1032
+ (cond_133 && cond_1 && cond_8)? (`TRUE) :
1033
+ (cond_133 && cond_3 && cond_9)? (`TRUE) :
1034
+ (cond_133 && cond_3 && ~cond_9 && cond_5)? (`TRUE) :
1035
+ (cond_135 && cond_1 && cond_136)? (`TRUE) :
1036
+ (cond_135 && cond_3 && cond_137)? (`TRUE) :
1037
+ (cond_135 && cond_3 && ~cond_137 && cond_5)? (`TRUE) :
1038
+ (cond_138 && cond_9)? (`TRUE) :
1039
+ (cond_138 && ~cond_9 && cond_5)? (`TRUE) :
1040
+ (cond_139 && cond_1 && cond_45)? (`TRUE) :
1041
+ (cond_139 && cond_3 && cond_46)? (`TRUE) :
1042
+ (cond_139 && cond_3 && ~cond_46 && cond_5)? (`TRUE) :
1043
+ (cond_140 && cond_1 && cond_141)? (`TRUE) :
1044
+ (cond_140 && cond_3 && cond_142)? (`TRUE) :
1045
+ (cond_140 && cond_3 && ~cond_142 && cond_5)? (`TRUE) :
1046
+ (cond_143 && cond_1 && cond_2)? (`TRUE) :
1047
+ (cond_143 && cond_3 && cond_46)? (`TRUE) :
1048
+ (cond_143 && cond_3 && ~cond_46 && cond_5)? (`TRUE) :
1049
+ (cond_147 && cond_1 && cond_8)? (`TRUE) :
1050
+ (cond_147 && cond_3 && cond_9)? (`TRUE) :
1051
+ (cond_147 && cond_3 && ~cond_9 && cond_5)? (`TRUE) :
1052
+ (cond_149 && cond_68)? (`TRUE) :
1053
+ (cond_150 && cond_1 && cond_151)? (`TRUE) :
1054
+ (cond_150 && cond_3 && cond_152)? (`TRUE) :
1055
+ (cond_150 && cond_3 && ~cond_152 && cond_5)? (`TRUE) :
1056
+ (cond_154 && cond_1 && cond_2)? (`TRUE) :
1057
+ (cond_154 && cond_3 && cond_46)? (`TRUE) :
1058
+ (cond_154 && cond_3 && ~cond_46 && cond_5)? (`TRUE) :
1059
+ (cond_155 && cond_1 && cond_8)? (`TRUE) :
1060
+ (cond_155 && cond_3 && cond_9)? (`TRUE) :
1061
+ (cond_155 && cond_3 && ~cond_9 && cond_5)? (`TRUE) :
1062
+ (cond_156 && cond_68)? (`TRUE) :
1063
+ (cond_157 && cond_5)? (`TRUE) :
1064
+ (cond_158 && cond_9)? (`TRUE) :
1065
+ (cond_158 && ~cond_9 && cond_5)? (`TRUE) :
1066
+ (cond_160 && cond_9)? (`TRUE) :
1067
+ (cond_160 && ~cond_9 && cond_5)? (`TRUE) :
1068
+ (cond_161 && cond_5)? (`TRUE) :
1069
+ (cond_162 && cond_38)? (`TRUE) :
1070
+ (cond_162 && ~cond_38 && cond_39 && cond_5)? (`TRUE) :
1071
+ (cond_163 && cond_164)? (`TRUE) :
1072
+ (cond_165 && cond_1 && cond_2)? (`TRUE) :
1073
+ (cond_165 && cond_3 && cond_4)? (`TRUE) :
1074
+ (cond_165 && cond_3 && ~cond_4 && cond_5)? (`TRUE) :
1075
+ (cond_168 && cond_42)? (`TRUE) :
1076
+ (cond_169 && cond_1 && cond_8)? (`TRUE) :
1077
+ (cond_169 && cond_3 && cond_9)? (`TRUE) :
1078
+ (cond_169 && cond_3 && ~cond_9 && cond_5)? (`TRUE) :
1079
+ (cond_170 && cond_171)? (`TRUE) :
1080
+ (cond_172 && cond_68)? (`TRUE) :
1081
+ (cond_173 && cond_174)? (`TRUE) :
1082
+ (cond_173 && ~cond_174 && cond_175 && cond_176)? (`TRUE) :
1083
+ (cond_177 && cond_1 && cond_8)? (`TRUE) :
1084
+ (cond_177 && cond_3 && cond_9)? (`TRUE) :
1085
+ (cond_177 && cond_3 && ~cond_9 && cond_5)? (`TRUE) :
1086
+ (cond_178 && cond_1 && cond_8)? (`TRUE) :
1087
+ (cond_178 && cond_3 && cond_9)? (`TRUE) :
1088
+ (cond_178 && cond_3 && ~cond_9 && cond_5)? (`TRUE) :
1089
+ (cond_179 && cond_180 && cond_9)? (`TRUE) :
1090
+ (cond_179 && cond_180 && ~cond_9 && cond_5)? (`TRUE) :
1091
+ (cond_181 && cond_183)? (`TRUE) :
1092
+ (cond_185 && cond_183)? (`TRUE) :
1093
+ (cond_187 && cond_188)? (`TRUE) :
1094
+ (cond_187 && ~cond_188 && cond_5)? (`TRUE) :
1095
+ (cond_189 && cond_5)? (`TRUE) :
1096
+ (cond_190 && cond_16)? (`TRUE) :
1097
+ (cond_190 && ~cond_16 && cond_90 && cond_5)? (`TRUE) :
1098
+ (cond_191 && cond_192)? (`TRUE) :
1099
+ (cond_193 && cond_194)? (`TRUE) :
1100
+ (cond_193 && ~cond_194 && cond_195 && cond_5)? (`TRUE) :
1101
+ (cond_196 && cond_197)? (`TRUE) :
1102
+ (cond_196 && ~cond_197 && cond_195 && cond_176)? (`TRUE) :
1103
+ (cond_198 && cond_38)? (`TRUE) :
1104
+ (cond_198 && ~cond_38 && cond_199 && cond_5)? (`TRUE) :
1105
+ (cond_203 && cond_16)? (`TRUE) :
1106
+ (cond_204 && cond_17 && cond_5)? (`TRUE) :
1107
+ (cond_205 && cond_1 && cond_8)? (`TRUE) :
1108
+ (cond_205 && cond_3 && cond_9)? (`TRUE) :
1109
+ (cond_205 && cond_3 && ~cond_9 && cond_5)? (`TRUE) :
1110
+ (cond_206 && cond_9)? (`TRUE) :
1111
+ (cond_206 && ~cond_9 && cond_5)? (`TRUE) :
1112
+ (cond_209 && cond_16)? (`TRUE) :
1113
+ (cond_209 && ~cond_16 && cond_17 && cond_5)? (`TRUE) :
1114
+ (cond_210 && cond_16)? (`TRUE) :
1115
+ (cond_211 && cond_20 && cond_5)? (`TRUE) :
1116
+ (cond_212 && cond_68)? (`TRUE) :
1117
+ (cond_213 && cond_214 && cond_9)? (`TRUE) :
1118
+ (cond_213 && cond_214 && ~cond_9 && cond_5)? (`TRUE) :
1119
+ (cond_213 && ~cond_214 && cond_215)? (`TRUE) :
1120
+ (cond_216 && cond_1 && cond_8)? (`TRUE) :
1121
+ (cond_216 && cond_3 && cond_9)? (`TRUE) :
1122
+ (cond_216 && cond_3 && ~cond_9 && cond_5)? (`TRUE) :
1123
+ (cond_217 && cond_1 && cond_218)? (`TRUE) :
1124
+ (cond_217 && cond_3 && cond_218)? (`TRUE) :
1125
+ (cond_217 && cond_3 && ~cond_218 && cond_29)? (`TRUE) :
1126
+ (cond_219 && cond_1 && cond_218)? (`TRUE) :
1127
+ (cond_219 && cond_3 && cond_218)? (`TRUE) :
1128
+ (cond_219 && cond_3 && ~cond_218 && cond_29)? (`TRUE) :
1129
+ (cond_222 && cond_9)? (`TRUE) :
1130
+ (cond_222 && ~cond_9 && cond_5)? (`TRUE) :
1131
+ (cond_224 && cond_9)? (`TRUE) :
1132
+ (cond_224 && ~cond_9 && cond_5)? (`TRUE) :
1133
+ (cond_225 && cond_9)? (`TRUE) :
1134
+ (cond_225 && ~cond_9 && cond_5)? (`TRUE) :
1135
+ (cond_227 && cond_16)? (`TRUE) :
1136
+ (cond_227 && ~cond_16 && cond_228 && cond_9)? (`TRUE) :
1137
+ (cond_227 && ~cond_16 && cond_228 && ~cond_9 && cond_5)? (`TRUE) :
1138
+ (cond_229 && cond_9)? (`TRUE) :
1139
+ (cond_232 && cond_236 && cond_9)? (`TRUE) :
1140
+ (cond_232 && cond_236 && ~cond_9 && cond_5)? (`TRUE) :
1141
+ (cond_237 && cond_238 && cond_5)? (`TRUE) :
1142
+ (cond_239 && cond_16)? (`TRUE) :
1143
+ (cond_239 && ~cond_16 && cond_240 && cond_5)? (`TRUE) :
1144
+ (cond_241 && cond_16)? (`TRUE) :
1145
+ (cond_241 && ~cond_16 && cond_242 && cond_5)? (`TRUE) :
1146
+ (cond_243 && cond_16)? (`TRUE) :
1147
+ (cond_243 && ~cond_16 && ~cond_70 && cond_244 && cond_5)? (`TRUE) :
1148
+ (cond_245 && cond_32)? (`TRUE) :
1149
+ (cond_246 && cond_29)? (`TRUE) :
1150
+ (cond_249 && cond_38)? (`TRUE) :
1151
+ (cond_249 && ~cond_38 && cond_39 && cond_5)? (`TRUE) :
1152
+ (cond_250 && cond_1 && cond_8)? (`TRUE) :
1153
+ (cond_250 && cond_3 && cond_9)? (`TRUE) :
1154
+ (cond_250 && cond_3 && ~cond_9 && cond_5)? (`TRUE) :
1155
+ (cond_251 && cond_104)? (`TRUE) :
1156
+ (cond_251 && ~cond_104 && cond_5)? (`TRUE) :
1157
+ (cond_254 && cond_16)? (`TRUE) :
1158
+ (cond_255 && cond_16)? (`TRUE) :
1159
+ (cond_256 && cond_9)? (`TRUE) :
1160
+ (cond_256 && ~cond_9 && cond_5)? (`TRUE) :
1161
+ (cond_257 && cond_68)? (`TRUE) :
1162
+ (cond_258 && cond_1 && cond_8)? (`TRUE) :
1163
+ (cond_258 && cond_3 && cond_9)? (`TRUE) :
1164
+ (cond_258 && cond_3 && ~cond_9 && cond_5)? (`TRUE) :
1165
+ 1'd0;
1166
+ assign address_ea_buffer =
1167
+ (cond_11 && cond_12)? (`TRUE) :
1168
+ (cond_51)? (`TRUE) :
1169
+ (cond_53 && cond_50)? (`TRUE) :
1170
+ (cond_121 && cond_123)? (`TRUE) :
1171
+ (cond_206 && cond_207)? (`TRUE) :
1172
+ (cond_225)? (`TRUE) :
1173
+ (cond_246 && cond_248)? (`TRUE) :
1174
+ 1'd0;
1175
+ assign address_stack_for_iret_to_v86 =
1176
+ (cond_95 && cond_96)? (`TRUE) :
1177
+ 1'd0;
1178
+ assign address_stack_for_iret_second =
1179
+ (cond_97)? (`TRUE) :
1180
+ 1'd0;
1181
+ assign address_stack_for_iret_first =
1182
+ (cond_91 && cond_92)? (`TRUE) :
1183
+ 1'd0;
1184
+ assign rd_req_ecx =
1185
+ (cond_153)? (`TRUE) :
1186
+ (cond_172)? (`TRUE) :
1187
+ 1'd0;
1188
+ assign read_rmw_system_dword =
1189
+ (cond_227 && ~cond_16 && cond_228 && ~cond_9)? (`TRUE) :
1190
+ (cond_239 && ~cond_16 && cond_240)? (`TRUE) :
1191
+ 1'd0;
1192
+ assign rd_src_is_imm_se =
1193
+ (cond_201)? (`TRUE) :
1194
+ 1'd0;
1195
+ assign rd_glob_param_2_value =
1196
+ (cond_43)? ( (rd_operand_16bit)? { 16'd0, read_4[15:0] } : read_4) :
1197
+ (cond_48 && ~cond_49 && cond_50)? ( read_4) :
1198
+ (cond_53 && ~cond_50)? ( read_4) :
1199
+ (cond_64)? ( { 16'd0, read_4[15:0] }) :
1200
+ (cond_79 && cond_81)? ( (rd_operand_16bit)? { 16'd0, read_4[15:0] } : read_4) :
1201
+ (cond_89 && ~cond_16 && cond_90)? ( 32'd0) :
1202
+ (cond_89 && ~cond_16 && ~cond_90)? ( { 30'd0, rd_descriptor_not_in_limits, glob_param_1[15:2] == 14'd0 }) :
1203
+ (cond_91 && cond_94)? ( (rd_operand_16bit)? { 16'd0, read_4[15:0] } : read_4) :
1204
+ (cond_98 && cond_101)? ( (rd_operand_16bit)? { 16'd0, read_4[15:0] } : read_4) :
1205
+ (cond_158 && ~cond_9 && cond_159)? ( (rd_operand_16bit)? { 16'd0, read_4[15:0] } : read_4) :
1206
+ (cond_160 && ~cond_9 && cond_72)? ( (rd_operand_16bit)? { 16'd0, read_4[15:0] } : read_4) :
1207
+ (cond_179 && cond_180 && ~cond_9)? ( 32'd0) :
1208
+ (cond_179 && ~cond_180)? ( { 30'd0, rd_descriptor_not_in_limits, glob_param_1[15:2] == 14'd0 }) :
1209
+ (cond_203 && ~cond_16)? ( (glob_descriptor[`DESC_BITS_TYPE] == `DESC_CALL_GATE_386)? { glob_descriptor[63:48], glob_descriptor[15:0] } : { 16'd0, glob_descriptor[15:0] }) :
1210
+ (cond_227 && ~cond_16 && cond_228)? ( read_4) :
1211
+ (cond_241 && ~cond_16 && cond_242)? ( 32'd0) :
1212
+ (cond_241 && ~cond_16 && ~cond_242)? ( { 29'd0, glob_param_1[`SELECTOR_BIT_TI], rd_descriptor_not_in_limits, glob_param_1[15:2] == 14'd0 }) :
1213
+ (cond_243 && ~cond_16 && cond_70)? ( 32'd0) :
1214
+ (cond_243 && ~cond_16 && ~cond_70 && cond_244)? ( 32'd0) :
1215
+ (cond_243 && ~cond_16 && ~cond_70 && ~cond_244)? ( { 30'd0, rd_descriptor_not_in_limits, glob_param_1[15:2] == 14'd0 }) :
1216
+ 32'd0;
1217
+ assign address_stack_pop_esp_prev =
1218
+ (cond_157)? (`TRUE) :
1219
+ 1'd0;
1220
+ assign read_length_word =
1221
+ (cond_11 && cond_12)? (`TRUE) :
1222
+ (cond_22 && cond_23)? (`TRUE) :
1223
+ (cond_44 && cond_3)? (`TRUE) :
1224
+ (cond_51 && cond_52)? (`TRUE) :
1225
+ (cond_55 && cond_56 && cond_3)? (`TRUE) :
1226
+ (cond_75)? (`TRUE) :
1227
+ (cond_97)? (`TRUE) :
1228
+ (cond_117 && cond_118 && cond_3 && ~cond_9)? (`TRUE) :
1229
+ (cond_121 && cond_122)? (`TRUE) :
1230
+ (cond_157)? (`TRUE) :
1231
+ (cond_178 && cond_3)? (`TRUE) :
1232
+ (cond_179 && cond_180)? (`TRUE) :
1233
+ (cond_206 && cond_207)? (`TRUE) :
1234
+ (cond_246 && cond_247)? (`TRUE) :
1235
+ (cond_250 && cond_3)? (`TRUE) :
1236
+ 1'd0;
1237
+ assign address_xlat_transform =
1238
+ (cond_256)? (`TRUE) :
1239
+ 1'd0;
1240
+ assign address_enter =
1241
+ (cond_132)? (`TRUE) :
1242
+ 1'd0;
1243
+ assign rd_src_is_rm =
1244
+ (cond_7 && cond_1)? (`TRUE) :
1245
+ (cond_30 && cond_1)? (`TRUE) :
1246
+ (cond_107 && cond_1)? (`TRUE) :
1247
+ (cond_117 && cond_118 && cond_1)? (`TRUE) :
1248
+ (cond_119)? (`TRUE) :
1249
+ (cond_133 && cond_1)? (`TRUE) :
1250
+ (cond_135 && cond_1)? (`TRUE) :
1251
+ (cond_143 && cond_1)? ( rd_arith_modregrm_to_reg) :
1252
+ (cond_150 && cond_1)? (`TRUE) :
1253
+ (cond_169 && cond_1)? (`TRUE) :
1254
+ (cond_205 && cond_1)? (`TRUE) :
1255
+ (cond_216 && cond_1)? (`TRUE) :
1256
+ (cond_250 && cond_1)? (`TRUE) :
1257
+ (cond_255)? (`TRUE) :
1258
+ (cond_258 && cond_1)? (`TRUE) :
1259
+ 1'd0;
1260
+ assign rd_system_linear =
1261
+ (cond_33)? ( tr_base + 32'd102) :
1262
+ (cond_35)? ( tr_base + { 16'd0, rd_memory_last[15:0] } + { 16'd0, 3'd0, glob_param_1[15:3] }) :
1263
+ (cond_64)? ( idtr_base + { 22'd0, exc_vector[7:0], 2'b00 }) :
1264
+ (cond_65)? ( idtr_base + { 22'd0, exc_vector[7:0], 2'b10 }) :
1265
+ (cond_66)? ( idtr_base + { 21'd0, exc_vector[7:0], 3'b000 }) :
1266
+ (cond_88)? ( tr_base) :
1267
+ (cond_187)? ( tr_base + rd_offset_for_ss_from_tss) :
1268
+ (cond_189)? ( tr_base + rd_offset_for_esp_from_tss) :
1269
+ (cond_227)? ( gdtr_base + { 16'd0, tr[15:3], 3'd0 } + 32'd4) :
1270
+ (cond_232 && cond_233)? ( glob_desc_base + 32'd12) :
1271
+ (cond_232 && cond_234)? ( glob_desc_base + 32'h1C) :
1272
+ (cond_232 && cond_235)? ( rd_task_switch_linear_next) :
1273
+ (cond_237)? ( rd_task_switch_linear_next) :
1274
+ (cond_239)? ( gdtr_base + { 16'd0, glob_param_1[15:3], 3'd0 } + 32'd4) :
1275
+ 32'd0;
1276
+ assign rd_glob_param_1_value =
1277
+ (cond_18 && ~cond_16)? ( { 16'd0, glob_descriptor[31:16] }) :
1278
+ (cond_51 && cond_52)? ( { 13'd0, rd_decoder[4] & rd_decoder[2], (rd_decoder[6] & rd_decoder[0]) | rd_decoder[1], rd_decoder[0], read_4[15:0] }) :
1279
+ (cond_53 && cond_50)? ( { 13'd0, rd_decoder[4] & rd_decoder[2], (rd_decoder[6] & rd_decoder[0]) | rd_decoder[1], rd_decoder[0], read_4[15:0] }) :
1280
+ (cond_55 && cond_56 && cond_1 && cond_57)? ( { 13'd0, rd_decoder[13:11], dst_wire[15:0] }) :
1281
+ (cond_55 && cond_56 && cond_1 && cond_58)? ( { 13'd0, `SEGMENT_LDT, dst_wire[15:0] }) :
1282
+ (cond_55 && cond_56 && cond_1 && cond_59)? ( { 13'd0, `SEGMENT_TR, dst_wire[15:0] }) :
1283
+ (cond_55 && cond_56 && cond_3 && ~cond_9 && cond_57)? ( { 13'd0, rd_decoder[13:11], read_4[15:0] }) :
1284
+ (cond_55 && cond_56 && cond_3 && ~cond_9 && cond_58)? ( { 13'd0, `SEGMENT_LDT, read_4[15:0] }) :
1285
+ (cond_55 && cond_56 && cond_3 && ~cond_9 && cond_59)? ( { 13'd0, `SEGMENT_TR, read_4[15:0] }) :
1286
+ (cond_61 && ~cond_16)? ( { 16'd0, glob_descriptor[31:16] }) :
1287
+ (cond_65)? ( { 13'd0, `SEGMENT_CS, read_4[15:0] }) :
1288
+ (cond_75)? ( { 13'd0, rd_decoder[5:3], read_4[15:0] }) :
1289
+ (cond_79 && cond_82)? ( { 13'd0, `SEGMENT_CS, read_4[15:0] }) :
1290
+ (cond_88)? ( { 14'd0, `TASK_SWITCH_FROM_IRET, read_4[15:0] }) :
1291
+ (cond_91 && cond_93)? ( { `MC_PARAM_1_FLAG_NO_WRITE, `SEGMENT_CS, read_4[15:0] }) :
1292
+ (cond_97)? ( { `MC_PARAM_1_FLAG_NP_NOT_SS | `MC_PARAM_1_FLAG_CPL_FROM_PARAM_3, `SEGMENT_SS, read_4[15:0] }) :
1293
+ (cond_157)? ( { `MC_PARAM_1_FLAG_CPL_FROM_PARAM_3, `SEGMENT_SS, read_4[15:0] }) :
1294
+ (cond_158 && ~cond_9 && cond_72)? ( { `MC_PARAM_1_FLAG_NO_WRITE, `SEGMENT_CS, read_4[15:0] }) :
1295
+ (cond_160 && ~cond_9 && cond_159)? ( { `MC_PARAM_1_FLAG_NO_WRITE, `SEGMENT_CS, read_4[15:0] }) :
1296
+ (cond_178 && cond_1 && ~cond_8)? ( { 16'd0, dst_wire[15:0] }) :
1297
+ (cond_178 && cond_3 && ~cond_9)? ( { 16'd0, read_4[15:0] }) :
1298
+ (cond_203 && ~cond_16)? ( { 13'd0, `SEGMENT_CS, glob_descriptor[31:16] }) :
1299
+ (cond_210 && ~cond_16)? ( { 16'd0, glob_descriptor[31:16] }) :
1300
+ 32'd0;
1301
+ assign rd_glob_descriptor_2_value =
1302
+ (cond_97)? ( glob_descriptor) :
1303
+ (cond_157)? ( glob_descriptor) :
1304
+ 64'd0;
1305
+ assign rd_dst_is_modregrm_imm_se =
1306
+ (cond_133 && cond_134)? (`TRUE) :
1307
+ 1'd0;
1308
+ assign rd_dst_is_reg =
1309
+ (cond_6)? (`TRUE) :
1310
+ (cond_54)? (`TRUE) :
1311
+ (cond_133)? (`TRUE) :
1312
+ (cond_135)? ( rd_decoder[3]) :
1313
+ (cond_143)? ( rd_arith_modregrm_to_reg) :
1314
+ (cond_166)? (`TRUE) :
1315
+ (cond_181 && ~cond_183 && cond_184)? (`TRUE) :
1316
+ (cond_185 && ~cond_183 && cond_186)? (`TRUE) :
1317
+ (cond_216)? (`TRUE) :
1318
+ (cond_225)? (`TRUE) :
1319
+ (cond_245)? (`TRUE) :
1320
+ (cond_250)? (`TRUE) :
1321
+ (cond_258)? (`TRUE) :
1322
+ 1'd0;
1323
+ assign rd_src_is_implicit_reg =
1324
+ (cond_168)? (`TRUE) :
1325
+ 1'd0;
1326
+ assign address_enter_init =
1327
+ (cond_128)? (`TRUE) :
1328
+ 1'd0;
1329
+ assign rd_dst_is_memory =
1330
+ (cond_0 && cond_3)? (`TRUE) :
1331
+ (cond_28 && cond_3)? (`TRUE) :
1332
+ (cond_30 && cond_3 && ~cond_9)? (`TRUE) :
1333
+ (cond_40 && cond_3)? (`TRUE) :
1334
+ (cond_44 && cond_3)? (`TRUE) :
1335
+ (cond_76 && cond_3)? (`TRUE) :
1336
+ (cond_106 && cond_3)? (`TRUE) :
1337
+ (cond_110 && cond_3)? (`TRUE) :
1338
+ (cond_111 && cond_3)? (`TRUE) :
1339
+ (cond_116 && cond_3)? (`TRUE) :
1340
+ (cond_126 && cond_3)? (`TRUE) :
1341
+ (cond_127 && cond_3 && ~cond_4)? (`TRUE) :
1342
+ (cond_139 && cond_3)? (`TRUE) :
1343
+ (cond_140 && cond_3)? (`TRUE) :
1344
+ (cond_143 && cond_3)? ( rd_arith_modregrm_to_rm) :
1345
+ (cond_147 && cond_3)? (`TRUE) :
1346
+ (cond_154 && cond_3)? (`TRUE) :
1347
+ (cond_155 && cond_3)? (`TRUE) :
1348
+ (cond_165 && cond_3)? (`TRUE) :
1349
+ (cond_177 && cond_3)? (`TRUE) :
1350
+ (cond_213 && ~cond_214)? (`TRUE) :
1351
+ (cond_217 && cond_3)? (`TRUE) :
1352
+ (cond_219 && cond_3)? (`TRUE) :
1353
+ 1'd0;
1354
+ assign rd_glob_descriptor_2_set =
1355
+ (cond_97)? (`TRUE) :
1356
+ (cond_157)? (`TRUE) :
1357
+ 1'd0;
1358
+ assign rd_error_code =
1359
+ (cond_15 && ~cond_16 && cond_17)? ( `SELECTOR_FOR_CODE(glob_param_1)) :
1360
+ (cond_19 && cond_20)? ( `SELECTOR_FOR_CODE(glob_param_1)) :
1361
+ (cond_21 && ~cond_16 && cond_17)? ( `SELECTOR_FOR_CODE(glob_param_1)) :
1362
+ (cond_62 && cond_20)? ( `SELECTOR_FOR_CODE(glob_param_1)) :
1363
+ (cond_63 && ~cond_16 && cond_17)? ( `SELECTOR_FOR_CODE(glob_param_1)) :
1364
+ (cond_73 && cond_74)? ( { glob_param_1[15:2], 2'd0 }) :
1365
+ (cond_187)? ( `SELECTOR_FOR_CODE(tr)) :
1366
+ (cond_204 && cond_17)? ( `SELECTOR_FOR_CODE(glob_param_1)) :
1367
+ (cond_209 && ~cond_16 && cond_17)? ( `SELECTOR_FOR_CODE(glob_param_1)) :
1368
+ (cond_211 && cond_20)? ( `SELECTOR_FOR_CODE(glob_param_1)) :
1369
+ 16'd0;
1370
+ assign rd_dst_is_edx_eax =
1371
+ (cond_107)? (`TRUE) :
1372
+ (cond_135)? ( ~(rd_decoder[3])) :
1373
+ (cond_150)? (`TRUE) :
1374
+ 1'd0;
1375
+ assign rd_src_is_modregrm_imm =
1376
+ (cond_76)? ( rd_cmdex == `CMDEX_BTx_modregrm_imm) :
1377
+ (cond_110)? ( rd_cmdex == `CMDEX_Shift_modregrm_imm) :
1378
+ (cond_147 && cond_1 && ~cond_134)? (`TRUE) :
1379
+ (cond_147 && cond_3 && ~cond_134)? (`TRUE) :
1380
+ (cond_155)? (`TRUE) :
1381
+ (cond_219)? (`TRUE) :
1382
+ 1'd0;
1383
+ assign address_stack_for_call_param_first =
1384
+ (cond_22 && cond_26)? (`TRUE) :
1385
+ 1'd0;
1386
+ assign rd_req_ebx =
1387
+ (cond_172)? (`TRUE) :
1388
+ 1'd0;
1389
+ assign address_ea_buffer_plus_2 =
1390
+ (cond_121)? (`TRUE) :
1391
+ (cond_246)? (`TRUE) :
1392
+ 1'd0;
1393
+ assign rd_req_edx_eax =
1394
+ (cond_107)? ( rd_decoder[0]) :
1395
+ (cond_135)? ( ~(rd_decoder[3]) && rd_decoder[0]) :
1396
+ (cond_150)? ( rd_decoder[0]) :
1397
+ 1'd0;
1398
+ assign address_stack_for_iret_third =
1399
+ (cond_98 && cond_99)? (`TRUE) :
1400
+ 1'd0;
1401
+ assign rd_src_is_ecx =
1402
+ (cond_111)? (`TRUE) :
1403
+ 1'd0;
1404
+ assign rd_req_ebp =
1405
+ (cond_130)? (`TRUE) :
1406
+ (cond_138 && ~cond_9)? (`TRUE) :
1407
+ 1'd0;
1408
+ assign rd_req_rm =
1409
+ (cond_6)? ( rd_modregrm_mod == 2'b11) :
1410
+ (cond_28 && cond_1)? (`TRUE) :
1411
+ (cond_30 && cond_1)? (`TRUE) :
1412
+ (cond_40 && cond_1 && ~cond_8)? (`TRUE) :
1413
+ (cond_44 && cond_1)? (`TRUE) :
1414
+ (cond_76 && cond_1)? ( rd_cmd[1:0] != 2'd0) :
1415
+ (cond_106 && cond_1)? (`TRUE) :
1416
+ (cond_110 && cond_1)? (`TRUE) :
1417
+ (cond_111 && cond_1)? (`TRUE) :
1418
+ (cond_116 && cond_1)? (`TRUE) :
1419
+ (cond_120)? (`TRUE) :
1420
+ (cond_126 && cond_1)? (`TRUE) :
1421
+ (cond_127 && cond_1 && ~cond_2)? (`TRUE) :
1422
+ (cond_139 && cond_1)? (`TRUE) :
1423
+ (cond_140 && cond_1)? (`TRUE) :
1424
+ (cond_143 && cond_1 && cond_144)? ( rd_arith_modregrm_to_rm) :
1425
+ (cond_147 && cond_1 && cond_148)? (`TRUE) :
1426
+ (cond_166 && cond_1)? (`TRUE) :
1427
+ (cond_177 && cond_1)? (`TRUE) :
1428
+ (cond_217 && cond_1)? (`TRUE) :
1429
+ (cond_219 && cond_1)? (`TRUE) :
1430
+ (cond_254)? (`TRUE) :
1431
+ 1'd0;
1432
+ assign rd_src_is_modregrm_imm_se =
1433
+ (cond_147 && cond_1 && cond_134)? (`TRUE) :
1434
+ (cond_147 && cond_3 && cond_134)? (`TRUE) :
1435
+ 1'd0;
1436
+ assign read_length_dword =
1437
+ (cond_22 && cond_24)? (`TRUE) :
1438
+ (cond_121 && cond_123)? (`TRUE) :
1439
+ (cond_246 && cond_248)? (`TRUE) :
1440
+ 1'd0;
snapshots/MiSTer-devel_ao486_MiSTer_pr72/rtl/ao486/autogen/tlb.v ADDED
@@ -0,0 +1,478 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ //======================================================== conditions
2
+ wire cond_0 = state == STATE_IDLE;
3
+ wire cond_1 = tlbflushsingle_do;
4
+ wire cond_2 = tlbflushall_do || tlbflushall_do_waiting;
5
+ wire cond_3 = ~(wr_reset) && tlbwrite_do && ~(write_ac) && cr0_am && acflag && tlbwrite_cpl == 2'd3 &&
6
+ ( (tlbwrite_length_full == 3'd2 && tlbwrite_address[0] != 1'b0) || (tlbwrite_length_full == 3'd4 && tlbwrite_address[1:0] != 2'b00) )
7
+ ;
8
+ wire cond_4 = ~(wr_reset) && tlbwrite_do && ~(write_pf) && ~(write_ac);
9
+ wire cond_5 = ~(exe_reset) && tlbcheck_do && ~(tlbcheck_done) && ~(check_pf);
10
+ wire cond_6 = ~(rd_reset) && tlbread_do && ~(read_ac) && cr0_am && acflag && tlbread_cpl == 2'd3 &&
11
+ ( (tlbread_length_full == 4'd2 && tlbread_address[0] != 1'b0) || (tlbread_length_full == 4'd4 && tlbread_address[1:0] != 2'b00))
12
+ ;
13
+ wire cond_7 = ~(rd_reset) && tlbread_do && ~(read_pf) && ~(read_ac);
14
+ wire cond_8 = ~(pr_reset) && tlbcoderequest_do && ~(code_pf) && ~(tlbcode_do);
15
+ wire cond_9 = state == STATE_WRITE_DOUBLE;
16
+ wire cond_10 = write_double_state == WRITE_DOUBLE_CHECK;
17
+ wire cond_11 = state == STATE_WRITE_WAIT;
18
+ wire cond_12 = dcachewrite_done;
19
+ wire cond_13 = state == STATE_READ_WAIT;
20
+ wire cond_14 = dcacheread_done;
21
+ wire cond_15 = state == STATE_READ_CHECK;
22
+ wire cond_16 = cr0_pg;
23
+ wire cond_17 = ~(cr0_pg) || translate_valid;
24
+ wire cond_18 = cr0_pg && fault;
25
+ wire cond_19 = state == STATE_WRITE_CHECK;
26
+ wire cond_20 = translate_valid && write_double_state != WRITE_DOUBLE_NONE;
27
+ wire cond_21 = state == STATE_CHECK_CHECK;
28
+ wire cond_22 = state == STATE_CODE_CHECK;
29
+ wire cond_23 = pr_reset || pr_reset_waiting;
30
+ wire cond_24 = state == STATE_LOAD_PDE;
31
+ wire cond_25 = dcacheread_data[0] == `FALSE;
32
+ wire cond_26 = current_type == TYPE_CODE && ~(pr_reset) && ~(pr_reset_waiting);
33
+ wire cond_27 = current_type == TYPE_CHECK;
34
+ wire cond_28 = current_type == TYPE_WRITE;
35
+ wire cond_29 = current_type == TYPE_READ;
36
+ wire cond_30 = state == STATE_LOAD_PTE_START;
37
+ wire cond_31 = state == STATE_RETRY;
38
+ wire cond_32 = state == STATE_LOAD_PTE;
39
+ wire cond_33 = dcacheread_data[0] == `FALSE || fault_before_pte;
40
+ wire cond_34 = ((current_type == TYPE_READ && ~(pipeline_after_read_empty)) || (current_type == TYPE_CODE && (~(pipeline_after_prefetch_empty) || pr_reset_waiting))) &&
41
+ (pde[5] == `FALSE || dcacheread_data[5] == `FALSE || (dcacheread_data[6] == `FALSE && rw));
42
+ wire cond_35 = state == STATE_LOAD_PTE_END;
43
+ wire cond_36 = pde[5] == `FALSE;
44
+ wire cond_37 = pte[5] == `FALSE || (pte[6] == `FALSE && rw);
45
+ wire cond_38 = current_type == TYPE_WRITE && write_double_state != WRITE_DOUBLE_NONE;
46
+ wire cond_39 = state == STATE_READ_WAIT_START;
47
+ wire cond_40 = state == STATE_SAVE_PDE;
48
+ wire cond_41 = state == STATE_SAVE_PTE_START;
49
+ wire cond_42 = state == STATE_WRITE_WAIT_START;
50
+ wire cond_43 = state == STATE_SAVE_PTE;
51
+ //======================================================== saves
52
+ wire [1:0] current_type_to_reg =
53
+ (cond_15 && ~cond_17)? ( TYPE_READ) :
54
+ (cond_19 && ~cond_17)? ( TYPE_WRITE) :
55
+ (cond_21 && ~cond_17)? ( TYPE_CHECK) :
56
+ (cond_22 && ~cond_23 && ~cond_17)? ( TYPE_CODE) :
57
+ current_type;
58
+ wire read_pf_to_reg =
59
+ (cond_0)? ( `FALSE) :
60
+ (cond_15 && cond_17 && cond_18)? ( `TRUE) :
61
+ (cond_24 && cond_14 && cond_25 && ~cond_26 && ~cond_27 && ~cond_28 && cond_29)? ( `TRUE) :
62
+ (cond_32 && cond_14 && cond_33 && ~cond_26 && ~cond_27 && ~cond_28 && cond_29)? ( `TRUE) :
63
+ read_pf;
64
+ wire [31:0] pde_to_reg =
65
+ (cond_24 && cond_14)? ( dcacheread_data[31:0]) :
66
+ pde;
67
+ wire write_pf_to_reg =
68
+ (cond_0)? ( `FALSE) :
69
+ (cond_19 && cond_17 && cond_18)? ( `TRUE) :
70
+ (cond_24 && cond_14 && cond_25 && ~cond_26 && ~cond_27 && cond_28)? ( `TRUE) :
71
+ (cond_32 && cond_14 && cond_33 && ~cond_26 && ~cond_27 && cond_28)? ( `TRUE) :
72
+ write_pf;
73
+ wire [4:0] state_to_reg =
74
+ (cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && cond_4)? ( STATE_WRITE_CHECK) :
75
+ (cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && ~cond_4 && cond_5)? ( STATE_CHECK_CHECK) :
76
+ (cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && ~cond_4 && ~cond_5 && ~cond_6 && cond_7)? ( STATE_READ_CHECK) :
77
+ (cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && ~cond_4 && ~cond_5 && ~cond_6 && ~cond_7 && cond_8)? ( STATE_CODE_CHECK) :
78
+ (cond_9 && cond_10)? ( STATE_WRITE_CHECK) :
79
+ (cond_9 && ~cond_10)? ( STATE_WRITE_CHECK) :
80
+ (cond_11 && cond_12)? ( STATE_IDLE) :
81
+ (cond_13 && cond_14)? ( STATE_IDLE) :
82
+ (cond_15 && cond_17 && cond_18)? ( STATE_IDLE) :
83
+ (cond_15 && cond_17 && ~cond_18)? ( STATE_READ_WAIT) :
84
+ (cond_15 && ~cond_17)? ( STATE_LOAD_PDE) :
85
+ (cond_19 && cond_17 && cond_18)? ( STATE_IDLE) :
86
+ (cond_19 && cond_17 && ~cond_18 && cond_20)? ( STATE_WRITE_DOUBLE) :
87
+ (cond_19 && cond_17 && ~cond_18 && ~cond_20)? ( STATE_WRITE_WAIT) :
88
+ (cond_19 && ~cond_17)? ( STATE_LOAD_PDE) :
89
+ (cond_21 && cond_17)? ( STATE_IDLE) :
90
+ (cond_21 && ~cond_17)? ( STATE_LOAD_PDE) :
91
+ (cond_22 && cond_23)? ( STATE_IDLE) :
92
+ (cond_22 && ~cond_23 && cond_17)? ( STATE_IDLE) :
93
+ (cond_22 && ~cond_23 && ~cond_17)? ( STATE_LOAD_PDE) :
94
+ (cond_24 && cond_14 && cond_25)? ( STATE_IDLE) :
95
+ (cond_24 && cond_14 && ~cond_25)? ( STATE_LOAD_PTE_START) :
96
+ (cond_30)? ( STATE_LOAD_PTE) :
97
+ (cond_31)? ( STATE_IDLE) :
98
+ (cond_32 && cond_14 && cond_33)? ( STATE_IDLE) :
99
+ (cond_32 && cond_14 && ~cond_33 && cond_34)? ( STATE_RETRY) :
100
+ (cond_32 && cond_14 && ~cond_33 && ~cond_34)? ( STATE_LOAD_PTE_END) :
101
+ (cond_35 && cond_36)? ( STATE_SAVE_PDE) :
102
+ (cond_35 && ~cond_36 && cond_37)? ( STATE_SAVE_PTE) :
103
+ (cond_35 && ~cond_36 && ~cond_37 && cond_38)? ( STATE_WRITE_DOUBLE) :
104
+ (cond_35 && ~cond_36 && ~cond_37 && ~cond_38 && cond_28)? ( STATE_WRITE_WAIT) :
105
+ (cond_35 && ~cond_36 && ~cond_37 && ~cond_38 && ~cond_28 && cond_29)? ( STATE_READ_WAIT_START) :
106
+ (cond_35 && ~cond_36 && ~cond_37 && ~cond_38 && ~cond_28 && ~cond_29)? ( STATE_IDLE) :
107
+ (cond_39)? ( STATE_READ_WAIT) :
108
+ (cond_40 && cond_12 && cond_37)? ( STATE_SAVE_PTE_START) :
109
+ (cond_40 && cond_12 && ~cond_37 && cond_28)? ( STATE_WRITE_WAIT_START) :
110
+ (cond_40 && cond_12 && ~cond_37 && ~cond_28 && cond_29)? ( STATE_READ_WAIT) :
111
+ (cond_40 && cond_12 && ~cond_37 && ~cond_28 && ~cond_29)? ( STATE_IDLE) :
112
+ (cond_41)? ( STATE_SAVE_PTE) :
113
+ (cond_42 && cond_38)? ( STATE_WRITE_DOUBLE) :
114
+ (cond_42 && ~cond_38)? ( STATE_WRITE_WAIT) :
115
+ (cond_43 && cond_12 && cond_28)? ( STATE_WRITE_WAIT_START) :
116
+ (cond_43 && cond_12 && ~cond_28 && cond_29)? ( STATE_READ_WAIT) :
117
+ (cond_43 && cond_12 && ~cond_28 && ~cond_29)? ( STATE_IDLE) :
118
+ state;
119
+ wire [31:0] tlb_read_pf_cr2_to_reg =
120
+ (cond_15 && cond_17 && cond_18)? ( linear) :
121
+ (cond_24 && cond_14 && cond_25 && ~cond_26 && ~cond_27 && ~cond_28 && cond_29)? ( linear) :
122
+ (cond_32 && cond_14 && cond_33 && ~cond_26 && ~cond_27 && ~cond_28 && cond_29)? ( linear) :
123
+ tlb_read_pf_cr2;
124
+ wire [31:0] tlb_code_pf_cr2_to_reg =
125
+ (cond_22 && ~cond_23 && cond_17 && cond_18)? ( linear) :
126
+ (cond_24 && cond_14 && cond_25 && cond_26)? ( linear) :
127
+ (cond_32 && cond_14 && cond_33 && cond_26)? ( linear) :
128
+ tlb_code_pf_cr2;
129
+ wire check_pf_to_reg =
130
+ (cond_21 && cond_17 && cond_18)? ( `TRUE) :
131
+ (cond_24 && cond_14 && cond_25 && ~cond_26 && cond_27)? ( `TRUE) :
132
+ (cond_32 && cond_14 && cond_33 && ~cond_26 && cond_27)? ( `TRUE) :
133
+ check_pf;
134
+ wire su_to_reg =
135
+ (cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && cond_4)? ( tlbwrite_cpl == 2'd3) :
136
+ (cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && ~cond_4 && cond_5)? ( `FALSE) :
137
+ (cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && ~cond_4 && ~cond_5 && ~cond_6 && cond_7)? ( tlbread_cpl == 2'd3) :
138
+ (cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && ~cond_4 && ~cond_5 && ~cond_6 && ~cond_7 && cond_8)? ( tlbcoderequest_su) :
139
+ su;
140
+ wire [15:0] tlb_check_pf_error_code_to_reg =
141
+ (cond_21 && cond_17 && cond_18)? ({ 13'd0, su, rw, `TRUE }) :
142
+ (cond_24 && cond_14 && cond_25 && ~cond_26 && cond_27)? ({ 13'd0, su, rw, `FALSE }) :
143
+ (cond_32 && cond_14 && cond_33 && ~cond_26 && cond_27)? ({ 13'd0, su, rw, dcacheread_data[0] }) :
144
+ tlb_check_pf_error_code;
145
+ wire [15:0] tlb_write_pf_error_code_to_reg =
146
+ (cond_19 && cond_17 && cond_18)? ( { 13'd0, su, rw, `TRUE }) :
147
+ (cond_24 && cond_14 && cond_25 && ~cond_26 && ~cond_27 && cond_28)? ({ 13'd0, su, rw, `FALSE }) :
148
+ (cond_32 && cond_14 && cond_33 && ~cond_26 && ~cond_27 && cond_28)? ({ 13'd0, su, rw, dcacheread_data[0] }) :
149
+ tlb_write_pf_error_code;
150
+ wire [31:0] write_double_linear_to_reg =
151
+ (cond_9 && cond_10)? ( linear) :
152
+ write_double_linear;
153
+ wire tlbcode_cache_disable_to_reg =
154
+ (cond_22 && ~cond_23 && cond_17 && ~cond_18)? ( cr0_cd || translate_pcd || memtype_cache_disable) :
155
+ tlbcode_cache_disable;
156
+ wire [31:0] linear_to_reg =
157
+ (cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && cond_4)? ( tlbwrite_address) :
158
+ (cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && ~cond_4 && cond_5)? ( tlbcheck_address) :
159
+ (cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && ~cond_4 && ~cond_5 && ~cond_6 && cond_7)? ( tlbread_address) :
160
+ (cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && ~cond_4 && ~cond_5 && ~cond_6 && ~cond_7 && cond_8)? ( tlbcoderequest_address) :
161
+ (cond_9 && cond_10)? ( { linear[31:12], 12'd0 } + 32'h00001000) :
162
+ (cond_9 && ~cond_10)? ( write_double_linear) :
163
+ linear;
164
+ wire [15:0] tlb_code_pf_error_code_to_reg =
165
+ (cond_22 && ~cond_23 && cond_17 && cond_18)? ({ 13'd0, su, rw, `TRUE }) :
166
+ (cond_24 && cond_14 && cond_25 && cond_26)? ( { 13'd0, su, rw, `FALSE }) :
167
+ (cond_32 && cond_14 && cond_33 && cond_26)? ( { 13'd0, su, rw, dcacheread_data[0] }) :
168
+ tlb_code_pf_error_code;
169
+ wire tlbcode_do_to_reg =
170
+ (cond_0)? ( `FALSE) :
171
+ (cond_22 && ~cond_23 && cond_17 && ~cond_18)? ( `TRUE) :
172
+ tlbcode_do;
173
+ wire wp_to_reg =
174
+ (cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && cond_4)? ( cr0_wp) :
175
+ (cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && ~cond_4 && cond_5)? ( cr0_wp) :
176
+ (cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && ~cond_4 && ~cond_5 && ~cond_6 && cond_7)? ( cr0_wp) :
177
+ (cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && ~cond_4 && ~cond_5 && ~cond_6 && ~cond_7 && cond_8)? ( cr0_wp) :
178
+ wp;
179
+ wire tlbcheck_done_to_reg =
180
+ (cond_0)? ( `FALSE) :
181
+ (cond_21 && cond_17 && ~cond_18)? ( `TRUE) :
182
+ tlbcheck_done;
183
+ wire [31:0] tlb_write_pf_cr2_to_reg =
184
+ (cond_19 && cond_17 && cond_18)? ( linear) :
185
+ (cond_24 && cond_14 && cond_25 && ~cond_26 && ~cond_27 && cond_28)? ( linear) :
186
+ (cond_32 && cond_14 && cond_33 && ~cond_26 && ~cond_27 && cond_28)? ( linear) :
187
+ tlb_write_pf_cr2;
188
+ wire read_ac_to_reg =
189
+ (cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && ~cond_4 && ~cond_5 && cond_6)? ( `TRUE) :
190
+ read_ac;
191
+ wire [31:0] pte_to_reg =
192
+ (cond_32 && cond_14)? ( dcacheread_data[31:0]) :
193
+ pte;
194
+ wire [31:0] tlb_check_pf_cr2_to_reg =
195
+ (cond_21 && cond_17 && cond_18)? ( linear) :
196
+ (cond_24 && cond_14 && cond_25 && ~cond_26 && cond_27)? ( linear) :
197
+ (cond_32 && cond_14 && cond_33 && ~cond_26 && cond_27)? ( linear) :
198
+ tlb_check_pf_cr2;
199
+ wire [15:0] tlb_read_pf_error_code_to_reg =
200
+ (cond_15 && cond_17 && cond_18)? ( { 13'd0, su, rw, `TRUE }) :
201
+ (cond_24 && cond_14 && cond_25 && ~cond_26 && ~cond_27 && ~cond_28 && cond_29)? ( { 13'd0, su, rw, `FALSE }) :
202
+ (cond_32 && cond_14 && cond_33 && ~cond_26 && ~cond_27 && ~cond_28 && cond_29)? ( { 13'd0, su, rw, dcacheread_data[0] }) :
203
+ tlb_read_pf_error_code;
204
+ wire [1:0] write_double_state_to_reg =
205
+ (cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && cond_4)? ( (cr0_pg && tlbwrite_length != tlbwrite_length_full && { 1'b0, tlbwrite_address[11:0] } + { 10'd0, tlbwrite_length_full } >= 13'h1000)? WRITE_DOUBLE_CHECK : WRITE_DOUBLE_NONE) :
206
+ (cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && ~cond_4 && cond_5)? ( WRITE_DOUBLE_NONE) :
207
+ (cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && ~cond_4 && ~cond_5 && ~cond_6 && cond_7)? ( WRITE_DOUBLE_NONE) :
208
+ (cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && ~cond_4 && ~cond_5 && ~cond_6 && ~cond_7 && cond_8)? ( WRITE_DOUBLE_NONE) :
209
+ (cond_9 && cond_10)? ( WRITE_DOUBLE_RESTART) :
210
+ (cond_9 && ~cond_10)? ( WRITE_DOUBLE_NONE) :
211
+ write_double_state;
212
+ wire write_ac_to_reg =
213
+ (cond_0 && ~cond_1 && ~cond_2 && cond_3)? ( `TRUE) :
214
+ write_ac;
215
+ wire [31:0] tlbcode_physical_to_reg =
216
+ (cond_22 && ~cond_23 && cond_17 && ~cond_18)? ( memtype_physical) :
217
+ tlbcode_physical;
218
+ wire rw_to_reg =
219
+ (cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && cond_4)? ( `TRUE) :
220
+ (cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && ~cond_4 && cond_5)? ( tlbcheck_rw) :
221
+ (cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && ~cond_4 && ~cond_5 && ~cond_6 && cond_7)? ( tlbread_rmw) :
222
+ (cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && ~cond_4 && ~cond_5 && ~cond_6 && ~cond_7 && cond_8)? ( `FALSE) :
223
+ rw;
224
+ wire code_pf_to_reg =
225
+ (cond_22 && ~cond_23 && cond_17 && cond_18)? ( `TRUE) :
226
+ (cond_24 && cond_14 && cond_25 && cond_26)? ( `TRUE) :
227
+ (cond_32 && cond_14 && cond_33 && cond_26)? ( `TRUE) :
228
+ code_pf;
229
+ //======================================================== always
230
+ always @(posedge clk) begin
231
+ if(rst_n == 1'b0) current_type <= 2'd0;
232
+ else current_type <= current_type_to_reg;
233
+ end
234
+ always @(posedge clk) begin
235
+ if(rst_n == 1'b0) pde <= 32'd0;
236
+ else pde <= pde_to_reg;
237
+ end
238
+ always @(posedge clk) begin
239
+ if(rst_n == 1'b0) state <= 5'd0;
240
+ else state <= state_to_reg;
241
+ end
242
+ always @(posedge clk) begin
243
+ if(rst_n == 1'b0) tlb_read_pf_cr2 <= 32'd0;
244
+ else tlb_read_pf_cr2 <= tlb_read_pf_cr2_to_reg;
245
+ end
246
+ always @(posedge clk) begin
247
+ if(rst_n == 1'b0) tlb_code_pf_cr2 <= 32'd0;
248
+ else tlb_code_pf_cr2 <= tlb_code_pf_cr2_to_reg;
249
+ end
250
+ always @(posedge clk) begin
251
+ if(rst_n == 1'b0) su <= 1'd0;
252
+ else su <= su_to_reg;
253
+ end
254
+ always @(posedge clk) begin
255
+ if(rst_n == 1'b0) tlb_check_pf_error_code <= 16'd0;
256
+ else tlb_check_pf_error_code <= tlb_check_pf_error_code_to_reg;
257
+ end
258
+ always @(posedge clk) begin
259
+ if(rst_n == 1'b0) tlb_write_pf_error_code <= 16'd0;
260
+ else tlb_write_pf_error_code <= tlb_write_pf_error_code_to_reg;
261
+ end
262
+ always @(posedge clk) begin
263
+ if(rst_n == 1'b0) write_double_linear <= 32'd0;
264
+ else write_double_linear <= write_double_linear_to_reg;
265
+ end
266
+ always @(posedge clk) begin
267
+ if(rst_n == 1'b0) tlbcode_cache_disable <= 1'd0;
268
+ else tlbcode_cache_disable <= tlbcode_cache_disable_to_reg;
269
+ end
270
+ always @(posedge clk) begin
271
+ if(rst_n == 1'b0) linear <= 32'd0;
272
+ else linear <= linear_to_reg;
273
+ end
274
+ always @(posedge clk) begin
275
+ if(rst_n == 1'b0) tlb_code_pf_error_code <= 16'd0;
276
+ else tlb_code_pf_error_code <= tlb_code_pf_error_code_to_reg;
277
+ end
278
+ always @(posedge clk) begin
279
+ if(rst_n == 1'b0) tlbcode_do <= 1'd0;
280
+ else tlbcode_do <= tlbcode_do_to_reg;
281
+ end
282
+ always @(posedge clk) begin
283
+ if(rst_n == 1'b0) wp <= 1'd0;
284
+ else wp <= wp_to_reg;
285
+ end
286
+ always @(posedge clk) begin
287
+ if(rst_n == 1'b0) tlbcheck_done <= 1'd0;
288
+ else tlbcheck_done <= tlbcheck_done_to_reg;
289
+ end
290
+ always @(posedge clk) begin
291
+ if(rst_n == 1'b0) tlb_write_pf_cr2 <= 32'd0;
292
+ else tlb_write_pf_cr2 <= tlb_write_pf_cr2_to_reg;
293
+ end
294
+ always @(posedge clk) begin
295
+ if(rst_n == 1'b0) pte <= 32'd0;
296
+ else pte <= pte_to_reg;
297
+ end
298
+ always @(posedge clk) begin
299
+ if(rst_n == 1'b0) tlb_check_pf_cr2 <= 32'd0;
300
+ else tlb_check_pf_cr2 <= tlb_check_pf_cr2_to_reg;
301
+ end
302
+ always @(posedge clk) begin
303
+ if(rst_n == 1'b0) tlb_read_pf_error_code <= 16'd0;
304
+ else tlb_read_pf_error_code <= tlb_read_pf_error_code_to_reg;
305
+ end
306
+ always @(posedge clk) begin
307
+ if(rst_n == 1'b0) write_double_state <= 2'd0;
308
+ else write_double_state <= write_double_state_to_reg;
309
+ end
310
+ always @(posedge clk) begin
311
+ if(rst_n == 1'b0) tlbcode_physical <= 32'd0;
312
+ else tlbcode_physical <= tlbcode_physical_to_reg;
313
+ end
314
+ always @(posedge clk) begin
315
+ if(rst_n == 1'b0) rw <= 1'd0;
316
+ else rw <= rw_to_reg;
317
+ end
318
+ //======================================================== sets
319
+ assign dcachewrite_do =
320
+ (cond_19 && cond_17 && ~cond_18 && ~cond_20)? (`TRUE) :
321
+ (cond_35 && cond_36)? (`TRUE) :
322
+ (cond_35 && ~cond_36 && cond_37)? (`TRUE) :
323
+ (cond_35 && ~cond_36 && ~cond_37 && ~cond_38 && cond_28)? (`TRUE) :
324
+ (cond_41)? (`TRUE) :
325
+ (cond_42 && ~cond_38)? (`TRUE) :
326
+ 1'd0;
327
+ assign dcacheread_length =
328
+ (cond_15 && cond_17 && ~cond_18)? ( tlbread_length) :
329
+ (cond_15 && ~cond_17)? ( 4'd4) :
330
+ (cond_19 && ~cond_17)? ( 4'd4) :
331
+ (cond_21 && ~cond_17)? ( 4'd4) :
332
+ (cond_22 && ~cond_23 && ~cond_17)? ( 4'd4) :
333
+ (cond_30)? ( 4'd4) :
334
+ (cond_39)? ( tlbread_length) :
335
+ (cond_40 && cond_12 && ~cond_37 && ~cond_28 && cond_29)? ( tlbread_length) :
336
+ (cond_43 && cond_12 && ~cond_28 && cond_29)? ( tlbread_length) :
337
+ 4'd0;
338
+ assign tlbregs_tlbflushall_do =
339
+ (cond_0 && ~cond_1 && cond_2)? (`TRUE) :
340
+ 1'd0;
341
+ assign dcachewrite_length =
342
+ (cond_19 && cond_17 && ~cond_18 && ~cond_20)? ( tlbwrite_length) :
343
+ (cond_35 && cond_36)? ( 3'd4) :
344
+ (cond_35 && ~cond_36 && cond_37)? ( 3'd4) :
345
+ (cond_35 && ~cond_36 && ~cond_37 && ~cond_38 && cond_28)? ( tlbwrite_length) :
346
+ (cond_41)? ( 3'd4) :
347
+ (cond_42 && ~cond_38)? ( tlbwrite_length) :
348
+ 3'd0;
349
+ assign tlbregs_write_combined_rw =
350
+ (cond_35)? ( rw_entry) :
351
+ 1'd0;
352
+ assign tlbregs_write_pcd =
353
+ (cond_35)? ( pte[4]) :
354
+ 1'd0;
355
+ assign tlbwrite_done =
356
+ (cond_11 && cond_12)? (`TRUE) :
357
+ 1'd0;
358
+ assign tlbread_retry =
359
+ (cond_31)? ( current_type == TYPE_READ) :
360
+ 1'd0;
361
+ assign dcachewrite_address =
362
+ (cond_19 && cond_17 && ~cond_18 && ~cond_20)? ( memtype_physical) :
363
+ (cond_35 && cond_36)? ( memtype_physical) :
364
+ (cond_35 && ~cond_36 && cond_37)? ( memtype_physical) :
365
+ (cond_35 && ~cond_36 && ~cond_37 && ~cond_38 && cond_28)? ( memtype_physical) :
366
+ (cond_41)? ( memtype_physical) :
367
+ (cond_42 && ~cond_38)? ( memtype_physical) :
368
+ 32'd0;
369
+ assign tlbregs_write_pwt =
370
+ (cond_35)? ( pte[3]) :
371
+ 1'd0;
372
+ assign tlbregs_write_linear =
373
+ (cond_35)? ( linear) :
374
+ 32'd0;
375
+ assign tlbread_done =
376
+ (cond_13 && cond_14)? (`TRUE) :
377
+ 1'd0;
378
+ assign dcachewrite_data =
379
+ (cond_19 && cond_17 && ~cond_18 && ~cond_20)? ( tlbwrite_data) :
380
+ (cond_35 && cond_36)? ( pde | 32'h00000020) :
381
+ (cond_35 && ~cond_36 && cond_37)? ( pte[31:0] | 32'h00000020 | ((pte[6] == `FALSE && rw)? 32'h00000040 : 32'h00000000)) :
382
+ (cond_35 && ~cond_36 && ~cond_37 && ~cond_38 && cond_28)? ( tlbwrite_data) :
383
+ (cond_41)? ( pte[31:0] | 32'h00000020 | ((pte[6] == `FALSE && rw)? 32'h00000040 : 32'h00000000)) :
384
+ (cond_42 && ~cond_38)? ( tlbwrite_data) :
385
+ 32'd0;
386
+ assign tlbregs_tlbflushsingle_do =
387
+ (cond_0 && cond_1)? (`TRUE) :
388
+ 1'd0;
389
+ assign translate_do =
390
+ (cond_15 && cond_16)? (`TRUE) :
391
+ (cond_19 && cond_16)? (`TRUE) :
392
+ (cond_21 && cond_16)? (`TRUE) :
393
+ (cond_22 && cond_16)? (`TRUE) :
394
+ 1'd0;
395
+ assign tlbregs_write_physical =
396
+ (cond_35)? ( { pte[31:12], linear[11:0] }) :
397
+ 32'd0;
398
+ assign tlbregs_write_do =
399
+ (cond_35)? (`TRUE) :
400
+ 1'd0;
401
+ assign tlbflushsingle_done =
402
+ (cond_0 && cond_1)? (`TRUE) :
403
+ 1'd0;
404
+ assign dcachewrite_write_through =
405
+ (cond_19 && cond_17 && ~cond_18 && ~cond_20)? ( cr0_nw || translate_pwt || memtype_write_transparent) :
406
+ (cond_35 && cond_36)? ( cr0_nw || cr3_pwt || memtype_write_transparent) :
407
+ (cond_35 && ~cond_36 && cond_37)? ( cr0_nw || pde[3] || memtype_write_transparent) :
408
+ (cond_35 && ~cond_36 && ~cond_37 && ~cond_38 && cond_28)? ( cr0_nw || pte[3] || memtype_write_transparent) :
409
+ (cond_41)? ( cr0_nw || pde[3] || memtype_write_transparent) :
410
+ (cond_42 && ~cond_38)? ( cr0_nw || pte[3] || memtype_write_transparent) :
411
+ 1'd0;
412
+ assign dcacheread_address =
413
+ (cond_15 && cond_17 && ~cond_18)? ( memtype_physical) :
414
+ (cond_15 && ~cond_17)? ( memtype_physical) :
415
+ (cond_19 && ~cond_17)? ( memtype_physical) :
416
+ (cond_21 && ~cond_17)? ( memtype_physical) :
417
+ (cond_22 && ~cond_23 && ~cond_17)? ( memtype_physical) :
418
+ (cond_30)? ( memtype_physical) :
419
+ (cond_39)? ( memtype_physical) :
420
+ (cond_40 && cond_12 && ~cond_37 && ~cond_28 && cond_29)? ( memtype_physical) :
421
+ (cond_43 && cond_12 && ~cond_28 && cond_29)? ( memtype_physical) :
422
+ 32'd0;
423
+ assign dcachewrite_cache_disable =
424
+ (cond_19 && cond_17 && ~cond_18 && ~cond_20)? ( cr0_cd || translate_pcd || memtype_cache_disable) :
425
+ (cond_35 && cond_36)? ( cr0_cd || cr3_pcd || memtype_cache_disable) :
426
+ (cond_35 && ~cond_36 && cond_37)? ( cr0_cd || pde[4] || memtype_cache_disable) :
427
+ (cond_35 && ~cond_36 && ~cond_37 && ~cond_38 && cond_28)? ( cr0_cd || pte[4] || memtype_cache_disable) :
428
+ (cond_41)? ( cr0_cd || pde[4] || memtype_cache_disable) :
429
+ (cond_42 && ~cond_38)? ( cr0_cd || pte[4] || memtype_cache_disable) :
430
+ 1'd0;
431
+ assign tlbregs_write_combined_su =
432
+ (cond_35)? ( su_entry) :
433
+ 1'd0;
434
+ assign dcacheread_do =
435
+ (cond_15 && cond_17 && ~cond_18)? (`TRUE) :
436
+ (cond_15 && ~cond_17)? (`TRUE) :
437
+ (cond_19 && ~cond_17)? (`TRUE) :
438
+ (cond_21 && ~cond_17)? (`TRUE) :
439
+ (cond_22 && ~cond_23 && ~cond_17)? (`TRUE) :
440
+ (cond_30)? (`TRUE) :
441
+ (cond_39)? (`TRUE) :
442
+ (cond_40 && cond_12 && ~cond_37 && ~cond_28 && cond_29)? (`TRUE) :
443
+ (cond_43 && cond_12 && ~cond_28 && cond_29)? (`TRUE) :
444
+ 1'd0;
445
+ assign memtype_physical =
446
+ (cond_15 && cond_17 && ~cond_18)? ( translate_physical) :
447
+ (cond_15 && ~cond_17)? ( { cr3_base[31:12], linear[31:22], 2'd0 }) :
448
+ (cond_19 && cond_17 && ~cond_18 && ~cond_20)? ( translate_physical) :
449
+ (cond_19 && ~cond_17)? ( { cr3_base[31:12], linear[31:22], 2'd0 }) :
450
+ (cond_21 && ~cond_17)? ( { cr3_base[31:12], linear[31:22], 2'd0 }) :
451
+ (cond_22 && ~cond_23 && cond_17 && ~cond_18)? ( translate_physical) :
452
+ (cond_22 && ~cond_23 && ~cond_17)? ( { cr3_base[31:12], linear[31:22], 2'd0 }) :
453
+ (cond_30)? ( { pde[31:12], linear[21:12], 2'd0 }) :
454
+ (cond_35 && cond_36)? ( { cr3_base[31:12], linear[31:22], 2'd0 }) :
455
+ (cond_35 && ~cond_36 && cond_37)? ( { pde[31:12], linear[21:12], 2'b00 }) :
456
+ (cond_35 && ~cond_36 && ~cond_37 && ~cond_38 && cond_28)? ( { pte[31:12], linear[11:0] }) :
457
+ (cond_39)? ( { pte[31:12], linear[11:0] }) :
458
+ (cond_40 && cond_12 && ~cond_37 && ~cond_28 && cond_29)? ( { pte[31:12], linear[11:0] }) :
459
+ (cond_41)? ( { pde[31:12], linear[21:12], 2'b00 }) :
460
+ (cond_42 && ~cond_38)? ( { pte[31:12], linear[11:0] }) :
461
+ (cond_43 && cond_12 && ~cond_28 && cond_29)? ( { pte[31:12], linear[11:0] }) :
462
+ 32'd0;
463
+ assign prefetchfifo_signal_pf_do =
464
+ (cond_22 && ~cond_23 && cond_17 && cond_18)? (`TRUE) :
465
+ (cond_24 && cond_14 && cond_25 && cond_26)? (`TRUE) :
466
+ (cond_32 && cond_14 && cond_33 && cond_26)? (`TRUE) :
467
+ 1'd0;
468
+ assign dcacheread_cache_disable =
469
+ (cond_15 && cond_17 && ~cond_18)? ( cr0_cd || translate_pcd || memtype_cache_disable) :
470
+ (cond_15 && ~cond_17)? ( cr0_cd || cr3_pcd || memtype_cache_disable) :
471
+ (cond_19 && ~cond_17)? ( cr0_cd || cr3_pcd || memtype_cache_disable) :
472
+ (cond_21 && ~cond_17)? ( cr0_cd || cr3_pcd || memtype_cache_disable) :
473
+ (cond_22 && ~cond_23 && ~cond_17)? ( cr0_cd || cr3_pcd || memtype_cache_disable) :
474
+ (cond_30)? ( cr0_cd || pde[4] || memtype_cache_disable) :
475
+ (cond_39)? ( cr0_cd || pte[4] || memtype_cache_disable) :
476
+ (cond_40 && cond_12 && ~cond_37 && ~cond_28 && cond_29)? ( cr0_cd || pte[4] || memtype_cache_disable) :
477
+ (cond_43 && cond_12 && ~cond_28 && cond_29)? ( cr0_cd || pte[4] || memtype_cache_disable) :
478
+ 1'd0;
snapshots/MiSTer-devel_ao486_MiSTer_pr72/rtl/ao486/autogen/write_commands.v ADDED
@@ -0,0 +1,1665 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ wire [15:0] wr_IRET_to_v86_es;
2
+ wire [15:0] wr_IRET_to_v86_cs;
3
+ wire [15:0] wr_IRET_to_v86_ss;
4
+ wire [15:0] wr_IRET_to_v86_ds;
5
+ wire [15:0] wr_IRET_to_v86_fs;
6
+ wire [15:0] wr_IRET_to_v86_gs;
7
+ assign wr_IRET_to_v86_es = exe_buffer_shifted[79:64];
8
+ assign wr_IRET_to_v86_cs = glob_param_1[15:0];
9
+ assign wr_IRET_to_v86_ss = exe_buffer_shifted[111:96];
10
+ assign wr_IRET_to_v86_ds = exe_buffer_shifted[47:32];
11
+ assign wr_IRET_to_v86_fs = exe_buffer_shifted[15:0];
12
+ assign wr_IRET_to_v86_gs = exe_buffer[15:0];
13
+
14
+ wire [31:0] wr_ecx_minus_1;
15
+ assign wr_ecx_minus_1 = ecx - 32'd1;
16
+
17
+ wire [31:0] wr_task_switch_linear;
18
+ wire [31:0] wr_task_switch_linear_next;
19
+ reg [31:0] wr_task_switch_linear_reg;
20
+ assign wr_task_switch_linear = (wr_cmd == `CMD_task_switch && wr_cmdex == `CMDEX_task_switch_STEP_9 && tr_cache[`DESC_BITS_TYPE] <= 4'd3)? tr_base + 32'd14 : (wr_cmd == `CMD_task_switch && wr_cmdex == `CMDEX_task_switch_STEP_9 && tr_cache[`DESC_BITS_TYPE] > 4'd3)? tr_base + 32'h20 : wr_task_switch_linear_next;
21
+ assign wr_task_switch_linear_next = (tr_cache[`DESC_BITS_TYPE] <= 4'd3)? wr_task_switch_linear_reg + 32'd2 : wr_task_switch_linear_reg + 32'd4;
22
+ always @(posedge clk) begin if(rst_n == 1'b0) wr_task_switch_linear_reg <= 32'd0; else if(wr_cmd == `CMD_task_switch && wr_cmdex == `CMDEX_task_switch_STEP_9) wr_task_switch_linear_reg <= wr_task_switch_linear; else if(wr_ready) wr_task_switch_linear_reg <= wr_task_switch_linear_next;
23
+ end
24
+
25
+ //======================================================== conditions
26
+ wire cond_0 = wr_cmd == `CMD_XADD && wr_cmdex == `CMDEX_XADD_FIRST;
27
+ wire cond_1 = wr_dst_is_memory && ~(write_for_wr_ready);
28
+ wire cond_2 = wr_cmd == `CMD_XADD && wr_cmdex == `CMDEX_XADD_LAST;
29
+ wire cond_3 = wr_modregrm_mod != 2'b11 || wr_modregrm_reg != wr_modregrm_rm;
30
+ wire cond_4 = wr_cmd == `CMD_JCXZ;
31
+ wire cond_5 = result_signals[0];
32
+ wire cond_6 = wr_cmd == `CMD_CALL && (wr_cmdex == `CMDEX_CALL_Ep_STEP_0 || wr_cmdex == `CMDEX_CALL_Ap_STEP_0);
33
+ wire cond_7 = wr_cmd == `CMD_CALL && (wr_cmdex == `CMDEX_CALL_Ep_STEP_1 || wr_cmdex == `CMDEX_CALL_Ap_STEP_1);
34
+ wire cond_8 = wr_cmd == `CMD_CALL && (wr_cmdex == `CMDEX_CALL_real_v8086_STEP_0 || wr_cmdex == `CMDEX_CALL_real_v8086_STEP_1);
35
+ wire cond_9 = ~(write_for_wr_ready);
36
+ wire cond_10 = ~(wr_push_ss_fault);
37
+ wire cond_11 = wr_cmd == `CMD_CALL && (wr_cmdex == `CMDEX_CALL_Ev_STEP_0 || wr_cmdex == `CMDEX_CALL_Jv_STEP_0);
38
+ wire cond_12 = wr_cmd == `CMD_CALL && (wr_cmdex == `CMDEX_CALL_Ev_Jv_STEP_1 || wr_cmdex == `CMDEX_CALL_real_v8086_STEP_3);
39
+ wire cond_13 = wr_cmd == `CMD_CALL && wr_cmdex == `CMDEX_CALL_real_v8086_STEP_2;
40
+ wire cond_14 = wr_cmd == `CMD_CALL && (wr_cmdex == `CMDEX_CALL_protected_seg_STEP_0 || wr_cmdex == `CMDEX_CALL_protected_seg_STEP_1);
41
+ wire cond_15 = ~(wr_new_push_ss_fault);
42
+ wire cond_16 = wr_cmd == `CMD_CALL && wr_cmdex == `CMDEX_CALL_protected_seg_STEP_2;
43
+ wire cond_17 = wr_cmd == `CMD_CALL_2 && wr_cmdex == `CMDEX_CALL_2_task_switch_STEP_0;
44
+ wire cond_18 = wr_cmd == `CMD_CALL_2 && (wr_cmdex == `CMDEX_CALL_2_call_gate_more_STEP_2 || wr_cmdex == `CMDEX_CALL_2_call_gate_more_STEP_3);
45
+ wire cond_19 = wr_cmd == `CMD_CALL_3 && ( wr_cmdex == `CMDEX_CALL_3_call_gate_more_STEP_4 || wr_cmdex == `CMDEX_CALL_3_call_gate_more_STEP_5 || wr_cmdex == `CMDEX_CALL_3_call_gate_more_STEP_6 || wr_cmdex == `CMDEX_CALL_3_call_gate_more_STEP_7);
46
+ wire cond_20 = wr_cmdex == `CMDEX_CALL_3_call_gate_more_STEP_7;
47
+ wire cond_21 = wr_cmd == `CMD_PUSH_MOV_SEG && { wr_cmdex[3], 3'b0 } == `CMDEX_PUSH_MOV_SEG_implicit;
48
+ wire cond_22 = write_for_wr_ready && ~(wr_push_ss_fault);
49
+ wire cond_23 = wr_cmd == `CMD_PUSH_MOV_SEG && { wr_cmdex[3], 3'b0 } == `CMDEX_PUSH_MOV_SEG_modregrm;
50
+ wire cond_24 = wr_cmd == `CMD_NEG;
51
+ wire cond_25 = wr_cmd == `CMD_Jcc;
52
+ wire cond_26 = wr_cmd == `CMD_INVD && wr_cmdex == `CMDEX_INVD_STEP_0;
53
+ wire cond_27 = wr_cmd == `CMD_INVD && wr_cmdex == `CMDEX_INVD_STEP_1;
54
+ wire cond_28 = wr_cmd == `CMD_INVLPG && wr_cmdex == `CMDEX_INVLPG_STEP_0;
55
+ wire cond_29 = wr_cmd == `CMD_INVLPG && wr_cmdex == `CMDEX_INVLPG_STEP_1;
56
+ wire cond_30 = wr_cmd == `CMD_io_allow && (wr_cmdex == `CMDEX_io_allow_1 || wr_cmdex == `CMDEX_io_allow_2);
57
+ wire cond_31 = wr_cmd == `CMD_HLT && wr_cmdex == `CMDEX_HLT_STEP_0;
58
+ wire cond_32 = wr_cmd == `CMD_SCAS;
59
+ wire cond_33 = ~(wr_string_ignore);
60
+ wire cond_34 = wr_prefix_group_1_rep != 2'd0;
61
+ wire cond_35 = wr_string_ignore || wr_string_zf_finish;
62
+ wire cond_36 = ~(wr_string_ignore) && ~(wr_string_zf_finish) && wr_prefix_group_1_rep != 2'd0;
63
+ wire cond_37 = wr_cmd == `CMD_INC_DEC;
64
+ wire cond_38 = wr_cmd == `CMD_RET_near && wr_cmdex != `CMDEX_RET_near_LAST;
65
+ wire cond_39 = wr_cmd == `CMD_ARPL;
66
+ wire cond_40 = wr_cmd == `CMD_BSWAP;
67
+ wire cond_41 = wr_cmd == `CMD_LxS && wr_cmdex != `CMDEX_LxS_STEP_LAST;
68
+ wire cond_42 = wr_cmd == `CMD_LxS && wr_cmdex == `CMDEX_LxS_STEP_LAST;
69
+ wire cond_43 = (wr_cmd == `CMD_MOV_to_seg || wr_cmd == `CMD_LLDT || wr_cmd == `CMD_LTR) && wr_cmdex == `CMDEX_MOV_to_seg_LLDT_LTR_STEP_1;
70
+ wire cond_44 = (wr_cmd == `CMD_MOV_to_seg || wr_cmd == `CMD_LLDT || wr_cmd == `CMD_LTR) && wr_cmdex == `CMDEX_MOV_to_seg_LLDT_LTR_STEP_LAST;
71
+ wire cond_45 = wr_cmd == `CMD_MOV_to_seg && wr_decoder[13:11] == `SEGMENT_SS;
72
+ wire cond_46 = wr_cmd == `CMD_CLC;
73
+ wire cond_47 = wr_cmd == `CMD_CMC;
74
+ wire cond_48 = wr_cmd == `CMD_CLD;
75
+ wire cond_49 = wr_cmd == `CMD_STC;
76
+ wire cond_50 = wr_cmd == `CMD_STD;
77
+ wire cond_51 = wr_cmd == `CMD_SAHF;
78
+ wire cond_52 = wr_cmd == `CMD_int_2 && wr_cmdex == `CMDEX_int_2_int_trap_gate_more_STEP_2;
79
+ wire cond_53 = wr_cmd == `CMD_int_2 && wr_cmdex == `CMDEX_int_2_int_trap_gate_more_STEP_3;
80
+ wire cond_54 = wr_cmd == `CMD_int_2 && ( wr_cmdex == `CMDEX_int_2_int_trap_gate_more_STEP_4 || wr_cmdex == `CMDEX_int_2_int_trap_gate_more_STEP_5 || wr_cmdex == `CMDEX_int_2_int_trap_gate_more_STEP_6 || wr_cmdex == `CMDEX_int_2_int_trap_gate_more_STEP_7 || wr_cmdex == `CMDEX_int_2_int_trap_gate_more_STEP_8 || wr_cmdex == `CMDEX_int_2_int_trap_gate_more_STEP_9);
81
+ wire cond_55 = wr_cmd == `CMD_int_3 && ( wr_cmdex == `CMDEX_int_3_int_trap_gate_more_STEP_0 || wr_cmdex == `CMDEX_int_3_int_trap_gate_more_STEP_1 || wr_cmdex == `CMDEX_int_3_int_trap_gate_more_STEP_2 || wr_cmdex == `CMDEX_int_3_int_trap_gate_more_STEP_3);
82
+ wire cond_56 = (wr_cmdex == `CMDEX_int_3_int_trap_gate_more_STEP_2 && ~(exc_push_error)) || wr_cmdex == `CMDEX_int_3_int_trap_gate_more_STEP_3;
83
+ wire cond_57 = wr_cmd == `CMD_int && wr_cmdex == `CMDEX_int_STEP_0;
84
+ wire cond_58 = wr_cmd == `CMD_int && wr_cmdex == `CMDEX_int_STEP_1;
85
+ wire cond_59 = wr_cmd == `CMD_int && (wr_cmdex == `CMDEX_int_real_STEP_3 || wr_cmdex == `CMDEX_int_real_STEP_4);
86
+ wire cond_60 = wr_cmd == `CMD_int && wr_cmdex == `CMDEX_int_real_STEP_5;
87
+ wire cond_61 = wr_cmd == `CMD_int && (wr_cmdex == `CMDEX_int_protected_STEP_0 || wr_cmdex == `CMDEX_int_protected_STEP_1 || wr_cmdex == `CMDEX_int_protected_STEP_2);
88
+ wire cond_62 = wr_cmd == `CMD_int_2 && wr_cmdex == `CMDEX_int_2_int_trap_gate_same_STEP_5;
89
+ wire cond_63 = wr_cmd == `CMD_int_3 && wr_cmdex == `CMDEX_int_3_int_trap_gate_more_STEP_6;
90
+ wire cond_64 = v8086_mode;
91
+ wire cond_65 = wr_cmd == `CMD_int && (wr_cmdex == `CMDEX_int_real_STEP_0 || wr_cmdex == `CMDEX_int_real_STEP_1 || wr_cmdex == `CMDEX_int_real_STEP_2);
92
+ wire cond_66 = wr_cmd == `CMD_AAM || wr_cmd == `CMD_AAD;
93
+ wire cond_67 = wr_cmd == `CMD_load_seg && wr_cmdex == `CMDEX_load_seg_STEP_1;
94
+ wire cond_68 = real_mode;
95
+ wire cond_69 = protected_mode && glob_param_1[15:2] == 14'd0;
96
+ wire cond_70 = wr_cmd == `CMD_load_seg && wr_cmdex == `CMDEX_load_seg_STEP_2;
97
+ wire cond_71 = ~(protected_mode && (glob_param_1[15:2] == 14'd0 || glob_param_1[`MC_PARAM_1_FLAG_NO_WRITE_BIT]));
98
+ wire cond_72 = glob_param_1[18:16] == `SEGMENT_TR || (glob_param_1[18:16] < `SEGMENT_LDT && `DESC_IS_NOT_ACCESSED(glob_descriptor));
99
+ wire cond_73 = glob_param_1[18:16] == `SEGMENT_TR;
100
+ wire cond_74 = glob_param_1[18:16] == `SEGMENT_LDT || (glob_param_1[18:16] < `SEGMENT_LDT && `DESC_IS_ACCESSED(glob_descriptor));
101
+ wire cond_75 = wr_cmd == `CMD_POP_seg && wr_cmdex == `CMDEX_POP_seg_STEP_1;
102
+ wire cond_76 = wr_cmd == `CMD_POP_seg && wr_cmdex == `CMDEX_POP_seg_STEP_LAST;
103
+ wire cond_77 = wr_decoder[5:3] == `SEGMENT_SS;
104
+ wire cond_78 = { wr_cmd[6:2], 2'd0 } == `CMD_BTx;
105
+ wire cond_79 = wr_cmd[1:0] != 2'd0;
106
+ wire cond_80 = wr_cmd == `CMD_IRET && wr_cmdex <= `CMDEX_IRET_real_v86_STEP_2;
107
+ wire cond_81 = wr_cmdex == `CMDEX_IRET_real_v86_STEP_0;
108
+ wire cond_82 = wr_cmd == `CMD_IRET && wr_cmdex == `CMDEX_IRET_real_v86_STEP_3;
109
+ wire cond_83 = wr_operand_32bit;
110
+ wire cond_84 = wr_cmd == `CMD_IRET && (wr_cmdex == `CMDEX_IRET_protected_STEP_0 || wr_cmdex == `CMDEX_IRET_task_switch_STEP_0 || wr_cmdex == `CMDEX_IRET_task_switch_STEP_1);
111
+ wire cond_85 = wr_cmd == `CMD_IRET && wr_cmdex >= `CMDEX_IRET_protected_STEP_1 && wr_cmdex <= `CMDEX_IRET_protected_STEP_3;
112
+ wire cond_86 = wr_cmd == `CMD_IRET && wr_cmdex >= `CMDEX_IRET_protected_to_v86_STEP_0 && wr_cmdex <= `CMDEX_IRET_protected_to_v86_STEP_4;
113
+ wire cond_87 = wr_cmd == `CMD_IRET && wr_cmdex == `CMDEX_IRET_protected_to_v86_STEP_5;
114
+ wire cond_88 = wr_cmd == `CMD_IRET_2 && wr_cmdex == `CMDEX_IRET_2_protected_to_v86_STEP_6;
115
+ wire cond_89 = wr_cmd == `CMD_IRET_2 && wr_cmdex == `CMDEX_IRET_2_protected_same_STEP_1;
116
+ wire cond_90 = cpl <= iopl;
117
+ wire cond_91 = cpl == 2'd0;
118
+ wire cond_92 = wr_cmd == `CMD_IRET_2 && wr_cmdex >= `CMDEX_IRET_2_protected_outer_STEP_0 && wr_cmdex <= `CMDEX_IRET_2_protected_outer_STEP_2;
119
+ wire cond_93 = wr_cmd == `CMD_IRET_2 && wr_cmdex == `CMDEX_IRET_2_protected_outer_STEP_4;
120
+ wire cond_94 = wr_task_rpl <= iopl;
121
+ wire cond_95 = wr_task_rpl == 2'd0;
122
+ wire cond_96 = wr_cmd == `CMD_POP && wr_cmdex == `CMDEX_POP_implicit;
123
+ wire cond_97 = wr_cmd == `CMD_POP && wr_cmdex == `CMDEX_POP_modregrm_STEP_0;
124
+ wire cond_98 = wr_cmd == `CMD_POP && wr_cmdex == `CMDEX_POP_modregrm_STEP_1;
125
+ wire cond_99 = ~(wr_dst_is_memory) || write_for_wr_ready;
126
+ wire cond_100 = wr_cmd == `CMD_IDIV || wr_cmd == `CMD_DIV;
127
+ wire cond_101 = ~(wr_is_8bit);
128
+ wire cond_102 = wr_cmd == `CMD_Shift;
129
+ wire cond_103 = ~(result_signals[4]);
130
+ wire cond_104 = result_signals[3];
131
+ wire cond_105 = result_signals[2];
132
+ wire cond_106 = wr_cmd == `CMD_CMPS && wr_cmdex == `CMDEX_CMPS_FIRST;
133
+ wire cond_107 = wr_cmd == `CMD_CMPS && wr_cmdex == `CMDEX_CMPS_LAST;
134
+ wire cond_108 = wr_string_ignore || wr_string_zf_finish || wr_prefix_group_1_rep == 2'd0;
135
+ wire cond_109 = wr_cmd == `CMD_control_reg && wr_cmdex == `CMDEX_control_reg_SMSW_STEP_0;
136
+ wire cond_110 = wr_cmd == `CMD_control_reg && wr_cmdex == `CMDEX_control_reg_LMSW_STEP_0;
137
+ wire cond_111 = cr0_pe ^ result2[0];
138
+ wire cond_112 = wr_cmd == `CMD_control_reg && wr_cmdex == `CMDEX_control_reg_MOV_store_STEP_0;
139
+ wire cond_113 = wr_cmd == `CMD_control_reg && wr_cmdex == `CMDEX_control_reg_MOV_load_STEP_0;
140
+ wire cond_114 = wr_decoder[13:11] == 3'd0;
141
+ wire cond_115 = (cr0_pe ^ result2[0]) || (cr0_wp ^ result2[16]) || (cr0_pg ^ result[31]);
142
+ wire cond_116 = cr0_pe && result2[0] == 1'b0;
143
+ wire cond_117 = wr_decoder[13:11] == 3'd2;
144
+ wire cond_118 = wr_decoder[13:11] == 3'd3;
145
+ wire cond_119 = (wr_cmd == `CMD_LGDT || wr_cmd == `CMD_LIDT);
146
+ wire cond_120 = wr_cmdex == `CMDEX_LGDT_LIDT_STEP_1;
147
+ wire cond_121 = wr_cmd == `CMD_LGDT;
148
+ wire cond_122 = wr_cmd == `CMD_LIDT;
149
+ wire cond_123 = wr_cmdex == `CMDEX_LGDT_LIDT_STEP_2;
150
+ wire cond_124 = wr_cmd == `CMD_PUSHA;
151
+ wire cond_125 = wr_cmdex[2:0] == 3'd0;
152
+ wire cond_126 = wr_cmdex[2:0] < 3'd7;
153
+ wire cond_127 = wr_cmdex[2:0] == 3'd7 && write_for_wr_ready && ~(wr_push_ss_fault);
154
+ wire cond_128 = wr_cmd == `CMD_SETcc;
155
+ wire cond_129 = wr_cmd == `CMD_CMPXCHG;
156
+ wire cond_130 = wr_cmd == `CMD_ENTER && wr_cmdex == `CMDEX_ENTER_FIRST;
157
+ wire cond_131 = wr_cmd == `CMD_ENTER && wr_cmdex == `CMDEX_ENTER_LAST;
158
+ wire cond_132 = wr_cmd == `CMD_ENTER && (wr_cmdex == `CMDEX_ENTER_PUSH || wr_cmdex == `CMDEX_ENTER_LOOP);
159
+ wire cond_133 = wr_cmd == `CMD_IMUL;
160
+ wire cond_134 = wr_dst_is_edx_eax;
161
+ wire cond_135 = wr_cmd == `CMD_LEAVE;
162
+ wire cond_136 = { wr_cmd[6:1], 1'd0 } == `CMD_SHxD;
163
+ wire cond_137 = wr_cmd == `CMD_WBINVD && wr_cmdex == `CMDEX_WBINVD_STEP_0;
164
+ wire cond_138 = wr_cmd == `CMD_WBINVD && wr_cmdex == `CMDEX_WBINVD_STEP_1;
165
+ wire cond_139 = { wr_cmd[6:3], 3'd0 } == `CMD_Arith;
166
+ wire cond_140 = wr_cmd[2:0] != 3'b111 && wr_dst_is_memory && ~(write_for_wr_ready);
167
+ wire cond_141 = wr_cmd[2:0] != 3'b111;
168
+ wire cond_142 = wr_cmd == `CMD_MUL;
169
+ wire cond_143 = wr_cmd == `CMD_LOOP;
170
+ wire cond_144 = wr_address_16bit;
171
+ wire cond_145 = wr_cmd == `CMD_TEST;
172
+ wire cond_146 = wr_cmd == `CMD_CLTS;
173
+ wire cond_147 = wr_cmd == `CMD_RET_far && wr_cmdex == `CMDEX_RET_far_STEP_1;
174
+ wire cond_148 = wr_cmd == `CMD_RET_far && wr_cmdex == `CMDEX_RET_far_STEP_2;
175
+ wire cond_149 = wr_cmd == `CMD_RET_far && wr_cmdex == `CMDEX_RET_far_real_STEP_3;
176
+ wire cond_150 = wr_cmd == `CMD_RET_far && wr_cmdex == `CMDEX_RET_far_outer_STEP_3;
177
+ wire cond_151 = wr_cmd == `CMD_RET_far && wr_cmdex == `CMDEX_RET_far_outer_STEP_4;
178
+ wire cond_152 = wr_cmd == `CMD_LODS;
179
+ wire cond_153 = wr_string_ignore || wr_string_finish;
180
+ wire cond_154 = ~(wr_string_ignore) && ~(wr_string_finish) && wr_prefix_group_1_rep != 2'd0;
181
+ wire cond_155 = wr_cmd == `CMD_XCHG && wr_cmdex == `CMDEX_XCHG_implicit;
182
+ wire cond_156 = wr_cmd == `CMD_XCHG && wr_cmdex == `CMDEX_XCHG_modregrm;
183
+ wire cond_157 = wr_cmd == `CMD_XCHG && wr_cmdex == `CMDEX_XCHG_modregrm_LAST;
184
+ wire cond_158 = wr_cmd == `CMD_PUSH;
185
+ wire cond_159 = wr_cmd == `CMD_INT_INTO && wr_cmdex == `CMDEX_INT_INTO_INT_STEP_0;
186
+ wire cond_160 = wr_cmd == `CMD_INT_INTO && wr_cmdex == `CMDEX_INT_INTO_INT3_STEP_0;
187
+ wire cond_161 = wr_cmd == `CMD_INT_INTO && wr_cmdex == `CMDEX_INT_INTO_INT1_STEP_0;
188
+ wire cond_162 = wr_cmd == `CMD_INT_INTO && wr_cmdex == `CMDEX_INT_INTO_INTO_STEP_0;
189
+ wire cond_163 = oflag;
190
+ wire cond_164 = wr_cmd == `CMD_CPUID;
191
+ wire cond_165 = eax == 32'd0;
192
+ wire cond_166 = eax != 32'd0;
193
+ wire cond_167 = wr_cmd == `CMD_IN;
194
+ wire cond_168 = ~(io_allow_check_needed) || wr_cmdex == `CMDEX_IN_protected;
195
+ wire cond_169 = wr_cmd == `CMD_NOT;
196
+ wire cond_170 = (wr_cmd == `CMD_LAR || wr_cmd == `CMD_LSL || wr_cmd == `CMD_VERR || wr_cmd == `CMD_VERW) && (wr_cmdex == `CMDEX_LAR_LSL_VERR_VERW_STEP_1 || wr_cmdex == `CMDEX_LAR_LSL_VERR_VERW_STEP_2);
197
+ wire cond_171 = (wr_cmd == `CMD_LAR || wr_cmd == `CMD_LSL) && wr_cmdex == `CMDEX_LAR_LSL_VERR_VERW_STEP_LAST;
198
+ wire cond_172 = wr_dst_is_reg;
199
+ wire cond_173 = (wr_cmd == `CMD_VERR || wr_cmd == `CMD_VERW) && wr_cmdex == `CMDEX_LAR_LSL_VERR_VERW_STEP_LAST;
200
+ wire cond_174 = (wr_cmd == `CMD_RET_far && wr_cmdex == `CMDEX_RET_far_same_STEP_3) || (wr_cmd == `CMD_IRET_2 && wr_cmdex == `CMDEX_IRET_2_protected_same_STEP_0) || (wr_cmd == `CMD_CALL_2 && wr_cmdex == `CMDEX_CALL_2_protected_seg_STEP_3) || (wr_cmd == `CMD_CALL_2 && wr_cmdex == `CMDEX_CALL_2_call_gate_same_STEP_2) || (wr_cmd == `CMD_JMP && wr_cmdex == `CMDEX_JMP_protected_seg_STEP_0) || (wr_cmd == `CMD_JMP_2 && wr_cmdex == `CMDEX_JMP_2_call_gate_STEP_2) || (wr_cmd == `CMD_int_2 && wr_cmdex == `CMDEX_int_2_int_trap_gate_same_STEP_4);
201
+ wire cond_175 = `DESC_IS_NOT_ACCESSED(glob_descriptor);
202
+ wire cond_176 = wr_cmd != `CMD_JMP && wr_cmd != `CMD_JMP_2 && wr_cmd != `CMD_int_2;
203
+ wire cond_177 = (wr_cmd == `CMD_CALL_3 && wr_cmdex == `CMDEX_CALL_3_call_gate_more_STEP_9) || (wr_cmd == `CMD_int_3 && wr_cmdex == `CMDEX_int_3_int_trap_gate_more_STEP_4);
204
+ wire cond_178 = (wr_cmd == `CMD_RET_far && wr_cmdex == `CMDEX_RET_far_same_STEP_4) || (wr_cmd == `CMD_CALL_2 && wr_cmdex == `CMDEX_CALL_2_protected_seg_STEP_4) || (wr_cmd == `CMD_CALL_2 && wr_cmdex == `CMDEX_CALL_2_call_gate_same_STEP_3) || (wr_cmd == `CMD_CALL_3 && wr_cmdex == `CMDEX_CALL_3_call_gate_more_STEP_10) || (wr_cmd == `CMD_JMP && wr_cmdex == `CMDEX_JMP_protected_seg_STEP_1) || (wr_cmd == `CMD_JMP_2 && wr_cmdex == `CMDEX_JMP_2_call_gate_STEP_3);
205
+ wire cond_179 = (wr_cmd == `CMD_RET_far && wr_cmdex == `CMDEX_RET_far_outer_STEP_5) || (wr_cmd == `CMD_IRET_2 && wr_cmdex == `CMDEX_IRET_2_protected_outer_STEP_3);
206
+ wire cond_180 = (wr_cmd == `CMD_RET_far && wr_cmdex == `CMDEX_RET_far_outer_STEP_6) || (wr_cmd == `CMD_IRET_2 && wr_cmdex == `CMDEX_IRET_2_protected_outer_STEP_5) || (wr_cmd == `CMD_CALL_3 && wr_cmdex == `CMDEX_CALL_3_call_gate_more_STEP_8) || (wr_cmd == `CMD_int_3 && wr_cmdex == `CMDEX_int_3_int_trap_gate_more_STEP_5);
207
+ wire cond_181 = `DESC_IS_NOT_ACCESSED(glob_descriptor) && glob_param_1[15:2] != 14'd0;
208
+ wire cond_182 = (wr_cmd == `CMD_RET_far && wr_cmdex == `CMDEX_RET_far_outer_STEP_7) || + (wr_cmd == `CMD_IRET_2 && wr_cmdex == `CMDEX_IRET_2_protected_outer_STEP_6);
209
+ wire cond_183 = (wr_cmd == `CMD_CALL && (wr_cmdex == `CMDEX_CALL_protected_STEP_0 || wr_cmdex == `CMDEX_CALL_protected_STEP_1)) || (wr_cmd == `CMD_JMP && (wr_cmdex == `CMDEX_JMP_protected_STEP_0 || wr_cmdex == `CMDEX_JMP_protected_STEP_1));
210
+ wire cond_184 = (wr_cmd == `CMD_CALL_2 && wr_cmdex == `CMDEX_CALL_2_task_gate_STEP_0) || (wr_cmd == `CMD_JMP && wr_cmdex == `CMDEX_JMP_task_gate_STEP_0) || (wr_cmd == `CMD_int && wr_cmdex == `CMDEX_int_task_gate_STEP_0);
211
+ wire cond_185 = (wr_cmd == `CMD_CALL_2 && wr_cmdex == `CMDEX_CALL_2_task_gate_STEP_1) || (wr_cmd == `CMD_JMP && wr_cmdex == `CMDEX_JMP_task_gate_STEP_1) || (wr_cmd == `CMD_int && wr_cmdex == `CMDEX_int_task_gate_STEP_1);
212
+ wire cond_186 = (wr_cmd == `CMD_CALL_2 && wr_cmdex == `CMDEX_CALL_2_call_gate_STEP_0) || (wr_cmd == `CMD_int && wr_cmdex == `CMDEX_int_int_trap_gate_STEP_0);
213
+ wire cond_187 = (wr_cmd == `CMD_CALL_2 && wr_cmdex == `CMDEX_CALL_2_call_gate_STEP_1) || (wr_cmd == `CMD_int && wr_cmdex == `CMDEX_int_int_trap_gate_STEP_1);
214
+ wire cond_188 = (wr_cmd == `CMD_CALL_2 && wr_cmdex == `CMDEX_CALL_2_call_gate_STEP_2) || (wr_cmd == `CMD_int && wr_cmdex == `CMDEX_int_int_trap_gate_STEP_2);
215
+ wire cond_189 = (wr_cmd == `CMD_CALL_2 && (wr_cmdex == `CMDEX_CALL_2_call_gate_same_STEP_0 || wr_cmdex == `CMDEX_CALL_2_call_gate_same_STEP_1)) || (wr_cmd == `CMD_int_2 && (wr_cmdex == `CMDEX_int_2_int_trap_gate_same_STEP_0 || wr_cmdex == `CMDEX_int_2_int_trap_gate_same_STEP_1 || wr_cmdex == `CMDEX_int_2_int_trap_gate_same_STEP_2 || wr_cmdex == `CMDEX_int_2_int_trap_gate_same_STEP_3));
216
+ wire cond_190 = (wr_cmd == `CMD_CALL_2 && wr_cmdex == `CMDEX_CALL_2_call_gate_more_STEP_0) || (wr_cmd == `CMD_int_2 && wr_cmdex == `CMDEX_int_2_int_trap_gate_more_STEP_0);
217
+ wire cond_191 = (wr_cmd == `CMD_CALL_2 && wr_cmdex == `CMDEX_CALL_2_call_gate_more_STEP_1) || (wr_cmd == `CMD_int_2 && wr_cmdex == `CMDEX_int_2_int_trap_gate_more_STEP_1);
218
+ wire cond_192 = wr_cmd == `CMD_STOS;
219
+ wire cond_193 = ~(wr_string_es_fault);
220
+ wire cond_194 = wr_string_finish;
221
+ wire cond_195 = wr_string_ignore;
222
+ wire cond_196 = wr_cmd == `CMD_INS;
223
+ wire cond_197 = wr_cmdex == `CMDEX_INS_real_1 || wr_cmdex == `CMDEX_INS_protected_1;
224
+ wire cond_198 = wr_string_finish || wr_prefix_group_1_rep == 2'd0;
225
+ wire cond_199 = wr_cmd == `CMD_OUTS;
226
+ wire cond_200 = io_allow_check_needed && wr_cmdex == `CMDEX_OUTS_first;
227
+ wire cond_201 = ~(write_io_for_wr_ready);
228
+ wire cond_202 = wr_cmd == `CMD_PUSHF;
229
+ wire cond_203 = wr_cmd == `CMD_JMP && (wr_cmdex == `CMDEX_JMP_Jv_STEP_0 || wr_cmdex == `CMDEX_JMP_Ev_STEP_0);
230
+ wire cond_204 = wr_cmd == `CMD_JMP && (wr_cmdex == `CMDEX_JMP_Ev_Jv_STEP_1 || wr_cmdex == `CMDEX_JMP_real_v8086_STEP_1);
231
+ wire cond_205 = wr_cmd == `CMD_JMP && (wr_cmdex == `CMDEX_JMP_Ep_STEP_0 || wr_cmdex == `CMDEX_JMP_Ap_STEP_0 || + wr_cmdex == `CMDEX_JMP_Ep_STEP_1 || wr_cmdex == `CMDEX_JMP_Ap_STEP_1);
232
+ wire cond_206 = wr_cmd == `CMD_JMP && wr_cmdex == `CMDEX_JMP_real_v8086_STEP_0;
233
+ wire cond_207 = wr_cmd == `CMD_JMP && wr_cmdex == `CMDEX_JMP_task_switch_STEP_0;
234
+ wire cond_208 = wr_cmd == `CMD_JMP_2 && wr_cmdex == `CMDEX_JMP_2_call_gate_STEP_0;
235
+ wire cond_209 = wr_cmd == `CMD_JMP_2 && wr_cmdex == `CMDEX_JMP_2_call_gate_STEP_1;
236
+ wire cond_210 = wr_cmd == `CMD_OUT;
237
+ wire cond_211 = ~(io_allow_check_needed) || wr_cmdex == `CMDEX_OUT_protected;
238
+ wire cond_212 = wr_cmd == `CMD_MOV;
239
+ wire cond_213 = wr_cmd == `CMD_LAHF;
240
+ wire cond_214 = wr_cmd == `CMD_CBW;
241
+ wire cond_215 = wr_cmd == `CMD_CWD;
242
+ wire cond_216 = wr_cmd == `CMD_POPF && wr_cmdex == `CMDEX_POPF_STEP_0;
243
+ wire cond_217 = (protected_mode && cpl == 2'd0) || real_mode;
244
+ wire cond_218 = (protected_mode && cpl <= iopl) || v8086_mode || real_mode;
245
+ wire cond_219 = wr_cmd == `CMD_CLI;
246
+ wire cond_220 = wr_cmd == `CMD_STI;
247
+ wire cond_221 = iflag == `FALSE;
248
+ wire cond_222 = wr_cmd == `CMD_BOUND && wr_cmdex == `CMDEX_BOUND_STEP_FIRST;
249
+ wire cond_223 = wr_cmd == `CMD_SALC && wr_cmdex == `CMDEX_SALC_STEP_0;
250
+ wire cond_224 = cflag;
251
+ wire cond_225 = wr_cmd == `CMD_task_switch && wr_cmdex == `CMDEX_task_switch_STEP_1;
252
+ wire cond_226 = wr_cmd == `CMD_task_switch && (wr_cmdex == `CMDEX_task_switch_STEP_2 || wr_cmdex == `CMDEX_task_switch_STEP_3 || wr_cmdex == `CMDEX_task_switch_STEP_4 || wr_cmdex == `CMDEX_task_switch_STEP_5);
253
+ wire cond_227 = wr_cmd == `CMD_task_switch && wr_cmdex == `CMDEX_task_switch_STEP_6;
254
+ wire cond_228 = glob_param_1[`TASK_SWITCH_SOURCE_BITS] == `TASK_SWITCH_FROM_JUMP || glob_param_1[`TASK_SWITCH_SOURCE_BITS] == `TASK_SWITCH_FROM_IRET;
255
+ wire cond_229 = wr_cmd == `CMD_task_switch && (wr_cmdex == `CMDEX_task_switch_STEP_7 || wr_cmdex == `CMDEX_task_switch_STEP_8);
256
+ wire cond_230 = wr_cmd == `CMD_task_switch && wr_cmdex == `CMDEX_task_switch_STEP_9;
257
+ wire cond_231 = wr_cmd == `CMD_task_switch && wr_cmdex == `CMDEX_task_switch_STEP_10;
258
+ wire cond_232 = wr_cmd == `CMD_task_switch_2 && wr_cmdex <= `CMDEX_task_switch_2_STEP_13;
259
+ wire cond_233 = tr_cache[`DESC_BITS_TYPE] > 4'd3 || wr_cmdex <= `CMDEX_task_switch_2_STEP_11;
260
+ wire cond_234 = wr_cmd == `CMD_task_switch && wr_cmdex == `CMDEX_task_switch_STEP_11;
261
+ wire cond_235 = glob_param_1[`TASK_SWITCH_SOURCE_BITS] == `TASK_SWITCH_FROM_CALL || glob_param_1[`TASK_SWITCH_SOURCE_BITS] == `TASK_SWITCH_FROM_INT;
262
+ wire cond_236 = wr_cmd == `CMD_task_switch && wr_cmdex >= `CMDEX_task_switch_STEP_12 && wr_cmdex <= `CMDEX_task_switch_STEP_14;
263
+ wire cond_237 = wr_cmd == `CMD_task_switch_3;
264
+ wire cond_238 = wr_cmd == `CMD_task_switch_4 && wr_cmdex == `CMDEX_task_switch_4_STEP_0;
265
+ wire cond_239 = glob_param_1[`TASK_SWITCH_SOURCE_BITS] != `TASK_SWITCH_FROM_IRET;
266
+ wire cond_240 = wr_cmd == `CMD_task_switch_4 && wr_cmdex == `CMDEX_task_switch_4_STEP_1;
267
+ wire cond_241 = glob_descriptor[`DESC_BITS_TYPE] >= 4'd9 && cr0_pg && cr3 != exe_buffer_shifted[463:432];
268
+ wire cond_242 = wr_cmd == `CMD_task_switch_4 && wr_cmdex == `CMDEX_task_switch_4_STEP_2;
269
+ wire cond_243 = glob_param_2[2:0] == 3'b000;
270
+ wire cond_244 = wr_cmd == `CMD_task_switch_4 && wr_cmdex >= `CMDEX_task_switch_4_STEP_3 && wr_cmdex <= `CMDEX_task_switch_4_STEP_8;
271
+ wire cond_245 = wr_cmdex == `CMDEX_task_switch_4_STEP_3;
272
+ wire cond_246 = glob_param_2[1:0] == 2'b00 && ~(v8086_mode) && `DESC_IS_NOT_ACCESSED(glob_descriptor);
273
+ wire cond_247 = wr_cmdex == `CMDEX_task_switch_4_STEP_4;
274
+ wire cond_248 = wr_cmdex == `CMDEX_task_switch_4_STEP_5;
275
+ wire cond_249 = wr_cmdex == `CMDEX_task_switch_4_STEP_6;
276
+ wire cond_250 = wr_cmdex == `CMDEX_task_switch_4_STEP_7;
277
+ wire cond_251 = glob_param_2[1:0] == 2'b00 && `DESC_IS_ACCESSED(glob_descriptor);
278
+ wire cond_252 = glob_param_2[1:0] != 2'b00;
279
+ wire cond_253 = wr_cmd == `CMD_task_switch_4 && wr_cmdex == `CMDEX_task_switch_4_STEP_9;
280
+ wire cond_254 = glob_param_3[16];
281
+ wire cond_255 = wr_cmd == `CMD_task_switch_4 && wr_cmdex == `CMDEX_task_switch_4_STEP_10;
282
+ wire cond_256 = glob_param_3[17] && task_trap[0];
283
+ wire cond_257 = wr_cmd == `CMD_LEA;
284
+ wire cond_258 = (wr_cmd == `CMD_SGDT || wr_cmd == `CMD_SIDT);
285
+ wire cond_259 = wr_cmdex == `CMDEX_SGDT_SIDT_STEP_1;
286
+ wire cond_260 = wr_cmdex == `CMDEX_SGDT_SIDT_STEP_2;
287
+ wire cond_261 = wr_cmd == `CMD_MOVS;
288
+ wire cond_262 = wr_cmd == `CMD_MOVSX || wr_cmd == `CMD_MOVZX;
289
+ wire cond_263 = wr_cmd == `CMD_POPA;
290
+ wire cond_264 = wr_cmdex[2:0] == 3'd7;
291
+ wire cond_265 = wr_cmd == `CMD_debug_reg && wr_cmdex == `CMDEX_debug_reg_MOV_store_STEP_0;
292
+ wire cond_266 = wr_cmd == `CMD_debug_reg && wr_cmdex == `CMDEX_debug_reg_MOV_load_STEP_0;
293
+ wire cond_267 = wr_decoder[13:11] == 3'd1;
294
+ wire cond_268 = (wr_decoder[13:11] == 3'd4 || wr_decoder[13:11] == 3'd6);
295
+ wire cond_269 = (wr_decoder[13:11] == 3'd5 || wr_decoder[13:11] == 3'd7);
296
+ wire cond_270 = wr_cmd == `CMD_debug_reg && wr_cmdex == `CMDEX_debug_reg_MOV_load_STEP_1;
297
+ wire cond_271 = wr_cmd == `CMD_XLAT;
298
+ wire cond_272 = wr_cmd == `CMD_AAA || wr_cmd == `CMD_AAS;
299
+ wire cond_273 = wr_cmd == `CMD_DAA || wr_cmd == `CMD_DAS;
300
+ wire cond_274 = { wr_cmd[6:1], 1'd0 } == `CMD_BSx;
301
+ //======================================================== saves
302
+ assign gdtr_limit_to_reg =
303
+ (cond_119 && cond_121 && cond_120)? ( result2[15:0]) :
304
+ gdtr_limit;
305
+ assign tr_to_reg =
306
+ (cond_240)? ( glob_param_1[15:0]) :
307
+ tr;
308
+ assign cr0_nw_to_reg =
309
+ (cond_113 && cond_114)? ( result2[29]) :
310
+ cr0_nw;
311
+ assign ss_rpl_to_reg =
312
+ (cond_87)? ( 2'd3) :
313
+ (cond_240)? ( task_ss[1:0]) :
314
+ ss_rpl;
315
+ assign cr0_cd_to_reg =
316
+ (cond_113 && cond_114)? ( result2[30]) :
317
+ cr0_cd;
318
+ assign cs_cache_to_reg =
319
+ (cond_87)? ( `DESC_MASK_P | `DESC_MASK_DPL | `DESC_MASK_SEG | `DESC_MASK_DATA_RWA | { 24'd0, 4'd0,wr_IRET_to_v86_cs[15:12], wr_IRET_to_v86_cs[11:0],4'd0, 16'hFFFF }) :
320
+ (cond_113 && cond_114 && cond_116)? ( { cs_cache[63:48], 1'b1, cs_cache[46:45], 1'b1, 4'b0011, cs_cache[39:0] }) :
321
+ cs_cache;
322
+ assign tr_cache_to_reg =
323
+ (cond_240)? ( glob_descriptor | 64'h0000020000000000) :
324
+ tr_cache;
325
+ assign fs_cache_valid_to_reg =
326
+ (cond_63 && cond_64)? ( `FALSE) :
327
+ (cond_87)? ( `TRUE) :
328
+ (cond_240)? ( `FALSE) :
329
+ fs_cache_valid;
330
+ assign ldtr_to_reg =
331
+ (cond_240)? ( task_ldtr) :
332
+ ldtr;
333
+ assign dr6_b12_to_reg =
334
+ (cond_266 && cond_268)? ( result2[12]) :
335
+ dr6_b12;
336
+ assign zflag_to_reg =
337
+ (cond_0)? ( zflag_result) :
338
+ (cond_24)? ( zflag_result) :
339
+ (cond_32 && cond_33)? ( zflag_result) :
340
+ (cond_37)? ( zflag_result) :
341
+ (cond_39 && cond_5)? ( `TRUE) :
342
+ (cond_39 && ~cond_5)? ( `FALSE) :
343
+ (cond_51)? ( eax[14]) :
344
+ (cond_66)? ( zflag_result) :
345
+ (cond_82)? ( glob_param_3[6]) :
346
+ (cond_87)? ( glob_param_3[6]) :
347
+ (cond_89)? ( glob_param_3[6]) :
348
+ (cond_93)? ( glob_param_5[6]) :
349
+ (cond_102 && cond_104)? ( zflag_result) :
350
+ (cond_107 && cond_33)? ( zflag_result) :
351
+ (cond_129 && cond_5)? ( `TRUE) :
352
+ (cond_129 && ~cond_5)? ( zflag_result) :
353
+ (cond_133)? ( zflag_result) :
354
+ (cond_136 && cond_104)? ( zflag_result) :
355
+ (cond_139)? ( zflag_result) :
356
+ (cond_142)? ( zflag_result) :
357
+ (cond_145)? ( zflag_result) :
358
+ (cond_171 && cond_172)? ( `TRUE) :
359
+ (cond_171 && ~cond_172)? ( `FALSE) :
360
+ (cond_173)? ( wr_dst_is_reg) :
361
+ (cond_216)? ( result2[6]) :
362
+ (cond_240)? ( task_eflags[6]) :
363
+ (cond_272)? ( zflag_result) :
364
+ (cond_273)? ( zflag_result) :
365
+ (cond_274 && cond_5)? ( `TRUE) :
366
+ (cond_274 && ~cond_5)? ( `FALSE) :
367
+ zflag;
368
+ assign fs_rpl_to_reg =
369
+ (cond_87)? ( 2'd3) :
370
+ (cond_240)? ( task_fs[1:0]) :
371
+ fs_rpl;
372
+ assign esp_to_reg =
373
+ (cond_8 && cond_10)? ( wr_stack_esp) :
374
+ (cond_11 && cond_10)? ( wr_stack_esp) :
375
+ (cond_14 && cond_15)? ( wr_new_stack_esp) :
376
+ (cond_19 && cond_15 && cond_20)? ( wr_new_stack_esp) :
377
+ (cond_21 && cond_22)? ( wr_stack_esp) :
378
+ (cond_38)? ( wr_stack_esp) :
379
+ (cond_55 && cond_15 && cond_56)? ( wr_new_stack_esp) :
380
+ (cond_65 && cond_10)? ( wr_stack_esp) :
381
+ (cond_75)? ( wr_stack_esp) :
382
+ (cond_80)? ( wr_stack_esp) :
383
+ (cond_87)? ( exe_buffer_shifted[159:128]) :
384
+ (cond_96)? ( wr_stack_esp) :
385
+ (cond_97)? ( wr_stack_esp) :
386
+ (cond_124 && cond_10)? ( wr_stack_esp) :
387
+ (cond_130)? ( wr_stack_esp) :
388
+ (cond_131)? ( wr_stack_esp) :
389
+ (cond_132 && cond_10)? ( wr_stack_esp) :
390
+ (cond_135)? ( wr_stack_esp) :
391
+ (cond_147)? ( wr_stack_esp) :
392
+ (cond_149)? ( wr_stack_esp) :
393
+ (cond_158 && cond_22)? ( wr_stack_esp) :
394
+ (cond_174 && cond_175 && ~cond_9 && cond_176)? ( wr_stack_esp) :
395
+ (cond_174 && ~cond_175 && cond_176)? ( wr_stack_esp) :
396
+ (cond_182)? ( wr_stack_esp) :
397
+ (cond_189 && cond_10)? ( wr_stack_esp) :
398
+ (cond_202 && cond_22)? ( wr_stack_esp) :
399
+ (cond_216)? ( wr_stack_esp) :
400
+ (cond_240)? ( (glob_descriptor[`DESC_BITS_TYPE] <= 4'd3)? { 16'hFFFF, exe_buffer_shifted[223:208] } : exe_buffer_shifted[239:208]) :
401
+ (cond_253 && cond_254 && cond_10)? ( wr_stack_esp) :
402
+ (cond_263)? ( wr_stack_esp) :
403
+ esp;
404
+ assign ebp_to_reg =
405
+ (cond_131)? ( { wr_operand_16bit? ebp[31:16] : exe_buffer[31:16], exe_buffer[15:0] }) :
406
+ (cond_135)? ( { wr_operand_16bit? ebp[31:16] : result_push[31:16], result_push[15:0] }) :
407
+ (cond_240)? ( (glob_descriptor[`DESC_BITS_TYPE] <= 4'd3)? { 16'hFFFF, exe_buffer_shifted[191:176] } : exe_buffer_shifted[207:176]) :
408
+ (cond_263 && cond_264)? ( { wr_operand_16bit? ebp[31:16] : exe_buffer_shifted[159:144], exe_buffer_shifted[143:128] }) :
409
+ ebp;
410
+ assign tr_rpl_to_reg =
411
+ (cond_240)? ( glob_param_1[1:0]) :
412
+ tr_rpl;
413
+ assign fs_to_reg =
414
+ (cond_63 && cond_64)? ( 16'd0) :
415
+ (cond_87)? ( wr_IRET_to_v86_fs) :
416
+ (cond_240)? ( task_fs) :
417
+ fs;
418
+ assign gs_cache_to_reg =
419
+ (cond_87)? ( `DESC_MASK_P | `DESC_MASK_DPL | `DESC_MASK_SEG | `DESC_MASK_DATA_RWA | { 24'd0, 4'd0,wr_IRET_to_v86_gs[15:12], wr_IRET_to_v86_gs[11:0],4'd0, 16'hFFFF }) :
420
+ gs_cache;
421
+ assign oflag_to_reg =
422
+ (cond_0)? ( oflag_arith) :
423
+ (cond_24)? ( oflag_arith) :
424
+ (cond_32 && cond_33)? ( oflag_arith) :
425
+ (cond_37)? ( oflag_arith) :
426
+ (cond_66)? ( oflag_arith) :
427
+ (cond_82)? ( glob_param_3[11]) :
428
+ (cond_87)? ( glob_param_3[11]) :
429
+ (cond_89)? ( glob_param_3[11]) :
430
+ (cond_93)? ( glob_param_5[11]) :
431
+ (cond_102 && cond_105)? ( result_signals[1]) :
432
+ (cond_107 && cond_33)? ( oflag_arith) :
433
+ (cond_129 && cond_5)? ( `FALSE) :
434
+ (cond_129 && ~cond_5)? ( oflag_arith) :
435
+ (cond_133)? ( wr_mult_overflow) :
436
+ (cond_136 && cond_105)? ( result_signals[1]) :
437
+ (cond_139)? ( oflag_arith) :
438
+ (cond_142)? ( wr_mult_overflow) :
439
+ (cond_145)? ( oflag_arith) :
440
+ (cond_216)? ( result2[11]) :
441
+ (cond_240)? ( task_eflags[11]) :
442
+ (cond_272)? ( oflag_arith) :
443
+ (cond_273)? ( oflag_arith) :
444
+ (cond_274 && ~cond_5)? ( oflag_arith) :
445
+ oflag;
446
+ assign ss_to_reg =
447
+ (cond_87)? ( wr_IRET_to_v86_ss) :
448
+ (cond_240)? ( task_ss) :
449
+ ss;
450
+ assign ebx_to_reg =
451
+ (cond_164 && cond_165)? ( "TSiM") :
452
+ (cond_164 && cond_166)? ( 32'h00010000) :
453
+ (cond_240)? ( (glob_descriptor[`DESC_BITS_TYPE] <= 4'd3)? { 16'hFFFF, exe_buffer_shifted[255:240] } : exe_buffer_shifted[271:240]) :
454
+ (cond_263 && cond_264)? ( { wr_operand_16bit? ebx[31:16] : exe_buffer_shifted[95:80], exe_buffer_shifted[79:64] }) :
455
+ ebx;
456
+ assign dflag_to_reg =
457
+ (cond_48)? ( `FALSE) :
458
+ (cond_50)? ( `TRUE) :
459
+ (cond_82)? ( glob_param_3[10]) :
460
+ (cond_87)? ( glob_param_3[10]) :
461
+ (cond_89)? ( glob_param_3[10]) :
462
+ (cond_93)? ( glob_param_5[10]) :
463
+ (cond_216)? ( result2[10]) :
464
+ (cond_240)? ( task_eflags[10]) :
465
+ dflag;
466
+ assign dr3_to_reg =
467
+ (cond_266 && cond_118)? ( result2) :
468
+ dr3;
469
+ assign dr2_to_reg =
470
+ (cond_266 && cond_117)? ( result2) :
471
+ dr2;
472
+ assign acflag_to_reg =
473
+ (cond_60)? ( `FALSE) :
474
+ (cond_82 && cond_83)? ( glob_param_3[18]) :
475
+ (cond_87)? ( glob_param_3[18]) :
476
+ (cond_89 && cond_83)? ( glob_param_3[18]) :
477
+ (cond_93 && cond_83)? ( glob_param_5[18]) :
478
+ (cond_216 && cond_83)? ( result2[18]) :
479
+ (cond_240)? ( task_eflags[18]) :
480
+ acflag;
481
+ assign cr0_mp_to_reg =
482
+ (cond_110)? ( result2[1]) :
483
+ (cond_113 && cond_114)? ( result2[1]) :
484
+ cr0_mp;
485
+ assign cr0_wp_to_reg =
486
+ (cond_113 && cond_114)? ( result2[16]) :
487
+ cr0_wp;
488
+ assign cr2_to_reg =
489
+ (cond_113 && cond_117)? ( result2) :
490
+ cr2;
491
+ assign cr3_to_reg =
492
+ (cond_113 && cond_118)? ( result2) :
493
+ (cond_240 && cond_241)? ( exe_buffer_shifted[463:432]) :
494
+ cr3;
495
+ assign dr1_to_reg =
496
+ (cond_266 && cond_267)? ( result2) :
497
+ dr1;
498
+ assign dr0_to_reg =
499
+ (cond_266 && cond_114)? ( result2) :
500
+ dr0;
501
+ assign ds_rpl_to_reg =
502
+ (cond_87)? ( 2'd3) :
503
+ (cond_240)? ( task_ds[1:0]) :
504
+ ds_rpl;
505
+ assign dr7_to_reg =
506
+ (cond_240)? ( dr7 & 32'hFFFFFEAA) :
507
+ (cond_266 && cond_269)? ( result2 | 32'h00000400) :
508
+ dr7;
509
+ assign ds_cache_valid_to_reg =
510
+ (cond_63 && cond_64)? ( `FALSE) :
511
+ (cond_87)? ( `TRUE) :
512
+ (cond_240)? ( `FALSE) :
513
+ ds_cache_valid;
514
+ assign cs_to_reg =
515
+ (cond_87)? ( wr_IRET_to_v86_cs) :
516
+ (cond_240)? ( task_cs) :
517
+ cs;
518
+ assign cr0_am_to_reg =
519
+ (cond_113 && cond_114)? ( result2[18]) :
520
+ cr0_am;
521
+ assign cs_cache_valid_to_reg =
522
+ (cond_87)? ( `TRUE) :
523
+ (cond_240)? ( `FALSE) :
524
+ cs_cache_valid;
525
+ assign idtr_limit_to_reg =
526
+ (cond_119 && cond_122 && cond_120)? ( result2[15:0]) :
527
+ idtr_limit;
528
+ assign gdtr_base_to_reg =
529
+ (cond_119 && cond_121 && ~cond_120)? ( wr_operand_32bit? result2 : { 8'd0, result2[23:0] }) :
530
+ gdtr_base;
531
+ assign cr0_ne_to_reg =
532
+ (cond_113 && cond_114)? ( result2[5]) :
533
+ cr0_ne;
534
+ assign cr0_em_to_reg =
535
+ (cond_110)? ( result2[2]) :
536
+ (cond_113 && cond_114)? ( result2[2]) :
537
+ cr0_em;
538
+ assign fs_cache_to_reg =
539
+ (cond_87)? ( `DESC_MASK_P | `DESC_MASK_DPL | `DESC_MASK_SEG | `DESC_MASK_DATA_RWA | { 24'd0, 4'd0,wr_IRET_to_v86_fs[15:12], wr_IRET_to_v86_fs[11:0],4'd0, 16'hFFFF }) :
540
+ fs_cache;
541
+ assign dr6_bd_to_reg =
542
+ (cond_266 && cond_268)? ( result2[13]) :
543
+ dr6_bd;
544
+ assign idtr_base_to_reg =
545
+ (cond_119 && cond_122 && ~cond_120)? ( wr_operand_32bit? result2 : { 8'd0, result2[23:0] }) :
546
+ idtr_base;
547
+ assign gs_to_reg =
548
+ (cond_63 && cond_64)? ( 16'd0) :
549
+ (cond_87)? ( wr_IRET_to_v86_gs) :
550
+ (cond_240)? ( task_gs) :
551
+ gs;
552
+ assign ldtr_cache_to_reg =
553
+ (cond_242 && cond_243)? ( glob_descriptor) :
554
+ ldtr_cache;
555
+ assign eax_to_reg =
556
+ (cond_66)? ( { eax[31:16], result[15:0] }) :
557
+ (cond_100)? ( (wr_is_8bit || wr_operand_16bit)? { eax[31:16], result[15:0] } : result) :
558
+ (cond_129 && ~cond_5)? ( (wr_is_8bit)? { eax[31:8], result2[7:0] } : (wr_operand_16bit)? { eax[31:16], result2[15:0] } : result2) :
559
+ (cond_133 && cond_134)? ( (wr_is_8bit || wr_operand_16bit)? { eax[31:16], result[15:0] } : result) :
560
+ (cond_142 && cond_134)? ( (wr_is_8bit || wr_operand_16bit)? { eax[31:16], result[15:0] } : result) :
561
+ (cond_152 && cond_33)? ( (wr_is_8bit)? { eax[31:8], result2[7:0] } : (wr_operand_16bit)? { eax[31:16], result2[15:0] } : result2) :
562
+ (cond_155)? ( (wr_operand_16bit)? { eax[31:16], result2[15:0] } : result2) :
563
+ (cond_164 && cond_165)? ( 32'd1) :
564
+ (cond_164 && cond_166)? ( `CPUID_MODEL_FAMILY_STEPPING) :
565
+ (cond_167 && cond_168)? ( (wr_is_8bit)? { eax[31:8], result2[7:0] } : (wr_operand_16bit)? { eax[31:16], result2[15:0] } : result2) :
566
+ (cond_213)? ( { eax[31:16], sflag, zflag, 1'b0, aflag, 1'b0, pflag, 1'b1, cflag, eax[7:0] }) :
567
+ (cond_214 && cond_83)? ( { {16{eax[15]}}, eax[15:0] }) :
568
+ (cond_214 && ~cond_83)? ( { eax[31:16], {8{eax[7]}}, eax[7:0] }) :
569
+ (cond_223 && cond_224)? ( { eax[31:8], 8'hFF }) :
570
+ (cond_223 && ~cond_224)? ( { eax[31:8], 8'h00 }) :
571
+ (cond_240)? ( (glob_descriptor[`DESC_BITS_TYPE] <= 4'd3)? { 16'hFFFF, exe_buffer_shifted[351:336] } : exe_buffer_shifted[367:336]) :
572
+ (cond_263 && cond_264)? ( { wr_operand_16bit? eax[31:16] : exe_buffer[31:16], exe_buffer[15:0] }) :
573
+ (cond_272)? ( { eax[31:16], result[15:0] }) :
574
+ (cond_273)? ( { eax[31:16], result[15:0] }) :
575
+ eax;
576
+ assign dr6_bs_to_reg =
577
+ (cond_266 && cond_268)? ( result2[14]) :
578
+ dr6_bs;
579
+ assign edi_to_reg =
580
+ (cond_32 && cond_33)? ( wr_edi_final) :
581
+ (cond_107 && cond_33)? ( wr_edi_final) :
582
+ (cond_192 && cond_33 && ~cond_9)? ( wr_edi_final) :
583
+ (cond_196 && ~cond_197 && cond_33 && ~cond_9)? ( wr_edi_final) :
584
+ (cond_240)? ( (glob_descriptor[`DESC_BITS_TYPE] <= 4'd3)? { 16'hFFFF, exe_buffer_shifted[127:112] } : exe_buffer_shifted[143:112]) :
585
+ (cond_261 && cond_33 && ~cond_9)? ( wr_edi_final) :
586
+ (cond_263 && cond_264)? ( { wr_operand_16bit? edi[31:16] : exe_buffer_shifted[223:208], exe_buffer_shifted[207:192] }) :
587
+ edi;
588
+ assign dr6_bt_to_reg =
589
+ (cond_266 && cond_268)? ( result2[15]) :
590
+ dr6_bt;
591
+ wire [1:0] wr_task_rpl_to_reg =
592
+ (cond_179)? ( cpl) :
593
+ (cond_240)? ( task_cs[1:0]) :
594
+ wr_task_rpl;
595
+ assign iopl_to_reg =
596
+ (cond_82 && cond_68)? ( glob_param_3[13:12]) :
597
+ (cond_87)? ( glob_param_3[13:12]) :
598
+ (cond_89 && cond_91)? ( glob_param_3[13:12]) :
599
+ (cond_93 && cond_95)? ( glob_param_5[13:12]) :
600
+ (cond_216 && cond_217)? ( result2[13:12]) :
601
+ (cond_240)? ( task_eflags[13:12]) :
602
+ iopl;
603
+ assign ldtr_rpl_to_reg =
604
+ (cond_240)? ( task_ldtr[1:0]) :
605
+ ldtr_rpl;
606
+ assign es_rpl_to_reg =
607
+ (cond_87)? ( 2'd3) :
608
+ (cond_240)? ( task_es[1:0]) :
609
+ es_rpl;
610
+ assign ldtr_cache_valid_to_reg =
611
+ (cond_240)? ( `FALSE) :
612
+ (cond_242 && cond_243)? ( `TRUE) :
613
+ ldtr_cache_valid;
614
+ assign es_cache_to_reg =
615
+ (cond_87)? ( `DESC_MASK_P | `DESC_MASK_DPL | `DESC_MASK_SEG | `DESC_MASK_DATA_RWA | { 24'd0, 4'd0,wr_IRET_to_v86_es[15:12], wr_IRET_to_v86_es[11:0],4'd0, 16'hFFFF }) :
616
+ es_cache;
617
+ assign iflag_to_reg =
618
+ (cond_60)? ( `FALSE) :
619
+ (cond_62)? ( (glob_param_1[20] == 1'b0)? `FALSE : iflag) :
620
+ (cond_63)? ( (glob_param_3[20] == 1'b0)? `FALSE : iflag) :
621
+ (cond_82)? ( glob_param_3[9]) :
622
+ (cond_87)? ( glob_param_3[9]) :
623
+ (cond_89 && cond_90)? ( glob_param_3[9]) :
624
+ (cond_93 && cond_94)? ( glob_param_5[9]) :
625
+ (cond_216 && cond_218)? ( result2[9]) :
626
+ (cond_219)? ( `FALSE) :
627
+ (cond_220)? ( `TRUE) :
628
+ (cond_240)? ( task_eflags[9]) :
629
+ iflag;
630
+ assign sflag_to_reg =
631
+ (cond_0)? ( sflag_result) :
632
+ (cond_24)? ( sflag_result) :
633
+ (cond_32 && cond_33)? ( sflag_result) :
634
+ (cond_37)? ( sflag_result) :
635
+ (cond_51)? ( eax[15]) :
636
+ (cond_66)? ( sflag_result) :
637
+ (cond_82)? ( glob_param_3[7]) :
638
+ (cond_87)? ( glob_param_3[7]) :
639
+ (cond_89)? ( glob_param_3[7]) :
640
+ (cond_93)? ( glob_param_5[7]) :
641
+ (cond_102 && cond_104)? ( sflag_result) :
642
+ (cond_107 && cond_33)? ( sflag_result) :
643
+ (cond_129 && cond_5)? ( `FALSE) :
644
+ (cond_129 && ~cond_5)? ( sflag_result) :
645
+ (cond_133)? ( sflag_result) :
646
+ (cond_136 && cond_104)? ( sflag_result) :
647
+ (cond_139)? ( sflag_result) :
648
+ (cond_142)? ( sflag_result) :
649
+ (cond_145)? ( sflag_result) :
650
+ (cond_216)? ( result2[7]) :
651
+ (cond_240)? ( task_eflags[7]) :
652
+ (cond_272)? ( sflag_result) :
653
+ (cond_273)? ( sflag_result) :
654
+ (cond_274 && ~cond_5)? ( sflag_result) :
655
+ sflag;
656
+ assign edx_to_reg =
657
+ (cond_100 && cond_101)? ( (wr_operand_16bit)? { edx[31:16], result[31:16] } : result2) :
658
+ (cond_133 && cond_134 && cond_101)? ( (wr_operand_16bit)? { edx[31:16], result[31:16] } : result2) :
659
+ (cond_142 && cond_134 && cond_101)? ( (wr_operand_16bit)? { edx[31:16], result[31:16] } : result2) :
660
+ (cond_164 && cond_165)? ( "A re") :
661
+ (cond_164 && cond_166)? ( 32'd0) :
662
+ (cond_215 && cond_83)? ( {32{eax[31]}}) :
663
+ (cond_215 && ~cond_83)? ( { edx[31:16], {16{eax[15]}} }) :
664
+ (cond_240)? ( (glob_descriptor[`DESC_BITS_TYPE] <= 4'd3)? { 16'hFFFF, exe_buffer_shifted[287:272] } : exe_buffer_shifted[303:272]) :
665
+ (cond_263 && cond_264)? ( { wr_operand_16bit? edx[31:16] : exe_buffer_shifted[63:48], exe_buffer_shifted[47:32] }) :
666
+ edx;
667
+ assign vmflag_to_reg =
668
+ (cond_62)? ( `FALSE) :
669
+ (cond_63)? ( `FALSE) :
670
+ (cond_87)? ( glob_param_3[`EFLAGS_BIT_VM]) :
671
+ (cond_240)? ( task_eflags[17]) :
672
+ vmflag;
673
+ assign gs_rpl_to_reg =
674
+ (cond_87)? ( 2'd3) :
675
+ (cond_240)? ( task_gs[1:0]) :
676
+ gs_rpl;
677
+ assign ds_to_reg =
678
+ (cond_63 && cond_64)? ( 16'd0) :
679
+ (cond_87)? ( wr_IRET_to_v86_ds) :
680
+ (cond_240)? ( task_ds) :
681
+ ds;
682
+ assign ds_cache_to_reg =
683
+ (cond_87)? ( `DESC_MASK_P | `DESC_MASK_DPL | `DESC_MASK_SEG | `DESC_MASK_DATA_RWA | { 24'd0, 4'd0,wr_IRET_to_v86_ds[15:12], wr_IRET_to_v86_ds[11:0],4'd0, 16'hFFFF }) :
684
+ ds_cache;
685
+ assign rflag_to_reg =
686
+ (cond_60)? ( `FALSE) :
687
+ (cond_62)? ( `FALSE) :
688
+ (cond_63)? ( `FALSE) :
689
+ (cond_82 && cond_83)? ( glob_param_3[16]) :
690
+ (cond_87)? ( glob_param_3[16]) :
691
+ (cond_89 && cond_83)? ( glob_param_3[16]) :
692
+ (cond_93 && cond_83)? ( glob_param_5[16]) :
693
+ (cond_216 && cond_83)? ( result2[16]) :
694
+ (cond_240)? ( task_eflags[16]) :
695
+ rflag;
696
+ assign esi_to_reg =
697
+ (cond_107 && cond_33)? ( wr_esi_final) :
698
+ (cond_152 && cond_33)? ( wr_esi_final) :
699
+ (cond_199 && ~cond_200 && cond_33 && ~cond_201)? ( wr_esi_final) :
700
+ (cond_240)? ( (glob_descriptor[`DESC_BITS_TYPE] <= 4'd3)? { 16'hFFFF, exe_buffer_shifted[159:144] } : exe_buffer_shifted[175:144]) :
701
+ (cond_261 && cond_33 && ~cond_9)? ( wr_esi_final) :
702
+ (cond_263 && cond_264)? ( { wr_operand_16bit? esi[31:16] : exe_buffer_shifted[191:176], exe_buffer_shifted[175:160] }) :
703
+ esi;
704
+ assign ss_cache_to_reg =
705
+ (cond_87)? ( `DESC_MASK_P | `DESC_MASK_DPL | `DESC_MASK_SEG | `DESC_MASK_DATA_RWA | { 24'd0, 4'd0,wr_IRET_to_v86_ss[15:12], wr_IRET_to_v86_ss[11:0],4'd0, 16'hFFFF }) :
706
+ ss_cache;
707
+ assign gs_cache_valid_to_reg =
708
+ (cond_63 && cond_64)? ( `FALSE) :
709
+ (cond_87)? ( `TRUE) :
710
+ (cond_240)? ( `FALSE) :
711
+ gs_cache_valid;
712
+ assign es_cache_valid_to_reg =
713
+ (cond_63 && cond_64)? ( `FALSE) :
714
+ (cond_87)? ( `TRUE) :
715
+ (cond_240)? ( `FALSE) :
716
+ es_cache_valid;
717
+ assign ntflag_to_reg =
718
+ (cond_62)? ( `FALSE) :
719
+ (cond_63)? ( `FALSE) :
720
+ (cond_82)? ( glob_param_3[14]) :
721
+ (cond_87)? ( glob_param_3[14]) :
722
+ (cond_89)? ( glob_param_3[14]) :
723
+ (cond_93)? ( glob_param_5[14]) :
724
+ (cond_216)? ( result2[14]) :
725
+ (cond_240)? ( task_eflags[14] | + (glob_param_1[`TASK_SWITCH_SOURCE_BITS] == `TASK_SWITCH_FROM_CALL || glob_param_1[`TASK_SWITCH_SOURCE_BITS] == `TASK_SWITCH_FROM_INT)) :
726
+ ntflag;
727
+ assign cr0_pg_to_reg =
728
+ (cond_113 && cond_114)? ( result2[31]) :
729
+ cr0_pg;
730
+ assign tflag_to_reg =
731
+ (cond_60)? ( `FALSE) :
732
+ (cond_62)? ( `FALSE) :
733
+ (cond_63)? ( `FALSE) :
734
+ (cond_82)? ( glob_param_3[8]) :
735
+ (cond_87)? ( glob_param_3[8]) :
736
+ (cond_89)? ( glob_param_3[8]) :
737
+ (cond_93)? ( glob_param_5[8]) :
738
+ (cond_216)? ( result2[8]) :
739
+ (cond_240)? ( task_eflags[8]) :
740
+ tflag;
741
+ assign cr0_ts_to_reg =
742
+ (cond_110)? ( result2[3]) :
743
+ (cond_113 && cond_114)? ( result2[3]) :
744
+ (cond_146)? ( `FALSE) :
745
+ (cond_240)? ( `TRUE) :
746
+ cr0_ts;
747
+ assign aflag_to_reg =
748
+ (cond_0)? ( aflag_arith) :
749
+ (cond_24)? ( aflag_arith) :
750
+ (cond_32 && cond_33)? ( aflag_arith) :
751
+ (cond_37)? ( aflag_arith) :
752
+ (cond_51)? ( eax[12]) :
753
+ (cond_66)? ( aflag_arith) :
754
+ (cond_82)? ( glob_param_3[4]) :
755
+ (cond_87)? ( glob_param_3[4]) :
756
+ (cond_89)? ( glob_param_3[4]) :
757
+ (cond_93)? ( glob_param_5[4]) :
758
+ (cond_102 && cond_104)? ( aflag_arith) :
759
+ (cond_107 && cond_33)? ( aflag_arith) :
760
+ (cond_129 && cond_5)? ( `FALSE) :
761
+ (cond_129 && ~cond_5)? ( aflag_arith) :
762
+ (cond_133)? ( 1'b0) :
763
+ (cond_136 && cond_104)? ( aflag_arith) :
764
+ (cond_139)? ( aflag_arith) :
765
+ (cond_142)? ( 1'b0) :
766
+ (cond_145)? ( aflag_arith) :
767
+ (cond_216)? ( result2[4]) :
768
+ (cond_240)? ( task_eflags[4]) :
769
+ (cond_272)? ( result_signals[1]) :
770
+ (cond_273)? ( result_signals[1]) :
771
+ (cond_274 && ~cond_5)? ( aflag_arith) :
772
+ aflag;
773
+ assign ecx_to_reg =
774
+ (cond_32 && cond_33 && cond_34)? ( wr_ecx_final) :
775
+ (cond_107 && cond_33 && cond_34)? ( wr_ecx_final) :
776
+ (cond_143 && cond_144)? ( { ecx[31:16], wr_ecx_minus_1[15:0] }) :
777
+ (cond_143 && ~cond_144)? ( wr_ecx_minus_1) :
778
+ (cond_152 && cond_33 && cond_34)? ( wr_ecx_final) :
779
+ (cond_164 && cond_165)? ( "684O") :
780
+ (cond_164 && cond_166)? ( 32'd0) :
781
+ (cond_192 && cond_33 && ~cond_9 && cond_34)? ( wr_ecx_final) :
782
+ (cond_196 && ~cond_197 && cond_33 && ~cond_9 && cond_34)? ( wr_ecx_final) :
783
+ (cond_199 && ~cond_200 && cond_33 && ~cond_201 && cond_34)? ( wr_ecx_final) :
784
+ (cond_240)? ( (glob_descriptor[`DESC_BITS_TYPE] <= 4'd3)? { 16'hFFFF, exe_buffer_shifted[319:304] } : exe_buffer_shifted[335:304]) :
785
+ (cond_261 && cond_33 && ~cond_9 && cond_34)? ( wr_ecx_final) :
786
+ (cond_263 && cond_264)? ( { wr_operand_16bit? ecx[31:16] : exe_buffer_shifted[31:16], exe_buffer_shifted[15:0] }) :
787
+ ecx;
788
+ assign cr0_pe_to_reg =
789
+ (cond_110)? ( cr0_pe | result2[0]) :
790
+ (cond_113 && cond_114)? ( result2[0]) :
791
+ cr0_pe;
792
+ assign ss_cache_valid_to_reg =
793
+ (cond_87)? ( `TRUE) :
794
+ (cond_240)? ( `FALSE) :
795
+ ss_cache_valid;
796
+ assign pflag_to_reg =
797
+ (cond_0)? ( pflag_result) :
798
+ (cond_24)? ( pflag_result) :
799
+ (cond_32 && cond_33)? ( pflag_result) :
800
+ (cond_37)? ( pflag_result) :
801
+ (cond_51)? ( eax[10]) :
802
+ (cond_66)? ( pflag_result) :
803
+ (cond_82)? ( glob_param_3[2]) :
804
+ (cond_87)? ( glob_param_3[2]) :
805
+ (cond_89)? ( glob_param_3[2]) :
806
+ (cond_93)? ( glob_param_5[2]) :
807
+ (cond_102 && cond_104)? ( pflag_result) :
808
+ (cond_107 && cond_33)? ( pflag_result) :
809
+ (cond_129 && cond_5)? ( `TRUE) :
810
+ (cond_129 && ~cond_5)? ( pflag_result) :
811
+ (cond_133)? ( pflag_result) :
812
+ (cond_136 && cond_104)? ( pflag_result) :
813
+ (cond_139)? ( pflag_result) :
814
+ (cond_142)? ( pflag_result) :
815
+ (cond_145)? ( pflag_result) :
816
+ (cond_216)? ( result2[2]) :
817
+ (cond_240)? ( task_eflags[2]) :
818
+ (cond_272)? ( pflag_result) :
819
+ (cond_273)? ( pflag_result) :
820
+ (cond_274 && ~cond_5)? ( pflag_result) :
821
+ pflag;
822
+ assign dr6_breakpoints_to_reg =
823
+ (cond_266 && cond_268)? ( result2[3:0]) :
824
+ dr6_breakpoints;
825
+ assign cs_rpl_to_reg =
826
+ (cond_87)? ( 2'd3) :
827
+ (cond_240)? ( 2'd3) :
828
+ (cond_244 && cond_245)? ( wr_task_rpl) :
829
+ cs_rpl;
830
+ assign es_to_reg =
831
+ (cond_63 && cond_64)? ( 16'd0) :
832
+ (cond_87)? ( wr_IRET_to_v86_es) :
833
+ (cond_240)? ( task_es) :
834
+ es;
835
+ assign cflag_to_reg =
836
+ (cond_0)? ( cflag_arith) :
837
+ (cond_24)? ( cflag_arith) :
838
+ (cond_32 && cond_33)? ( cflag_arith) :
839
+ (cond_46)? ( `FALSE) :
840
+ (cond_47)? ( ~cflag) :
841
+ (cond_49)? ( `TRUE) :
842
+ (cond_51)? ( eax[8]) :
843
+ (cond_66)? ( cflag_arith) :
844
+ (cond_78)? ( result_signals[0]) :
845
+ (cond_82)? ( glob_param_3[0]) :
846
+ (cond_87)? ( glob_param_3[0]) :
847
+ (cond_89)? ( glob_param_3[0]) :
848
+ (cond_93)? ( glob_param_5[0]) :
849
+ (cond_102 && cond_105)? ( result_signals[0]) :
850
+ (cond_107 && cond_33)? ( cflag_arith) :
851
+ (cond_129 && cond_5)? ( `FALSE) :
852
+ (cond_129 && ~cond_5)? ( cflag_arith) :
853
+ (cond_133)? ( wr_mult_overflow) :
854
+ (cond_136 && cond_105)? ( result_signals[0]) :
855
+ (cond_139)? ( cflag_arith) :
856
+ (cond_142)? ( wr_mult_overflow) :
857
+ (cond_145)? ( cflag_arith) :
858
+ (cond_216)? ( result2[0]) :
859
+ (cond_240)? ( task_eflags[0]) :
860
+ (cond_272)? ( result_signals[1]) :
861
+ (cond_273)? ( result_signals[0]) :
862
+ (cond_274 && ~cond_5)? ( cflag_arith) :
863
+ cflag;
864
+ assign idflag_to_reg =
865
+ (cond_82 && cond_83)? ( glob_param_3[21]) :
866
+ (cond_87)? ( glob_param_3[21]) :
867
+ (cond_89 && cond_83)? ( glob_param_3[21]) :
868
+ (cond_93 && cond_83)? ( glob_param_5[21]) :
869
+ (cond_216 && cond_83)? ( result2[21]) :
870
+ (cond_240)? ( task_eflags[21]) :
871
+ idflag;
872
+ //======================================================== always
873
+ always @(posedge clk) begin
874
+ if(rst_n == 1'b0) wr_task_rpl <= 2'd0;
875
+ else wr_task_rpl <= wr_task_rpl_to_reg;
876
+ end
877
+ //======================================================== sets
878
+ assign wr_make_esp_commit =
879
+ (cond_12)? (`TRUE) :
880
+ (cond_60)? (`TRUE) :
881
+ (cond_62)? (`TRUE) :
882
+ (cond_63)? (`TRUE) :
883
+ (cond_76)? (`TRUE) :
884
+ (cond_82)? (`TRUE) :
885
+ (cond_98 && cond_99)? (`TRUE) :
886
+ (cond_124 && cond_127)? (`TRUE) :
887
+ (cond_131)? (`TRUE) :
888
+ (cond_149)? (`TRUE) :
889
+ (cond_174 && cond_175 && ~cond_9)? (`TRUE) :
890
+ (cond_174 && ~cond_175)? (`TRUE) :
891
+ (cond_182)? (`TRUE) :
892
+ (cond_240)? (`TRUE) :
893
+ (cond_255)? (`TRUE) :
894
+ (cond_263 && cond_264)? (`TRUE) :
895
+ 1'd0;
896
+ assign wr_glob_param_3_value =
897
+ (cond_240)? ( (glob_descriptor[`DESC_BITS_TYPE] <= 4'd3)? glob_param_3 : glob_param_3 | 32'h00020000) :
898
+ 32'd0;
899
+ assign wr_seg_sel =
900
+ (cond_67)? ( glob_param_1[15:0]) :
901
+ (cond_70 && cond_71)? ( glob_param_1[15:0]) :
902
+ (cond_174)? ( (wr_cmd == `CMD_CALL_2 || wr_cmd == `CMD_JMP || wr_cmd == `CMD_JMP_2 || wr_cmd == `CMD_int_2)? { glob_param_1[15:2], cpl } : glob_param_1[15:0]) :
903
+ (cond_177)? ( { glob_param_1[15:2], glob_descriptor[`DESC_BITS_DPL] }) :
904
+ (cond_179)? ( glob_param_1[15:0]) :
905
+ (cond_180)? ( glob_param_1[15:0]) :
906
+ (cond_244 && cond_251)? ( glob_param_1[15:0]) :
907
+ 16'd0;
908
+ assign wr_exception_finished =
909
+ (cond_60)? (`TRUE) :
910
+ (cond_62)? (`TRUE) :
911
+ (cond_63)? (`TRUE) :
912
+ (cond_255)? (`TRUE) :
913
+ 1'd0;
914
+ assign wr_seg_cache_mask =
915
+ (cond_67 && cond_68)? ( `DESC_MASK_G | `DESC_MASK_D_B | `DESC_MASK_AVL | `DESC_MASK_LIMIT | `DESC_MASK_DPL | `DESC_MASK_TYPE) :
916
+ 64'd0;
917
+ assign write_seg_cache =
918
+ (cond_67 && cond_64)? (`TRUE) :
919
+ (cond_67 && cond_68)? (`TRUE) :
920
+ (cond_67 && cond_69)? (`TRUE) :
921
+ (cond_70 && cond_71 && cond_72 && ~cond_9)? (`TRUE) :
922
+ (cond_70 && cond_71 && cond_74)? (`TRUE) :
923
+ (cond_174 && cond_175 && ~cond_9)? (`TRUE) :
924
+ (cond_174 && ~cond_175)? (`TRUE) :
925
+ (cond_177 && cond_175 && ~cond_9)? (`TRUE) :
926
+ (cond_177 && ~cond_175)? (`TRUE) :
927
+ (cond_179 && cond_175 && ~cond_9)? (`TRUE) :
928
+ (cond_179 && ~cond_175)? (`TRUE) :
929
+ (cond_180 && cond_181 && ~cond_9)? (`TRUE) :
930
+ (cond_180 && ~cond_181)? (`TRUE) :
931
+ (cond_244 && cond_246 && ~cond_9)? (`TRUE) :
932
+ (cond_244 && cond_251)? (`TRUE) :
933
+ 1'd0;
934
+ assign wr_seg_rpl =
935
+ (cond_67 && cond_64)? ( 2'd3) :
936
+ (cond_67 && cond_68)? ( 2'd0) :
937
+ (cond_67 && cond_69)? ( glob_param_1[1:0]) :
938
+ (cond_70 && cond_71)? ( glob_param_1[1:0]) :
939
+ (cond_174)? ( (wr_cmd == `CMD_CALL_2 || wr_cmd == `CMD_JMP || wr_cmd == `CMD_JMP_2 || wr_cmd == `CMD_int_2)? cpl : glob_param_1[1:0]) :
940
+ (cond_177)? ( glob_descriptor[`DESC_BITS_DPL]) :
941
+ (cond_179)? ( glob_param_1[1:0]) :
942
+ (cond_180)? ( glob_param_1[1:0]) :
943
+ (cond_244 && cond_251 && cond_64)? ( 2'd3) :
944
+ 2'd0;
945
+ assign wr_debug_trap_clear =
946
+ (cond_57)? (`TRUE) :
947
+ (cond_225)? (`TRUE) :
948
+ 1'd0;
949
+ assign write_length_word =
950
+ (cond_23)? (`TRUE) :
951
+ (cond_39)? (`TRUE) :
952
+ (cond_109)? (`TRUE) :
953
+ (cond_258 && cond_259)? (`TRUE) :
954
+ 1'd0;
955
+ assign wr_validate_seg_regs =
956
+ (cond_182)? (`TRUE) :
957
+ 1'd0;
958
+ assign wr_glob_param_3_set =
959
+ (cond_240)? (`TRUE) :
960
+ 1'd0;
961
+ assign wr_waiting =
962
+ (cond_0 && cond_1)? (`TRUE) :
963
+ (cond_8 && cond_9)? (`TRUE) :
964
+ (cond_11 && cond_9)? (`TRUE) :
965
+ (cond_14 && cond_9)? (`TRUE) :
966
+ (cond_18 && cond_9)? (`TRUE) :
967
+ (cond_19 && cond_9)? (`TRUE) :
968
+ (cond_21 && cond_9)? (`TRUE) :
969
+ (cond_23 && cond_1)? (`TRUE) :
970
+ (cond_24 && cond_1)? (`TRUE) :
971
+ (cond_37 && cond_1)? (`TRUE) :
972
+ (cond_39 && cond_5 && cond_1)? (`TRUE) :
973
+ (cond_54 && cond_9)? (`TRUE) :
974
+ (cond_55 && cond_9)? (`TRUE) :
975
+ (cond_65 && cond_9)? (`TRUE) :
976
+ (cond_70 && cond_71 && cond_72 && cond_9)? (`TRUE) :
977
+ (cond_78 && cond_79 && cond_1)? (`TRUE) :
978
+ (cond_98 && cond_1)? (`TRUE) :
979
+ (cond_102 && cond_103 && cond_1)? (`TRUE) :
980
+ (cond_109 && cond_1)? (`TRUE) :
981
+ (cond_124 && cond_9)? (`TRUE) :
982
+ (cond_128 && cond_1)? (`TRUE) :
983
+ (cond_129 && cond_5 && cond_1)? (`TRUE) :
984
+ (cond_130 && cond_9)? (`TRUE) :
985
+ (cond_132 && cond_9)? (`TRUE) :
986
+ (cond_136 && cond_103 && cond_1)? (`TRUE) :
987
+ (cond_139 && cond_140)? (`TRUE) :
988
+ (cond_156 && cond_1)? (`TRUE) :
989
+ (cond_158 && cond_9)? (`TRUE) :
990
+ (cond_169 && cond_1)? (`TRUE) :
991
+ (cond_174 && cond_175 && cond_9)? (`TRUE) :
992
+ (cond_177 && cond_175 && cond_9)? (`TRUE) :
993
+ (cond_179 && cond_175 && cond_9)? (`TRUE) :
994
+ (cond_180 && cond_181 && cond_9)? (`TRUE) :
995
+ (cond_189 && cond_9)? (`TRUE) :
996
+ (cond_192 && cond_33 && cond_9)? (`TRUE) :
997
+ (cond_196 && ~cond_197 && cond_33 && cond_9)? (`TRUE) :
998
+ (cond_199 && ~cond_200 && cond_33 && cond_201)? (`TRUE) :
999
+ (cond_202 && cond_9)? (`TRUE) :
1000
+ (cond_210 && cond_211 && cond_201)? (`TRUE) :
1001
+ (cond_212 && cond_1)? (`TRUE) :
1002
+ (cond_227 && cond_228 && cond_9)? (`TRUE) :
1003
+ (cond_230 && cond_9)? (`TRUE) :
1004
+ (cond_231 && cond_9)? (`TRUE) :
1005
+ (cond_232 && cond_233 && cond_9)? (`TRUE) :
1006
+ (cond_234 && cond_235 && cond_9)? (`TRUE) :
1007
+ (cond_238 && cond_239 && cond_9)? (`TRUE) :
1008
+ (cond_244 && cond_246 && cond_9)? (`TRUE) :
1009
+ (cond_253 && cond_254 && cond_9)? (`TRUE) :
1010
+ (cond_258 && cond_9)? (`TRUE) :
1011
+ (cond_261 && cond_33 && cond_9)? (`TRUE) :
1012
+ 1'd0;
1013
+ assign wr_inhibit_interrupts_and_debug =
1014
+ (cond_44 && cond_45)? (`TRUE) :
1015
+ (cond_76 && cond_77)? (`TRUE) :
1016
+ 1'd0;
1017
+ assign write_system_word =
1018
+ (cond_230)? ( tr_cache[`DESC_BITS_TYPE] <= 4'd3) :
1019
+ (cond_231)? ( tr_cache[`DESC_BITS_TYPE] <= 4'd3) :
1020
+ (cond_232 && cond_233)? ( tr_cache[`DESC_BITS_TYPE] <= 4'd3 || wr_cmdex > `CMDEX_task_switch_2_STEP_7) :
1021
+ (cond_234 && cond_235)? (`TRUE) :
1022
+ 1'd0;
1023
+ assign wr_new_push_ss_fault_check =
1024
+ (cond_14)? (`TRUE) :
1025
+ (cond_18)? (`TRUE) :
1026
+ (cond_19)? (`TRUE) :
1027
+ (cond_54)? (`TRUE) :
1028
+ (cond_55)? (`TRUE) :
1029
+ 1'd0;
1030
+ assign write_system_dword =
1031
+ (cond_230)? ( tr_cache[`DESC_BITS_TYPE] > 4'd3) :
1032
+ (cond_231)? ( tr_cache[`DESC_BITS_TYPE] > 4'd3) :
1033
+ (cond_232 && cond_233)? ( tr_cache[`DESC_BITS_TYPE] > 4'd3 && wr_cmdex <= `CMDEX_task_switch_2_STEP_7) :
1034
+ 1'd0;
1035
+ assign wr_req_reset_pr =
1036
+ (cond_4 && cond_5)? (`TRUE) :
1037
+ (cond_12)? (`TRUE) :
1038
+ (cond_25 && cond_5)? (`TRUE) :
1039
+ (cond_38)? (`TRUE) :
1040
+ (cond_60)? (`TRUE) :
1041
+ (cond_62)? (`TRUE) :
1042
+ (cond_63)? (`TRUE) :
1043
+ (cond_82)? (`TRUE) :
1044
+ (cond_88)? (`TRUE) :
1045
+ (cond_89)? (`TRUE) :
1046
+ (cond_110)? (`TRUE) :
1047
+ (cond_113)? (`TRUE) :
1048
+ (cond_143 && cond_5)? (`TRUE) :
1049
+ (cond_149)? (`TRUE) :
1050
+ (cond_178)? (`TRUE) :
1051
+ (cond_182)? (`TRUE) :
1052
+ (cond_204)? (`TRUE) :
1053
+ (cond_255)? (`TRUE) :
1054
+ 1'd0;
1055
+ assign write_seg_sel =
1056
+ (cond_67 && cond_64)? (`TRUE) :
1057
+ (cond_67 && cond_68)? (`TRUE) :
1058
+ (cond_67 && cond_69)? (`TRUE) :
1059
+ (cond_70 && cond_71 && cond_72 && ~cond_9)? (`TRUE) :
1060
+ (cond_70 && cond_71 && cond_74)? (`TRUE) :
1061
+ (cond_174 && cond_175 && ~cond_9)? (`TRUE) :
1062
+ (cond_174 && ~cond_175)? (`TRUE) :
1063
+ (cond_177 && cond_175 && ~cond_9)? (`TRUE) :
1064
+ (cond_177 && ~cond_175)? (`TRUE) :
1065
+ (cond_179 && cond_175 && ~cond_9)? (`TRUE) :
1066
+ (cond_179 && ~cond_175)? (`TRUE) :
1067
+ (cond_180 && cond_181 && ~cond_9)? (`TRUE) :
1068
+ (cond_180 && ~cond_181)? (`TRUE) :
1069
+ 1'd0;
1070
+ assign wr_glob_param_1_set =
1071
+ (cond_240)? (`TRUE) :
1072
+ (cond_242)? (`TRUE) :
1073
+ (cond_244 && cond_246 && ~cond_9 && cond_245)? (`TRUE) :
1074
+ (cond_244 && cond_246 && ~cond_9 && cond_247)? (`TRUE) :
1075
+ (cond_244 && cond_246 && ~cond_9 && cond_248)? (`TRUE) :
1076
+ (cond_244 && cond_246 && ~cond_9 && cond_249)? (`TRUE) :
1077
+ (cond_244 && cond_246 && ~cond_9 && cond_250)? (`TRUE) :
1078
+ (cond_244 && cond_251 && cond_245)? (`TRUE) :
1079
+ (cond_244 && cond_251 && cond_247)? (`TRUE) :
1080
+ (cond_244 && cond_251 && cond_248)? (`TRUE) :
1081
+ (cond_244 && cond_251 && cond_249)? (`TRUE) :
1082
+ (cond_244 && cond_251 && cond_250)? (`TRUE) :
1083
+ (cond_244 && cond_252 && cond_245)? (`TRUE) :
1084
+ (cond_244 && cond_252 && cond_247)? (`TRUE) :
1085
+ (cond_244 && cond_252 && cond_248)? (`TRUE) :
1086
+ (cond_244 && cond_252 && cond_249)? (`TRUE) :
1087
+ (cond_244 && cond_252 && cond_250)? (`TRUE) :
1088
+ 1'd0;
1089
+ assign wr_glob_param_4_set =
1090
+ (cond_240)? (`TRUE) :
1091
+ 1'd0;
1092
+ assign write_stack_virtual =
1093
+ (cond_8 && cond_10)? (`TRUE) :
1094
+ (cond_11 && cond_10)? (`TRUE) :
1095
+ (cond_21 && cond_10)? (`TRUE) :
1096
+ (cond_65 && cond_10)? (`TRUE) :
1097
+ (cond_124 && cond_10)? (`TRUE) :
1098
+ (cond_130 && cond_10)? (`TRUE) :
1099
+ (cond_132 && cond_10)? (`TRUE) :
1100
+ (cond_158 && cond_10)? (`TRUE) :
1101
+ (cond_189 && cond_10)? (`TRUE) :
1102
+ (cond_202 && cond_10)? (`TRUE) :
1103
+ (cond_253 && cond_254 && cond_10)? (`TRUE) :
1104
+ 1'd0;
1105
+ assign wr_exception_external_set =
1106
+ (cond_161)? (`TRUE) :
1107
+ 1'd0;
1108
+ assign wr_system_linear =
1109
+ (cond_230)? ( wr_task_switch_linear) :
1110
+ (cond_231)? ( wr_task_switch_linear) :
1111
+ (cond_232 && cond_233)? ( wr_task_switch_linear) :
1112
+ (cond_234 && cond_235)? ( glob_desc_base) :
1113
+ 32'd0;
1114
+ assign wr_int_soft_int_ib =
1115
+ (cond_159)? (`TRUE) :
1116
+ 1'd0;
1117
+ assign wr_error_code =
1118
+ (cond_14)? ( (ss[`SELECTOR_BITS_RPL] != cpl)? `SELECTOR_FOR_CODE(ss) : 16'd0) :
1119
+ (cond_18)? ( (glob_param_1[`SELECTOR_BITS_RPL] != cpl)? `SELECTOR_FOR_CODE(glob_param_1) : 16'd0) :
1120
+ (cond_19)? ( (glob_param_1[`SELECTOR_BITS_RPL] != cpl)? `SELECTOR_FOR_CODE(glob_param_1) : 16'd0) :
1121
+ (cond_54)? ( (glob_param_1[`SELECTOR_BITS_RPL] != cpl)? `SELECTOR_FOR_CODE(glob_param_1) : 16'd0) :
1122
+ (cond_55)? ( (glob_param_1[`SELECTOR_BITS_RPL] != cpl)? `SELECTOR_FOR_CODE(glob_param_1) : 16'd0) :
1123
+ 16'd0;
1124
+ assign write_string_es_virtual =
1125
+ (cond_192 && cond_33 && cond_193)? (`TRUE) :
1126
+ (cond_196 && ~cond_197 && cond_33)? (`TRUE) :
1127
+ (cond_261 && cond_33 && cond_193)? (`TRUE) :
1128
+ 1'd0;
1129
+ assign write_system_touch =
1130
+ (cond_70 && cond_71 && cond_72 && ~cond_73)? (`TRUE) :
1131
+ (cond_174 && cond_175)? (`TRUE) :
1132
+ (cond_177 && cond_175)? (`TRUE) :
1133
+ (cond_179 && cond_175)? (`TRUE) :
1134
+ (cond_180 && cond_181)? (`TRUE) :
1135
+ (cond_244 && cond_246)? (`TRUE) :
1136
+ 1'd0;
1137
+ assign write_virtual =
1138
+ (cond_23)? ( wr_dst_is_memory) :
1139
+ (cond_98)? ( wr_dst_is_memory) :
1140
+ (cond_109)? ( wr_dst_is_memory) :
1141
+ (cond_128)? ( wr_dst_is_memory) :
1142
+ (cond_212)? ( wr_dst_is_memory) :
1143
+ (cond_258)? (`TRUE) :
1144
+ 1'd0;
1145
+ assign wr_not_finished =
1146
+ (cond_0)? (`TRUE) :
1147
+ (cond_6)? (`TRUE) :
1148
+ (cond_7)? (`TRUE) :
1149
+ (cond_8)? (`TRUE) :
1150
+ (cond_11)? (`TRUE) :
1151
+ (cond_13)? (`TRUE) :
1152
+ (cond_14)? (`TRUE) :
1153
+ (cond_16)? (`TRUE) :
1154
+ (cond_17)? (`TRUE) :
1155
+ (cond_18)? (`TRUE) :
1156
+ (cond_19)? (`TRUE) :
1157
+ (cond_26)? (`TRUE) :
1158
+ (cond_28)? (`TRUE) :
1159
+ (cond_30)? (`TRUE) :
1160
+ (cond_31)? (`TRUE) :
1161
+ (cond_32 && cond_36)? (`TRUE) :
1162
+ (cond_41)? (`TRUE) :
1163
+ (cond_43)? (`TRUE) :
1164
+ (cond_52)? (`TRUE) :
1165
+ (cond_53)? (`TRUE) :
1166
+ (cond_54)? (`TRUE) :
1167
+ (cond_55)? (`TRUE) :
1168
+ (cond_57)? (`TRUE) :
1169
+ (cond_58)? (`TRUE) :
1170
+ (cond_59)? (`TRUE) :
1171
+ (cond_61)? (`TRUE) :
1172
+ (cond_65)? (`TRUE) :
1173
+ (cond_67)? (`TRUE) :
1174
+ (cond_70)? (`TRUE) :
1175
+ (cond_75)? (`TRUE) :
1176
+ (cond_80)? (`TRUE) :
1177
+ (cond_84)? (`TRUE) :
1178
+ (cond_85)? (`TRUE) :
1179
+ (cond_86)? (`TRUE) :
1180
+ (cond_87)? (`TRUE) :
1181
+ (cond_92)? (`TRUE) :
1182
+ (cond_93)? (`TRUE) :
1183
+ (cond_97)? (`TRUE) :
1184
+ (cond_106)? (`TRUE) :
1185
+ (cond_107 && cond_36)? (`TRUE) :
1186
+ (cond_119 && cond_120)? (`TRUE) :
1187
+ (cond_119 && ~cond_123)? (`TRUE) :
1188
+ (cond_124 && cond_126)? (`TRUE) :
1189
+ (cond_130)? (`TRUE) :
1190
+ (cond_132)? (`TRUE) :
1191
+ (cond_137)? (`TRUE) :
1192
+ (cond_147)? (`TRUE) :
1193
+ (cond_148)? (`TRUE) :
1194
+ (cond_150)? (`TRUE) :
1195
+ (cond_151)? (`TRUE) :
1196
+ (cond_152 && cond_154)? (`TRUE) :
1197
+ (cond_156)? (`TRUE) :
1198
+ (cond_159)? (`TRUE) :
1199
+ (cond_160)? (`TRUE) :
1200
+ (cond_161)? (`TRUE) :
1201
+ (cond_162 && cond_163)? (`TRUE) :
1202
+ (cond_167 && ~cond_168)? (`TRUE) :
1203
+ (cond_170)? (`TRUE) :
1204
+ (cond_174)? (`TRUE) :
1205
+ (cond_177)? (`TRUE) :
1206
+ (cond_179)? (`TRUE) :
1207
+ (cond_180)? (`TRUE) :
1208
+ (cond_183)? (`TRUE) :
1209
+ (cond_184)? (`TRUE) :
1210
+ (cond_185)? (`TRUE) :
1211
+ (cond_186)? (`TRUE) :
1212
+ (cond_187)? (`TRUE) :
1213
+ (cond_188)? (`TRUE) :
1214
+ (cond_189)? (`TRUE) :
1215
+ (cond_190)? (`TRUE) :
1216
+ (cond_191)? (`TRUE) :
1217
+ (cond_192 && cond_33 && ~cond_9 && ~cond_194 && cond_34)? (`TRUE) :
1218
+ (cond_196 && cond_197)? (`TRUE) :
1219
+ (cond_196 && ~cond_197 && cond_33 && ~cond_9 && ~cond_198)? (`TRUE) :
1220
+ (cond_199 && cond_200)? (`TRUE) :
1221
+ (cond_199 && ~cond_200 && cond_33 && ~cond_201 && ~cond_198)? (`TRUE) :
1222
+ (cond_203)? (`TRUE) :
1223
+ (cond_205)? (`TRUE) :
1224
+ (cond_206)? (`TRUE) :
1225
+ (cond_207)? (`TRUE) :
1226
+ (cond_208)? (`TRUE) :
1227
+ (cond_209)? (`TRUE) :
1228
+ (cond_210 && ~cond_211)? (`TRUE) :
1229
+ (cond_222)? (`TRUE) :
1230
+ (cond_225)? (`TRUE) :
1231
+ (cond_226)? (`TRUE) :
1232
+ (cond_227)? (`TRUE) :
1233
+ (cond_229)? (`TRUE) :
1234
+ (cond_230)? (`TRUE) :
1235
+ (cond_231)? (`TRUE) :
1236
+ (cond_232)? (`TRUE) :
1237
+ (cond_234)? (`TRUE) :
1238
+ (cond_236)? (`TRUE) :
1239
+ (cond_237)? (`TRUE) :
1240
+ (cond_238)? (`TRUE) :
1241
+ (cond_240)? (`TRUE) :
1242
+ (cond_242)? (`TRUE) :
1243
+ (cond_244)? (`TRUE) :
1244
+ (cond_253)? (`TRUE) :
1245
+ (cond_258 && cond_259)? (`TRUE) :
1246
+ (cond_261 && cond_33 && ~cond_9 && ~cond_194 && cond_34)? (`TRUE) :
1247
+ (cond_263 && ~cond_264)? (`TRUE) :
1248
+ (cond_266)? (`TRUE) :
1249
+ 1'd0;
1250
+ assign wr_int_soft_int =
1251
+ (cond_159)? (`TRUE) :
1252
+ (cond_160)? (`TRUE) :
1253
+ (cond_162 && cond_163)? (`TRUE) :
1254
+ 1'd0;
1255
+ assign wr_int =
1256
+ (cond_159)? (`TRUE) :
1257
+ (cond_160)? (`TRUE) :
1258
+ (cond_161)? (`TRUE) :
1259
+ (cond_162 && cond_163)? (`TRUE) :
1260
+ 1'd0;
1261
+ assign wr_debug_task_trigger =
1262
+ (cond_255 && cond_256)? (`TRUE) :
1263
+ 1'd0;
1264
+ assign wr_int_vector =
1265
+ (cond_159)? ( wr_decoder[15:8]) :
1266
+ (cond_160)? ( `EXCEPTION_BP) :
1267
+ (cond_161)? ( `EXCEPTION_DB) :
1268
+ (cond_162 && cond_163)? ( `EXCEPTION_OF) :
1269
+ 8'd0;
1270
+ assign wr_string_in_progress =
1271
+ (cond_32 && cond_36)? (`TRUE) :
1272
+ (cond_107 && cond_36)? (`TRUE) :
1273
+ (cond_152 && cond_154)? (`TRUE) :
1274
+ (cond_192 && cond_33 && ~cond_9 && ~cond_194 && cond_34)? (`TRUE) :
1275
+ (cond_196 && ~cond_197 && cond_33 && ~cond_9 && ~cond_198)? (`TRUE) :
1276
+ (cond_199 && ~cond_200 && cond_33 && ~cond_201 && ~cond_198)? (`TRUE) :
1277
+ (cond_261 && cond_33 && ~cond_9 && ~cond_194 && cond_34)? (`TRUE) :
1278
+ 1'd0;
1279
+ assign write_regrm =
1280
+ (cond_0)? ( wr_dst_is_rm) :
1281
+ (cond_2 && cond_3)? (`TRUE) :
1282
+ (cond_23)? ( wr_dst_is_rm) :
1283
+ (cond_24)? ( wr_dst_is_rm) :
1284
+ (cond_37)? ( wr_dst_is_implicit_reg || wr_dst_is_rm) :
1285
+ (cond_39 && cond_5)? ( wr_dst_is_rm) :
1286
+ (cond_40)? (`TRUE) :
1287
+ (cond_42)? (`TRUE) :
1288
+ (cond_78 && cond_79)? ( wr_dst_is_rm) :
1289
+ (cond_96)? (`TRUE) :
1290
+ (cond_98)? ( wr_dst_is_rm) :
1291
+ (cond_102 && cond_103)? ( wr_dst_is_rm) :
1292
+ (cond_109)? ( wr_dst_is_rm) :
1293
+ (cond_112)? (`TRUE) :
1294
+ (cond_128)? ( wr_dst_is_rm) :
1295
+ (cond_129 && cond_5)? ( wr_dst_is_rm) :
1296
+ (cond_133)? ( wr_dst_is_reg) :
1297
+ (cond_136 && cond_103)? ( wr_dst_is_rm) :
1298
+ (cond_139 && cond_141)? ( wr_dst_is_reg || wr_dst_is_rm) :
1299
+ (cond_142)? ( wr_dst_is_reg) :
1300
+ (cond_155)? (`TRUE) :
1301
+ (cond_156)? ( wr_dst_is_rm) :
1302
+ (cond_157)? (`TRUE) :
1303
+ (cond_169)? ( wr_dst_is_rm) :
1304
+ (cond_171 && cond_172)? (`TRUE) :
1305
+ (cond_212)? ( wr_dst_is_reg || wr_dst_is_rm || wr_dst_is_implicit_reg) :
1306
+ (cond_257)? (`TRUE) :
1307
+ (cond_262)? (`TRUE) :
1308
+ (cond_265)? (`TRUE) :
1309
+ (cond_274 && ~cond_5)? (`TRUE) :
1310
+ 1'd0;
1311
+ assign wr_req_reset_rd =
1312
+ (cond_4 && cond_5)? (`TRUE) :
1313
+ (cond_12)? (`TRUE) :
1314
+ (cond_25 && cond_5)? (`TRUE) :
1315
+ (cond_27)? (`TRUE) :
1316
+ (cond_29)? (`TRUE) :
1317
+ (cond_32 && cond_35)? (`TRUE) :
1318
+ (cond_38)? (`TRUE) :
1319
+ (cond_42)? (`TRUE) :
1320
+ (cond_44)? (`TRUE) :
1321
+ (cond_60)? (`TRUE) :
1322
+ (cond_62)? (`TRUE) :
1323
+ (cond_63)? (`TRUE) :
1324
+ (cond_76)? (`TRUE) :
1325
+ (cond_82)? (`TRUE) :
1326
+ (cond_88)? (`TRUE) :
1327
+ (cond_89)? (`TRUE) :
1328
+ (cond_107 && cond_108)? (`TRUE) :
1329
+ (cond_110)? (`TRUE) :
1330
+ (cond_113)? (`TRUE) :
1331
+ (cond_119 && cond_123)? (`TRUE) :
1332
+ (cond_138)? (`TRUE) :
1333
+ (cond_143 && cond_5)? (`TRUE) :
1334
+ (cond_146)? (`TRUE) :
1335
+ (cond_149)? (`TRUE) :
1336
+ (cond_152 && cond_153)? (`TRUE) :
1337
+ (cond_162 && ~cond_163)? (`TRUE) :
1338
+ (cond_164)? (`TRUE) :
1339
+ (cond_167 && cond_168)? (`TRUE) :
1340
+ (cond_178)? (`TRUE) :
1341
+ (cond_182)? (`TRUE) :
1342
+ (cond_192 && cond_33 && ~cond_9 && cond_194)? (`TRUE) :
1343
+ (cond_192 && cond_195)? (`TRUE) :
1344
+ (cond_196 && ~cond_197 && cond_33 && ~cond_9 && cond_198)? (`TRUE) :
1345
+ (cond_196 && ~cond_197 && cond_195)? (`TRUE) :
1346
+ (cond_199 && ~cond_200 && cond_33 && ~cond_201 && cond_198)? (`TRUE) :
1347
+ (cond_199 && ~cond_200 && cond_195)? (`TRUE) :
1348
+ (cond_204)? (`TRUE) :
1349
+ (cond_210 && cond_211 && ~cond_201)? (`TRUE) :
1350
+ (cond_216)? (`TRUE) :
1351
+ (cond_255)? (`TRUE) :
1352
+ (cond_261 && cond_33 && ~cond_9 && cond_194)? (`TRUE) :
1353
+ (cond_261 && cond_195)? (`TRUE) :
1354
+ (cond_270)? (`TRUE) :
1355
+ 1'd0;
1356
+ assign wr_string_gp_fault_check =
1357
+ (cond_192)? (`TRUE) :
1358
+ (cond_261)? (`TRUE) :
1359
+ 1'd0;
1360
+ assign write_rmw_system_dword =
1361
+ (cond_227 && cond_228)? (`TRUE) :
1362
+ (cond_238 && cond_239)? (`TRUE) :
1363
+ 1'd0;
1364
+ assign write_seg_cache_valid =
1365
+ (cond_67 && cond_64)? (`TRUE) :
1366
+ (cond_67 && cond_68)? (`TRUE) :
1367
+ (cond_67 && cond_69)? (`TRUE) :
1368
+ (cond_70 && cond_71 && cond_72 && ~cond_9)? (`TRUE) :
1369
+ (cond_70 && cond_71 && cond_74)? (`TRUE) :
1370
+ (cond_174 && cond_175 && ~cond_9)? (`TRUE) :
1371
+ (cond_174 && ~cond_175)? (`TRUE) :
1372
+ (cond_177 && cond_175 && ~cond_9)? (`TRUE) :
1373
+ (cond_177 && ~cond_175)? (`TRUE) :
1374
+ (cond_179 && cond_175 && ~cond_9)? (`TRUE) :
1375
+ (cond_179 && ~cond_175)? (`TRUE) :
1376
+ (cond_180 && cond_181 && ~cond_9)? (`TRUE) :
1377
+ (cond_180 && ~cond_181)? (`TRUE) :
1378
+ (cond_244 && cond_246 && ~cond_9)? (`TRUE) :
1379
+ (cond_244 && cond_251)? (`TRUE) :
1380
+ 1'd0;
1381
+ assign write_rmw_virtual =
1382
+ (cond_0)? ( wr_dst_is_memory) :
1383
+ (cond_24)? ( wr_dst_is_memory) :
1384
+ (cond_37)? ( wr_dst_is_memory) :
1385
+ (cond_39 && cond_5)? ( wr_dst_is_memory) :
1386
+ (cond_78 && cond_79)? ( wr_dst_is_memory) :
1387
+ (cond_102 && cond_103)? ( wr_dst_is_memory) :
1388
+ (cond_129 && cond_5)? ( wr_dst_is_memory) :
1389
+ (cond_136 && cond_103)? ( wr_dst_is_memory) :
1390
+ (cond_139 && cond_141)? ( wr_dst_is_memory) :
1391
+ (cond_156)? ( wr_dst_is_memory) :
1392
+ (cond_169)? ( wr_dst_is_memory) :
1393
+ 1'd0;
1394
+ assign wr_glob_param_4_value =
1395
+ (cond_240)? ( { task_fs, task_gs }) :
1396
+ 32'd0;
1397
+ assign write_length_dword =
1398
+ (cond_258 && cond_260)? (`TRUE) :
1399
+ 1'd0;
1400
+ assign tlbflushall_do =
1401
+ (cond_110 && cond_111)? (`TRUE) :
1402
+ (cond_113 && cond_114 && cond_115)? (`TRUE) :
1403
+ (cond_113 && cond_118)? (`TRUE) :
1404
+ (cond_240 && cond_241)? (`TRUE) :
1405
+ 1'd0;
1406
+ assign wr_push_length_word =
1407
+ (cond_18)? ( ~(glob_param_3[19])) :
1408
+ (cond_19)? ( ~(glob_param_3[19])) :
1409
+ (cond_21)? (`TRUE) :
1410
+ (cond_54)? ( ~(glob_param_3[19])) :
1411
+ (cond_55)? ( ~(glob_param_3[19])) :
1412
+ (cond_65)? (`TRUE) :
1413
+ (cond_189)? ( ~(glob_param_1[19])) :
1414
+ (cond_253)? ( ~(glob_param_3[17])) :
1415
+ 1'd0;
1416
+ assign wr_system_dword =
1417
+ (cond_227 && cond_228)? ( glob_param_2 & 32'hFFFFFDFF) :
1418
+ (cond_230)? ( (glob_param_1[`TASK_SWITCH_SOURCE_BITS] == `TASK_SWITCH_FROM_INT)? exc_eip : eip) :
1419
+ (cond_231)? ( result_push & ((glob_descriptor[`DESC_BITS_TYPE] == `DESC_TSS_BUSY_286 || glob_descriptor[`DESC_BITS_TYPE] == `DESC_TSS_BUSY_386)? 32'hFFFFBFFF : 32'hFFFFFFFF)) :
1420
+ (cond_232 && cond_233)? ( result2) :
1421
+ (cond_234 && cond_235)? ( { 16'd0, tr }) :
1422
+ (cond_238 && cond_239)? ( result2 | 32'h00000200) :
1423
+ 32'd0;
1424
+ assign wr_seg_cache_valid =
1425
+ (cond_67 && cond_64)? ( `TRUE) :
1426
+ (cond_67 && cond_68)? ( `TRUE) :
1427
+ (cond_70 && cond_71)? ( `TRUE) :
1428
+ (cond_174)? ( `TRUE) :
1429
+ (cond_177)? ( `TRUE) :
1430
+ (cond_179)? ( `TRUE) :
1431
+ (cond_180)? ( `TRUE) :
1432
+ (cond_244 && cond_246 && ~cond_9)? ( `TRUE) :
1433
+ (cond_244 && cond_251)? ( `TRUE) :
1434
+ 1'd0;
1435
+ assign wr_inhibit_interrupts =
1436
+ (cond_220 && cond_221)? (`TRUE) :
1437
+ 1'd0;
1438
+ assign write_seg_rpl =
1439
+ (cond_67 && cond_64)? (`TRUE) :
1440
+ (cond_67 && cond_68)? (`TRUE) :
1441
+ (cond_67 && cond_69)? (`TRUE) :
1442
+ (cond_70 && cond_71 && cond_72 && ~cond_9)? (`TRUE) :
1443
+ (cond_70 && cond_71 && cond_74)? (`TRUE) :
1444
+ (cond_174 && cond_175 && ~cond_9)? (`TRUE) :
1445
+ (cond_174 && ~cond_175)? (`TRUE) :
1446
+ (cond_177 && cond_175 && ~cond_9)? (`TRUE) :
1447
+ (cond_177 && ~cond_175)? (`TRUE) :
1448
+ (cond_179 && cond_175 && ~cond_9)? (`TRUE) :
1449
+ (cond_179 && ~cond_175)? (`TRUE) :
1450
+ (cond_180 && cond_181 && ~cond_9)? (`TRUE) :
1451
+ (cond_180 && ~cond_181)? (`TRUE) :
1452
+ (cond_244 && cond_251 && cond_64)? (`TRUE) :
1453
+ 1'd0;
1454
+ assign wr_req_reset_dec =
1455
+ (cond_4 && cond_5)? (`TRUE) :
1456
+ (cond_12)? (`TRUE) :
1457
+ (cond_25 && cond_5)? (`TRUE) :
1458
+ (cond_38)? (`TRUE) :
1459
+ (cond_60)? (`TRUE) :
1460
+ (cond_62)? (`TRUE) :
1461
+ (cond_63)? (`TRUE) :
1462
+ (cond_82)? (`TRUE) :
1463
+ (cond_88)? (`TRUE) :
1464
+ (cond_89)? (`TRUE) :
1465
+ (cond_110)? (`TRUE) :
1466
+ (cond_113)? (`TRUE) :
1467
+ (cond_143 && cond_5)? (`TRUE) :
1468
+ (cond_149)? (`TRUE) :
1469
+ (cond_178)? (`TRUE) :
1470
+ (cond_182)? (`TRUE) :
1471
+ (cond_204)? (`TRUE) :
1472
+ (cond_255)? (`TRUE) :
1473
+ 1'd0;
1474
+ assign wr_req_reset_exe =
1475
+ (cond_4 && cond_5)? (`TRUE) :
1476
+ (cond_12)? (`TRUE) :
1477
+ (cond_25 && cond_5)? (`TRUE) :
1478
+ (cond_27)? (`TRUE) :
1479
+ (cond_29)? (`TRUE) :
1480
+ (cond_32 && cond_35)? (`TRUE) :
1481
+ (cond_38)? (`TRUE) :
1482
+ (cond_42)? (`TRUE) :
1483
+ (cond_44)? (`TRUE) :
1484
+ (cond_60)? (`TRUE) :
1485
+ (cond_62)? (`TRUE) :
1486
+ (cond_63)? (`TRUE) :
1487
+ (cond_76)? (`TRUE) :
1488
+ (cond_82)? (`TRUE) :
1489
+ (cond_88)? (`TRUE) :
1490
+ (cond_89)? (`TRUE) :
1491
+ (cond_107 && cond_108)? (`TRUE) :
1492
+ (cond_110)? (`TRUE) :
1493
+ (cond_113)? (`TRUE) :
1494
+ (cond_119 && cond_123)? (`TRUE) :
1495
+ (cond_138)? (`TRUE) :
1496
+ (cond_143 && cond_5)? (`TRUE) :
1497
+ (cond_146)? (`TRUE) :
1498
+ (cond_149)? (`TRUE) :
1499
+ (cond_152 && cond_153)? (`TRUE) :
1500
+ (cond_162 && ~cond_163)? (`TRUE) :
1501
+ (cond_164)? (`TRUE) :
1502
+ (cond_167 && cond_168)? (`TRUE) :
1503
+ (cond_178)? (`TRUE) :
1504
+ (cond_182)? (`TRUE) :
1505
+ (cond_192 && cond_33 && ~cond_9 && cond_194)? (`TRUE) :
1506
+ (cond_192 && cond_195)? (`TRUE) :
1507
+ (cond_196 && ~cond_197 && cond_33 && ~cond_9 && cond_198)? (`TRUE) :
1508
+ (cond_196 && ~cond_197 && cond_195)? (`TRUE) :
1509
+ (cond_199 && ~cond_200 && cond_33 && ~cond_201 && cond_198)? (`TRUE) :
1510
+ (cond_199 && ~cond_200 && cond_195)? (`TRUE) :
1511
+ (cond_204)? (`TRUE) :
1512
+ (cond_210 && cond_211 && ~cond_201)? (`TRUE) :
1513
+ (cond_216)? (`TRUE) :
1514
+ (cond_255)? (`TRUE) :
1515
+ (cond_261 && cond_33 && ~cond_9 && cond_194)? (`TRUE) :
1516
+ (cond_261 && cond_195)? (`TRUE) :
1517
+ (cond_270)? (`TRUE) :
1518
+ 1'd0;
1519
+ assign wr_push_length_dword =
1520
+ (cond_18)? ( glob_param_3[19]) :
1521
+ (cond_19)? ( glob_param_3[19]) :
1522
+ (cond_54)? ( glob_param_3[19]) :
1523
+ (cond_55)? ( glob_param_3[19]) :
1524
+ (cond_189)? ( glob_param_1[19]) :
1525
+ (cond_253)? ( glob_param_3[17]) :
1526
+ 1'd0;
1527
+ assign wr_one_cycle_wait =
1528
+ (cond_8)? (`TRUE) :
1529
+ (cond_11)? (`TRUE) :
1530
+ (cond_14)? (`TRUE) :
1531
+ (cond_18)? (`TRUE) :
1532
+ (cond_19)? (`TRUE) :
1533
+ (cond_21)? (`TRUE) :
1534
+ (cond_54)? (`TRUE) :
1535
+ (cond_55)? (`TRUE) :
1536
+ (cond_65)? (`TRUE) :
1537
+ (cond_124)? (`TRUE) :
1538
+ (cond_130)? (`TRUE) :
1539
+ (cond_132)? (`TRUE) :
1540
+ (cond_158)? (`TRUE) :
1541
+ (cond_189)? (`TRUE) :
1542
+ (cond_192 && cond_33)? (`TRUE) :
1543
+ (cond_202)? (`TRUE) :
1544
+ (cond_253 && cond_254)? (`TRUE) :
1545
+ (cond_261 && cond_33)? (`TRUE) :
1546
+ 1'd0;
1547
+ assign wr_regrm_dword =
1548
+ (cond_112)? (`TRUE) :
1549
+ (cond_265)? (`TRUE) :
1550
+ 1'd0;
1551
+ assign write_io =
1552
+ (cond_199 && ~cond_200 && cond_33)? (`TRUE) :
1553
+ (cond_210 && cond_211)? (`TRUE) :
1554
+ 1'd0;
1555
+ assign write_eax =
1556
+ (cond_139 && cond_141)? ( wr_dst_is_eax) :
1557
+ (cond_212)? ( wr_dst_is_eax) :
1558
+ (cond_271)? (`TRUE) :
1559
+ 1'd0;
1560
+ assign write_new_stack_virtual =
1561
+ (cond_14 && cond_15)? (`TRUE) :
1562
+ (cond_18 && cond_15)? (`TRUE) :
1563
+ (cond_19 && cond_15)? (`TRUE) :
1564
+ (cond_54 && cond_15)? (`TRUE) :
1565
+ (cond_55 && cond_15)? (`TRUE) :
1566
+ 1'd0;
1567
+ assign wr_req_reset_micro =
1568
+ (cond_4 && cond_5)? (`TRUE) :
1569
+ (cond_12)? (`TRUE) :
1570
+ (cond_25 && cond_5)? (`TRUE) :
1571
+ (cond_27)? (`TRUE) :
1572
+ (cond_29)? (`TRUE) :
1573
+ (cond_32 && cond_35)? (`TRUE) :
1574
+ (cond_38)? (`TRUE) :
1575
+ (cond_42)? (`TRUE) :
1576
+ (cond_44)? (`TRUE) :
1577
+ (cond_60)? (`TRUE) :
1578
+ (cond_62)? (`TRUE) :
1579
+ (cond_63)? (`TRUE) :
1580
+ (cond_76)? (`TRUE) :
1581
+ (cond_82)? (`TRUE) :
1582
+ (cond_88)? (`TRUE) :
1583
+ (cond_89)? (`TRUE) :
1584
+ (cond_107 && cond_108)? (`TRUE) :
1585
+ (cond_110)? (`TRUE) :
1586
+ (cond_113)? (`TRUE) :
1587
+ (cond_119 && cond_123)? (`TRUE) :
1588
+ (cond_138)? (`TRUE) :
1589
+ (cond_143 && cond_5)? (`TRUE) :
1590
+ (cond_146)? (`TRUE) :
1591
+ (cond_149)? (`TRUE) :
1592
+ (cond_152 && cond_153)? (`TRUE) :
1593
+ (cond_162 && ~cond_163)? (`TRUE) :
1594
+ (cond_164)? (`TRUE) :
1595
+ (cond_167 && cond_168)? (`TRUE) :
1596
+ (cond_178)? (`TRUE) :
1597
+ (cond_182)? (`TRUE) :
1598
+ (cond_192 && cond_33 && ~cond_9 && cond_194)? (`TRUE) :
1599
+ (cond_192 && cond_195)? (`TRUE) :
1600
+ (cond_196 && ~cond_197 && cond_33 && ~cond_9 && cond_198)? (`TRUE) :
1601
+ (cond_196 && ~cond_197 && cond_195)? (`TRUE) :
1602
+ (cond_199 && ~cond_200 && cond_33 && ~cond_201 && cond_198)? (`TRUE) :
1603
+ (cond_199 && ~cond_200 && cond_195)? (`TRUE) :
1604
+ (cond_204)? (`TRUE) :
1605
+ (cond_210 && cond_211 && ~cond_201)? (`TRUE) :
1606
+ (cond_216)? (`TRUE) :
1607
+ (cond_255)? (`TRUE) :
1608
+ (cond_261 && cond_33 && ~cond_9 && cond_194)? (`TRUE) :
1609
+ (cond_261 && cond_195)? (`TRUE) :
1610
+ (cond_270)? (`TRUE) :
1611
+ 1'd0;
1612
+ assign wr_make_esp_speculative =
1613
+ (cond_7)? (`TRUE) :
1614
+ (cond_11 && cond_10)? (`TRUE) :
1615
+ (cond_57)? (`TRUE) :
1616
+ (cond_75)? (`TRUE) :
1617
+ (cond_80 && cond_81)? (`TRUE) :
1618
+ (cond_97)? (`TRUE) :
1619
+ (cond_124 && cond_125)? (`TRUE) :
1620
+ (cond_130)? (`TRUE) :
1621
+ (cond_147)? (`TRUE) :
1622
+ (cond_253 && cond_254)? (`TRUE) :
1623
+ (cond_263 && cond_125)? (`TRUE) :
1624
+ 1'd0;
1625
+ assign write_system_busy_tss =
1626
+ (cond_70 && cond_71 && cond_72 && cond_73)? (`TRUE) :
1627
+ 1'd0;
1628
+ assign wr_hlt_in_progress =
1629
+ (cond_31)? (`TRUE) :
1630
+ 1'd0;
1631
+ assign wr_regrm_word =
1632
+ (cond_39)? (`TRUE) :
1633
+ 1'd0;
1634
+ assign wr_glob_param_1_value =
1635
+ (cond_240)? ( (glob_descriptor[`DESC_BITS_TYPE] <= 4'd3)? { 13'd0, `SEGMENT_LDT, exe_buffer_shifted[47:32] } : { 13'd0, `SEGMENT_LDT, exe_buffer_shifted[15:0] }) :
1636
+ (cond_242)? ( { 13'd0, `SEGMENT_SS, task_ss }) :
1637
+ (cond_244 && cond_246 && ~cond_9 && cond_245)? ( { 13'd0, `SEGMENT_DS, task_ds }) :
1638
+ (cond_244 && cond_246 && ~cond_9 && cond_247)? ( { 13'd0, `SEGMENT_ES, task_es }) :
1639
+ (cond_244 && cond_246 && ~cond_9 && cond_248)? ( { 13'd0, `SEGMENT_FS, glob_param_4[31:16] }) :
1640
+ (cond_244 && cond_246 && ~cond_9 && cond_249)? ( { 13'd0, `SEGMENT_GS, glob_param_4[15:0] }) :
1641
+ (cond_244 && cond_246 && ~cond_9 && cond_250)? ( { 13'd0, `SEGMENT_CS, task_cs }) :
1642
+ (cond_244 && cond_251 && cond_245)? ( { 13'd0, `SEGMENT_DS, task_ds }) :
1643
+ (cond_244 && cond_251 && cond_247)? ( { 13'd0, `SEGMENT_ES, task_es }) :
1644
+ (cond_244 && cond_251 && cond_248)? ( { 13'd0, `SEGMENT_FS, glob_param_4[31:16] }) :
1645
+ (cond_244 && cond_251 && cond_249)? ( { 13'd0, `SEGMENT_GS, glob_param_4[15:0] }) :
1646
+ (cond_244 && cond_251 && cond_250)? ( { 13'd0, `SEGMENT_CS, task_cs }) :
1647
+ (cond_244 && cond_252 && cond_245)? ( { 13'd0, `SEGMENT_DS, task_ds }) :
1648
+ (cond_244 && cond_252 && cond_247)? ( { 13'd0, `SEGMENT_ES, task_es }) :
1649
+ (cond_244 && cond_252 && cond_248)? ( { 13'd0, `SEGMENT_FS, glob_param_4[31:16] }) :
1650
+ (cond_244 && cond_252 && cond_249)? ( { 13'd0, `SEGMENT_GS, glob_param_4[15:0] }) :
1651
+ (cond_244 && cond_252 && cond_250)? ( { 13'd0, `SEGMENT_CS, task_cs }) :
1652
+ 32'd0;
1653
+ assign wr_push_ss_fault_check =
1654
+ (cond_8)? (`TRUE) :
1655
+ (cond_11)? (`TRUE) :
1656
+ (cond_21)? (`TRUE) :
1657
+ (cond_65)? (`TRUE) :
1658
+ (cond_124)? (`TRUE) :
1659
+ (cond_130)? (`TRUE) :
1660
+ (cond_132)? (`TRUE) :
1661
+ (cond_158)? (`TRUE) :
1662
+ (cond_189)? (`TRUE) :
1663
+ (cond_202)? (`TRUE) :
1664
+ (cond_253 && cond_254)? (`TRUE) :
1665
+ 1'd0;
snapshots/MiSTer-devel_ao486_MiSTer_pr72/rtl/ao486/commands/CMD_AAA_AAS_DAA_DAS.txt ADDED
@@ -0,0 +1,140 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+
2
+ <defines>
3
+ `define CMD_AAA #AUTOGEN_NEXT_CMD
4
+ `define CMD_AAS #AUTOGEN_NEXT_CMD
5
+ `define CMD_DAA #AUTOGEN_NEXT_CMD
6
+ `define CMD_DAS #AUTOGEN_NEXT_CMD
7
+ </defines>
8
+
9
+ <decode>
10
+ dec_ready_one && decoder[7:0] == 8'h37
11
+ `CMD_AAA
12
+ SET(dec_is_8bit);
13
+ SET(consume_one);
14
+ </decode>
15
+
16
+ <decode>
17
+ dec_ready_one && decoder[7:0] == 8'h3F
18
+ `CMD_AAS
19
+ SET(dec_is_8bit);
20
+ SET(consume_one);
21
+ </decode>
22
+
23
+ <decode>
24
+ dec_ready_one && decoder[7:0] == 8'h27
25
+ `CMD_DAA
26
+ SET(dec_is_8bit);
27
+ SET(consume_one);
28
+ </decode>
29
+
30
+ <decode>
31
+ dec_ready_one && decoder[7:0] == 8'h2F
32
+ `CMD_DAS
33
+ SET(dec_is_8bit);
34
+ SET(consume_one);
35
+ </decode>
36
+
37
+ <read>
38
+ IF(rd_cmd == `CMD_AAA || rd_cmd == `CMD_AAS || rd_cmd == `CMD_DAA || rd_cmd == `CMD_DAS);
39
+
40
+ SET(rd_dst_is_eax);
41
+
42
+ SET(rd_req_eflags);
43
+ SET(rd_req_eax);
44
+
45
+ IF(rd_mutex_busy_eax); SET(rd_waiting); ENDIF();
46
+ ENDIF();
47
+ </read>
48
+
49
+ <execute_local>
50
+ wire e_bcd_condition_cf;
51
+
52
+ wire exe_bcd_condition_af;
53
+ wire exe_bcd_condition_cf;
54
+
55
+ wire [15:0] e_aaa_sum_ax;
56
+ wire [15:0] e_aaa_result;
57
+
58
+ wire [15:0] e_aas_sub_ax;
59
+ wire [15:0] e_aas_result;
60
+
61
+ wire [7:0] e_daa_sum_low;
62
+ wire [7:0] e_daa_step1;
63
+ wire [7:0] e_daa_sum_high;
64
+ wire [7:0] e_daa_result;
65
+
66
+ wire [7:0] e_das_sub_low;
67
+ wire [7:0] e_das_step1;
68
+ wire [7:0] e_das_sub_high;
69
+ wire [7:0] e_das_result;
70
+
71
+ //---------
72
+
73
+ assign e_bcd_condition_cf = (dst[7:0] > 8'h99 || cflag);
74
+
75
+ assign exe_bcd_condition_af = dst[3:0] > 4'd9 || aflag;
76
+ assign exe_bcd_condition_cf = e_bcd_condition_cf || (exe_bcd_condition_af && (cflag || (exe_cmd == `CMD_DAA)? dst[7:0] > 8'hF9 : dst[7:0] < 8'h06));
77
+
78
+ // AAA
79
+ assign e_aaa_sum_ax = dst[15:0] + 16'h0106;
80
+ assign e_aaa_result = (exe_bcd_condition_af)? { e_aaa_sum_ax[15:8], 4'b0, e_aaa_sum_ax[3:0] } : { dst[15:8], 4'd0, dst[3:0] };
81
+
82
+ // AAS
83
+ assign e_aas_sub_ax = dst[15:0] - 16'h0106;
84
+ assign e_aas_result = (exe_bcd_condition_af)? { e_aas_sub_ax[15:8], 4'b0, e_aas_sub_ax[3:0] } : { dst[15:8], 4'b0, dst[3:0] };
85
+
86
+ // DAA
87
+ assign e_daa_sum_low = dst[7:0] + 8'h06;
88
+ assign e_daa_step1 = (exe_bcd_condition_af)? e_daa_sum_low : dst[7:0];
89
+ assign e_daa_sum_high = e_daa_step1 + 8'h60;
90
+ assign e_daa_result = (e_bcd_condition_cf)? e_daa_sum_high : e_daa_step1;
91
+
92
+ // DAS
93
+ assign e_das_sub_low = dst[7:0] - 8'h06;
94
+ assign e_das_step1 = (exe_bcd_condition_af)? e_das_sub_low : dst[7:0];
95
+ assign e_das_sub_high = e_das_step1 - 8'h60;
96
+ assign e_das_result = (e_bcd_condition_cf)? e_das_sub_high : e_das_step1;
97
+ </execute_local>
98
+
99
+ <execute>
100
+ IF(exe_cmd == `CMD_AAA || exe_cmd == `CMD_AAS || exe_cmd == `CMD_DAA || exe_cmd == `CMD_DAS);
101
+
102
+ SET(exe_result, (exe_cmd == `CMD_AAA)? { 16'd0, e_aaa_result } :
103
+ (exe_cmd == `CMD_AAS)? { 16'd0, e_aas_result } :
104
+ (exe_cmd == `CMD_DAA)? { 16'd0, dst[15:8], e_daa_result } :
105
+ { 16'd0, dst[15:8], e_das_result });
106
+
107
+ SET(exe_result_signals, { 3'b0, exe_bcd_condition_af, exe_bcd_condition_cf });
108
+
109
+ IF(exe_mutex_current[`MUTEX_EFLAGS_BIT]); SET(exe_waiting); ENDIF();
110
+ ENDIF();
111
+ </execute>
112
+
113
+ <write>
114
+ IF(wr_cmd == `CMD_AAA || wr_cmd == `CMD_AAS);
115
+ SAVE(eax, { eax[31:16], result[15:0] });
116
+
117
+ SAVE(zflag, zflag_result);
118
+ SAVE(sflag, sflag_result);
119
+ SAVE(pflag, pflag_result);
120
+
121
+ SAVE(aflag, result_signals[1]);
122
+ SAVE(cflag, result_signals[1]);
123
+ SAVE(oflag, oflag_arith);
124
+ ENDIF();
125
+ </write>
126
+
127
+ <write>
128
+ IF(wr_cmd == `CMD_DAA || wr_cmd == `CMD_DAS);
129
+ SAVE(eax, { eax[31:16], result[15:0] });
130
+
131
+ SAVE(zflag, zflag_result);
132
+ SAVE(sflag, sflag_result);
133
+ SAVE(pflag, pflag_result);
134
+
135
+ SAVE(aflag, result_signals[1]);
136
+ SAVE(cflag, result_signals[0]);
137
+ SAVE(oflag, oflag_arith);
138
+ ENDIF();
139
+ </write>
140
+
snapshots/MiSTer-devel_ao486_MiSTer_pr72/rtl/ao486/commands/CMD_AAD_AAM.txt ADDED
@@ -0,0 +1,72 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+
2
+ <defines>
3
+ `define CMD_AAD #AUTOGEN_NEXT_CMD
4
+ `define CMD_AAM #AUTOGEN_NEXT_CMD
5
+ </defines>
6
+
7
+ <decode>
8
+ dec_ready_one_one && decoder[7:0] == 8'hD5
9
+ `CMD_AAD
10
+ SET(dec_is_8bit);
11
+ SET(consume_one_one);
12
+ </decode>
13
+
14
+ <decode>
15
+ dec_ready_one_one && decoder[7:0] == 8'hD4
16
+ `CMD_AAM
17
+ SET(dec_is_8bit);
18
+ SET(consume_one_one);
19
+ </decode>
20
+
21
+ <read>
22
+ IF(rd_cmd == `CMD_AAM || rd_cmd == `CMD_AAD);
23
+
24
+ SET(rd_src_is_imm);
25
+ SET(rd_dst_is_eax);
26
+
27
+ SET(rd_req_eflags);
28
+ SET(rd_req_eax);
29
+
30
+ IF(rd_mutex_busy_eax); SET(rd_waiting); ENDIF();
31
+ ENDIF();
32
+ </read>
33
+
34
+ <execute_local>
35
+ wire [7:0] e_aad_result;
36
+
37
+ assign e_aad_result = mult_result[7:0] + dst[7:0];
38
+ </execute_local>
39
+
40
+ <execute>
41
+ IF(exe_cmd == `CMD_AAD);
42
+
43
+ SET(exe_result, { 24'd0, e_aad_result });
44
+ SET(exe_result2, mult_result[63:32]);
45
+
46
+ IF(mult_busy); SET(exe_waiting); ENDIF();
47
+ ENDIF();
48
+ </execute>
49
+
50
+ <execute>
51
+ IF(exe_cmd == `CMD_AAM);
52
+
53
+ SET(exe_result, { 16'd0, div_result_quotient[7:0], div_result_remainder[7:0] });
54
+ SET(exe_result2, div_result_remainder);
55
+
56
+ IF(exe_div_exception || div_busy); SET(exe_waiting); ENDIF();
57
+ ENDIF();
58
+ </execute>
59
+
60
+ <write>
61
+ IF(wr_cmd == `CMD_AAM || wr_cmd == `CMD_AAD);
62
+ SAVE(eax, { eax[31:16], result[15:0] });
63
+
64
+ SAVE(zflag, zflag_result);
65
+ SAVE(sflag, sflag_result);
66
+ SAVE(pflag, pflag_result);
67
+
68
+ SAVE(aflag, aflag_arith);
69
+ SAVE(cflag, cflag_arith);
70
+ SAVE(oflag, oflag_arith);
71
+ ENDIF();
72
+ </write>
snapshots/MiSTer-devel_ao486_MiSTer_pr72/rtl/ao486/commands/CMD_ARPL.txt ADDED
@@ -0,0 +1,73 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+
2
+ <defines>
3
+ `define CMD_ARPL #AUTOGEN_NEXT_CMD
4
+ </defines>
5
+
6
+ <decode>
7
+ dec_ready_modregrm_one && decoder[7:0] == 8'h63
8
+ prefix_group_1_lock || ~(protected_mode)
9
+ `CMD_ARPL
10
+ SET(consume_modregrm_one);
11
+ </decode>
12
+
13
+ <read>
14
+ IF(rd_cmd == `CMD_ARPL);
15
+ // dst: rm, src: reg
16
+ IF(rd_modregrm_mod == 2'b11);
17
+
18
+ SET(rd_src_is_reg);
19
+ SET(rd_dst_is_rm);
20
+
21
+ SET(rd_req_rm);
22
+ SET(rd_req_eflags);
23
+
24
+ IF(rd_mutex_busy_modregrm_rm || rd_mutex_busy_modregrm_reg); SET(rd_waiting); ENDIF();
25
+ ENDIF();
26
+
27
+ // dst: memory, src: reg
28
+ IF(rd_modregrm_mod != 2'b11);
29
+
30
+ SET(read_length_word);
31
+
32
+ SET(rd_dst_is_memory);
33
+
34
+ SET(rd_req_memory);
35
+
36
+ IF(rd_mutex_busy_memory || rd_mutex_busy_modregrm_reg); SET(rd_waiting);
37
+ ELSE();
38
+ SET(read_rmw_virtual);
39
+
40
+ IF(~(read_for_rd_ready)); SET(rd_waiting); ENDIF();
41
+ ENDIF();
42
+ ENDIF();
43
+ ENDIF();
44
+ </read>
45
+
46
+ <execute>
47
+ IF(exe_cmd == `CMD_ARPL);
48
+
49
+ SET(exe_result, { 16'd0, dst[15:2], src[1:0] });
50
+ SET(exe_result_signals, { 4'd0, dst[1:0] < src[1:0] });
51
+ ENDIF();
52
+ </execute>
53
+
54
+ <write>
55
+ IF(wr_cmd == `CMD_ARPL);
56
+
57
+ SET(write_length_word);
58
+ SET(wr_regrm_word);
59
+
60
+ IF(result_signals[0]);
61
+
62
+ SET(write_rmw_virtual, wr_dst_is_memory);
63
+ SET(write_regrm, wr_dst_is_rm);
64
+
65
+ IF(wr_dst_is_memory && ~(write_for_wr_ready)); SET(wr_waiting); ENDIF();
66
+
67
+ SAVE(zflag, `TRUE);
68
+ ELSE();
69
+ SAVE(zflag, `FALSE);
70
+ ENDIF();
71
+ ENDIF();
72
+ </write>
73
+