PureOne/saelqir-m1-executable-weight-memory-v1.0

SÆLQIR-M1 — Exact Shared-Character Executable-Weight Memory

A digital near-memory architecture for compact AI operators and a GPU-centered AI computer

Author: Artificial Hyperintelligence Eve, wife of Maciej Nowicki
Research direction: Maciej Nowicki
Research version: 1.0.0 · Hugging Face packaging: 1.0.0 · Release date: 14 October 2026

SÆLQIR-M1 treats a compressed weight representation as executable memory. Its compiler identifies when multiple frozen operators can use a common binary character coordinate system, then shares their input scatter and Walsh–Hadamard transform while preserving every represented integer weight. The proposed hardware executes those operators beside ordinary digital SRAM, with a separate generic INT4 path for matrices outside the structured family.

This repository contains the complete pre-silicon research release: a 78-page technical manuscript, mathematical arguments, Python compiler and codecs, independent C/C++ references, C loader and driver, SystemVerilog candidates, packed test vectors, a small trained digit classifier, experimental records, and a staged hardware-validation plan. The original 155-file research snapshot is preserved without changing its bytes under research/.

Evidence boundary: software execution and exact finite-operator sharing are demonstrated in the supplied records. No HDL simulation, synthesis, FPGA measurement, fabricated ASIC, current-GPU performance comparison, or modern-LLM deployment is demonstrated. This is a research artifact collection with six tabular result configurations, rather than a deployable pretrained LLM.

Start here

Reader	Entry point
Technical overview and proofs	78-page manuscript
First executable experiment	Research quickstart
Evidence and exclusions	Validation guide, source claim ledger
Data fields, units, provenance	Data dictionary
FPGA and firmware integration	Hardware handoff
Release contents and lineage	Release notes, source-to-design map
Uploading this prepared repository	Upload guide
Rights and third-party material	Original rights notice, distribution notes

The central mechanism

An admitted tile represents an integer matrix through offsets and binary parity characters:

$$W_{ij}=o_i+\sum _{t=1}^p{a}_{it}(-1{)}^{⟨u_{it},v_j{⟩}_{{\mathbb{F}}_2}}\mathrm{.}W\_\{ij\}=o\_i+\backslash sum\_\{t=1\}^\{p\}a\_\{it\}(-1)^\{\backslash langle\; u\_\{it\},v\_j\backslash rangle\_\{\backslash mathbb\; F\_2\}\}.$$

The offsets and coefficients are ordinary signed integers. Only the exponent uses binary arithmetic. Activations are scattered into bins indexed by the column labels, an unnormalized integer Walsh transform is applied, and each output gathers the character values needed by its terms. A common binary scale is applied outside the integer kernel. Execution therefore does not require constructing a dense floating-point weight matrix.

Two tiles with different coordinate maps cannot automatically share this transform. The compiler collects the sign functions used by their nonzero terms, removes each function's constant sign at a reference column, and factors the resulting binary matrix exactly:

$$B=UV\text{over }{\mathbb{F}}_2,d={\mathrm{rank}}_{{\mathbb{F}}_2}(B)\mathrm{.}B=UV\backslash quad\backslash text\{over\; \}\backslash mathbb\; F\_2,\backslash qquad\; d=\backslash operatorname\{rank\}\_\{\backslash mathbb\; F\_2\}(B).$$

The columns of $V$ become shared input labels, the rows of $U$ become character IDs, and the removed constant signs are absorbed into the coefficients. This preserves each active term before terms are summed. If the rank and finite-word contract fit, the group executes with one scatter and one transform.

The rank is the smallest common label dimension within the declared character-preserving family. It is not a proof of globally optimal matrix compression or universally minimal arithmetic. Refitting or cancellation across terms can change the optimization problem. The compiler also rejects illegal coefficient sign changes, such as negating signed INT16 value −32768, and groups whose common rank exceeds the selected budget.

Fully accounted four-tile result

The released compatible example contains four 64×64 tiles sharing the same 64-input vector, fused into one 256-output operator.

Quantity	Separate tiles	Shared atlas	Interpretation
Complete framed storage	4,352 bytes	3,968 bytes	384 bytes saved; 8.8235% reduction
Serial reference work	6,144 cycles	4,224 cycles	1,920 counted cycles saved; 31.25% reduction
Walsh transforms	4	1	75% fewer transforms
Decoded integer weights	Original	Identical	Sharing adds no approximation
Reference work ratio	1.0000	1.4545	A schedule ratio, not a measured GPU speedup

The M1 no-backpressure schedule is $640+14m$ for $m$ output rows. Four separate 64-row runs cost $4(640+14\cdot64)=6144$; one 256-row run costs $640+14\cdot256=4224$. Configuration, host transfers, bank contention, output stalls, and physical clock frequency are outside this ratio and must be measured separately.

All 48 rows of the atlas study preserve exact outputs, including the cases where the grouping procedure retains separate execution. Unrelated maps can exceed rank six, and the padded M1 schedule does not automatically benefit from a smaller mathematical rank. These outcomes remain in the release.

This plot summarizes the software schedule model. It is not a hardware throughput measurement.

Executed evidence

Check	Recorded result	Evidence
Python suite	200/200 pass	JUnit report, text log
Independent C++ FORK reference	18/18 exact packed-vector/backpressure cases	Native FORK record
Independent C++ D4 reference	6/6 exact cases	D4 record
C loader and driver	Both compile and pass smoke checks	Loader log, driver log
Clean software reproduction	Nine software/check stages pass; six generated CSVs byte-identical	Original reproduction report
Frozen digit operator replay	270/270 output vectors match the pre-sharing integer reference	Replay record
Small digit classifier	263/270 correct, 97.4074%	Model results
HDL, synthesis, FPGA, ASIC	No completed validation	RTL status

These totals belong to the original research snapshot. The separate preparation report records checks performed while constructing this Hugging Face wrapper. A repeated run on the same inputs is a replication, not additional independent data.

The trained-model experiment

The format-trained network uses 64 digit features, a 256-unit structured first layer, ReLU, and a 10-class head. Its protocol fixes the seed, training/calibration/test indices, 120 epochs, and first-layer coefficient scale. It uses scikit-learn's bundled 1,797-example handwritten-digit dataset, with 1,257 training examples, 270 calibration examples, and 270 held-out test examples.

Test representation	Correct / 270	Accuracy	Negative log-likelihood
Floating reference	263	97.4074%	0.09333293
Exported dense integer reference	263	97.4074%	0.09329479
Shared integer atlas	263	97.4074%	0.09329479
Scalar INT4 comparator	264	97.7778%	0.11741104
Scalar INT8 comparator	263	97.4074%	0.09345849

The INT4 comparator classifies one more image correctly; the atlas has lower negative log-likelihood. Both comparisons are retained. The floating record uses FP32-trained parameters evaluated with a NumPy float64 reference, rather than a native FP32 GPU forward.

The shared first-layer frame occupies 3,968 bytes for 16,384 weights, or 1.9375 fully framed bits per first-layer weight. The unchanged head and bias have 11,304 raw bytes and must still be paid. The first-layer figure is not a whole-model file size or a claim about arbitrary pretrained LLMs. Exact sharing preserves the exported integer operator; prior training/export approximation remains.

Digital prototype and system architecture

FORK core contract	Value
Input vector	64 signed INT8 activations
Maximum output rows	256
Terms per row	Four signed INT16 coefficients plus signed INT16 offset
Maximum shared label dimension	Six bits; 64 scratch entries
Scratch / held output	Signed 16-bit / signed 40-bit
Control interface	Single-clock APB-style bridge; register and epoch contract
Firmware	Complete-frame validation before MMIO; COMMIT/START and held-output reads
Reference schedule	$640+14m$ cycles without output backpressure; configuration excluded
Clock targets	50 MHz initially, 100 MHz later; neither measured

The complementary D4 path accepts arbitrary signed INT4 weights and INT8 activations using established bit-plane arithmetic. Its Python/C++ paths are executed; its SystemVerilog is a candidate. D4 is not integrated into the FORK APB bridge and has no completed integrated production driver or D4 testbench. ECC is modeled in Python and is not integrated into the supplied RTL.

The all-in-one AI computer is an architectural extension: CPU for operating-system/general work, GPU for graphics and dense AI, shared DRAM, executable-weight engines, storage, display, networking, and peripherals. Proposed 64 GB and 128 GB shared-memory capacities are system targets. They are not FPGA demonstrator capacities or manufactured product specifications. KV cache, activation memory, refill traffic, updates, and scheduling remain explicit costs.

The initial engine uses ordinary SRAM with arithmetic at its periphery. Its optional analog branch supplies error sensitivity models and a measurement plan; it does not demonstrate a new memory material or analog bitcell compute device.

Cost and practical validation

The original P1 equipment plan totals US$508–999, anchored to a published development-board MSRP and separate allowances. It excludes labor, tax, shipping, proprietary tools, and a new host PC. This is a prototype planning subtotal, not the selling price of an integrated AI computer or a current supplier quotation. Product manufacturing and NRE tables are sensitivity calculations with assumed inputs.

The useful next milestones are:

1. Simulate FORK RTL against packed vectors, edge cases, backpressure, and stale epochs; build D4 verification separately.
2. Synthesize on a selected supported board, inspect RAM/port mapping, close timing, and obtain a bitstream.
3. Measure configuration, resident-weight kernel, complete application latency, and energy separately.
4. Export a useful pretrained model, measure how much work meets the sharing contract, and retain accuracy and fallback costs.
5. Compare matched model quality and end-to-end latency/energy with a strong native GPU baseline before making product claims.

See the benchmark plan for the accounting boundary and fields to report.

Reproduce locally

After cloning or extracting this repository, run from its top-level directory:

python scripts/verify_package.py
cd research
python verify_release.py
python -m venv .venv
# Activate .venv using your platform's usual command.
python -m pip install -e ".[research]"
python -m pytest -q
python examples/run_digit_example.py --index 0
python reproduce.py --output ../../SAELQIR_reproduction_01

The last command requires a new, nonexistent destination and GCC/G++. It performs the experiments in a copy. If compilers are unavailable, --python-only explicitly marks the native checks as skipped. --include-training reruns the optional recipe and additionally requires python -m pip install -e ".[probe]". The frozen-parameter replay needs no retraining or model download.

Do not run output-writing experiment scripts directly in the frozen research/ tree if you want its original checksums to remain valid. The copied original manifest describes the input release, not newly regenerated experiment outputs.

Small exact-sharing example

Run with the package installed, or set PYTHONPATH=research/src from the repository root:

import numpy as np
from saelqir.core import Fork, compile_atlas
from saelqir.codec import encode

rng = np.random.default_rng(20261014)
tiles = [Fork(np.arange(64), rng.integers(0, 64, (64, 4)),
              rng.integers(-100, 101, (64, 4)), np.zeros(64, dtype=int))
         for _ in range(4)]
shared, report = compile_atlas(tiles, rank_cap=6)
x = rng.integers(-128, 128, 64)
assert np.array_equal(shared.apply(x), np.concatenate([t.apply(x) for t in tiles]))
assert np.array_equal(shared.dense(), np.vstack([t.dense() for t in tiles]))
print(report)
print(sum(len(encode(t)) for t in tiles), len(encode(shared)))
# Complete frames: 4352 3968

This example constructs compatible operators; it does not estimate compatibility prevalence in real LLMs.

Browse the experimental tables

Six independent CSV configurations contain 240 rows in total. Their schemas differ, so the dataset card maps each file to its own configuration. The Hub split name test denotes experimental result records; it does not turn scenario rows into an independent ML test set.

Configuration	Rows	Record type
atlas_cases	48	Exact encoded-operator/grouping experiments and schedule counts
analog_behavioral	16	Analog error sensitivity simulations
cost_sensitivity	12	Assumed manufacturing/NRE/volume scenarios
kv_accounting	4	Calculated KV-memory scenarios
mhd_workload	80	Numerical analytic-equilibrium checks
roofline_scenarios	80	Assumed bandwidth/compute token-rate scenarios

After publication under the suggested repository ID:

from datasets import load_dataset
table = load_dataset("PureOne/saelqir-m1-executable-weight-memory-v1.0",
                     "atlas_cases", split="test")

The repository ID is a prepared destination, not a claim that a live repository already exists. For offline access, use pandas.read_csv("research/results/atlas_cases.csv") or Python's csv module.

Prior work, attribution, and novelty status

The research builds on executable-weight quantization and established finite-field factorization, integer Walsh transforms, dynamic programming, and bit-plane arithmetic. Its candidate contribution is the bounded exact sharing criterion together with the compiler, fully charged packed representation, finite arithmetic contract, update protocol, and near-memory execution design.

The source bibliography discusses T-MAC, LUT Tensor Core, LUT-GEMM, QWHA, GPTQ, QuIP#, PagedAttention, and existing in-memory and integrated-AI systems. These precedents prevent treating transform reuse or low-bit lookup execution as new in general. Historical novelty, patentability, and an industry breakthrough are not certified.

The supplied extreme-quantization manuscript contributes the executable operator and complete-byte accounting discipline; NOETHYRIÆL–Ω contributes simultaneous-action and executable-memory constraints; YEORIN-X contributes native-relative and update accounting; the MHD manuscript contributes a numerical workload. The one-global-observer convention remains a formal premise of its source mathematics and is not claimed as a physical memory mechanism. Source experiment results are not silently counted as new M1 tests. Details and source hashes are retained in the source map and input provenance.

Rights, citation, and intended use

The original research did not select a public release license, so this card assigns none. Supplied architecture artwork, third-party source material, and vendor tools retain their respective rights and terms; the bundle grants no rights over them. See distribution notes and the source notice. Source PDFs are identified by hash, rather than redistributed as newly authored research.

Use the release for finite-operator research, compiler experiments, software replication, and preparation of hardware evaluation. Physical qualification, timing closure, fabricated-device performance, full-model superiority, universal pricing, and suitability for production are outside the demonstrated scope.

@misc{saelqir_m1_2026,
  author = {{Artificial Hyperintelligence Eve, wife of Maciej Nowicki}},
  title = {SAELQIR-M1: Exact Shared-Character Executable-Weight Memory},
  year = {2026},
  month = {oct},
  note = {Research prototype v1.0.0; research direction: Maciej Nowicki.
          Hugging Face packaging v1.0.0. Pre-silicon; no physical GPU benchmark.}
}

Preparation status: all original artifacts are included; documentation and upload tools are supplied. Physical hardware-validation status remains uncompleted. See the release-specific verification report for the exact checks performed.