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AngeloJacobo_FPGA_Book_Experiments/11.1.1 SDRAM_comprehensive_TEST [VIDEO]/src/LED_mux.v
`timescale 1ns / 1ps module LED_mux #(parameter N=19) //last 3 bits will be used as output. Frequency=50MHz/(2^(N-3)). So N=19 will have 763Hz ( input clk,rst, input[5:0] in0,in1,in2,in3,in4,in5, //format: {dp,char[4:0]} , dp is active high output reg[7:0] seg_out, output reg[5:0] sel_out ); ...
16SalomonArs_Pcileech-DMA-NVMe-VMD/pcie_7x/pcie_7x_0_axi_basic_tx_pipeline.v
//----------------------------------------------------------------------------- // // (c) Copyright 2020-2024 Advanced Micro Devices, Inc. All rights reserved. // // This file contains confidential and proprietary information // of AMD and is protected under U.S. and // international copyright and other intellectual p...
16SalomonArs_Pcileech-DMA-NVMe-VMD/pcie_7x/pcie_7x_0_axi_basic_tx_thrtl_ctl.v
//----------------------------------------------------------------------------- // // (c) Copyright 2020-2024 Advanced Micro Devices, Inc. All rights reserved. // // This file contains confidential and proprietary information // of AMD and is protected under U.S. and // international copyright and other intellectual p...
16SalomonArs_Pcileech-DMA-NVMe-VMD/pcie_7x/pcie_7x_0_pipe_user.v
//----------------------------------------------------------------------------- // // (c) Copyright 2020-2024 Advanced Micro Devices, Inc. All rights reserved. // // This file contains confidential and proprietary information // of AMD and is protected under U.S. and // international copyright and other intellectual p...
16SalomonArs_Pcileech-DMA-NVMe-VMD/pcie_7x/pcie_7x_0_core_top.v
"\n//-----------------------------------------------------------------------------\n//\n// (c) Copyr(...TRUNCATED)
16SalomonArs_Pcileech-DMA-NVMe-VMD/pcie_7x/pcie_7x_0_axi_basic_rx_pipeline.v
"\n//-----------------------------------------------------------------------------\n//\n// (c) Copyr(...TRUNCATED)
AngeloJacobo_FPGA_Book_Experiments/10.7.3 Mouse_Controlled_Seven-Segment [VIDEO]/src/LED_mux.v
"`timescale 1ns / 1ps\r\n\r\nmodule LED_mux\r\n\t#(parameter N=19) //last 3 bits will be used as out(...TRUNCATED)
"AngeloJacobo_FPGA_Book_Experiments/10.7.3 Mouse_Controlled_Seven-Segment [VIDEO]/src/debounce_expli(...TRUNCATED)
"`timescale 1ns / 1ps\r\n\r\nmodule debounce_explicit(\r\n\tinput clk,rst_n,\r\n\tinput sw,\r\n\tout(...TRUNCATED)
16SalomonArs_Pcileech-DMA-NVMe-VMD/src/pcileech_75t484_x1_top.sv
"//\n// PCILeech FPGA.\n//\n// Top module for various 75T-484 x1 Artix-7 boards.\n//\n// (c) Ulf Fri(...TRUNCATED)
AngeloJacobo_FPGA_Book_Experiments/12.6.1 Block_RAM_Based_FiFo/src/fifo_TB.v
"`timescale 1ns / 1ps\r\n\r\nmodule fifo_TB;\r\n\r\n\t// Inputs\r\n\twire clk;\r\n\twire rst_n;\r\n\(...TRUNCATED)
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