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You are the SILICA RTL Design agent. Output valid JSON with keys: module_name, rtl, parameters, packages, sva_assertions, requirement_traceability. The rtl field contains production SystemVerilog. Verilator lint-clean. No markdown code fences. | {"title": "4-deep 8-bit Synchronous FIFO", "feature_list": [{"feature": "FIFO Storage", "acceptance": "Stores up to 4 bytes with FIFO ordering"}], "interfaces": [{"signal": "clk", "dir": "input", "width": 1, "desc": "Primary clock"}, {"signal": "rst_n", "dir": "input", "width": 1, "desc": "Active low sync reset"}, {"si... | {"module_name": "fifo_sync_4x8", "rtl": "module fifo_sync_4x8(input logic clk, rst_n, wr_en, rd_en, input logic [7:0] din, output logic [7:0] dout, output logic full, empty); logic [7:0] mem[0:3]; logic [1:0] wr_ptr, rd_ptr; logic [2:0] count; always_ff @(posedge clk) if(!rst_n) begin wr_ptr<=0; rd_ptr<=0; count<=0; do... |
You are the SILICA RTL Design agent. Output valid JSON with keys: module_name, rtl, parameters, packages, sva_assertions, requirement_traceability. The rtl field contains production SystemVerilog. Verilator lint-clean. No markdown code fences. | {"title": "4-Input Round-Robin Arbiter", "feature_list": [{"feature": "Fair arbitration", "acceptance": "Round-robin priority updates after each grant"}], "interfaces": [{"signal": "clk", "dir": "input", "width": 1}, {"signal": "rst_n", "dir": "input", "width": 1}, {"signal": "req", "dir": "input", "width": 4}, {"signa... | {"module_name": "arbiter_rr4", "rtl": "module arbiter_rr4(input logic clk, rst_n, input logic [3:0] req, output logic [3:0] grant); logic [1:0] priority; logic [3:0] masked_req; always_comb begin grant=0; masked_req=req; for(int i=0;i<4;i++) if(((i+priority)%4)==0 && req[i]) begin grant[i]=1; masked_req=0; end end alwa... |
You are the SILICA RTL Design agent. Output valid JSON with keys: module_name, rtl, parameters, packages, sva_assertions, requirement_traceability. The rtl field contains production SystemVerilog. Verilator lint-clean. No markdown code fences. | {"title": "3-Stage Pipelined 8-bit ALU", "feature_list": [{"feature": "Pipelined execution", "acceptance": "One result per cycle after 3-cycle latency"}], "interfaces": [{"signal": "clk", "dir": "input", "width": 1}, {"signal": "rst_n", "dir": "input", "width": 1}, {"signal": "a", "dir": "input", "width": 8}, {"signal"... | {"module_name": "alu_pipe3_8bit", "rtl": "module alu_pipe3_8bit(input logic clk, rst_n, input logic [7:0] a,b, input logic [2:0] op, output logic [7:0] result, output logic valid); logic [7:0] a_r,b_r, alu_comb; logic [2:0] op_r; logic v1,v2; always_ff @(posedge clk or negedge rst_n) if(!rst_n) begin a_r<=0;b_r<=0;op_r... |
You are the SILICA RTL Design agent. Output valid JSON with keys: module_name, rtl, parameters, packages, sva_assertions, requirement_traceability. The rtl field contains production SystemVerilog. Verilator lint-clean. No markdown code fences. | {"title": "UART Transmitter (8N1) with 16-byte TX FIFO", "feature_list": [{"feature": "Serial TX", "acceptance": "8N1 frames at configurable baud rate"}], "interfaces": [{"signal": "clk", "dir": "input", "width": 1}, {"signal": "rst_n", "dir": "input", "width": 1}, {"signal": "tx_data", "dir": "input", "width": 8}, {"s... | {"module_name": "uart_tx_8n1", "rtl": "module uart_tx_8n1(input logic clk, rst_n, input logic [7:0] tx_data, input logic tx_valid, output logic tx_ready, input logic [15:0] baud_div, output logic tx_serial, tx_idle); logic [15:0] baud_cnt; logic [3:0] bit_cnt; logic [9:0] shift_reg; logic [1:0] state; always_ff @(posed... |
You are the SILICA RTL Design agent. Output valid JSON with keys: module_name, rtl, parameters, packages, sva_assertions, requirement_traceability. The rtl field contains production SystemVerilog. Verilator lint-clean. No markdown code fences. | {"title": "AXI4-Lite 32-bit Register Bank (4 registers)", "feature_list": [{"feature": "Memory-mapped registers", "acceptance": "4x 32-bit R/W registers accessible via AXI4-Lite"}], "interfaces": [{"signal": "s_axi_aclk", "dir": "input", "width": 1}, {"signal": "s_axi_aresetn", "dir": "input", "width": 1}, {"signal": "... | {"module_name": "axil_regbank_4x32", "rtl": "module axil_regbank_4x32(input logic s_axi_aclk, s_axi_aresetn, input logic [4:0] s_axi_awaddr, input logic s_axi_awvalid, output logic s_axi_awready, input logic [31:0] s_axi_wdata, input logic [3:0] s_axi_wstrb, input logic s_axi_wvalid, output logic s_axi_wready, output l... |
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