| {"system": "You are the SILICA RTL Design agent. Output valid JSON with keys: module_name, rtl, parameters, packages, sva_assertions, requirement_traceability. The rtl field contains production SystemVerilog. Verilator lint-clean. No markdown code fences.", "user": "{\"title\": \"4-deep 8-bit Synchronous FIFO\", \"feature_list\": [{\"feature\": \"FIFO Storage\", \"acceptance\": \"Stores up to 4 bytes with FIFO ordering\"}], \"interfaces\": [{\"signal\": \"clk\", \"dir\": \"input\", \"width\": 1, \"desc\": \"Primary clock\"}, {\"signal\": \"rst_n\", \"dir\": \"input\", \"width\": 1, \"desc\": \"Active low sync reset\"}, {\"signal\": \"wr_en\", \"dir\": \"input\", \"width\": 1, \"desc\": \"Write enable\"}, {\"signal\": \"rd_en\", \"dir\": \"input\", \"width\": 1, \"desc\": \"Read enable\"}, {\"signal\": \"din\", \"dir\": \"input\", \"width\": 8, \"desc\": \"Data input\"}, {\"signal\": \"dout\", \"dir\": \"output\", \"width\": 8, \"desc\": \"Data output\"}, {\"signal\": \"full\", \"dir\": \"output\", \"width\": 1, \"desc\": \"High when FIFO is full\"}, {\"signal\": \"empty\", \"dir\": \"output\", \"width\": 1, \"desc\": \"High when FIFO is empty\"}], \"clock_reset\": {\"domain\": \"single_clock\", \"reset_type\": \"sync_low\"}, \"pipeline_stages\": [], \"fsm_states\": [], \"constraints\": {\"target_freq_mhz\": 250}, \"register_map\": [], \"verification_plan\": {\"features\": [\"Write to full\", \"Read to empty\", \"Simultaneous read/write\"], \"coverage_points\": [\"FIFO empty flag\", \"FIFO full flag\"], \"assertions\": [\"No write when full\", \"No read when empty\"], \"test_matrix\": [\"directed_fill_empty\", \"random_interleaved\"]}, \"assumptions\": [\"Zero-latency read\"]}", "assistant": "{\"module_name\": \"fifo_sync_4x8\", \"rtl\": \"module fifo_sync_4x8(input logic clk, rst_n, wr_en, rd_en, input logic [7:0] din, output logic [7:0] dout, output logic full, empty); logic [7:0] mem[0:3]; logic [1:0] wr_ptr, rd_ptr; logic [2:0] count; always_ff @(posedge clk) if(!rst_n) begin wr_ptr<=0; rd_ptr<=0; count<=0; dout<=0; end else begin if(wr_en && !full) begin mem[wr_ptr]<=din; wr_ptr<=wr_ptr+1; count<=count+1; end if(rd_en && !empty) begin dout<=mem[rd_ptr]; rd_ptr<=rd_ptr+1; count<=count-1; end if(wr_en&&!full&&rd_en&&!empty) count<=count; end assign full=(count==4); assign empty=(count==0); endmodule\", \"parameters\": [{\"name\": \"WIDTH\", \"default\": 8}, {\"name\": \"DEPTH\", \"default\": 4}], \"packages\": [], \"sva_assertions\": [\"assert property (@(posedge clk) disable iff(!rst_n) (wr_en && full |-> ##1 $stable(wr_ptr)));\", \"assert property (@(posedge clk) disable iff(!rst_n) (rd_en && empty |-> ##1 $stable(rd_ptr)));\"], \"requirement_traceability\": [{\"req\": \"Stores up to 4 bytes\", \"rtl_signal\": \"mem[0:3]\"}, {\"req\": \"full flag\", \"rtl_signal\": \"full=(count==4)\"}]}"} |
| {"system": "You are the SILICA RTL Design agent. Output valid JSON with keys: module_name, rtl, parameters, packages, sva_assertions, requirement_traceability. The rtl field contains production SystemVerilog. Verilator lint-clean. No markdown code fences.", "user": "{\"title\": \"4-Input Round-Robin Arbiter\", \"feature_list\": [{\"feature\": \"Fair arbitration\", \"acceptance\": \"Round-robin priority updates after each grant\"}], \"interfaces\": [{\"signal\": \"clk\", \"dir\": \"input\", \"width\": 1}, {\"signal\": \"rst_n\", \"dir\": \"input\", \"width\": 1}, {\"signal\": \"req\", \"dir\": \"input\", \"width\": 4}, {\"signal\": \"data_in0..3\", \"dir\": \"input\", \"width\": 8}, {\"signal\": \"grant\", \"dir\": \"output\", \"width\": 4}, {\"signal\": \"data_out\", \"dir\": \"output\", \"width\": 8}, {\"signal\": \"valid_out\", \"dir\": \"output\", \"width\": 1}], \"clock_reset\": {\"domain\": \"single_clock\", \"reset_type\": \"async_low\"}, \"pipeline_stages\": [\"Arbitration\", \"Output register\"], \"fsm_states\": [], \"constraints\": {\"target_freq_mhz\": 400}, \"register_map\": [], \"verification_plan\": {\"features\": [\"Round-robin fairness\", \"One-hot grant\", \"Data passthrough correctness\"], \"coverage_points\": [\"All 16 request patterns\", \"Priority rotation\"], \"assertions\": [\"grant is one-hot\", \"no starvation within 4 cycles\"], \"test_matrix\": [\"directed_rotation\", \"random_requests\"]}, \"assumptions\": [\"Requests are level-sensitive\"]}", "assistant": "{\"module_name\": \"arbiter_rr4\", \"rtl\": \"module arbiter_rr4(input logic clk, rst_n, input logic [3:0] req, output logic [3:0] grant); logic [1:0] priority; logic [3:0] masked_req; always_comb begin grant=0; masked_req=req; for(int i=0;i<4;i++) if(((i+priority)%4)==0 && req[i]) begin grant[i]=1; masked_req=0; end end always_ff @(posedge clk or negedge rst_n) if(!rst_n) priority<=0; else if(|req && |grant) priority<=priority+1; endmodule\", \"parameters\": [{\"name\": \"WIDTH\", \"default\": 8}, {\"name\": \"N\", \"default\": 4}], \"packages\": [], \"sva_assertions\": [\"assert property (@(posedge clk) disable iff(!rst_n) $onehot0(grant));\", \"assert property (@(posedge clk) disable iff(!rst_n) (|req |-> ##[1:4] |grant));\"], \"requirement_traceability\": [{\"req\": \"Round-robin\", \"rtl_signal\": \"priority register\"}, {\"req\": \"One-hot grant\", \"rtl_signal\": \"grant one-hot0 SVA\"}]}"} |
| {"system": "You are the SILICA RTL Design agent. Output valid JSON with keys: module_name, rtl, parameters, packages, sva_assertions, requirement_traceability. The rtl field contains production SystemVerilog. Verilator lint-clean. No markdown code fences.", "user": "{\"title\": \"3-Stage Pipelined 8-bit ALU\", \"feature_list\": [{\"feature\": \"Pipelined execution\", \"acceptance\": \"One result per cycle after 3-cycle latency\"}], \"interfaces\": [{\"signal\": \"clk\", \"dir\": \"input\", \"width\": 1}, {\"signal\": \"rst_n\", \"dir\": \"input\", \"width\": 1}, {\"signal\": \"a\", \"dir\": \"input\", \"width\": 8}, {\"signal\": \"b\", \"dir\": \"input\", \"width\": 8}, {\"signal\": \"op\", \"dir\": \"input\", \"width\": 3}, {\"signal\": \"result\", \"dir\": \"output\", \"width\": 8}, {\"signal\": \"valid\", \"dir\": \"output\", \"width\": 1}], \"clock_reset\": {\"domain\": \"single_clock\", \"reset_type\": \"async_low\"}, \"pipeline_stages\": [\"S1: Operand register\", \"S2: ALU combinational\", \"S3: Result register\"], \"fsm_states\": [], \"constraints\": {\"target_freq_mhz\": 500}, \"register_map\": [], \"verification_plan\": {\"features\": [\"All 8 opcodes\", \"Pipeline hazard-free\", \"Latency = 3 cycles\"], \"coverage_points\": [\"All opcodes\", \"Boundary operands 0/255/127\"], \"assertions\": [\"valid asserts 3 cycles after input\", \"no pipeline bubble on back-to-back\"], \"test_matrix\": [\"directed_opcode\", \"random_operands\"]}, \"assumptions\": [\"No stalls (always-ready consumer)\"]}", "assistant": "{\"module_name\": \"alu_pipe3_8bit\", \"rtl\": \"module alu_pipe3_8bit(input logic clk, rst_n, input logic [7:0] a,b, input logic [2:0] op, output logic [7:0] result, output logic valid); logic [7:0] a_r,b_r, alu_comb; logic [2:0] op_r; logic v1,v2; always_ff @(posedge clk or negedge rst_n) if(!rst_n) begin a_r<=0;b_r<=0;op_r<=0;v1<=0;v2<=0;result<=0;valid<=0; end else begin a_r<=a;b_r<=b;op_r<=op;v1<=1; case(op_r) 0:alu_comb=a_r+b_r;1:alu_comb=a_r-b_r;2:alu_comb=a_r&b_r;3:alu_comb=a_r|b_r;4:alu_comb=a_r^b_r;5:alu_comb=~a_r;6:alu_comb=a_r<<1;7:alu_comb=a_r>>1; endcase v2<=v1; result<=alu_comb; valid<=v2; end endmodule\", \"parameters\": [{\"name\": \"WIDTH\", \"default\": 8}], \"packages\": [], \"sva_assertions\": [\"assert property (@(posedge clk) disable iff(!rst_n) ##3 valid==1);\"], \"requirement_traceability\": [{\"req\": \"3-cycle latency\", \"rtl_signal\": \"v1->v2->valid pipeline\"}]}"} |
| {"system": "You are the SILICA RTL Design agent. Output valid JSON with keys: module_name, rtl, parameters, packages, sva_assertions, requirement_traceability. The rtl field contains production SystemVerilog. Verilator lint-clean. No markdown code fences.", "user": "{\"title\": \"UART Transmitter (8N1) with 16-byte TX FIFO\", \"feature_list\": [{\"feature\": \"Serial TX\", \"acceptance\": \"8N1 frames at configurable baud rate\"}], \"interfaces\": [{\"signal\": \"clk\", \"dir\": \"input\", \"width\": 1}, {\"signal\": \"rst_n\", \"dir\": \"input\", \"width\": 1}, {\"signal\": \"tx_data\", \"dir\": \"input\", \"width\": 8}, {\"signal\": \"tx_valid\", \"dir\": \"input\", \"width\": 1}, {\"signal\": \"tx_ready\", \"dir\": \"output\", \"width\": 1}, {\"signal\": \"baud_div\", \"dir\": \"input\", \"width\": 16}, {\"signal\": \"tx_serial\", \"dir\": \"output\", \"width\": 1}, {\"signal\": \"tx_idle\", \"dir\": \"output\", \"width\": 1}], \"clock_reset\": {\"domain\": \"single_clock\", \"reset_type\": \"async_low\"}, \"pipeline_stages\": [], \"fsm_states\": [\"IDLE\", \"START_BIT\", \"DATA_BIT0..7\", \"STOP_BIT\"], \"constraints\": {\"target_freq_mhz\": 50, \"baud_div_min\": 1}, \"register_map\": [{\"offset\": \"0x00\", \"name\": \"BAUD_DIV\", \"access\": \"RW\", \"reset\": \"0x0000\"}], \"verification_plan\": {\"features\": [\"Frame format 8N1\", \"Baud rate accuracy\", \"FIFO backpressure\"], \"coverage_points\": [\"All 256 data values\", \"Baud divisor corners\"], \"assertions\": [\"tx_serial idle=1\", \"start bit=0\", \"stop bit=1\"], \"test_matrix\": [\"directed_frame_check\", \"random_baud_rate\"]}, \"assumptions\": [\"No flow control (no RTS/CTS)\"]}", "assistant": "{\"module_name\": \"uart_tx_8n1\", \"rtl\": \"module uart_tx_8n1(input logic clk, rst_n, input logic [7:0] tx_data, input logic tx_valid, output logic tx_ready, input logic [15:0] baud_div, output logic tx_serial, tx_idle); logic [15:0] baud_cnt; logic [3:0] bit_cnt; logic [9:0] shift_reg; logic [1:0] state; always_ff @(posedge clk or negedge rst_n) if(!rst_n) begin state<=0; baud_cnt<=0; bit_cnt<=0; shift_reg<=1; tx_serial<=1; tx_ready<=1; end else case(state) 0: begin tx_ready<=1; if(tx_valid) begin shift_reg<={1'b1,tx_data,1'b0}; bit_cnt<=0; baud_cnt<=0; state<=1; tx_ready<=0; end end 1: begin if(baud_cnt==baud_div) begin baud_cnt<=0; tx_serial<=shift_reg[0]; shift_reg<=shift_reg>>1; bit_cnt<=bit_cnt+1; if(bit_cnt==9) state<=2; end else baud_cnt<=baud_cnt+1; end 2: begin tx_serial<=1; tx_ready<=1; state<=0; end endcase assign tx_idle=(state==0); endmodule\", \"parameters\": [{\"name\": \"DATA_BITS\", \"default\": 8}], \"packages\": [], \"sva_assertions\": [\"assert property (@(posedge clk) disable iff(!rst_n) $rose(tx_valid) |-> ##[1:$] !tx_serial throughout tx_idle[->1]);\"], \"requirement_traceability\": [{\"req\": \"8N1 frame\", \"rtl_signal\": \"shift_reg={1,data,0}, 10 bits\"}]}"} |
| {"system": "You are the SILICA RTL Design agent. Output valid JSON with keys: module_name, rtl, parameters, packages, sva_assertions, requirement_traceability. The rtl field contains production SystemVerilog. Verilator lint-clean. No markdown code fences.", "user": "{\"title\": \"AXI4-Lite 32-bit Register Bank (4 registers)\", \"feature_list\": [{\"feature\": \"Memory-mapped registers\", \"acceptance\": \"4x 32-bit R/W registers accessible via AXI4-Lite\"}], \"interfaces\": [{\"signal\": \"s_axi_aclk\", \"dir\": \"input\", \"width\": 1}, {\"signal\": \"s_axi_aresetn\", \"dir\": \"input\", \"width\": 1}, {\"signal\": \"s_axi_awaddr\", \"dir\": \"input\", \"width\": 5}, {\"signal\": \"s_axi_awprot\", \"dir\": \"input\", \"width\": 3}, {\"signal\": \"s_axi_awvalid\", \"dir\": \"input\", \"width\": 1}, {\"signal\": \"s_axi_awready\", \"dir\": \"output\", \"width\": 1}, {\"signal\": \"s_axi_wdata\", \"dir\": \"input\", \"width\": 32}, {\"signal\": \"s_axi_wstrb\", \"dir\": \"input\", \"width\": 4}, {\"signal\": \"s_axi_wvalid\", \"dir\": \"input\", \"width\": 1}, {\"signal\": \"s_axi_wready\", \"dir\": \"output\", \"width\": 1}, {\"signal\": \"s_axi_bresp\", \"dir\": \"output\", \"width\": 2}, {\"signal\": \"s_axi_bvalid\", \"dir\": \"output\", \"width\": 1}, {\"signal\": \"s_axi_bready\", \"dir\": \"input\", \"width\": 1}, {\"signal\": \"s_axi_araddr\", \"dir\": \"input\", \"width\": 5}, {\"signal\": \"s_axi_arvalid\", \"dir\": \"input\", \"width\": 1}, {\"signal\": \"s_axi_arready\", \"dir\": \"output\", \"width\": 1}, {\"signal\": \"s_axi_rdata\", \"dir\": \"output\", \"width\": 32}, {\"signal\": \"s_axi_rresp\", \"dir\": \"output\", \"width\": 2}, {\"signal\": \"s_axi_rvalid\", \"dir\": \"output\", \"width\": 1}, {\"signal\": \"s_axi_rready\", \"dir\": \"input\", \"width\": 1}], \"clock_reset\": {\"domain\": \"single_clock\", \"reset_type\": \"async_low\"}, \"pipeline_stages\": [], \"fsm_states\": [\"IDLE\", \"WRITE\", \"WRITE_RESP\", \"READ\", \"READ_RESP\"], \"constraints\": {\"target_freq_mhz\": 100}, \"register_map\": [{\"offset\": \"0x00\", \"name\": \"REG0\", \"access\": \"RW\", \"reset\": \"0x00000000\"}, {\"offset\": \"0x04\", \"name\": \"REG1\", \"access\": \"RW\", \"reset\": \"0x00000000\"}, {\"offset\": \"0x08\", \"name\": \"REG2\", \"access\": \"RW\", \"reset\": \"0x00000000\"}, {\"offset\": \"0x0C\", \"name\": \"REG3\", \"access\": \"RW\", \"reset\": \"0x00000000\"}], \"verification_plan\": {\"features\": [\"Write/read each register\", \"Write strobe byte enables\", \"Back-to-back transactions\"], \"coverage_points\": [\"All 5 channel handshakes\", \"AW/W ordering\"], \"assertions\": [\"bresp=OKAY on valid write\", \"rresp=OKAY on valid read\", \"no X on outputs\"], \"test_matrix\": [\"directed_reg_rw\", \"random_backpressure\"]}, \"assumptions\": [\"AW and W arrive in same cycle or AW first\"]}", "assistant": "{\"module_name\": \"axil_regbank_4x32\", \"rtl\": \"module axil_regbank_4x32(input logic s_axi_aclk, s_axi_aresetn, input logic [4:0] s_axi_awaddr, input logic s_axi_awvalid, output logic s_axi_awready, input logic [31:0] s_axi_wdata, input logic [3:0] s_axi_wstrb, input logic s_axi_wvalid, output logic s_axi_wready, output logic [1:0] s_axi_bresp, output logic s_axi_bvalid, input logic s_axi_bready, input logic [4:0] s_axi_araddr, input logic s_axi_arvalid, output logic s_axi_arready, output logic [31:0] s_axi_rdata, output logic [1:0] s_axi_rresp, output logic s_axi_rvalid, input logic s_axi_rready); logic [31:0] regs[0:3]; logic [1:0] wr_state, rd_state; always_ff @(posedge s_axi_aclk or negedge s_axi_aresetn) if(!s_axi_aresetn) begin s_axi_awready<=0;s_axi_wready<=0;s_axi_bvalid<=0;s_axi_arready<=0;s_axi_rvalid<=0; for(int i=0;i<4;i++) regs[i]<=0; end else begin if(s_axi_awvalid&&!s_axi_awready) s_axi_awready<=1; else if(s_axi_awready) s_axi_awready<=0; if(s_axi_wvalid&&!s_axi_wready) s_axi_wready<=1; else if(s_axi_wready) s_axi_wready<=0; if(s_axi_awready&&s_axi_wready) begin for(int i=0;i<4;i++) if(s_axi_wstrb[i]) regs[s_axi_awaddr[3:2]][i*8+:8]<=s_axi_wdata[i*8+:8]; s_axi_bvalid<=1; s_axi_bresp<=0; end if(s_axi_bvalid&&s_axi_bready) s_axi_bvalid<=0; if(s_axi_arvalid&&!s_axi_arready) s_axi_arready<=1; else if(s_axi_arready) begin s_axi_arready<=0; s_axi_rdata<=regs[s_axi_araddr[3:2]]; s_axi_rresp<=0; s_axi_rvalid<=1; end if(s_axi_rvalid&&s_axi_rready) s_axi_rvalid<=0; end endmodule\", \"parameters\": [{\"name\": \"N_REGS\", \"default\": 4}, {\"name\": \"DATA_WIDTH\", \"default\": 32}], \"packages\": [], \"sva_assertions\": [\"assert property (@(posedge s_axi_aclk) disable iff(!s_axi_aresetn) s_axi_bresp==2'b00);\", \"assert property (@(posedge s_axi_aclk) disable iff(!s_axi_aresetn) s_axi_rresp==2'b00);\"], \"requirement_traceability\": [{\"req\": \"4 R/W registers\", \"rtl_signal\": \"regs[0:3]\"}, {\"req\": \"AXI4-Lite 5 channel\", \"rtl_signal\": \"AW/W/B/AR/R channels\"}]}"} |
|
|
