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You are the SILICA Specification & Architecture agent. Output valid JSON with keys: title, feature_list, interfaces, clock_reset, pipeline_stages, fsm_states, constraints, register_map, verification_plan, assumptions. No markdown. | Design a 4-deep, 8-bit synchronous FIFO with empty and full status flags and synchronous reset. | {"title": "4-deep 8-bit Synchronous FIFO", "feature_list": [{"feature": "FIFO Storage", "acceptance": "Stores up to 4 bytes with FIFO ordering"}], "interfaces": [{"signal": "clk", "dir": "input", "width": 1, "desc": "Primary clock"}, {"signal": "rst_n", "dir": "input", "width": 1, "desc": "Active low sync reset"}, {"si... |
You are the SILICA Specification & Architecture agent. Output valid JSON with keys: title, feature_list, interfaces, clock_reset, pipeline_stages, fsm_states, constraints, register_map, verification_plan, assumptions. No markdown. | Design an AXI4-Lite 32-bit register bank with 4 read/write registers and active-low async reset. | {"title": "AXI4-Lite 32-bit Register Bank (4 registers)", "feature_list": [{"feature": "Memory-mapped registers", "acceptance": "4x 32-bit R/W registers accessible via AXI4-Lite"}], "interfaces": [{"signal": "s_axi_aclk", "dir": "input", "width": 1}, {"signal": "s_axi_aresetn", "dir": "input", "width": 1}, {"signal": "... |
You are the SILICA Specification & Architecture agent. Output valid JSON with keys: title, feature_list, interfaces, clock_reset, pipeline_stages, fsm_states, constraints, register_map, verification_plan, assumptions. No markdown. | Design a UART transmitter with 8N1 format, 16-byte TX FIFO, and baud rate divisor register. | {"title": "UART Transmitter (8N1) with 16-byte TX FIFO", "feature_list": [{"feature": "Serial TX", "acceptance": "8N1 frames at configurable baud rate"}], "interfaces": [{"signal": "clk", "dir": "input", "width": 1}, {"signal": "rst_n", "dir": "input", "width": 1}, {"signal": "tx_data", "dir": "input", "width": 8}, {"s... |
You are the SILICA Specification & Architecture agent. Output valid JSON with keys: title, feature_list, interfaces, clock_reset, pipeline_stages, fsm_states, constraints, register_map, verification_plan, assumptions. No markdown. | Design a 4-input round-robin priority arbiter with 8-bit data pass-through and registered outputs. | {"title": "4-Input Round-Robin Arbiter", "feature_list": [{"feature": "Fair arbitration", "acceptance": "Round-robin priority updates after each grant"}], "interfaces": [{"signal": "clk", "dir": "input", "width": 1}, {"signal": "rst_n", "dir": "input", "width": 1}, {"signal": "req", "dir": "input", "width": 4}, {"signa... |
You are the SILICA Specification & Architecture agent. Output valid JSON with keys: title, feature_list, interfaces, clock_reset, pipeline_stages, fsm_states, constraints, register_map, verification_plan, assumptions. No markdown. | Design a 3-stage pipelined 8-bit ALU with registered operand inputs and result output. | {"title": "3-Stage Pipelined 8-bit ALU", "feature_list": [{"feature": "Pipelined execution", "acceptance": "One result per cycle after 3-cycle latency"}], "interfaces": [{"signal": "clk", "dir": "input", "width": 1}, {"signal": "rst_n", "dir": "input", "width": 1}, {"signal": "a", "dir": "input", "width": 8}, {"signal"... |
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