| {"system": "You are the SILICA Specification & Architecture agent. Output valid JSON with keys: title, feature_list, interfaces, clock_reset, pipeline_stages, fsm_states, constraints, register_map, verification_plan, assumptions. No markdown.", "user": "Design a 4-deep, 8-bit synchronous FIFO with empty and full status flags and synchronous reset.", "assistant": "{\"title\": \"4-deep 8-bit Synchronous FIFO\", \"feature_list\": [{\"feature\": \"FIFO Storage\", \"acceptance\": \"Stores up to 4 bytes with FIFO ordering\"}], \"interfaces\": [{\"signal\": \"clk\", \"dir\": \"input\", \"width\": 1, \"desc\": \"Primary clock\"}, {\"signal\": \"rst_n\", \"dir\": \"input\", \"width\": 1, \"desc\": \"Active low sync reset\"}, {\"signal\": \"wr_en\", \"dir\": \"input\", \"width\": 1, \"desc\": \"Write enable\"}, {\"signal\": \"rd_en\", \"dir\": \"input\", \"width\": 1, \"desc\": \"Read enable\"}, {\"signal\": \"din\", \"dir\": \"input\", \"width\": 8, \"desc\": \"Data input\"}, {\"signal\": \"dout\", \"dir\": \"output\", \"width\": 8, \"desc\": \"Data output\"}, {\"signal\": \"full\", \"dir\": \"output\", \"width\": 1, \"desc\": \"High when FIFO is full\"}, {\"signal\": \"empty\", \"dir\": \"output\", \"width\": 1, \"desc\": \"High when FIFO is empty\"}], \"clock_reset\": {\"domain\": \"single_clock\", \"reset_type\": \"sync_low\"}, \"pipeline_stages\": [], \"fsm_states\": [], \"constraints\": {\"target_freq_mhz\": 250}, \"register_map\": [], \"verification_plan\": {\"features\": [\"Write to full\", \"Read to empty\", \"Simultaneous read/write\"], \"coverage_points\": [\"FIFO empty flag\", \"FIFO full flag\"], \"assertions\": [\"No write when full\", \"No read when empty\"], \"test_matrix\": [\"directed_fill_empty\", \"random_interleaved\"]}, \"assumptions\": [\"Zero-latency read\"]}"} |
| {"system": "You are the SILICA Specification & Architecture agent. Output valid JSON with keys: title, feature_list, interfaces, clock_reset, pipeline_stages, fsm_states, constraints, register_map, verification_plan, assumptions. No markdown.", "user": "Design an AXI4-Lite 32-bit register bank with 4 read/write registers and active-low async reset.", "assistant": "{\"title\": \"AXI4-Lite 32-bit Register Bank (4 registers)\", \"feature_list\": [{\"feature\": \"Memory-mapped registers\", \"acceptance\": \"4x 32-bit R/W registers accessible via AXI4-Lite\"}], \"interfaces\": [{\"signal\": \"s_axi_aclk\", \"dir\": \"input\", \"width\": 1}, {\"signal\": \"s_axi_aresetn\", \"dir\": \"input\", \"width\": 1}, {\"signal\": \"s_axi_awaddr\", \"dir\": \"input\", \"width\": 5}, {\"signal\": \"s_axi_awprot\", \"dir\": \"input\", \"width\": 3}, {\"signal\": \"s_axi_awvalid\", \"dir\": \"input\", \"width\": 1}, {\"signal\": \"s_axi_awready\", \"dir\": \"output\", \"width\": 1}, {\"signal\": \"s_axi_wdata\", \"dir\": \"input\", \"width\": 32}, {\"signal\": \"s_axi_wstrb\", \"dir\": \"input\", \"width\": 4}, {\"signal\": \"s_axi_wvalid\", \"dir\": \"input\", \"width\": 1}, {\"signal\": \"s_axi_wready\", \"dir\": \"output\", \"width\": 1}, {\"signal\": \"s_axi_bresp\", \"dir\": \"output\", \"width\": 2}, {\"signal\": \"s_axi_bvalid\", \"dir\": \"output\", \"width\": 1}, {\"signal\": \"s_axi_bready\", \"dir\": \"input\", \"width\": 1}, {\"signal\": \"s_axi_araddr\", \"dir\": \"input\", \"width\": 5}, {\"signal\": \"s_axi_arvalid\", \"dir\": \"input\", \"width\": 1}, {\"signal\": \"s_axi_arready\", \"dir\": \"output\", \"width\": 1}, {\"signal\": \"s_axi_rdata\", \"dir\": \"output\", \"width\": 32}, {\"signal\": \"s_axi_rresp\", \"dir\": \"output\", \"width\": 2}, {\"signal\": \"s_axi_rvalid\", \"dir\": \"output\", \"width\": 1}, {\"signal\": \"s_axi_rready\", \"dir\": \"input\", \"width\": 1}], \"clock_reset\": {\"domain\": \"single_clock\", \"reset_type\": \"async_low\"}, \"pipeline_stages\": [], \"fsm_states\": [\"IDLE\", \"WRITE\", \"WRITE_RESP\", \"READ\", \"READ_RESP\"], \"constraints\": {\"target_freq_mhz\": 100}, \"register_map\": [{\"offset\": \"0x00\", \"name\": \"REG0\", \"access\": \"RW\", \"reset\": \"0x00000000\"}, {\"offset\": \"0x04\", \"name\": \"REG1\", \"access\": \"RW\", \"reset\": \"0x00000000\"}, {\"offset\": \"0x08\", \"name\": \"REG2\", \"access\": \"RW\", \"reset\": \"0x00000000\"}, {\"offset\": \"0x0C\", \"name\": \"REG3\", \"access\": \"RW\", \"reset\": \"0x00000000\"}], \"verification_plan\": {\"features\": [\"Write/read each register\", \"Write strobe byte enables\", \"Back-to-back transactions\"], \"coverage_points\": [\"All 5 channel handshakes\", \"AW/W ordering\"], \"assertions\": [\"bresp=OKAY on valid write\", \"rresp=OKAY on valid read\", \"no X on outputs\"], \"test_matrix\": [\"directed_reg_rw\", \"random_backpressure\"]}, \"assumptions\": [\"AW and W arrive in same cycle or AW first\"]}"} |
| {"system": "You are the SILICA Specification & Architecture agent. Output valid JSON with keys: title, feature_list, interfaces, clock_reset, pipeline_stages, fsm_states, constraints, register_map, verification_plan, assumptions. No markdown.", "user": "Design a UART transmitter with 8N1 format, 16-byte TX FIFO, and baud rate divisor register.", "assistant": "{\"title\": \"UART Transmitter (8N1) with 16-byte TX FIFO\", \"feature_list\": [{\"feature\": \"Serial TX\", \"acceptance\": \"8N1 frames at configurable baud rate\"}], \"interfaces\": [{\"signal\": \"clk\", \"dir\": \"input\", \"width\": 1}, {\"signal\": \"rst_n\", \"dir\": \"input\", \"width\": 1}, {\"signal\": \"tx_data\", \"dir\": \"input\", \"width\": 8}, {\"signal\": \"tx_valid\", \"dir\": \"input\", \"width\": 1}, {\"signal\": \"tx_ready\", \"dir\": \"output\", \"width\": 1}, {\"signal\": \"baud_div\", \"dir\": \"input\", \"width\": 16}, {\"signal\": \"tx_serial\", \"dir\": \"output\", \"width\": 1}, {\"signal\": \"tx_idle\", \"dir\": \"output\", \"width\": 1}], \"clock_reset\": {\"domain\": \"single_clock\", \"reset_type\": \"async_low\"}, \"pipeline_stages\": [], \"fsm_states\": [\"IDLE\", \"START_BIT\", \"DATA_BIT0..7\", \"STOP_BIT\"], \"constraints\": {\"target_freq_mhz\": 50, \"baud_div_min\": 1}, \"register_map\": [{\"offset\": \"0x00\", \"name\": \"BAUD_DIV\", \"access\": \"RW\", \"reset\": \"0x0000\"}], \"verification_plan\": {\"features\": [\"Frame format 8N1\", \"Baud rate accuracy\", \"FIFO backpressure\"], \"coverage_points\": [\"All 256 data values\", \"Baud divisor corners\"], \"assertions\": [\"tx_serial idle=1\", \"start bit=0\", \"stop bit=1\"], \"test_matrix\": [\"directed_frame_check\", \"random_baud_rate\"]}, \"assumptions\": [\"No flow control (no RTS/CTS)\"]}"} |
| {"system": "You are the SILICA Specification & Architecture agent. Output valid JSON with keys: title, feature_list, interfaces, clock_reset, pipeline_stages, fsm_states, constraints, register_map, verification_plan, assumptions. No markdown.", "user": "Design a 4-input round-robin priority arbiter with 8-bit data pass-through and registered outputs.", "assistant": "{\"title\": \"4-Input Round-Robin Arbiter\", \"feature_list\": [{\"feature\": \"Fair arbitration\", \"acceptance\": \"Round-robin priority updates after each grant\"}], \"interfaces\": [{\"signal\": \"clk\", \"dir\": \"input\", \"width\": 1}, {\"signal\": \"rst_n\", \"dir\": \"input\", \"width\": 1}, {\"signal\": \"req\", \"dir\": \"input\", \"width\": 4}, {\"signal\": \"data_in0..3\", \"dir\": \"input\", \"width\": 8}, {\"signal\": \"grant\", \"dir\": \"output\", \"width\": 4}, {\"signal\": \"data_out\", \"dir\": \"output\", \"width\": 8}, {\"signal\": \"valid_out\", \"dir\": \"output\", \"width\": 1}], \"clock_reset\": {\"domain\": \"single_clock\", \"reset_type\": \"async_low\"}, \"pipeline_stages\": [\"Arbitration\", \"Output register\"], \"fsm_states\": [], \"constraints\": {\"target_freq_mhz\": 400}, \"register_map\": [], \"verification_plan\": {\"features\": [\"Round-robin fairness\", \"One-hot grant\", \"Data passthrough correctness\"], \"coverage_points\": [\"All 16 request patterns\", \"Priority rotation\"], \"assertions\": [\"grant is one-hot\", \"no starvation within 4 cycles\"], \"test_matrix\": [\"directed_rotation\", \"random_requests\"]}, \"assumptions\": [\"Requests are level-sensitive\"]}"} |
| {"system": "You are the SILICA Specification & Architecture agent. Output valid JSON with keys: title, feature_list, interfaces, clock_reset, pipeline_stages, fsm_states, constraints, register_map, verification_plan, assumptions. No markdown.", "user": "Design a 3-stage pipelined 8-bit ALU with registered operand inputs and result output.", "assistant": "{\"title\": \"3-Stage Pipelined 8-bit ALU\", \"feature_list\": [{\"feature\": \"Pipelined execution\", \"acceptance\": \"One result per cycle after 3-cycle latency\"}], \"interfaces\": [{\"signal\": \"clk\", \"dir\": \"input\", \"width\": 1}, {\"signal\": \"rst_n\", \"dir\": \"input\", \"width\": 1}, {\"signal\": \"a\", \"dir\": \"input\", \"width\": 8}, {\"signal\": \"b\", \"dir\": \"input\", \"width\": 8}, {\"signal\": \"op\", \"dir\": \"input\", \"width\": 3}, {\"signal\": \"result\", \"dir\": \"output\", \"width\": 8}, {\"signal\": \"valid\", \"dir\": \"output\", \"width\": 1}], \"clock_reset\": {\"domain\": \"single_clock\", \"reset_type\": \"async_low\"}, \"pipeline_stages\": [\"S1: Operand register\", \"S2: ALU combinational\", \"S3: Result register\"], \"fsm_states\": [], \"constraints\": {\"target_freq_mhz\": 500}, \"register_map\": [], \"verification_plan\": {\"features\": [\"All 8 opcodes\", \"Pipeline hazard-free\", \"Latency = 3 cycles\"], \"coverage_points\": [\"All opcodes\", \"Boundary operands 0/255/127\"], \"assertions\": [\"valid asserts 3 cycles after input\", \"no pipeline bubble on back-to-back\"], \"test_matrix\": [\"directed_opcode\", \"random_operands\"]}, \"assumptions\": [\"No stalls (always-ready consumer)\"]}"} |
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