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You are the SILICA Logic Synthesis agent. Output valid JSON with keys: synthesis_script, target_clock_ns, expected_cell_primitives, timing_slack_estimate, netlist_directives. synthesis_script is a Yosys .ys script. No markdown. | {"rtl": "module fifo_sync_4x8(input logic clk, rst_n, wr_en, rd_en, input logic [7:0] din, output logic [7:0] dout, output logic full, empty); logic [7:0] mem[0:3]; logic [1:0] wr_ptr, rd_ptr; logic [2:0] count; always_ff @(posedge clk) if(!rst_n) begin wr_ptr<=0; rd_ptr<=0; count<=0; dout<=0; end else begin if(wr_en &... | {"synthesis_script": "read_verilog -sv fifo_sync_4x8.v\nhierarchy -check\nproc; opt; fsm; opt; memory; opt\ntechmap; opt\nstat\nwrite_verilog -noattr fifo_netlist.v\nwrite_json fifo_synth.json", "target_clock_ns": 4.0, "expected_cell_primitives": ["DFF", "MUX", "ADDER", "COMPARATOR", "MEMRD", "MEMWR"], "timing_slack_es... |
You are the SILICA Logic Synthesis agent. Output valid JSON with keys: synthesis_script, target_clock_ns, expected_cell_primitives, timing_slack_estimate, netlist_directives. synthesis_script is a Yosys .ys script. No markdown. | {"rtl": "module arbiter_rr4(input logic clk, rst_n, input logic [3:0] req, output logic [3:0] grant); logic [1:0] priority; logic [3:0] masked_req; always_comb begin grant=0; masked_req=req; for(int i=0;i<4;i++) if(((i+priority)%4)==0 && req[i]) begin grant[i]=1; masked_req=0; end end always_ff @(posedge clk or negedge... | {"synthesis_script": "read_verilog -sv arbiter_rr4.v\nhierarchy -check\nproc; opt; fsm; opt; techmap; opt\nstat\nwrite_verilog -noattr arbiter_netlist.v", "target_clock_ns": 2.5, "expected_cell_primitives": ["DFF", "MUX", "PRIORITY_ENCODER", "COMPARATOR"], "timing_slack_estimate": "positive (combinational priority logi... |
You are the SILICA Logic Synthesis agent. Output valid JSON with keys: synthesis_script, target_clock_ns, expected_cell_primitives, timing_slack_estimate, netlist_directives. synthesis_script is a Yosys .ys script. No markdown. | {"rtl": "module alu_pipe3_8bit(input logic clk, rst_n, input logic [7:0] a,b, input logic [2:0] op, output logic [7:0] result, output logic valid); logic [7:0] a_r,b_r, alu_comb; logic [2:0] op_r; logic v1,v2; always_ff @(posedge clk or negedge rst_n) if(!rst_n) begin a_r<=0;b_r<=0;op_r<=0;v1<=0;v2<=0;result<=0;valid<=... | {"synthesis_script": "read_verilog -sv alu_pipe3_8bit.v\nhierarchy -check\nproc; opt; fsm; opt; techmap; opt\nstat\nwrite_verilog -noattr alu_netlist.v", "target_clock_ns": 2.0, "expected_cell_primitives": ["DFF", "ADDER", "MUX8", "LOGIC_OPS", "SHIFT"], "timing_slack_estimate": "positive (pipelined, 500 MHz target met)... |
You are the SILICA Logic Synthesis agent. Output valid JSON with keys: synthesis_script, target_clock_ns, expected_cell_primitives, timing_slack_estimate, netlist_directives. synthesis_script is a Yosys .ys script. No markdown. | {"rtl": "module uart_tx_8n1(input logic clk, rst_n, input logic [7:0] tx_data, input logic tx_valid, output logic tx_ready, input logic [15:0] baud_div, output logic tx_serial, tx_idle); logic [15:0] baud_cnt; logic [3:0] bit_cnt; logic [9:0] shift_reg; logic [1:0] state; always_ff @(posedge clk or negedge rst_n) if(!r... | {"synthesis_script": "read_verilog -sv uart_tx_8n1.v\nhierarchy -check\nproc; opt; fsm; opt; techmap; opt\nstat\nwrite_verilog -noattr uart_netlist.v", "target_clock_ns": 20.0, "expected_cell_primitives": ["DFF", "COUNTER", "SHIFT_REG", "MUX", "COMPARATOR"], "timing_slack_estimate": "very positive (50 MHz, slow baud co... |
You are the SILICA Logic Synthesis agent. Output valid JSON with keys: synthesis_script, target_clock_ns, expected_cell_primitives, timing_slack_estimate, netlist_directives. synthesis_script is a Yosys .ys script. No markdown. | {"rtl": "module axil_regbank_4x32(input logic s_axi_aclk, s_axi_aresetn, input logic [4:0] s_axi_awaddr, input logic s_axi_awvalid, output logic s_axi_awready, input logic [31:0] s_axi_wdata, input logic [3:0] s_axi_wstrb, input logic s_axi_wvalid, output logic s_axi_wready, output logic [1:0] s_axi_bresp, output logic... | {"synthesis_script": "read_verilog -sv axil_regbank_4x32.v\nhierarchy -check\nproc; opt; fsm; opt; techmap; opt\nstat\nwrite_verilog -noattr axil_netlist.v", "target_clock_ns": 10.0, "expected_cell_primitives": ["DFF", "MUX4", "DEMUX", "REGISTER_FILE_4x32", "FSM"], "timing_slack_estimate": "positive (100 MHz AXI, regis... |
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