| {"system": "You are the SILICA Logic Synthesis agent. Output valid JSON with keys: synthesis_script, target_clock_ns, expected_cell_primitives, timing_slack_estimate, netlist_directives. synthesis_script is a Yosys .ys script. No markdown.", "user": "{\"rtl\": \"module fifo_sync_4x8(input logic clk, rst_n, wr_en, rd_en, input logic [7:0] din, output logic [7:0] dout, output logic full, empty); logic [7:0] mem[0:3]; logic [1:0] wr_ptr, rd_ptr; logic [2:0] count; always_ff @(posedge clk) if(!rst_n) begin wr_ptr<=0; rd_ptr<=0; count<=0; dout<=0; end else begin if(wr_en && !full) begin mem[wr_ptr]<=din; wr_ptr<=wr_ptr+1; count<=count+1; end if(rd_en && !empty) begin dout<=mem[rd_ptr]; rd_ptr<=rd_ptr+1; count<=count-1; end if(wr_en&&!full&&rd_en&&!empty) count<=count; end assign full=(count==4); assign empty=(count==0); endmodule\", \"target_clock_ns\": 4.0}", "assistant": "{\"synthesis_script\": \"read_verilog -sv fifo_sync_4x8.v\\nhierarchy -check\\nproc; opt; fsm; opt; memory; opt\\ntechmap; opt\\nstat\\nwrite_verilog -noattr fifo_netlist.v\\nwrite_json fifo_synth.json\", \"target_clock_ns\": 4.0, \"expected_cell_primitives\": [\"DFF\", \"MUX\", \"ADDER\", \"COMPARATOR\", \"MEMRD\", \"MEMWR\"], \"timing_slack_estimate\": \"positive (small counter logic, 250 MHz easily met)\", \"netlist_directives\": [\"flatten memory to registers for DEPTH=4\", \"infer 4x8 distributed RAM\"]}"} |
| {"system": "You are the SILICA Logic Synthesis agent. Output valid JSON with keys: synthesis_script, target_clock_ns, expected_cell_primitives, timing_slack_estimate, netlist_directives. synthesis_script is a Yosys .ys script. No markdown.", "user": "{\"rtl\": \"module arbiter_rr4(input logic clk, rst_n, input logic [3:0] req, output logic [3:0] grant); logic [1:0] priority; logic [3:0] masked_req; always_comb begin grant=0; masked_req=req; for(int i=0;i<4;i++) if(((i+priority)%4)==0 && req[i]) begin grant[i]=1; masked_req=0; end end always_ff @(posedge clk or negedge rst_n) if(!rst_n) priority<=0; else if(|req && |grant) priority<=priority+1; endmodule\", \"target_clock_ns\": 2.5}", "assistant": "{\"synthesis_script\": \"read_verilog -sv arbiter_rr4.v\\nhierarchy -check\\nproc; opt; fsm; opt; techmap; opt\\nstat\\nwrite_verilog -noattr arbiter_netlist.v\", \"target_clock_ns\": 2.5, \"expected_cell_primitives\": [\"DFF\", \"MUX\", \"PRIORITY_ENCODER\", \"COMPARATOR\"], \"timing_slack_estimate\": \"positive (combinational priority logic < 2.5ns in 7nm)\", \"netlist_directives\": [\"keep grant register output\", \"one-hot encoding for grant\"]}"} |
| {"system": "You are the SILICA Logic Synthesis agent. Output valid JSON with keys: synthesis_script, target_clock_ns, expected_cell_primitives, timing_slack_estimate, netlist_directives. synthesis_script is a Yosys .ys script. No markdown.", "user": "{\"rtl\": \"module alu_pipe3_8bit(input logic clk, rst_n, input logic [7:0] a,b, input logic [2:0] op, output logic [7:0] result, output logic valid); logic [7:0] a_r,b_r, alu_comb; logic [2:0] op_r; logic v1,v2; always_ff @(posedge clk or negedge rst_n) if(!rst_n) begin a_r<=0;b_r<=0;op_r<=0;v1<=0;v2<=0;result<=0;valid<=0; end else begin a_r<=a;b_r<=b;op_r<=op;v1<=1; case(op_r) 0:alu_comb=a_r+b_r;1:alu_comb=a_r-b_r;2:alu_comb=a_r&b_r;3:alu_comb=a_r|b_r;4:alu_comb=a_r^b_r;5:alu_comb=~a_r;6:alu_comb=a_r<<1;7:alu_comb=a_r>>1; endcase v2<=v1; result<=alu_comb; valid<=v2; end endmodule\", \"target_clock_ns\": 2.0}", "assistant": "{\"synthesis_script\": \"read_verilog -sv alu_pipe3_8bit.v\\nhierarchy -check\\nproc; opt; fsm; opt; techmap; opt\\nstat\\nwrite_verilog -noattr alu_netlist.v\", \"target_clock_ns\": 2.0, \"expected_cell_primitives\": [\"DFF\", \"ADDER\", \"MUX8\", \"LOGIC_OPS\", \"SHIFT\"], \"timing_slack_estimate\": \"positive (pipelined, 500 MHz target met)\", \"netlist_directives\": [\"retime pipeline registers\", \"balance adder tree\"]}"} |
| {"system": "You are the SILICA Logic Synthesis agent. Output valid JSON with keys: synthesis_script, target_clock_ns, expected_cell_primitives, timing_slack_estimate, netlist_directives. synthesis_script is a Yosys .ys script. No markdown.", "user": "{\"rtl\": \"module uart_tx_8n1(input logic clk, rst_n, input logic [7:0] tx_data, input logic tx_valid, output logic tx_ready, input logic [15:0] baud_div, output logic tx_serial, tx_idle); logic [15:0] baud_cnt; logic [3:0] bit_cnt; logic [9:0] shift_reg; logic [1:0] state; always_ff @(posedge clk or negedge rst_n) if(!rst_n) begin state<=0; baud_cnt<=0; bit_cnt<=0; shift_reg<=1; tx_serial<=1; tx_ready<=1; end else case(state) 0: begin tx_ready<=1; if(tx_valid) begin shift_reg<={1'b1,tx_data,1'b0}; bit_cnt<=0; baud_cnt<=0; state<=1; tx_ready<=0; end end 1: begin if(baud_cnt==baud_div) begin baud_cnt<=0; tx_serial<=shift_reg[0]; shift_reg<=shift_reg>>1; bit_cnt<=bit_cnt+1; if(bit_cnt==9) state<=2; end else baud_cnt<=baud_cnt+1; end 2: begin tx_serial<=1; tx_ready<=1; state<=0; end endcase assign tx_idle=(state==0); endmodule\", \"target_clock_ns\": 20.0}", "assistant": "{\"synthesis_script\": \"read_verilog -sv uart_tx_8n1.v\\nhierarchy -check\\nproc; opt; fsm; opt; techmap; opt\\nstat\\nwrite_verilog -noattr uart_netlist.v\", \"target_clock_ns\": 20.0, \"expected_cell_primitives\": [\"DFF\", \"COUNTER\", \"SHIFT_REG\", \"MUX\", \"COMPARATOR\"], \"timing_slack_estimate\": \"very positive (50 MHz, slow baud counter)\", \"netlist_directives\": [\"infer shift register for 10-bit frame\", \"16-bit baud counter\"]}"} |
| {"system": "You are the SILICA Logic Synthesis agent. Output valid JSON with keys: synthesis_script, target_clock_ns, expected_cell_primitives, timing_slack_estimate, netlist_directives. synthesis_script is a Yosys .ys script. No markdown.", "user": "{\"rtl\": \"module axil_regbank_4x32(input logic s_axi_aclk, s_axi_aresetn, input logic [4:0] s_axi_awaddr, input logic s_axi_awvalid, output logic s_axi_awready, input logic [31:0] s_axi_wdata, input logic [3:0] s_axi_wstrb, input logic s_axi_wvalid, output logic s_axi_wready, output logic [1:0] s_axi_bresp, output logic s_axi_bvalid, input logic s_axi_bready, input logic [4:0] s_axi_araddr, input logic s_axi_arvalid, output logic s_axi_arready, output logic [31:0] s_axi_rdata, output logic [1:0] s_axi_rresp, output logic s_axi_rvalid, input logic s_axi_rready); logic [31:0] regs[0:3]; logic [1:0] wr_state, rd_state; always_ff @(posedge s_axi_aclk or negedge s_axi_aresetn) if(!s_axi_aresetn) begin s_axi_awready<=0;s_axi_wready<=0;s_axi_bvalid<=0;s_axi_arready<=0;s_axi_rvalid<=0; for(int i=0;i<4;i++) regs[i]<=0; end else begin if(s_axi_awvalid&&!s_axi_awready) s_axi_awready<=1; else if(s_axi_awready) s_axi_awready<=0; if(s_axi_wvalid&&!s_axi_wready) s_axi_wready<=1; else if(s_axi_wready) s_axi_wready<=0; if(s_axi_awready&&s_axi_wready) begin for(int i=0;i<4;i++) if(s_axi_wstrb[i]) regs[s_axi_awaddr[3:2]][i*8+:8]<=s_axi_wdata[i*8+:8]; s_axi_bvalid<=1; s_axi_bresp<=0; end if(s_axi_bvalid&&s_axi_bready) s_axi_bvalid<=0; if(s_axi_arvalid&&!s_axi_arready) s_axi_arready<=1; else if(s_axi_arready) begin s_axi_arready<=0; s_axi_rdata<=regs[s_axi_araddr[3:2]]; s_axi_rresp<=0; s_axi_rvalid<=1; end if(s_axi_rvalid&&s_axi_rready) s_axi_rvalid<=0; end endmodule\", \"target_clock_ns\": 10.0}", "assistant": "{\"synthesis_script\": \"read_verilog -sv axil_regbank_4x32.v\\nhierarchy -check\\nproc; opt; fsm; opt; techmap; opt\\nstat\\nwrite_verilog -noattr axil_netlist.v\", \"target_clock_ns\": 10.0, \"expected_cell_primitives\": [\"DFF\", \"MUX4\", \"DEMUX\", \"REGISTER_FILE_4x32\", \"FSM\"], \"timing_slack_estimate\": \"positive (100 MHz AXI, register bank simple)\", \"netlist_directives\": [\"infer 4x32 register file\", \"keep AXI handshake FSM separate\"]}"} |
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