system stringclasses 1
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You are the SILICA Functional Verification agent. Output valid JSON with keys: testbench_file, golden_reference_model, stimulus_sequences, assertion_checks, coverage_points. testbench_file is C++ for Verilator. No markdown. | {"spec": {"title": "4-deep 8-bit Synchronous FIFO", "feature_list": [{"feature": "FIFO Storage", "acceptance": "Stores up to 4 bytes with FIFO ordering"}], "interfaces": [{"signal": "clk", "dir": "input", "width": 1, "desc": "Primary clock"}, {"signal": "rst_n", "dir": "input", "width": 1, "desc": "Active low sync rese... | {"testbench_file": "#include \"Vfifo_sync_4x8.h\"\n#include \"verilated.h\"\nint main(int argc, char** argv){ Verilated::commandArgs(argc, argv); Vfifo_sync_4x8* top = new Vfifo_sync_4x8; top->clk=0; top->rst_n=0; top->eval(); top->rst_n=1; int errors=0; for(int cycle=0; cycle<1000; cycle++){ top->clk=!top->clk; top->e... |
You are the SILICA Functional Verification agent. Output valid JSON with keys: testbench_file, golden_reference_model, stimulus_sequences, assertion_checks, coverage_points. testbench_file is C++ for Verilator. No markdown. | {"spec": {"title": "4-Input Round-Robin Arbiter", "feature_list": [{"feature": "Fair arbitration", "acceptance": "Round-robin priority updates after each grant"}], "interfaces": [{"signal": "clk", "dir": "input", "width": 1}, {"signal": "rst_n", "dir": "input", "width": 1}, {"signal": "req", "dir": "input", "width": 4}... | {"testbench_file": "#include \"Varbiter_rr4.h\"\n#include \"verilated.h\"\nint main(int argc,char**argv){Verilated::commandArgs(argc,argv); Varbiter_rr4* t=new Varbiter_rr4; t->clk=0;t->rst_n=0;t->eval();t->rst_n=1;int err=0; for(int c=0;c<500;c++){t->clk=!t->clk;t->eval(); if(c%2==0){ t->req = (c*7+3)&0xF; } int g=t->... |
You are the SILICA Functional Verification agent. Output valid JSON with keys: testbench_file, golden_reference_model, stimulus_sequences, assertion_checks, coverage_points. testbench_file is C++ for Verilator. No markdown. | {"spec": {"title": "3-Stage Pipelined 8-bit ALU", "feature_list": [{"feature": "Pipelined execution", "acceptance": "One result per cycle after 3-cycle latency"}], "interfaces": [{"signal": "clk", "dir": "input", "width": 1}, {"signal": "rst_n", "dir": "input", "width": 1}, {"signal": "a", "dir": "input", "width": 8}, ... | {"testbench_file": "#include \"Valu_pipe3_8bit.h\"\n#include \"verilated.h\"\nint main(int argc,char**argv){Verilated::commandArgs(argc,argv); Valu_pipe3_8bit* t=new Valu_pipe3_8bit; t->clk=0;t->rst_n=0;t->eval();t->rst_n=1;int err=0; unsigned char expected[3]={0}; for(int c=0;c<200;c++){ t->clk=!t->clk; t->eval(); if(... |
You are the SILICA Functional Verification agent. Output valid JSON with keys: testbench_file, golden_reference_model, stimulus_sequences, assertion_checks, coverage_points. testbench_file is C++ for Verilator. No markdown. | {"spec": {"title": "UART Transmitter (8N1) with 16-byte TX FIFO", "feature_list": [{"feature": "Serial TX", "acceptance": "8N1 frames at configurable baud rate"}], "interfaces": [{"signal": "clk", "dir": "input", "width": 1}, {"signal": "rst_n", "dir": "input", "width": 1}, {"signal": "tx_data", "dir": "input", "width"... | {"testbench_file": "#include \"Vuart_tx_8n1.h\"\n#include \"verilated.h\"\nint main(int argc,char**argv){Verilated::commandArgs(argc,argv); Vuart_tx_8n1* t=new Vuart_tx_8n1; t->clk=0;t->rst_n=0;t->eval();t->rst_n=1;t->baud_div=10; int err=0; int bit_idx=0; unsigned char expect=0xA5; for(int c=0;c<2000;c++){ t->clk=!t->... |
You are the SILICA Functional Verification agent. Output valid JSON with keys: testbench_file, golden_reference_model, stimulus_sequences, assertion_checks, coverage_points. testbench_file is C++ for Verilator. No markdown. | {"spec": {"title": "AXI4-Lite 32-bit Register Bank (4 registers)", "feature_list": [{"feature": "Memory-mapped registers", "acceptance": "4x 32-bit R/W registers accessible via AXI4-Lite"}], "interfaces": [{"signal": "s_axi_aclk", "dir": "input", "width": 1}, {"signal": "s_axi_aresetn", "dir": "input", "width": 1}, {"s... | {"testbench_file": "#include \"Vaxil_regbank_4x32.h\"\n#include \"verilated.h\"\nint main(int argc,char**argv){Verilated::commandArgs(argc,argv); Vaxil_regbank_4x32* t=new Vaxil_regbank_4x32; t->s_axi_aclk=0;t->s_axi_aresetn=0;t->eval();t->s_axi_aresetn=1;int err=0; for(int c=0;c<500;c++){ t->s_axi_aclk=!t->s_axi_aclk;... |
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