Datasets:

Senlimulin
/

CodeV_R1_11kRTL_dataset

question listlengths 2 2	problem_id int64 7 165k	ground_truth listlengths 1 1	r1_response dict
[ { "content": "You are a helpful assistant. The assistant first thinks about the reasoning process in the mind and then provides the user with the answer. The reasoning process and answer are enclosed within <think> </think> and<answer> </answer> tags, respectively, i.e., <think> reasoning process here </think><...	488	[ { "content": "module Winner(\n\t//input clk, rst, \n\tinput [8:0] marked, owner,\n\toutput reg draw, winner, gameOver\n );\n\twire [1:0] pos1, pos2, pos3, pos4, pos5, pos6, pos7, pos8, pos9;\n\treg NoWin;\n\t\tassign pos1 = {marked[0], owner[0]};\n \tassign pos2 = {marked[1], owner[1]};\n \tassign pos3 = ...	{ "content": "\n\n<answer>\n```verilog\nmodule Winner (\n input [8:0] marked,\n input [8:0] owner,\n output draw,\n output winner,\n output gameOver\n);\n // Check rows for Player 1 and Player 2 wins\n wire p1_row0 = (&marked[2:0]) & (&owner[2:0]);\n wire p2_row0 = (&marked[2:0]) & ~(\|owner[2:...
[ { "content": "You are a helpful assistant. The assistant first thinks about the reasoning process in the mind and then provides the user with the answer. The reasoning process and answer are enclosed within <think> </think> and<answer> </answer> tags, respectively, i.e., <think> reasoning process here </think><...	95	[ { "content": "module ALU_Control\n(\n\tinput funct7_i, \n\tinput [2:0] ALU_Op_i,\n\tinput [2:0] funct3_i,\n\toutput [3:0] ALU_Operation_o\n);\n//R types\t\t\t\t\t\t\t f7 upc f3\nlocalparam R_Type_ADD\t\t= 7'b0_000_000;\nlocalparam R_Type_SUB\t\t= 7'b1_000_000;\nlocalparam R_Type_AND\t\t= 7'b0_000_111;\nlocalpa...	{ "content": "\n\n<answer>\n```verilog\nmodule ALU_Control (\n input funct7_i,\n input [2:0] ALU_Op_i,\n input [2:0] funct3_i,\n output reg [3:0] ALU_Operation_o\n);\n\nalways @(*) begin\n case (ALU_Op_i)\n // R-type instructions\n 3'b000: begin\n case (funct3_i)\n ...
[ { "content": "You are a helpful assistant. The assistant first thinks about the reasoning process in the mind and then provides the user with the answer. The reasoning process and answer are enclosed within <think> </think> and<answer> </answer> tags, respectively, i.e., <think> reasoning process here </think><...	29	[ { "content": "module expression_00547(a0, a1, a2, a3, a4, a5, b0, b1, b2, b3, b4, b5, y);\n input [3:0] a0;\n input [4:0] a1;\n input [5:0] a2;\n input signed [3:0] a3;\n input signed [4:0] a4;\n input signed [5:0] a5;\n input [3:0] b0;\n input [4:0] b1;\n input [5:0] b2;\n input signed [3:0] b3;\n i...	{ "content": "\n\n<answer>\n```verilog\nmodule expression_00547 (\n input [3:0] a0,\n input [4:0] a1,\n input [5:0] a2,\n input signed [3:0] a3,\n input signed [4:0] a4,\n input signed [5:0] a5,\n input [3:0] b0,\n input [4:0] b1,\n input [5:0] b2,\n input signed [3:0] b3,\n input sig...
[ { "content": "You are a helpful assistant. The assistant first thinks about the reasoning process in the mind and then provides the user with the answer. The reasoning process and answer are enclosed within <think> </think> and<answer> </answer> tags, respectively, i.e., <think> reasoning process here </think><...	320	[ { "content": "// R11552144.v \n//\n// Implement a 5-to-32 Line Decoder.\n//\nmodule top(A, D);\ninput [4:0] A;\noutput [31:0] D;\ndec5to32 u0(A, D);\nendmodule\n// OTHER MODULES HERE (IF REQUIRED)\nmodule dec5to32(A, D);\ninput [4:0] A;\noutput [31:0] D;\nwire [11:0] W;\ndec3to8 u0(.A(A[4:2]), .D(W[11:4]));\nde...	{ "content": "\n\n<answer>\n```verilog\nmodule decoder_1_to_2 (en, in, out);\n input en;\n input in;\n output [1:0] out;\n\n assign out[0] = en & ~in;\n assign out[1] = en & in;\nendmodule\n\nmodule decoder_2_to_4 (in, en, out);\n input [1:0] in;\n input en;\n output [3:0] out;\n\n wire [1:...
[ { "content": "You are a helpful assistant. The assistant first thinks about the reasoning process in the mind and then provides the user with the answer. The reasoning process and answer are enclosed within <think> </think> and<answer> </answer> tags, respectively, i.e., <think> reasoning process here </think><...	376	[ { "content": "module partsel_00574(ctrl, s0, s1, s2, s3, x0, x1, x2, x3, y);\n input [3:0] ctrl;\n input [2:0] s0;\n input [2:0] s1;\n input [2:0] s2;\n input [2:0] s3;\n input signed [31:0] x0;\n input signed [31:0] x1;\n input signed [31:0] x2;\n input [31:0] x3;\n wire [7:26] x4;\n wire [31:5] x5;...	{ "content": "\n\n<answer>\n```verilog\nmodule partsel_00574 (\n input [3:0] ctrl,\n input [2:0] s0,\n input [2:0] s1,\n input [2:0] s2,\n input [2:0] s3,\n input [31:0] x0,\n input [31:0] x1,\n input [31:0] x2,\n input [31:0] x3,\n output [127:0] y\n);\n\n // Local parameters\n lo...
[{"content":"You are a helpful assistant. The assistant first thinks about the reasoning process in (...TRUNCATED)	599	[{"content":"module controller (CLK, ST, SH, LD, D, C, REM, QUOT, REM_IN);\n input CLK, ST, C;\n (...TRUNCATED)	{"content":"\n\n<answer>\n```verilog\nmodule controller (\n input CLK,\n input ST,\n input (...TRUNCATED)
[{"content":"You are a helpful assistant. The assistant first thinks about the reasoning process in (...TRUNCATED)	150	[{"content":"module segdisplay(number,d0,d1,d2,d3);\ninput [15:0]number;\noutput reg [7:0]d0,d1,d2,d(...TRUNCATED)	{"content":"\n\n<answer>\n```verilog\nmodule segdisplay (\n input [15:0] number,\n output [7:0(...TRUNCATED)
[{"content":"You are a helpful assistant. The assistant first thinks about the reasoning process in (...TRUNCATED)	388	[{"content":"module partsel_00619(ctrl, s0, s1, s2, s3, x0, x1, x2, x3, y);\n input [3:0] ctrl;\n (...TRUNCATED)	{"content":"\n\n<answer> ```verilog\nmodule partsel_00619 (\n input [3:0] ctrl,\n input [2:0] (...TRUNCATED)
[{"content":"You are a helpful assistant. The assistant first thinks about the reasoning process in (...TRUNCATED)	523	[{"content":"`timescale 1ns / 1ps\nmodule seven_seg(\n\tinput wire [31:0] disp_num, // ′y??ê?μ?3(...TRUNCATED)	{"content":"\n\n<answer>\n```verilog\nmodule seven_seg (\n input [31:0] disp_num,\n input clr,(...TRUNCATED)
[{"content":"You are a helpful assistant. The assistant first thinks about the reasoning process in (...TRUNCATED)	634	[{"content":"module din7seg \n#(\n parameter razr_val = 8, //袣芯谢懈褔械褋褌胁芯褉邪(...TRUNCATED)	{"content":"\n\n<answer>\n```verilog\nmodule din7seg #(\n parameter NUM_DIGITS = 9\n) (\n input cl(...TRUNCATED)

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CodeV R1 1k RTL Dataset

Filtered from zhuyaoyu/CodeV-R1-dataset (sft/train, revision ffc4698071098044c72bde14fdad309eb3a1c5da).

Filter used for this version:

rtl_tokens > 1000
exactly one top module candidate: len(potential_top) == 1

Rows: 11,488.

Columns are kept in the LLM4Cov training format:

question
problem_id
ground_truth
r1_response

The accompanying .ids file lists problem_id values in parquet order.

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