repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
pavel-demin/red-pitaya-notes | cores/axi_bram_reader_v1_0/axi_bram_reader.v | 4,045 | module MODULE1 #
(
parameter integer VAR14 = 32,
parameter integer VAR28 = 16,
parameter integer VAR16 = 32,
parameter integer VAR13 = 10
)
(
input wire VAR6,
input wire VAR10,
input wire [VAR28-1:0] VAR40, input wire VAR31, output wire VAR1, input wire [VAR14-1:0] VAR21, input wire VAR20, output wire VAR12, output wir... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/fa/sky130_fd_sc_lp__fa.functional.v | 1,881 | module MODULE1 (
VAR20,
VAR10 ,
VAR6 ,
VAR19 ,
VAR16
);
output VAR20;
output VAR10 ;
input VAR6 ;
input VAR19 ;
input VAR16 ;
wire VAR13 ;
wire VAR2 ;
wire VAR9 ;
wire VAR18 ;
wire VAR3 ;
wire VAR23 ;
wire VAR12;
wire VAR11 ;
or VAR5 (VAR13 , VAR16, VAR19 );
and VAR22 (VAR2 , VAR13, VAR6 );
and VAR7 (VAR9 , VAR19, VAR1... | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/common/ad_ss_422to444.v | 5,031 | module MODULE1 (
clk,
VAR8,
VAR2,
VAR16,
VAR12,
VAR11);
parameter VAR14 = 0;
parameter VAR9 = 16;
localparam VAR10 = VAR9 - 1;
input clk;
input VAR8;
input [VAR10:0] VAR2;
input [15:0] VAR16;
output [VAR10:0] VAR12;
output [23:0] VAR11;
reg VAR4 = 'd0;
reg VAR1 = 'd0;
reg [VAR10:0] VAR15 = 'd0;
reg VAR5 = 'd0;
reg [7:0... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/clkdlybuf4s15/sky130_fd_sc_hd__clkdlybuf4s15_2.v | 2,163 | module MODULE2 (
VAR6 ,
VAR8 ,
VAR7,
VAR1,
VAR5 ,
VAR2
);
output VAR6 ;
input VAR8 ;
input VAR7;
input VAR1;
input VAR5 ;
input VAR2 ;
VAR3 VAR4 (
.VAR6(VAR6),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR2(VAR2)
);
endmodule
module MODULE2 (
VAR6,
VAR8
);
output VAR6;
input VAR8;
supply1 VAR7;
supply0 VAR1;... | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig39_2/mig_39_2/example_design/rtl/ui/ui_cmd.v | 7,971 | module MODULE1 #
(
parameter VAR19 = 100,
parameter VAR44 = 33,
parameter VAR53 = 3,
parameter VAR29 = 12,
parameter VAR39 = 2,
parameter VAR55 = 16,
parameter VAR2 = 4,
parameter VAR17 = "VAR38"
)
(
VAR36, VAR27, VAR48, VAR42, VAR28, VAR45, VAR52, VAR14, VAR26,
VAR4, VAR47, VAR10,
rst, clk, VAR51, VAR23, VAR30, VAR5, ... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/xnor3/sky130_fd_sc_hd__xnor3.behavioral.pp.v | 1,828 | module MODULE1 (
VAR10 ,
VAR13 ,
VAR12 ,
VAR2 ,
VAR8,
VAR14,
VAR9 ,
VAR6
);
output VAR10 ;
input VAR13 ;
input VAR12 ;
input VAR2 ;
input VAR8;
input VAR14;
input VAR9 ;
input VAR6 ;
wire VAR11 ;
wire VAR5;
xnor VAR1 (VAR11 , VAR13, VAR12, VAR2 );
VAR3 VAR7 (VAR5, VAR11, VAR8, VAR14);
buf VAR4 (VAR10 , VAR5 );
endmodul... | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/srams/rtl/bw_r_tlb.v | 67,841 | module MODULE2 (
VAR107, VAR95, VAR19, VAR105,
VAR69, VAR147, VAR43, VAR16,
VAR128, VAR63, VAR3,
VAR54, VAR61, VAR134,
VAR31, VAR162, VAR156, VAR112,
VAR151, VAR113, VAR178, VAR130,
VAR167, VAR80, VAR89, VAR66,
VAR13, VAR62, VAR65, VAR158,
VAR41, VAR85, VAR145, VAR79, VAR9, VAR120, VAR56, VAR164,
VAR122
) ;
input VAR12... | gpl-2.0 |
maijohnson/comp3601_blue_15s2 | AudioController/audio_player.v | 4,387 | module MODULE1(VAR28, VAR25, VAR34, VAR46, VAR30, VAR29, VAR48, VAR8,
VAR26, VAR47, VAR19, VAR35, VAR15, VAR43,
VAR27, VAR41, VAR39, VAR40, VAR33, VAR36,
VAR5, VAR7, VAR11, VAR49, VAR3, VAR14,
VAR13, VAR24, VAR20, VAR33, VAR12, VAR42, VAR18, VAR50
);
input VAR28; input [3:0] VAR34; input VAR46;
input VAR25;
input VAR26... | mit |
liqimai/Assignment1-Calculator | Integer-Arithmetic/AdderAndSuuber64/Adder16.v | 1,217 | module MODULE1(
input [15:0] VAR8,
input [15:0] VAR5,
input VAR10,
output [3:0] VAR23,
output [3:0] VAR3,
output [15:0] sum,
output VAR13,
output VAR15,
output VAR16,
output VAR22,
output VAR19
);
wire[15:0] VAR11,VAR26;
wire[4:0] VAR20;
wire[3:0] VAR24,VAR9,VAR17,VAR12,VAR1;
VAR25 VAR25(VAR11,VAR26,VAR23,VAR3);
VAR14 ... | gpl-2.0 |
cyrozap/blake2 | src/rtl/blake2_core.v | 26,016 | module MODULE1(
input wire clk,
input wire VAR171,
input wire VAR158,
input wire VAR8,
input wire VAR51,
input wire [1023 : 0] VAR63,
input wire [127 : 0] VAR36,
output wire ready,
output wire [511 : 0] VAR77,
output wire VAR116
);
parameter VAR82 = 4'hc;
parameter [7:0] VAR31 = 8'd64;
parameter [7:0] VAR182 = 8'd0;
pa... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/clkbuf/sky130_fd_sc_hs__clkbuf.functional.pp.v | 1,670 | module MODULE1 (
VAR3,
VAR2,
VAR7 ,
VAR6
);
input VAR3;
input VAR2;
output VAR7 ;
input VAR6 ;
wire VAR5 ;
wire VAR9;
buf VAR4 (VAR5 , VAR6 );
VAR1 VAR8 (VAR9, VAR5, VAR3, VAR2);
buf VAR10 (VAR7 , VAR9 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dfrtn/sky130_fd_sc_hd__dfrtn_1.v | 2,371 | module MODULE2 (
VAR2 ,
VAR6 ,
VAR8 ,
VAR5,
VAR9 ,
VAR1 ,
VAR10 ,
VAR7
);
output VAR2 ;
input VAR6 ;
input VAR8 ;
input VAR5;
input VAR9 ;
input VAR1 ;
input VAR10 ;
input VAR7 ;
VAR3 VAR4 (
.VAR2(VAR2),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR10(VAR10),
.VAR7(VAR7)
);
endmodule
module MODU... | apache-2.0 |
CospanDesign/nysa-verilog | verilog/axi/slave/axi_nes/rtl/cart/cart.v | 4,476 | module MODULE1 (
input VAR20,
input [39:0] VAR9, input VAR21,
input VAR22, input [14:0] VAR12, input VAR3, input [ 7:0] VAR1, output [ 7:0] VAR11,
input [13:0] VAR7, input VAR16, input [ 7:0] VAR14, output [ 7:0] VAR2, output VAR23, output VAR4 );
wire VAR26;
wire [14:0] VAR27;
wire [7:0] VAR8;
VAR17 #(
.VAR28 (15 ),
.... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | models/udp_dlatch_pr_pp_pkg_s/sky130_fd_sc_hs__udp_dlatch_pr_pp_pkg_s.symbol.v | 1,525 | module MODULE1 (
input VAR7 ,
output VAR8 ,
input VAR5 ,
input VAR3 ,
input VAR4,
input VAR2 ,
input VAR6 ,
input VAR1
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/busdriver2/sky130_fd_sc_lp__busdriver2.pp.symbol.v | 1,344 | module MODULE1 (
input VAR3 ,
output VAR2 ,
input VAR5,
input VAR7 ,
input VAR6,
input VAR4,
input VAR1
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_3.v | 2,031 | module MODULE1 (
VAR6,
VAR7 ,
VAR1 ,
VAR5 ,
VAR2
);
input VAR6;
input VAR7 ;
input VAR1 ;
input VAR5 ;
input VAR2 ;
VAR3 VAR4 (
.VAR6(VAR6),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR2(VAR2)
);
endmodule
module MODULE1 ();
supply1 VAR6;
supply1 VAR7 ;
supply0 VAR1 ;
supply1 VAR5 ;
supply0 VAR2 ;
VAR3 VAR4 ();
endmodul... | apache-2.0 |
m-labs/milkymist | cores/tmu2/rtl/tmu2_burst.v | 4,473 | module MODULE1 #(
parameter VAR13 = 26
) (
input VAR25,
input VAR1,
input VAR10,
output reg VAR18,
input VAR21,
output VAR24,
input [15:0] VAR14,
input [VAR13-1-1:0] VAR19,
output reg VAR8,
input VAR6,
output reg [VAR13-5-1:0] VAR5,
output reg [15:0] VAR12,
output reg [255:0] VAR22
);
wire VAR9 = VAR19[VAR13-1-1:4] == ... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/xnor2/sky130_fd_sc_hs__xnor2.behavioral.v | 1,719 | module MODULE1 (
VAR9 ,
VAR11 ,
VAR6 ,
VAR8,
VAR4
);
output VAR9 ;
input VAR11 ;
input VAR6 ;
input VAR8;
input VAR4;
wire VAR10 ;
wire VAR1;
xnor VAR5 (VAR10 , VAR11, VAR6 );
VAR3 VAR2 (VAR1, VAR10, VAR8, VAR4);
buf VAR7 (VAR9 , VAR1 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a2111o/sky130_fd_sc_lp__a2111o.functional.v | 1,489 | module MODULE1 (
VAR2 ,
VAR5,
VAR6,
VAR4,
VAR7,
VAR9
);
output VAR2 ;
input VAR5;
input VAR6;
input VAR4;
input VAR7;
input VAR9;
wire VAR3 ;
wire VAR1;
and VAR8 (VAR3 , VAR5, VAR6 );
or VAR10 (VAR1, VAR7, VAR4, VAR3, VAR9);
buf VAR11 (VAR2 , VAR1 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdlclkp/sky130_fd_sc_ls__sdlclkp.pp.symbol.v | 1,332 | module MODULE1 (
input VAR7 ,
input VAR8 ,
input VAR1,
output VAR6,
input VAR3 ,
input VAR2,
input VAR4,
input VAR5
);
endmodule | apache-2.0 |
lvd2/zxevo | unsupported/solegstar/fpga/current/slave/slavespi.v | 6,025 | module MODULE1(
input wire VAR6,
input wire VAR27,
input wire VAR23, output wire VAR20, input wire VAR9, input wire VAR1,
input wire [ 7:0] VAR4,
output wire [39:0] VAR26,
output wire VAR21,
output wire [ 7:0] VAR11,
output wire VAR5,
output wire VAR18,
output wire VAR22,
output wire VAR10,
input wire [ 7:0] VAR2,
inpu... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/invz/gf180mcu_fd_sc_mcu9t5v0__invz_12.behavioral.v | 1,185 | module MODULE1( VAR1, VAR2, VAR5 );
input VAR1, VAR2;
output VAR5;
VAR3 VAR6(.VAR1(VAR1),.VAR2(VAR2),.VAR5(VAR5));
VAR3 VAR4(.VAR1(VAR1),.VAR2(VAR2),.VAR5(VAR5)); | apache-2.0 |
hoangt/multiported-ram | mpram_xor.v | 9,433 | module MODULE1
localparam VAR35 = VAR5(VAR25);
reg [VAR35*VAR16-1:0] VAR1; reg [VAR7*VAR16-1:0] VAR33; reg [ VAR16-1:0] VAR3 ; always @(posedge clk) begin
VAR1 <= VAR11;
VAR33 <= VAR14;
VAR3 <= VAR31 ;
end
reg [VAR35 -1:0] VAR32 [VAR16-1:0] ; reg [VAR35 -1:0] VAR12 [VAR16-1:0] ; reg [VAR7 -1:0] VAR2 [VAR16-1:0] ; reg [... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | models/udp_dlatch_pr/sky130_fd_sc_lp__udp_dlatch_pr.blackbox.v | 1,291 | module MODULE1 (
VAR1 ,
VAR3 ,
VAR4 ,
VAR2
);
output VAR1 ;
input VAR3 ;
input VAR4 ;
input VAR2;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/dfrtp/sky130_fd_sc_hvl__dfrtp.behavioral.pp.v | 2,365 | module MODULE1 (
VAR20 ,
VAR12 ,
VAR9 ,
VAR18,
VAR14 ,
VAR22 ,
VAR16 ,
VAR5
);
output VAR20 ;
input VAR12 ;
input VAR9 ;
input VAR18;
input VAR14 ;
input VAR22 ;
input VAR16 ;
input VAR5 ;
wire VAR3 ;
wire VAR4 ;
reg VAR19 ;
wire VAR17 ;
wire VAR1 ;
wire VAR8;
wire VAR2 ;
wire VAR7 ;
not VAR10 (VAR4 , VAR8 );
VAR6 VAR2... | apache-2.0 |
alexforencich/xfcp | lib/eth/example/HXT100G/fpga_cxpt16/rtl/gth_i2c_init.v | 18,380 | module MODULE1 (
input wire clk,
input wire rst,
output wire [6:0] VAR16,
output wire VAR15,
output wire VAR10,
output wire VAR11,
output wire VAR1,
output wire VAR13,
output wire VAR14,
input wire VAR12,
output wire [7:0] VAR5,
output wire VAR6,
input wire VAR9,
output wire VAR4,
output wire VAR7,
input wire VAR3
);
l... | mit |
bluespec/Flute | builds/Flute_RV64GC_MSU_WB_L1_L2_verilator_tohost/Verilog_RTL/mkAXI4_Deburster_A.v | 48,649 | module MODULE1(VAR46,
VAR73,
VAR123,
VAR103,
VAR199,
VAR23,
VAR216,
VAR296,
VAR171,
VAR159,
VAR137,
VAR120,
VAR284,
VAR84,
VAR42,
VAR58,
VAR183,
VAR226,
VAR292,
VAR161,
VAR133,
VAR65,
VAR271,
VAR111,
VAR293,
VAR93,
VAR153,
VAR52,
VAR170,
VAR139,
VAR282,
VAR178,
VAR60,
VAR298,
VAR276,
VAR249,
VAR205,
VAR214,
VAR89,
VAR2... | apache-2.0 |
ShepardSiegel/ocpi | coregen/ddr3_s4_uniphy/ddr3_s4_uniphy.v | 24,125 | module MODULE1 (
input wire VAR34, input wire VAR6, input wire VAR17, output wire VAR5, output wire VAR28, output wire VAR4, output wire [12:0] VAR3, output wire [2:0] VAR31, output wire VAR11, output wire VAR33, output wire VAR27, output wire VAR40, output wire [1:0] VAR26, output wire VAR22, output wire VAR7, output ... | lgpl-3.0 |
SeanZarzycki/openSPARC-FPU | dc_compiler/iscas_benchmarks/s444.v | 7,657 | module MODULE1 (VAR408,VAR257,VAR198);
input VAR408,VAR198;
output VAR257;
wire VAR192,VAR75;
trireg VAR391,VAR260;
nmos VAR252 (VAR260,VAR198,VAR75);
not VAR219 (VAR192,VAR260);
nmos VAR200 (VAR391,VAR192,VAR408);
not VAR196 (VAR257,VAR391);
not VAR203 (VAR75,VAR408);
endmodule
module MODULE2(VAR421,VAR242,VAR408,VAR1... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/bufbuf/sky130_fd_sc_lp__bufbuf_16.v | 2,036 | module MODULE2 (
VAR8 ,
VAR3 ,
VAR2,
VAR1,
VAR4 ,
VAR6
);
output VAR8 ;
input VAR3 ;
input VAR2;
input VAR1;
input VAR4 ;
input VAR6 ;
VAR7 VAR5 (
.VAR8(VAR8),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR6(VAR6)
);
endmodule
module MODULE2 (
VAR8,
VAR3
);
output VAR8;
input VAR3;
supply1 VAR2;
supply0 VAR1;... | apache-2.0 |
tomhartley/EIEProj | dot_product/dot_product/dot_product.v7/cycle_mgc_ioport.v | 12,881 | module MODULE20 (VAR37, VAR17);
parameter integer VAR27 = 1;
parameter integer VAR23 = 8;
output [VAR23-1:0] VAR37;
input [VAR23-1:0] VAR17;
wire [VAR23-1:0] VAR37;
assign VAR37 = VAR17;
endmodule
module MODULE13 (VAR1, VAR37, VAR20, VAR17);
parameter integer VAR27 = 1;
parameter integer VAR23 = 8;
input VAR1;
output [... | mit |
fallen/milkymist-mmu | cores/bt656cap/rtl/bt656cap_ctlif.v | 2,790 | module MODULE1 #(
parameter VAR18 = 4'h0,
parameter VAR2 = 27
) (
input VAR6,
input VAR12,
input [13:0] VAR15,
input VAR11,
input [31:0] VAR16,
output reg [31:0] VAR17,
output reg irq,
output reg [1:0] VAR9,
input VAR22,
output reg [VAR2-1-5:0] VAR20,
input VAR19,
input VAR1,
output reg VAR8,
inout VAR13,
);
reg VAR24... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o21a/sky130_fd_sc_ms__o21a_1.v | 2,248 | module MODULE1 (
VAR6 ,
VAR9 ,
VAR10 ,
VAR3 ,
VAR2,
VAR4,
VAR8 ,
VAR7
);
output VAR6 ;
input VAR9 ;
input VAR10 ;
input VAR3 ;
input VAR2;
input VAR4;
input VAR8 ;
input VAR7 ;
VAR5 VAR1 (
.VAR6(VAR6),
.VAR9(VAR9),
.VAR10(VAR10),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR7(VAR7)
);
endmodule
module MODULE... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/tapvpwrvgnd/sky130_fd_sc_hdll__tapvpwrvgnd.behavioral.v | 1,171 | module MODULE1 ();
supply1 VAR4;
supply0 VAR1;
supply1 VAR3 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
MarcoVogt/basil | firmware/modules/m26_rx/m26_rx.v | 1,898 | module MODULE1
parameter VAR6 = 16'h0000,
parameter VAR13 = 16'h0000,
parameter VAR28 = 16,
parameter VAR16 = 0,
parameter VAR11 = 0
)(
input wire VAR20,
input wire [VAR28-1:0] VAR27,
inout wire [7:0] VAR1,
input wire VAR26,
input wire VAR15,
input wire VAR24,
input wire VAR5,
input wire VAR17,
input wire [1:0] VAR22,
... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a21o/sky130_fd_sc_ms__a21o.functional.pp.v | 1,994 | module MODULE1 (
VAR5 ,
VAR9 ,
VAR14 ,
VAR13 ,
VAR4,
VAR12,
VAR16 ,
VAR10
);
output VAR5 ;
input VAR9 ;
input VAR14 ;
input VAR13 ;
input VAR4;
input VAR12;
input VAR16 ;
input VAR10 ;
wire VAR15 ;
wire VAR1 ;
wire VAR11;
and VAR8 (VAR15 , VAR9, VAR14 );
or VAR3 (VAR1 , VAR15, VAR13 );
VAR2 VAR7 (VAR11, VAR1, VAR4, VAR... | apache-2.0 |
tnsrb93/G1_RealTimeDCTSteganography | src/ips/stream_encoder_ip_prj/stream_encoder_ip_prj.runs/scfifo_5in_5out_5kb_synth_1/scfifo_5in_5out_5kb_stub.v | 1,427 | module MODULE1(clk, rst, din, VAR3, VAR2, dout, VAR1, VAR4)
;
input clk;
input rst;
input [4:0]din;
input VAR3;
input VAR2;
output [4:0]dout;
output VAR1;
output VAR4;
endmodule | gpl-3.0 |
MeshSr/onetswitch20 | ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/core/eth_queue.v | 6,253 | module MODULE1
parameter VAR7 = 64,
parameter VAR19=VAR7/8,
parameter VAR11 = 0,
parameter VAR32 = 'hff,
parameter VAR5 = 0
)(
output [VAR7-1:0] VAR24,
output [VAR19-1:0] VAR27,
output VAR3,
input VAR8,
input [VAR7-1:0] VAR20,
input [VAR19-1:0] VAR2,
input VAR4,
output VAR29,
input [31:0] VAR38,
input VAR30,
input VAR2... | lgpl-2.1 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/decap/sky130_fd_sc_hdll__decap_8.v | 1,886 | module MODULE1 (
VAR1,
VAR2,
VAR5 ,
VAR6
);
input VAR1;
input VAR2;
input VAR5 ;
input VAR6 ;
VAR4 VAR3 (
.VAR1(VAR1),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR6(VAR6)
);
endmodule
module MODULE1 ();
supply1 VAR1;
supply0 VAR2;
supply1 VAR5 ;
supply0 VAR6 ;
VAR4 VAR3 ();
endmodule | apache-2.0 |
ShepardSiegel/ocpi | vhdl/mkBiasWorker.v | 2,359 | module MODULE1(
VAR31,
VAR28,
VAR36,
VAR9,
VAR7,
VAR24,
VAR2,
VAR6,
VAR38,
VAR10,
VAR5,
VAR42,
VAR18,
VAR23,
VAR19);
input VAR31;
input VAR28;
input [59 : 0] VAR36;
output [33 : 0] VAR9;
output VAR7;
output [1 : 0] VAR24;
input [1 : 0] VAR2;
input [60 : 0] VAR6;
output VAR38;
output [60 : 0] VAR10;
input VAR5;
output V... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/busdriver2/sky130_fd_sc_lp__busdriver2.symbol.v | 1,350 | module MODULE1 (
input VAR1 ,
output VAR6 ,
input VAR5
);
supply1 VAR4;
supply0 VAR7;
supply1 VAR2 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
SLongofono/Senior_Design_Capstone | hdl/Ram2Ddr_RefComp/Source/Ram2DdrXadc_RefComp/ipcore_dir/ddr/user_design/rtl/phy/mig_7series_v1_9_ddr_prbs_gen.v | 7,727 | module MODULE1 #
(
parameter VAR12 = 100, parameter VAR7 = 64 )
(
input VAR6, input VAR2, input VAR5, input [VAR7-1:0] VAR15, input VAR18, input VAR9, output [VAR7-1:0] VAR16 );
function integer VAR1 (input integer VAR14);
begin
VAR14 = VAR14 - 1;
for (VAR1=1; VAR14>1; VAR1=VAR1+1)
VAR14 = VAR14 >> 1;
end
endfunction
l... | mit |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.3/OpenSSD2_2Ch8Way-1.0.3/OpenSSD2.srcs/sources_1/ipshared/ENCLab/Tiger4NSC_v1_2_5/ab882192/src/uProgROM.v | 4,498 | module MODULE1
(
parameter VAR31 = 64 ,
parameter VAR9 = 256
)
(
VAR5 ,
VAR4 ,
VAR21 ,
VAR13 ,
VAR25 ,
VAR18 ,
VAR22 ,
VAR2 ,
VAR23 ,
VAR29 ,
VAR12 ,
VAR15 ,
VAR14 ,
VAR28
);
input VAR5 ;
input VAR4 ;
input [VAR17(VAR9) - 1:0] VAR21 ;
input VAR13 ;
output [VAR31 - 1:0] VAR25 ;
output VAR18 ;
input VAR22 ;
output VAR2 ;... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfstp/sky130_fd_sc_ls__sdfstp.behavioral.pp.v | 2,802 | module MODULE1 (
VAR22 ,
VAR28 ,
VAR25 ,
VAR29 ,
VAR14 ,
VAR27,
VAR11 ,
VAR1 ,
VAR5 ,
VAR30
);
output VAR22 ;
input VAR28 ;
input VAR25 ;
input VAR29 ;
input VAR14 ;
input VAR27;
input VAR11 ;
input VAR1 ;
input VAR5 ;
input VAR30 ;
wire VAR2 ;
wire VAR10 ;
wire VAR8 ;
reg VAR19 ;
wire VAR3 ;
wire VAR13 ;
wire VAR9 ;
w... | apache-2.0 |
takeshineshiro/fpga_linear_128 | Transmit_Delay_ROM_bb.v | 5,193 | module MODULE1 (
address,
VAR2,
VAR1);
input [2:0] address;
input VAR2;
output [127:0] VAR1;
endmodule | mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/system/synthesis/submodules/acl_work_group_limiter.v | 9,309 | module MODULE1 #(
parameter unsigned VAR12 = 1, parameter unsigned VAR29 = 1, parameter unsigned VAR32 = 1, parameter unsigned VAR16 = 1, parameter string VAR30 = "local" )
(
VAR23,
VAR24,
VAR15,
VAR33,
VAR4,
VAR17,
VAR8,
VAR9,
VAR14,
VAR27,
VAR28,
VAR1,
VAR22,
VAR10
);
input logic VAR23;
input logic VAR24;
localparam ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric.symbol.v | 1,430 | module MODULE1 (
input VAR3,
output VAR1
);
supply1 VAR6 ;
supply0 VAR2 ;
supply1 VAR4;
supply1 VAR5 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
yanhongwang/ColorImage | SaturationEnhancement/SaturationEnhancement.v | 1,237 | module MODULE2
(
input signed[ VAR8 - 1 : 0 ]VAR1,
input signed[ VAR8 - 1 : 0 ]VAR4,
output wire signed[ VAR8 - 1 : 0 ]VAR6,
output wire signed[ VAR8 - 1 : 0 ]VAR9
);
assign VAR6 = ( VAR1 * VAR5 ) >> VAR7;
assign VAR9 = ( VAR4 * VAR2 ) >> VAR7;
endmodule
module MODULE1;
reg signed[ VAR8 - 1 : 0 ]VAR1;
reg signed[ VAR8 ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/einvn/sky130_fd_sc_ls__einvn_4.v | 2,150 | module MODULE2 (
VAR7 ,
VAR5 ,
VAR8,
VAR1,
VAR4,
VAR9 ,
VAR3
);
output VAR7 ;
input VAR5 ;
input VAR8;
input VAR1;
input VAR4;
input VAR9 ;
input VAR3 ;
VAR2 VAR6 (
.VAR7(VAR7),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR3(VAR3)
);
endmodule
module MODULE2 (
VAR7 ,
VAR5 ,
VAR8
);
output VAR7 ;... | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_mem/bsg_mem_1r1w_sync_mask_write_bit_synth.v | 3,142 | module MODULE1 #(parameter VAR17(VAR24)
, parameter VAR17(VAR22)
, parameter VAR8=0
, parameter VAR3=VAR10(VAR22)
, parameter VAR28=0
, parameter VAR12=1
)
(input VAR27
, input VAR20
, input VAR2
, input [VAR1(VAR24, 1):0] VAR23
, input [VAR3-1:0] VAR19
, input [VAR1(VAR24, 1):0] VAR18
, input VAR9
, input [VAR3-1:0] V... | bsd-3-clause |
mbus/mbus | m3_mbus_releases/r04p2g/sample/FLPv3L/verilog/mbus/flpv3l_mbus_isolation.v | 3,820 | module MODULE1 (
input VAR31,
input [31:0] VAR43,
input [31:0] VAR62,
input VAR30,
input VAR9,
input VAR7,
input VAR18,
input VAR17,
output [31:0] VAR40,
output [31:0] VAR39,
output VAR57,
output VAR52,
output VAR3,
output VAR63,
output VAR26,
input VAR10,
input VAR36,
input VAR44,
input VAR51,
output VAR27,
output VAR... | apache-2.0 |
markusC64/1541ultimate2 | fpga/nios_dut/nios_dut/synthesis/submodules/nios_dut_mm_interconnect_0_avalon_st_adapter_011.v | 6,185 | module MODULE1 #(
parameter VAR19 = 130,
parameter VAR18 = 0,
parameter VAR24 = 130,
parameter VAR9 = 0,
parameter VAR8 = 0,
parameter VAR21 = 0,
parameter VAR7 = 1,
parameter VAR1 = 1,
parameter VAR17 = 0,
parameter VAR23 = 130,
parameter VAR12 = 0,
parameter VAR3 = 1,
parameter VAR15 = 0,
parameter VAR6 = 1,
paramete... | gpl-3.0 |
finnball/igloo | infra/hdl/uart_rx.v | 2,746 | module MODULE1(
input VAR20,
input VAR19,
output [VAR16 - 1 : 0] VAR6,
output VAR26
);
localparam VAR22 = VAR24;
localparam VAR25 = VAR30;
localparam VAR15 = VAR11;
localparam VAR2 = VAR1;
localparam VAR13 = VAR7(VAR22);
localparam VAR3 = VAR9;
localparam VAR29 = VAR7(VAR3);
localparam VAR16 = VAR18;
localparam VAR17 =... | gpl-3.0 |
hakehuang/pycpld | ips/ip/enc/enc.v | 2,633 | module MODULE1(VAR13, VAR11, enable, VAR4, VAR6, VAR14, VAR15, VAR8);
input VAR13;
input VAR11;
input enable;
output VAR4;
output VAR6;
output VAR14;
output VAR15;
output VAR8;
reg VAR10;
reg VAR3;
reg VAR2;
reg VAR5;
reg[7:0] VAR9;
reg VAR8;
reg [31:0] VAR7;
reg VAR1;
always @(posedge VAR11 or negedge VAR13) begin
if ... | mit |
combinatorylogic/soc | backends/tiny1/hw/ice/3rdparty.v | 6,596 | module MODULE6(
input wire clk,
output wire VAR37);
localparam VAR7 = (VAR24 / VAR22) - 1;
localparam VAR4 = VAR31(VAR7);
wire [VAR4-1:0] VAR23 = VAR7;
reg [VAR4-1:0] counter;
assign VAR37 = (counter == VAR23);
always @(posedge clk)
counter <= VAR37 ? 0 : (counter + 1);
endmodule
module MODULE7(
input wire clk,
input w... | mit |
ShepardSiegel/ocpi | coregen/pcie_4243_trn_v5_gtp_x1_125/example_design/xilinx_pci_exp_ep.v | 18,588 | module MODULE1
(
VAR47,
VAR16,
VAR139,
VAR128,
VAR48,
VAR150,
VAR149,
VAR77
);
output [(1 - 1):0] VAR47;
output [(1 - 1):0] VAR16;
input [(1 - 1):0] VAR139;
input [(1 - 1):0] VAR128;
input VAR48;
input VAR150;
input VAR149;
output VAR77;
wire VAR34;
wire VAR88;
wire VAR73; wire VAR105;
wire VAR135;
wire VAR109;
wire [(... | lgpl-3.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src/yf32/pc_next_ipv4.v | 4,254 | module MODULE1 (clk, reset, VAR10, VAR6, VAR7,
VAR2, VAR3, VAR1, VAR4,VAR8);
input clk;
input reset;
input [31:2] VAR10;
input VAR6;
input VAR7;
input [25:0] VAR2;
input [ 1:0] VAR3;
output [31:0] VAR1;
output [31:0] VAR4;
output [31:0] VAR8;
reg[31:2] VAR9;
reg[31:2] VAR11;
wire [31:2] VAR5 = VAR11 + 1;
wire [31:0] VA... | mit |
lokisz/openzcore | pippo-riscv/rtl/verilog/pippo_alu.v | 5,488 | module MODULE1(
clk, rst,
VAR16, VAR11, VAR4,
VAR21,
VAR28
);
parameter VAR27 = VAR5;
input clk;
input rst;
input [VAR18-1:0] VAR16;
input [VAR27-1:0] VAR11;
input [VAR27-1:0] VAR4;
input VAR7;
input [14:0] VAR21;
output [VAR27-1:0] VAR28;
wire [VAR27-1:0] VAR11;
wire [VAR27-1:0] VAR4;
wire [VAR29-1:0] VAR25;
assign VA... | gpl-2.0 |
cfangmeier/VFPIX-telescope-Code | DAQ_Firmware/src/ram/ram_controller_phy_alt_mem_phy_seq_wrapper.v | 19,975 | module MODULE1 (
VAR67,
VAR106,
VAR115,
VAR169,
VAR3,
VAR160,
VAR30,
VAR144,
VAR109,
VAR119,
VAR139,
VAR20,
VAR37,
VAR13,
VAR39,
VAR87,
VAR68,
VAR102,
VAR116,
VAR61,
VAR103,
VAR24,
VAR129,
VAR143,
VAR178,
VAR97,
VAR141,
VAR88,
VAR10,
VAR101,
VAR179,
VAR62,
VAR25,
VAR70,
VAR83,
VAR51,
VAR174,
VAR180,
VAR161,
VAR40,
VAR1... | gpl-2.0 |
kulp/tenyr | hw/verilog/vga_text.v | 5,330 | module MODULE3(
clk, reset, en,
out, VAR50, VAR40
);
parameter integer VAR60 = 0;
parameter integer VAR46 = 255;
parameter integer VAR5 = 1;
input clk, reset, en;
output integer out;
output reg VAR50; output reg VAR40;
always @(posedge clk)
if (reset) begin
out <= VAR60;
VAR40 <= 0;
VAR50 <= 0;
end else if (en) begin
V... | mit |
jairov4/accel-oil | solution_spartan3/syn/verilog/nfa_accept_sample.v | 43,674 | module MODULE1 (
VAR226,
VAR47,
VAR199,
VAR117,
VAR131,
VAR154,
VAR44,
VAR56,
VAR173,
VAR10,
VAR113,
VAR258,
VAR69,
VAR54,
VAR265,
VAR277,
VAR217,
VAR127,
VAR169,
VAR134,
VAR157,
VAR163,
VAR133,
VAR174,
VAR281,
VAR207,
VAR238,
VAR225,
VAR20,
VAR246,
VAR65,
VAR211,
VAR52,
VAR5,
VAR123,
VAR210,
VAR94,
VAR231,
VAR203,
VAR... | lgpl-3.0 |
da-steve101/binary_connect_cifar | src/main/verilog/Queue_2048.v | 1,275 | module MODULE1
(
input VAR8,
input reset,
input [2047:0] VAR13,
input VAR7,
output VAR15,
output [2047:0] VAR14,
output VAR6,
input VAR17
);
wire VAR2;
wire VAR16;
wire VAR4;
wire VAR5;
wire [1023:0] VAR1;
wire [1023:0] VAR12;
wire [1023:0] VAR11;
wire [1023:0] VAR3;
assign VAR1 = VAR13[1023:0];
assign VAR12 = VAR13[20... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/dffnq/gf180mcu_fd_sc_mcu9t5v0__dffnq_4.behavioral.pp.v | 2,214 | module MODULE1( VAR6, VAR7, VAR10, VAR3, VAR5 );
input VAR6, VAR7;
inout VAR3, VAR5;
output VAR10;
reg VAR12;
VAR9 VAR11(.VAR6(VAR6),.VAR7(VAR7),.VAR10(VAR10),.VAR3(VAR3),.VAR5(VAR5),.VAR12(VAR12));
VAR9 VAR1(.VAR6(VAR6),.VAR7(VAR7),.VAR10(VAR10),.VAR3(VAR3),.VAR5(VAR5),.VAR12(VAR12));
not VAR8(VAR2,VAR7);
buf VAR13(VA... | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/controllerHdl_Reset_Delay.v | 2,071 | module MODULE1
(
VAR3,
reset,
VAR6,
VAR8,
VAR1,
VAR11
);
input VAR3;
input reset;
input VAR6;
input VAR8;
input signed [31:0] VAR1; output signed [31:0] VAR11;
wire signed [31:0] VAR5; wire signed [31:0] VAR4; reg signed [31:0] VAR9; wire signed [31:0] VAR12; wire signed [31:0] VAR2;
assign VAR5 = 32'VAR7;
assign VAR4 ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/xnor2/sky130_fd_sc_hs__xnor2.blackbox.v | 1,238 | module MODULE1 (
VAR5,
VAR1,
VAR4
);
output VAR5;
input VAR1;
input VAR4;
supply1 VAR2;
supply0 VAR3;
endmodule | apache-2.0 |
Digilent/vivado-library | ip/video_scaler/hdl/verilog/video_scaler.v | 28,149 | module MODULE1 (
VAR13,
VAR138,
VAR5,
VAR42,
VAR160,
VAR6,
VAR157,
VAR35,
VAR46,
VAR113,
VAR1,
VAR15,
VAR154,
VAR30,
VAR80,
VAR111,
VAR144,
VAR132,
VAR88,
interrupt,
VAR31,
VAR130,
VAR4,
VAR133,
VAR60,
VAR59,
VAR190,
VAR83,
VAR81,
VAR50,
VAR137,
VAR147,
VAR110,
VAR121,
VAR120,
VAR124,
VAR178,
VAR122
);
parameter VAR76 ... | mit |
esonghori/TinyGarbled | circuit_synthesis/sha3/sha3_comb.v | 1,698 | module MODULE1
parameter VAR6=1
)
(
clk,
rst,
VAR15,
VAR3,
VAR9
);
input clk;
input rst;
input [287:0] VAR15;
input [287:0] VAR3;
output [1599:0] VAR9;
wire [63:0] VAR4 [24/VAR6-1:0];
wire [1599:0] VAR8 [24/VAR6-1:0];
wire [1599:0] VAR5 [24/VAR6-1:0];
assign VAR8[0] = {VAR3, VAR15};
assign VAR9 = VAR5[24/VAR6-1];
genva... | gpl-3.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_misc/bsg_crossbar_control_basic_o_by_i.v | 2,009 | module MODULE1
, parameter VAR5(VAR28)
, parameter VAR1=VAR29(VAR28)
)
(
input VAR6
, input VAR9
, input [VAR36-1:0] VAR2
, input [VAR36-1:0][VAR1-1:0] VAR13
, output [VAR36-1:0] VAR4
, input [VAR28-1:0] VAR20
, output [VAR28-1:0] VAR3
, output [VAR28-1:0][VAR36-1:0] VAR31
);
logic [VAR36-1:0][VAR28-1:0] VAR26;
logic [... | bsd-3-clause |
sehugg/8bitworkshop | presets/verilog/alu.v | 1,393 | module MODULE1(VAR1, VAR3, VAR4, VAR2, VAR6);
parameter VAR5 = 8; input [VAR5-1:0] VAR1; input [VAR5-1:0] VAR3; input VAR4; input [3:0] VAR2; output reg [VAR5:0] VAR6;
always @(*)
case (VAR2)
endcase
endmodule | gpl-3.0 |
BilkentCompGen/GateKeeper | FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/pcie3_7x_0/source/pcie3_7x_0_gt_common.v | 7,154 | module MODULE1 #(
parameter VAR37 = "VAR43", parameter VAR52 = "VAR18", parameter VAR9 = "2.1", parameter VAR28 = "VAR23", parameter VAR8 = 0 )
(
input VAR56,
input VAR24,
input VAR19,
input VAR35,
input VAR6,
input VAR4,
input VAR15,
input VAR21,
output [5:0] VAR38,
output [8:0] VAR29,
output VAR40,
output VAR54,
outp... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/xor2/sky130_fd_sc_ls__xor2.pp.blackbox.v | 1,291 | module MODULE1 (
VAR3 ,
VAR4 ,
VAR2 ,
VAR6,
VAR7,
VAR5 ,
VAR1
);
output VAR3 ;
input VAR4 ;
input VAR2 ;
input VAR6;
input VAR7;
input VAR5 ;
input VAR1 ;
endmodule | apache-2.0 |
olajep/oh | src/common/hdl/oh_crc32_8b.v | 6,022 | module MODULE1(
VAR3,
VAR2, VAR1
);
input [7:0] VAR2; input [31:0] VAR1; output [31:0] VAR3;
assign VAR3[0] = VAR1[2] ^ VAR1[8] ^ VAR2[2];
assign VAR3[1] = VAR1[0] ^ VAR1[3] ^ VAR1[9] ^ VAR2[0] ^ VAR2[3];
assign VAR3[2] = VAR1[0] ^ VAR1[1] ^ VAR1[4] ^ VAR1[10] ^ VAR2[0] ^ VAR2[1] ^ VAR2[4];
assign VAR3[3] = VAR1[1] ^ V... | mit |
ShepardSiegel/ocpi | rtl/mkFlashController2416.v | 64,419 | module MODULE1(VAR81,
VAR220,
VAR15,
VAR209,
VAR161,
VAR96,
VAR55,
VAR193,
VAR45,
VAR183,
VAR145,
VAR52,
VAR217,
VAR115,
VAR25,
VAR234,
VAR41,
VAR104,
VAR216);
input VAR81;
input VAR220;
inout [15 : 0] VAR15;
output [23 : 0] VAR209;
output VAR161;
output VAR96;
output VAR55;
output VAR193;
output VAR45;
output VAR183;
... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o2111a/sky130_fd_sc_lp__o2111a.behavioral.v | 1,588 | module MODULE1 (
VAR13 ,
VAR4,
VAR10,
VAR8,
VAR7,
VAR1
);
output VAR13 ;
input VAR4;
input VAR10;
input VAR8;
input VAR7;
input VAR1;
supply1 VAR6;
supply0 VAR2;
supply1 VAR14 ;
supply0 VAR11 ;
wire VAR12 ;
wire VAR9;
or VAR3 (VAR12 , VAR10, VAR4 );
and VAR5 (VAR9, VAR8, VAR7, VAR12, VAR1);
buf VAR15 (VAR13 , VAR9 );
e... | apache-2.0 |
rkrajnc/minimig-de1 | rtl/or1200/or1200_spram_64x14.v | 8,772 | module MODULE1(
VAR7, VAR45, VAR44,
clk, rst, VAR25, VAR24, VAR1, addr, VAR15, VAR34
);
parameter VAR6 = 6;
parameter VAR17 = 14;
input VAR7;
input [VAR33 - 1:0] VAR44;
output VAR45;
input clk; input rst; input VAR25; input VAR24; input VAR1; input [VAR6-1:0] addr; input [VAR17-1:0] VAR15; output [VAR17-1:0] VAR34;
wir... | gpl-3.0 |
P3Stor/P3Stor | pcie/core/pcie_trn_128.v | 9,319 | module MODULE1 #(
parameter VAR46 = 100
)(
input VAR16,
input VAR35,
input VAR68,
input VAR19,
input [1:0] VAR6,
output [6:0] VAR14,
output [127:0] VAR74,
output VAR44,
output VAR33,
output VAR8,
output VAR27,
output [1:0] VAR43,
output VAR25,
output VAR10,
input VAR71,
input VAR78,
output [5:0] VAR75,
output VAR53,
ou... | gpl-2.0 |
xuefei1/ElectronicEngineControl | niosII_system/synthesis/submodules/niosII_system_green_leds.v | 2,262 | module MODULE1 (
address,
VAR8,
clk,
VAR9,
VAR4,
VAR6,
VAR1,
VAR2
)
;
output [ 7: 0] VAR1;
output [ 31: 0] VAR2;
input [ 1: 0] address;
input VAR8;
input clk;
input VAR9;
input VAR4;
input [ 31: 0] VAR6;
wire VAR5;
reg [ 7: 0] VAR7;
wire [ 7: 0] VAR1;
wire [ 7: 0] VAR3;
wire [ 31: 0] VAR2;
assign VAR5 = 1;
assign VAR3 ... | apache-2.0 |
dingzh/piplined-MIPS-CPU | src/LAB4/Register.v | 1,082 | module MODULE1(
input VAR8,
input VAR2,
input [4:0] VAR7, input [4:0] VAR1,
input [4:0] VAR9, input [31:0] VAR4,
output reg [31:0] VAR5,
output reg [31:0] VAR3
);
reg [31:0] VAR6[31:0];
always @(VAR7 or VAR1 or posedge VAR8)
begin
VAR5 = VAR6[VAR7];
VAR3 = VAR6[VAR1];
end
always @(negedge VAR8)
begin
if(VAR2)
VAR6[VAR9... | gpl-3.0 |
KestrelComputer/kestrel | cores/SIA/rtl/verilog/sia_transmitter.v | 2,121 | module MODULE1(
input VAR12,
input VAR17,
input VAR18,
input [VAR19:0] VAR20,
input VAR10,
input VAR15,
input [VAR1:0] VAR13,
input [VAR2:0] VAR14,
output VAR3,
output VAR23,
output VAR7,
output [VAR1:0] VAR4,
output [VAR2:0] VAR6,
output [VAR19:0] VAR21
);
parameter VAR9 = 16;
parameter VAR22 = 32;
parameter VAR5 = 5;... | mpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/or2b/sky130_fd_sc_hs__or2b.pp.symbol.v | 1,251 | module MODULE1 (
input VAR3 ,
input VAR2 ,
output VAR1 ,
input VAR5,
input VAR4
);
endmodule | apache-2.0 |
azonenberg/antikernel-ipcores | device_abstraction/JtagTAP.v | 5,007 | module MODULE1 #(
parameter VAR25 = 1
) (
output wire VAR3,
output wire VAR7,
output wire VAR21,
output wire VAR15,
output wire VAR19,
output wire VAR11,
output wire VAR5,
output wire VAR4,
output wire VAR18,
output wire VAR1,
input wire VAR14 );
VAR23 #(
.VAR20(VAR25)
)
VAR10 (
.VAR12(VAR3),
.VAR8(VAR5),
.VAR27(VAR7),... | bsd-3-clause |
Gurint/EPC-Gen2-RFID-Tag-Baseband-Processor | frmgen.v | 4,197 | module MODULE1
(
output reg VAR1,
output VAR16,
output reg VAR17,
output VAR13,
output VAR2,
output reg VAR14,
input VAR11,
input VAR9,
input VAR3,
input [15:0]VAR7,
input [1:0]VAR10,
input VAR5,
input VAR19,
input VAR15
);
reg VAR18;
reg [4:0]VAR4;
reg [4:0]VAR8;
reg [3:0]VAR6;
reg VAR12;
assign VAR16 = (VAR10 == 2'b0... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dfbbn/sky130_fd_sc_hd__dfbbn.pp.symbol.v | 1,490 | module MODULE1 (
input VAR6 ,
output VAR2 ,
output VAR9 ,
input VAR10,
input VAR3 ,
input VAR8 ,
input VAR1 ,
input VAR7 ,
input VAR4 ,
input VAR5
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nor2/sky130_fd_sc_hd__nor2_4.v | 2,086 | module MODULE1 (
VAR9 ,
VAR5 ,
VAR7 ,
VAR4,
VAR6,
VAR1 ,
VAR8
);
output VAR9 ;
input VAR5 ;
input VAR7 ;
input VAR4;
input VAR6;
input VAR1 ;
input VAR8 ;
VAR2 VAR3 (
.VAR9(VAR9),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR8(VAR8)
);
endmodule
module MODULE1 (
VAR9,
VAR5,
VAR7
);
output VAR9;
... | apache-2.0 |
craftdrones/MPU9250 | src/hdl/sensor_interface_v1_0.v | 4,476 | module MODULE1 #
(
parameter integer VAR18 = 100000000,
parameter integer VAR44 = 400000,
parameter integer VAR86 = 32,
parameter integer VAR75 = 8
)
(
input wire VAR17,
output wire VAR84,
output wire VAR70,
input wire VAR90,
output wire VAR67,
output wire VAR2,
input wire sync,
output wire interrupt,
input wire VAR39,... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/einvp/sky130_fd_sc_hd__einvp_4.v | 2,130 | module MODULE2 (
VAR7 ,
VAR3 ,
VAR8 ,
VAR5,
VAR1,
VAR2 ,
VAR9
);
output VAR7 ;
input VAR3 ;
input VAR8 ;
input VAR5;
input VAR1;
input VAR2 ;
input VAR9 ;
VAR6 VAR4 (
.VAR7(VAR7),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR9(VAR9)
);
endmodule
module MODULE2 (
VAR7 ,
VAR3 ,
VAR8
);
output VAR7... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/or3/sky130_fd_sc_ms__or3_1.v | 2,153 | module MODULE2 (
VAR4 ,
VAR3 ,
VAR9 ,
VAR5 ,
VAR7,
VAR6,
VAR2 ,
VAR10
);
output VAR4 ;
input VAR3 ;
input VAR9 ;
input VAR5 ;
input VAR7;
input VAR6;
input VAR2 ;
input VAR10 ;
VAR1 VAR8 (
.VAR4(VAR4),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR10(VAR10)
);
endmodule
module MODULE... | apache-2.0 |
vad-rulezz/megabot | minsoc/rtl/verilog/minsoc_startup/OR1K_startup_generic.v | 1,725 | module MODULE1
(
input [6:2] VAR3,
input VAR6,
input VAR1,
output reg [31:0] VAR2,
output reg VAR5,
input VAR4,
input VAR8
);
always @ (posedge VAR4 or posedge VAR8)
if (VAR8)
VAR2 <= 32'h15000000;
else
case (VAR3)
0 : VAR2 <= 32'h18000000;
1 : VAR2 <= 32'hA8200000;
2 : VAR2 <= { 16'h1880 , VAR7 , 8'h00 };
3 : VAR2 <= ... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sedfxbp/sky130_fd_sc_hs__sedfxbp.functional.v | 2,083 | module MODULE1 (
VAR14 ,
VAR16 ,
VAR11 ,
VAR15 ,
VAR12 ,
VAR1 ,
VAR10 ,
VAR19,
VAR4
);
output VAR14 ;
output VAR16 ;
input VAR11 ;
input VAR15 ;
input VAR12 ;
input VAR1 ;
input VAR10 ;
input VAR19;
input VAR4;
wire VAR2 ;
wire VAR5;
wire VAR20 ;
VAR17 VAR3 (VAR5, VAR20, VAR1, VAR10 );
VAR17 VAR6 (VAR20 , VAR2, VAR15, ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/xnor2/sky130_fd_sc_lp__xnor2_4.v | 2,132 | module MODULE1 (
VAR3 ,
VAR2 ,
VAR8 ,
VAR5,
VAR7,
VAR1 ,
VAR9
);
output VAR3 ;
input VAR2 ;
input VAR8 ;
input VAR5;
input VAR7;
input VAR1 ;
input VAR9 ;
VAR4 VAR6 (
.VAR3(VAR3),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR9(VAR9)
);
endmodule
module MODULE1 (
VAR3,
VAR2,
VAR8
);
output VAR3;
... | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/lib/verilog/core/utils/src/reg_grp.v | 4,671 | module MODULE1 #(parameter
VAR7 = 10,
VAR10 = 4
)
(
input VAR26,
input VAR30,
input [VAR7 -1:0] VAR29,
input [VAR5 -1:0] VAR12,
output reg VAR11,
output reg [VAR5 -1:0] VAR3,
output [VAR10 - 1 : 0] VAR15,
output [VAR10 - 1 : 0] VAR9,
output [VAR10 * (VAR7 - VAR4(VAR10)) -1:0] VAR22,
output [VAR10 * VAR5 -1:0] VAR21,
in... | mit |
BilkentCompGen/GateKeeper | FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/riffa/fifo.v | 7,489 | module MODULE1
parameter VAR19 = 32, parameter VAR28 = 1024, parameter VAR45 = 2
)
(
input VAR38, input VAR2,
input [VAR19-1:0] VAR3, input VAR5, output VAR33,
output [VAR19-1:0] VAR22, input VAR6, output VAR1 );
localparam VAR39 = 2**VAR8(VAR28);
localparam VAR42 = VAR14(VAR39);
wire [VAR45:0] VAR18;
wire VAR29;
wire ... | gpl-3.0 |
Elphel/x393_sata | host/gtx_comma_align.v | 6,321 | module MODULE1(
input wire rst,
input wire clk,
input wire [19:0] VAR16,
output wire [19:0] VAR10,
output wire VAR7,
output wire VAR1
);
reg [19:0] VAR11;
wire [38:0] VAR6;
always @ (posedge clk)
VAR11 <= VAR16;
assign VAR6 = {VAR16[18:0], VAR11};
wire [19:0] VAR15 [19:0];
wire [19:0] VAR18;
wire [19:0] VAR8;
reg [19:0... | gpl-3.0 |
ShepardSiegel/ocpi | coregen/dram_k7_mig12/mig_7series_v1_2/user_design/rtl/clocking/clk_ibuf.v | 4,415 | module MODULE1 #
(
parameter VAR12 = "VAR5",
parameter VAR2 = "VAR20"
)
(
input VAR13, input VAR16,
input VAR7,
output VAR10
);
wire VAR8;
generate
if (VAR12 == "VAR5") begin: VAR18
VAR9 #
(
.VAR19 (VAR2),
.VAR11 ("VAR1")
)
VAR3
(
.VAR21 (VAR13),
.VAR4 (VAR16),
.VAR15 (VAR8)
);
end else if (VAR12 == "VAR14") begin: VAR... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/or2b/sky130_fd_sc_hdll__or2b_2.v | 2,143 | module MODULE2 (
VAR1 ,
VAR6 ,
VAR8 ,
VAR7,
VAR3,
VAR4 ,
VAR5
);
output VAR1 ;
input VAR6 ;
input VAR8 ;
input VAR7;
input VAR3;
input VAR4 ;
input VAR5 ;
VAR2 VAR9 (
.VAR1(VAR1),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR5(VAR5)
);
endmodule
module MODULE2 (
VAR1 ,
VAR6 ,
VAR8
);
output VAR1... | apache-2.0 |
mammenx/pegasus | wxp/dgn/rtl/common/dd_sync.v | 3,460 | module MODULE1 #(VAR5 = 1, VAR8 = 2, VAR3 = 0)
(
clk,
VAR7,
VAR9,
VAR1
);
input clk;
input VAR7;
input [VAR5-1:0] VAR9;
output [VAR5-1:0] VAR1;
reg [VAR5-1:0] VAR6 [0:VAR8-1];
genvar VAR2;
generate
for(VAR2=0; VAR2<VAR8; VAR2++)
begin : VAR4
always@(posedge clk, negedge VAR7)
begin
if(~VAR7)
begin
VAR6[VAR2] <= VAR3;
e... | gpl-3.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/common/altera/ad_jesd_align.v | 4,236 | module MODULE1 (
VAR2,
VAR1,
VAR7,
VAR5,
VAR4);
input VAR2;
input [ 3:0] VAR1;
input [31:0] VAR7;
output VAR5;
output [31:0] VAR4;
reg [31:0] VAR3 = 'd0;
reg [ 3:0] VAR6 = 'd0;
reg VAR5 = 'd0;
reg [31:0] VAR4 = 'd0;
always @(posedge VAR2) begin
VAR3 <= VAR7;
if (VAR1 != 4'd0) begin
VAR6 <= VAR1;
end
VAR5 <= |VAR1;
if (... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/probec_p/sky130_fd_sc_hdll__probec_p.pp.blackbox.v | 1,277 | module MODULE1 (
VAR4 ,
VAR2 ,
VAR6,
VAR5,
VAR3 ,
VAR1
);
output VAR4 ;
input VAR2 ;
input VAR6;
input VAR5;
input VAR3 ;
input VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfsbp/sky130_fd_sc_ms__sdfsbp.symbol.v | 1,524 | module MODULE1 (
input VAR7 ,
output VAR2 ,
output VAR11 ,
input VAR10,
input VAR3 ,
input VAR9 ,
input VAR1
);
supply1 VAR8;
supply0 VAR6;
supply1 VAR5 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nor3b/sky130_fd_sc_ls__nor3b_2.v | 2,254 | module MODULE2 (
VAR2 ,
VAR3 ,
VAR10 ,
VAR7 ,
VAR4,
VAR9,
VAR6 ,
VAR1
);
output VAR2 ;
input VAR3 ;
input VAR10 ;
input VAR7 ;
input VAR4;
input VAR9;
input VAR6 ;
input VAR1 ;
VAR8 VAR5 (
.VAR2(VAR2),
.VAR3(VAR3),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR1(VAR1)
);
endmodule
module MODULE... | apache-2.0 |
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