repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
GLADICOS/SPACEWIRESYSTEMC | altera_work/spw_light/spw_light/synthesis/submodules/spw_light_connecting.v | 1,886 | module MODULE1 (
address,
clk,
VAR2,
VAR4,
VAR3
)
;
output [ 31: 0] VAR3;
input [ 1: 0] address;
input clk;
input VAR2;
input VAR4;
wire VAR5;
wire VAR1;
wire VAR6;
reg [ 31: 0] VAR3;
assign VAR5 = 1;
assign VAR6 = {1 {(address == 0)}} & VAR1;
always @(posedge clk or negedge VAR4)
begin
if (VAR4 == 0)
VAR3 <= 0;
end
el... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/or2/sky130_fd_sc_ms__or2.functional.v | 1,244 | module MODULE1 (
VAR1,
VAR2,
VAR4
);
output VAR1;
input VAR2;
input VAR4;
wire VAR5;
or VAR3 (VAR5, VAR4, VAR2 );
buf VAR6 (VAR1 , VAR5 );
endmodule | apache-2.0 |
ridecore/ridecore | src/fpga/system.v | 5,686 | module MODULE6(VAR39, VAR79, VAR4);
input wire VAR39;
output wire VAR79, VAR4;
wire VAR21;
wire VAR10;
wire VAR78, VAR68;
VAR52 VAR63 (.VAR18(VAR39),
.VAR38(VAR21));
VAR3 VAR75 (.VAR18(VAR10),
.VAR38(VAR79));
VAR3 VAR8 (.VAR18(VAR78),
.VAR38(VAR68));
VAR9 VAR15 ( .VAR39 (VAR21),
.VAR73 (1'b0),
.VAR29 (VAR10),
.VAR4 (VA... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_lsbuf_lh_isowell/sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell.functional.v | 1,373 | module MODULE1 (
VAR3,
VAR2
);
output VAR3;
input VAR2;
buf VAR1 (VAR3 , VAR2 );
endmodule | apache-2.0 |
jkanasu/utl | lab14eve16/fpga/j06serialadder.v | 3,356 | module MODULE1(VAR3,VAR2,VAR13,VAR14,VAR1,VAR12,clk,rst,VAR6,VAR10,VAR15);
output reg [3:0]VAR3;
output reg VAR2;
output reg VAR13; output reg VAR14, VAR1;
output reg [1:0]VAR12; input clk,rst;
input VAR6,VAR10,VAR15;
wire VAR4;
assign VAR4 = ( VAR12 == 3'd0) ? VAR15 : VAR1;
always@(posedge clk)
begin
VAR14 <= VAR6 ^ V... | apache-2.0 |
cambridgehackers/connectal | verilog/SyncReset.v | 3,112 | module MODULE1 (
VAR2,
VAR7,
VAR9
);
parameter VAR3 = 1 ;
input VAR7 ;
input VAR2 ;
output VAR9 ;
reg VAR4;
reg [VAR3:1] VAR6 ;
wire [VAR3+1:0] VAR1 = {VAR6, VAR4, ~ VAR8};
assign VAR9 = VAR6[VAR3] ;
always @( posedge VAR7 ) begin
if (VAR2 == VAR8)
begin
VAR4 <= VAR5 VAR8 ;
end
else
begin
VAR4 <= VAR5 ~ VAR8 ;
end
if (... | mit |
fbelavenuto/msx1fpga | src/audio/jt51/jt51_mod.v | 1,769 | module MODULE1(
input VAR5,
input VAR8,
input VAR6,
input VAR7,
input [2:0] VAR1,
output reg VAR9,
output reg VAR3,
output reg VAR11,
output reg VAR4,
output reg VAR2
);
reg [7:0] VAR10;
always @ begin
VAR9 = VAR5 | (VAR8&VAR10[5]);
VAR4 = (VAR8&(|VAR10[2:0])) | (VAR7&VAR10[3]);
VAR3 = VAR7 & VAR10[2];
VAR11 = VAR7 & (... | gpl-3.0 |
alexforencich/xfcp | lib/eth/rtl/axis_gmii_rx.v | 10,595 | module MODULE1 #
(
parameter VAR6 = 8,
parameter VAR1 = 0,
parameter VAR7 = 96,
parameter VAR15 = (VAR1 ? VAR7 : 0) + 1
)
(
input wire clk,
input wire rst,
input wire [VAR6-1:0] VAR5,
input wire VAR12,
input wire VAR9,
output wire [VAR6-1:0] VAR11,
output wire VAR13,
output wire VAR10,
output wire [VAR15-1:0] VAR8,
inp... | mit |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_mem/bsg_mem_1r1w_sync.v | 2,997 | module MODULE1 #(parameter VAR15(VAR24)
, parameter VAR15(VAR3)
, parameter VAR5=0
, parameter VAR10=VAR2(VAR3)
, parameter VAR23=0
, parameter VAR6=0
, parameter VAR25=0
)
(input VAR14
, input VAR12
, input VAR13
, input [VAR10-1:0] VAR9
, input [VAR11(VAR24, 1):0] VAR7
, input VAR1
, input [VAR10-1:0] VAR18
, output ... | bsd-3-clause |
bbrown1867/ObjectTracking | hw/sram_controller/sram_controller.v | 1,739 | module MODULE1(
input VAR13,
input VAR7,
input VAR11,
output [8:0] VAR3,
output [17:0] VAR15,
input [3:0] VAR17,
input [17:0] VAR2,
output [19:0] VAR18,
output VAR1,
inout [15:0] VAR4,
output VAR14,
output VAR8,
output VAR9,
output VAR16
);
wire VAR12;
wire [19:0] addr;
wire [15:0] din;
wire [15:0] dout;
assign din = {... | mit |
plyr0/snake-alteraDE2 | clk_25_2/synthesis/submodules/clock_25_2_altpll_0.v | 10,287 | module MODULE1
(
VAR6,
VAR8,
VAR1,
VAR3) ;
input VAR6;
input VAR8;
input [0:0] VAR1;
output [0:0] VAR3;
tri0 VAR6;
tri1 VAR8;
reg [0:0] VAR5;
reg [0:0] VAR2;
reg [0:0] VAR4;
wire VAR7;
wire VAR9;
wire VAR10; | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a22oi/sky130_fd_sc_ls__a22oi_1.v | 2,352 | module MODULE1 (
VAR2 ,
VAR11 ,
VAR3 ,
VAR6 ,
VAR10 ,
VAR5,
VAR8,
VAR4 ,
VAR1
);
output VAR2 ;
input VAR11 ;
input VAR3 ;
input VAR6 ;
input VAR10 ;
input VAR5;
input VAR8;
input VAR4 ;
input VAR1 ;
VAR7 VAR9 (
.VAR2(VAR2),
.VAR11(VAR11),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR4(VAR4),
.... | apache-2.0 |
gabesk/xmascard | hdl/lights.v | 6,061 | module MODULE1(
input clk,
input VAR6,
output VAR10,
output [2*12-1:0] VAR11
);
wire VAR24;
VAR15 VAR35(.VAR37(clk),
.VAR18(VAR24),
.VAR7(),
.VAR31());
wire VAR16;
reg [4:0] VAR23 = 0;
always @ (posedge VAR24) VAR23 <= {VAR23[3:0], VAR6};
assign VAR16 = VAR23[4];
reg [26:0] VAR21; VAR4 VAR21 = 0;
always @ (posedge VAR2... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/inv/sky130_fd_sc_hs__inv_8.v | 1,868 | module MODULE1 (
VAR2 ,
VAR1 ,
VAR3,
VAR6
);
output VAR2 ;
input VAR1 ;
input VAR3;
input VAR6;
VAR4 VAR5 (
.VAR2(VAR2),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR6(VAR6)
);
endmodule
module MODULE1 (
VAR2,
VAR1
);
output VAR2;
input VAR1;
supply1 VAR3;
supply0 VAR6;
VAR4 VAR5 (
.VAR2(VAR2),
.VAR1(VAR1)
);
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai211/gf180mcu_fd_sc_mcu7t5v0__oai211_2.behavioral.pp.v | 1,868 | module MODULE1( VAR5, VAR6, VAR9, VAR4, VAR1, VAR7, VAR3 );
input VAR9, VAR5, VAR4, VAR1;
inout VAR7, VAR3;
output VAR6;
VAR10 VAR8(.VAR5(VAR5),.VAR6(VAR6),.VAR9(VAR9),.VAR4(VAR4),.VAR1(VAR1),.VAR7(VAR7),.VAR3(VAR3));
VAR10 VAR2(.VAR5(VAR5),.VAR6(VAR6),.VAR9(VAR9),.VAR4(VAR4),.VAR1(VAR1),.VAR7(VAR7),.VAR3(VAR3)); | apache-2.0 |
DProvinciani/Arquitectura_TPF | Codigo_fuente/7-uart/debounce.v | 1,919 | module MODULE1
(
input wire clk, reset,
input wire VAR11,
output reg VAR12, VAR5
);
localparam [1:0]
VAR4 = 2'b00,
VAR8 = 2'b01,
VAR10 = 2'b10,
VAR2 = 2'b11;
localparam VAR1=21;
reg [VAR1-1:0] VAR7, VAR6;
reg [1:0] VAR9, VAR3;
always @(posedge clk, posedge reset)
if (reset)
begin
VAR9 <= VAR4;
VAR7 <= 0;
end
else
begin... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/einvp/sky130_fd_sc_hdll__einvp.behavioral.pp.v | 1,881 | module MODULE1 (
VAR12 ,
VAR2 ,
VAR8 ,
VAR13,
VAR1,
VAR11 ,
VAR3
);
output VAR12 ;
input VAR2 ;
input VAR8 ;
input VAR13;
input VAR1;
input VAR11 ;
input VAR3 ;
wire VAR9 ;
wire VAR10;
VAR6 VAR7 (VAR9 , VAR2, VAR13, VAR1 );
VAR6 VAR4 (VAR10, VAR8, VAR13, VAR1 );
notif1 VAR5 (VAR12 , VAR9, VAR10);
endmodule | apache-2.0 |
plindstroem/oh | elink/hdl/ecfg_if.v | 5,414 | module MODULE1 (
VAR46, VAR44, VAR1, VAR36, VAR48, VAR28,
VAR35, VAR12,
clk, reset, VAR26, VAR34, VAR32, VAR53, VAR37,
VAR20, VAR42
);
parameter VAR33 = 0; parameter VAR27 = 104;
parameter VAR7 = 32;
parameter VAR14 = 32;
parameter VAR22 = 12'h810;
input clk;
input reset;
input VAR26;
input [VAR27-1:0] VAR34;
output VA... | gpl-3.0 |
ShirmanXia/EE469SPRING16 | lab4/nios_system/synthesis/submodules/nios_system_nios2_qsys_0_cpu_debug_slave_sysclk.v | 7,061 | module MODULE1 (
clk,
VAR32,
VAR10,
VAR4,
VAR28,
VAR11,
VAR13,
VAR30,
VAR19,
VAR3,
VAR14,
VAR6,
VAR5,
VAR31,
VAR20,
VAR1,
VAR26,
VAR27,
VAR22
)
;
output [ 37: 0] VAR11;
output VAR13;
output VAR30;
output VAR19;
output VAR3;
output VAR14;
output VAR6;
output VAR5;
output VAR31;
output VAR20;
output VAR1;
output VAR26;
o... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nand2/sky130_fd_sc_hs__nand2.pp.symbol.v | 1,236 | module MODULE1 (
input VAR4 ,
input VAR5 ,
output VAR2 ,
input VAR1,
input VAR3
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/or4/sky130_fd_sc_hs__or4.behavioral.pp.v | 1,726 | module MODULE1 (
VAR10,
VAR3,
VAR6 ,
VAR4 ,
VAR1 ,
VAR12 ,
VAR13
);
input VAR10;
input VAR3;
output VAR6 ;
input VAR4 ;
input VAR1 ;
input VAR12 ;
input VAR13 ;
wire VAR7 ;
wire VAR5;
or VAR8 (VAR7 , VAR13, VAR12, VAR1, VAR4 );
VAR9 VAR11 (VAR5, VAR7, VAR10, VAR3);
buf VAR2 (VAR6 , VAR5 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/einvn/sky130_fd_sc_hd__einvn_2.v | 2,150 | module MODULE2 (
VAR9 ,
VAR4 ,
VAR3,
VAR7,
VAR2,
VAR5 ,
VAR8
);
output VAR9 ;
input VAR4 ;
input VAR3;
input VAR7;
input VAR2;
input VAR5 ;
input VAR8 ;
VAR1 VAR6 (
.VAR9(VAR9),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR8(VAR8)
);
endmodule
module MODULE2 (
VAR9 ,
VAR4 ,
VAR3
);
output VAR9 ;... | apache-2.0 |
nsauzede/cpu86 | mx_sdram/NIOS_sdram_controller_0.v | 23,868 | module MODULE1 (
clk,
rd,
VAR3,
wr,
VAR34,
VAR60,
VAR23,
VAR39,
VAR83,
VAR45
)
;
output VAR60;
output VAR23;
output VAR39;
output VAR83;
output [ 40: 0] VAR45;
input clk;
input rd;
input VAR3;
input wr;
input [ 40: 0] VAR34;
wire VAR60;
wire VAR23;
wire VAR39;
reg [ 1: 0] VAR59;
reg [ 40: 0] VAR6;
reg [ 40: 0] VAR16;
w... | gpl-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/top/mem_lipo_1p.v | 12,050 | module MODULE1 (
clk ,
VAR5 ,
VAR21 ,
VAR44 ,
VAR24 ,
VAR52 ,
VAR9 ,
VAR55 ,
VAR16 ,
VAR26 ,
VAR30 ,
VAR49
);
localparam VAR18 = 2'b00,
VAR20 = 2'b01,
VAR57 = 2'b10,
VAR39 = 2'b11;
input clk ; input VAR5 ;
input VAR21 ; input [7:0] VAR44 ; input [VAR10*32-1:0] VAR24 ;
input VAR52 ; input VAR9 ; input [1:0] VAR55 ; inpu... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlymetal6s6s/sky130_fd_sc_hs__dlymetal6s6s.functional.v | 1,757 | module MODULE1 (
VAR3,
VAR10,
VAR8 ,
VAR4
);
input VAR3;
input VAR10;
output VAR8 ;
input VAR4 ;
wire VAR5 ;
wire VAR6;
buf VAR7 (VAR5 , VAR4 );
VAR1 VAR2 (VAR6, VAR5, VAR3, VAR10);
buf VAR9 (VAR8 , VAR6 );
endmodule | apache-2.0 |
omicronns/studies-sys-rek | de1-soc/v/Line_Buffer1.v | 5,218 | module MODULE1 (
VAR18,
VAR12,
VAR13,
VAR17,
VAR21,
VAR3);
input VAR18;
input VAR12;
input [11:0] VAR13;
output [11:0] VAR17;
output [11:0] VAR21;
output [11:0] VAR3;
tri1 VAR18;
wire [11:0] VAR16;
wire [23:0] VAR20;
wire [11:0] VAR17 = VAR16[11:0];
wire [23:12] VAR5 = VAR20[23:12];
wire [11:0] VAR1 = VAR20[11:0];
wire... | mit |
iamllama/EE2020 | ee2020.srcs/sources_1/new/uart.v | 5,371 | module MODULE1(
input clk,
input VAR11,
output reg VAR6 = 0,
output reg [7:0] VAR3 = 0,
output VAR7, output reg VAR18 = 0 );
parameter VAR13 = 25000000; parameter VAR26 = 1152000;
parameter VAR28 = 16;
generate
if(VAR13<VAR26*VAR28) MODULE2 VAR34("VAR10 VAR25 VAR29 for VAR22 VAR26 VAR19 and VAR32");
if(VAR28<8 || ((VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/and4bb/sky130_fd_sc_hd__and4bb.symbol.v | 1,333 | module MODULE1 (
input VAR1,
input VAR3,
input VAR7 ,
input VAR4 ,
output VAR8
);
supply1 VAR9;
supply0 VAR6;
supply1 VAR5 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o2111a/sky130_fd_sc_lp__o2111a_2.v | 2,448 | module MODULE2 (
VAR7 ,
VAR8 ,
VAR2 ,
VAR12 ,
VAR3 ,
VAR4 ,
VAR11,
VAR1,
VAR5 ,
VAR10
);
output VAR7 ;
input VAR8 ;
input VAR2 ;
input VAR12 ;
input VAR3 ;
input VAR4 ;
input VAR11;
input VAR1;
input VAR5 ;
input VAR10 ;
VAR9 VAR6 (
.VAR7(VAR7),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR12(VAR12),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR11(... | apache-2.0 |
mcgodfrey/kinetic_sculpture | counter.v | 1,333 | module MODULE1 #(parameter VAR3 = 27) (
input wire clk,
input wire rst,
output reg [7:0] VAR2
);
reg[VAR3-1:0] VAR4, VAR1;
always @(VAR1) begin
VAR4 = VAR1 + 1'b1;
if (VAR1[VAR3-1] == 1)
VAR2 = ~VAR1[VAR3-2:VAR3-9];
end
else
VAR2 = VAR1[VAR3-2:VAR3-9];
end
always @(posedge clk) begin
if (rst == 1) begin
VAR1 <= 'b0;
en... | mit |
talshorer/verilog | fifo/fifo.v | 1,134 | module MODULE1(clk, rst, VAR4, VAR13, VAR1, VAR9, VAR6, VAR7, VAR11);
parameter VAR8 = 1;
parameter VAR3 = 1;
input clk, rst, VAR1, VAR9;
input[VAR8-1:0] VAR4;
output[VAR8-1:0] VAR13;
output VAR6, VAR7;
output[VAR3-1:0] VAR11;
reg[VAR8-1:0] VAR13;
reg[VAR3-1:0] VAR11;
reg[VAR3-1:0] VAR10, VAR12;
reg[VAR8-1:0] VAR2[VAR5... | gpl-2.0 |
redfern314/RFIDuino | verilog/getID_4digits.v | 2,061 | module MODULE1(
input enable,
input [44:0] VAR1,
output reg [15:0] VAR4
);
integer VAR2;
integer VAR3, VAR5;
always @(posedge enable) begin
VAR2 = VAR1[16:1];
if(VAR2>=9000) VAR4[15:12] = 9;
end
else if(VAR2>=8000) VAR4[15:12] = 8;
else if(VAR2>=7000) VAR4[15:12] = 7;
else if(VAR2>=6000) VAR4[15:12] = 6;
else if(VAR2>=... | gpl-3.0 |
theapi/de0-nano | keyboard/ps2clock.v | 1,114 | module MODULE1 (
input clk,
input VAR5,
output VAR3
);
reg [10:0] VAR4 = 0;
reg VAR1 = 0;
reg VAR2 = 0;
assign VAR3 = VAR2;
always @(VAR5) begin
if (!VAR5) begin
VAR1 <= 1;
end else begin
VAR1 <= 0;
end
end
always @(posedge clk) begin
if (VAR1) begin
VAR4 <= VAR4 + 11'b1;
end else begin
VAR4 <= 0;
end
end
always @(pose... | mit |
jmesmon/trifles | verilog/hw3/p17.v | 1,299 | module MODULE3(output VAR20, VAR18, input VAR14, VAR6, VAR26, clk);
wire [3:0]VAR7;
nand VAR8(VAR7[0], VAR6, VAR7[1], VAR7[3]),
VAR25(VAR7[1], VAR7[0], clk, VAR14),
VAR21(VAR7[2], VAR7[1], clk, VAR7[3]),
VAR2(VAR7[3], VAR26, VAR7[2], VAR14);
nand VAR16(VAR20, VAR7[1], VAR6, VAR18),
VAR1(VAR18, VAR7[2], VAR20, VAR14);
e... | gpl-3.0 |
khldragon/Sora | FPGA/MIMO/rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/Sora_FRL_STATUS_encoder.v | 4,113 | module MODULE1(
input clk,
output VAR6,
input VAR13,
input VAR14,
input VAR10,
input VAR11
);
reg [2:0] counter;
reg VAR4;
reg [1:0] VAR7;
parameter VAR12 = 2'b00;
parameter VAR2 = 2'b01;
parameter VAR3 = 2'b10;
parameter VAR1 = 2'b11;
parameter VAR15 = 8'b00000000;
parameter VAR5 = 8'b00110011;
parameter VAR8 = 8'b000... | bsd-2-clause |
linuxbest/lzs | encode/rtl/verilog/encode_out.v | 2,556 | module MODULE1(
VAR3, VAR1, VAR2,
clk, rst, VAR9, VAR5, VAR11, VAR4,
VAR15
);
input clk, rst, VAR9;
input VAR5, VAR11;
input [12:0] VAR4;
input [3:0] VAR15;
output [15:0] VAR3;
output VAR1;
output VAR2;
reg [15:0] VAR3;
reg VAR2;
reg VAR1;
reg [3:0] VAR12;
reg [12:0] VAR13;
reg VAR10;
always @(VAR15 or VAR4 or VAR5)
be... | gpl-2.0 |
secworks/gcm | src/rtl/gcm.v | 11,237 | module MODULE1(
input wire clk,
input wire VAR34,
input wire VAR26,
input wire VAR94,
input wire [7 : 0] address,
input wire [31 : 0] VAR86,
output wire [31 : 0] VAR95
);
localparam VAR50 = 8'h00;
localparam VAR38 = 8'h01;
localparam VAR78 = 8'h02;
localparam VAR87 = 8'h08;
localparam VAR51 = 0;
localparam VAR48 = 1;
l... | bsd-2-clause |
olgirard/opengfx430 | core/rtl/verilog/interfaces/ogfx_if_lt24.v | 41,041 | module MODULE1 (
VAR116 , VAR176 ,
VAR34 , VAR147 , VAR20 , VAR151 , VAR124 ,
VAR158 , VAR115 ,
VAR138 , VAR92 , VAR83 , VAR39 , VAR91 , VAR168 , VAR50 , VAR19 , VAR75 ,
VAR5 , VAR8 , VAR57 , VAR88 , VAR61 , VAR67 ,
VAR169 , VAR60 , VAR64 , VAR129 , VAR139 );
parameter [14:0] VAR117 = 15'h0280 ;
input VAR116 ; input VA... | bsd-3-clause |
AmeerAbdelhadi/Indirectly-Indexed-2D-Binary-Content-Addressable-Memory-BCAM | setram.v | 8,400 | module MODULE1
wire [1 :0] VAR18 = VAR24[1 :0];
wire [2 :0] VAR9 = VAR24[4 :2];
wire [4 :0] VAR16 = VAR24[4 :0];
wire [VAR30(VAR31)+4:0] VAR10 = VAR24[VAR30(VAR31)+9:5];
reg [31:0] VAR19;
always @
for (VAR13=0;VAR13<32;VAR13=VAR13+1)
VAR33[VAR13] = (VAR4[VAR13*9 +: 9] == VAR7) & !(VAR19[VAR13]) & VAR5[VAR13];
always @(... | bsd-3-clause |
jvesely/verilog_ALU | alu.v | 1,315 | module MODULE1(
input clk,
input reset,
input [31:0] VAR2, input [31:0] VAR10, input [1:0] VAR1,
output [31:0] VAR9,
output VAR3,
output VAR5 );
reg [31:0] VAR4;
reg VAR11 = 1'b0;
reg [1:0] VAR14 = VAR7;
always @(posedge clk && reset) begin
VAR14 <= VAR12;
end
assign VAR5 = ((VAR14 == VAR12) && !reset);
assign VAR3 = (... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a31oi/sky130_fd_sc_lp__a31oi_4.v | 2,350 | module MODULE1 (
VAR11 ,
VAR5 ,
VAR7 ,
VAR3 ,
VAR2 ,
VAR8,
VAR4,
VAR9 ,
VAR1
);
output VAR11 ;
input VAR5 ;
input VAR7 ;
input VAR3 ;
input VAR2 ;
input VAR8;
input VAR4;
input VAR9 ;
input VAR1 ;
VAR6 VAR10 (
.VAR11(VAR11),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR... | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_misc/bsg_mul_array_row.v | 2,315 | module MODULE1 #(parameter VAR4(VAR3)
, parameter VAR4(VAR31)
, parameter VAR4(VAR33))
(
input VAR34
, input VAR18
, input VAR36
, input [VAR3-1:0] VAR7
, input [VAR3-1:0] VAR20
, input [VAR3-1:0] VAR12
, input VAR8
, input [VAR31:0] VAR13
, output logic [VAR3-1:0] VAR30
, output logic [VAR3-1:0] VAR29
, output logic [... | bsd-3-clause |
scalable-networks/ext | uhd/fpga/usrp2/control_lib/setting_reg.v | 1,202 | module MODULE1
parameter VAR4 = 32,
parameter VAR3=32'd0)
(input clk, input rst, input VAR1, input wire [7:0] addr,
input wire [31:0] in, output reg [VAR4-1:0] out, output reg VAR5);
always @(posedge clk)
if(rst)
begin
out <= VAR3;
VAR5 <= 1'b0;
end
else
if(VAR1 & (VAR2==addr))
begin
out <= in;
VAR5 <= 1'b1;
end
else
V... | gpl-2.0 |
bluespec/Flute | builds/AWSteria_Core_Flute_RV64_Linux/Verilog_RTL_PLATFORM_AWSF1/mkDM_CSR_Tap.v | 7,838 | module MODULE1(VAR9,
VAR13,
VAR57,
VAR50,
VAR65,
VAR69,
VAR8,
VAR37,
VAR4,
VAR70,
VAR7,
VAR14,
VAR33,
VAR61,
VAR31,
VAR26,
VAR3);
input VAR9;
input VAR13;
input VAR57;
output [76 : 0] VAR50;
output VAR65;
input [64 : 0] VAR69;
input VAR8;
output VAR37;
input [76 : 0] VAR4;
input VAR70;
output VAR7;
input VAR14;
output ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/clkdlyinv3sd3/sky130_fd_sc_hs__clkdlyinv3sd3.functional.pp.v | 1,768 | module MODULE1 (
VAR4 ,
VAR9 ,
VAR1,
VAR6
);
output VAR4 ;
input VAR9 ;
input VAR1;
input VAR6;
wire VAR10 ;
wire VAR7;
not VAR5 (VAR10 , VAR9 );
VAR2 VAR8 (VAR7, VAR10, VAR1, VAR6);
buf VAR3 (VAR4 , VAR7 );
endmodule | apache-2.0 |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | bin_Erosion_Operation/ip/Erosion/acl_fp_cos.v | 1,523 | module MODULE1 (
enable,
VAR7,
VAR2,
VAR3,
VAR12);
input enable;
input VAR7;
input VAR3;
input [31:0] VAR2;
output [31:0] VAR12;
wire [31:0] VAR1;
wire [31:0] VAR12 = VAR1[31:0];
VAR8 VAR14(
.VAR4(VAR7),
.reset(~VAR3),
.enable(enable),
.VAR6(VAR2[31]),
.VAR11(VAR2[30:23]),
.VAR13(VAR2[22:0]),
.VAR10(VAR1[31]),
.VAR9(VA... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/invz/gf180mcu_fd_sc_mcu9t5v0__invz_1.behavioral.pp.v | 1,246 | module MODULE1( VAR3, VAR7, VAR1, VAR6, VAR8 );
input VAR3, VAR1;
inout VAR6, VAR8;
output VAR7;
VAR4 VAR5(.VAR3(VAR3),.VAR7(VAR7),.VAR1(VAR1),.VAR6(VAR6),.VAR8(VAR8));
VAR4 VAR2(.VAR3(VAR3),.VAR7(VAR7),.VAR1(VAR1),.VAR6(VAR6),.VAR8(VAR8)); | apache-2.0 |
balanx/laotzu | RTL/stream_asyn_fifo_controller.v | 4,186 | module MODULE1 #(
parameter VAR14 = 1, parameter VAR11 = 6,
parameter [VAR11:0] VAR31 = 44, parameter [VAR11:0] VAR25 = 0
) (
input VAR22 ,
input VAR12 ,
input [2:0] VAR3 , output VAR38 ,
output VAR30 ,
output [VAR11:0] VAR5 ,
input VAR10 ,
input VAR28 ,
input VAR35 ,
output VAR9 ,
output VAR2 ,
output [VAR11:0] VAR27 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlymetal6s6s/sky130_fd_sc_hd__dlymetal6s6s_1.v | 2,160 | module MODULE2 (
VAR8 ,
VAR5 ,
VAR4,
VAR7,
VAR6 ,
VAR2
);
output VAR8 ;
input VAR5 ;
input VAR4;
input VAR7;
input VAR6 ;
input VAR2 ;
VAR3 VAR1 (
.VAR8(VAR8),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR2(VAR2)
);
endmodule
module MODULE2 (
VAR8,
VAR5
);
output VAR8;
input VAR5;
supply1 VAR4;
supply0 VAR7;... | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/common/ad_addsub.v | 4,301 | module MODULE1 (
clk,
VAR14,
VAR4,
out,
VAR8
);
parameter VAR2 = 32;
parameter VAR13 = 32'h1;
parameter VAR5 = 0;
localparam VAR15 = 0;
localparam VAR9 = 1;
input clk;
input [(VAR2-1):0] VAR14;
input [(VAR2-1):0] VAR4;
output [(VAR2-1):0] out;
input VAR8;
reg [(VAR2-1):0] out = 'b0;
reg [VAR2:0] VAR11 = 'b0;
reg [VAR2:... | gpl-3.0 |
Ricky-Gong/LegoCar | DE0-Nano/DE0Course/db/ip/NIOS_Sys/submodules/NIOS_Sys_nios2_qsys_0_jtag_debug_module_sysclk.v | 7,219 | module MODULE1 (
clk,
VAR11,
VAR30,
VAR12,
VAR20,
VAR27,
VAR28,
VAR14,
VAR16,
VAR3,
VAR1,
VAR26,
VAR15,
VAR13,
VAR2,
VAR5,
VAR19,
VAR8,
VAR18
)
;
output [ 37: 0] VAR27;
output VAR28;
output VAR14;
output VAR16;
output VAR3;
output VAR1;
output VAR26;
output VAR15;
output VAR13;
output VAR2;
output VAR5;
output VAR19;
o... | gpl-2.0 |
mfkiwl/parallella-platform | hdl/fifo_empty_block.v | 2,747 | module MODULE1 (
VAR7, VAR3, VAR11,
reset, VAR2, VAR10, VAR8
);
parameter VAR4 = 2;
input reset;
input VAR2;
input [VAR4:0] VAR10; input VAR8;
output VAR7;
output [VAR4-1:0] VAR3;
output [VAR4:0] VAR11;
reg [VAR4:0] VAR11;
reg [VAR4:0] VAR6;
reg VAR7;
wire VAR9;
wire [VAR4:0] VAR5;
wire [VAR4:0] VAR1;
always @(posedge ... | gpl-3.0 |
DougFirErickson/parallella-hw | fpga/old/emon/dv/dv_emon.v | 4,044 | module MODULE1();
parameter VAR1 = 32;
reg clk;
reg reset;
reg VAR18;
reg [19:0] VAR10;
reg [31:0] VAR19;
reg VAR9;
reg [1:0] VAR3;
reg VAR11;
reg VAR16; reg VAR8; reg VAR15; reg VAR4; reg VAR14; reg VAR2; reg VAR5; reg VAR6; reg VAR12; reg VAR7; reg VAR17; reg VAR13;
begin
begin
begin
begin
end
begin
begin | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a22o/sky130_fd_sc_ms__a22o_4.v | 2,339 | module MODULE2 (
VAR4 ,
VAR6 ,
VAR7 ,
VAR9 ,
VAR2 ,
VAR5,
VAR8,
VAR10 ,
VAR1
);
output VAR4 ;
input VAR6 ;
input VAR7 ;
input VAR9 ;
input VAR2 ;
input VAR5;
input VAR8;
input VAR10 ;
input VAR1 ;
VAR3 VAR11 (
.VAR4(VAR4),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/xor3/gf180mcu_fd_sc_mcu7t5v0__xor3_2.behavioral.v | 2,510 | module MODULE1( VAR7, VAR1, VAR6, VAR4 );
input VAR1, VAR7, VAR6;
output VAR4;
VAR2 VAR5(.VAR7(VAR7),.VAR1(VAR1),.VAR6(VAR6),.VAR4(VAR4));
VAR2 VAR3(.VAR7(VAR7),.VAR1(VAR1),.VAR6(VAR6),.VAR4(VAR4)); | apache-2.0 |
varunnagpaal/Digital-Hardware-Modelling | xilinx-vivado/gcd_snickerdoodle/gcd_snickerdoodle.cache/ip/2018.2/45a3d2c626abd576/gcd_zynq_snick_gcd_0_0_stub.v | 2,702 | module MODULE1(VAR2,
VAR6, VAR8, VAR15, VAR14,
VAR9, VAR12, VAR19, VAR13,
VAR16, VAR17, VAR18,
VAR7, VAR5, VAR3, VAR11,
VAR4, VAR1, VAR10, interrupt)
;
input [5:0]VAR2;
input VAR6;
output VAR8;
input [31:0]VAR15;
input [3:0]VAR14;
input VAR9;
output VAR12;
output [1:0]VAR19;
output VAR13;
input VAR16;
input [5:0]VAR17;... | mit |
efabless/openlane | designs/jpeg_encoder/src/jpeg_rle.v | 5,865 | module MODULE1(clk, rst, VAR29, VAR9, din, VAR2, VAR37, VAR6, VAR50, VAR47);
input clk; input rst; input VAR29; input VAR9;
input [11:0] din;
output [ 3:0] VAR2; output [ 3:0] VAR37; output [11:0] VAR6; output VAR50; output VAR47;
wire [ 3:0] VAR7, VAR10, VAR45, VAR3, VAR39;
wire [ 3:0] VAR15, VAR35, VAR49, VAR33, VAR4... | apache-2.0 |
BilkentCompGen/GateKeeper | FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/riffa/ram_2clk_1w_1r.v | 3,318 | module MODULE1
parameter VAR5 = 32,
parameter VAR10 = 1024
)
(
input VAR12,
input VAR4,
input VAR13,
input [VAR2(VAR10)-1:0] VAR6,
input [VAR2(VAR10)-1:0] VAR11,
input [VAR5-1:0] VAR9,
output [VAR5-1:0] VAR3
);
localparam VAR1 = VAR2(VAR10);
reg [VAR5-1:0] VAR7 [VAR10-1:0];
reg [VAR5-1:0] VAR8;
assign VAR3 = VAR8;
alwa... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/muxb4to1/sky130_fd_sc_hdll__muxb4to1_4.v | 2,219 | module MODULE1 (
VAR6 ,
VAR2 ,
VAR8 ,
VAR5,
VAR9,
VAR1 ,
VAR4
);
output VAR6 ;
input [3:0] VAR2 ;
input [3:0] VAR8 ;
input VAR5;
input VAR9;
input VAR1 ;
input VAR4 ;
VAR7 VAR3 (
.VAR6(VAR6),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR4(VAR4)
);
endmodule
module MODULE1 (
VAR6,
VAR2,
VAR8
);
o... | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/cmp/rtl/ff_dram_sc_bank3.v | 25,507 | module MODULE1(
VAR24, VAR33,
VAR32, VAR5,
VAR41, VAR6,
VAR34, VAR10,
VAR48, VAR42, VAR15,
VAR27, VAR22,
VAR21, VAR2,
VAR12, VAR47,
VAR11, VAR16, VAR51,
VAR29, VAR30, VAR20,
VAR46, VAR23,
VAR37, VAR40, VAR43,
VAR18, VAR7, VAR31,
VAR4, VAR44, VAR8,
VAR36, VAR14,
VAR17, VAR28,
VAR1, VAR3, VAR38, VAR35
);
input [127:0] VA... | gpl-2.0 |
SymbiFlow/yosys | techlibs/intel/cycloneive/arith_map.v | 3,235 | module MODULE2
(input VAR24,
input VAR36,
input VAR40,
output VAR27,
output VAR35);
wire VAR24;
wire VAR36;
wire VAR27;
wire VAR40;
wire VAR35;
wire VAR7;
assign VAR7 = 1'b1;
VAR30 VAR2 (.VAR28(VAR35),
.VAR26(VAR24),
.VAR3(VAR36),
.VAR29(VAR40),
.VAR14(VAR7));
VAR30 VAR43 (.VAR28(VAR27),
.VAR26(VAR40),
.VAR3(VAR36),
... | isc |
lfmunoz/vhdl | ip_blocks/axi_to_stellarip/vivado_prj/vivado_prj.srcs/sources_1/ip/axi_traffic_gen_0/axi_traffic_gen_v2_0/hdl/src/verilog/axi_traffic_gen_v2_0_sharedram_wrap.v | 9,077 | module MODULE1 #
(
parameter VAR63 = "VAR12",
parameter VAR26 = 32 ,
parameter VAR21 = 32 ,
parameter VAR41 = "VAR11"
) (
input VAR27 ,
input VAR33 ,
input [10:0] VAR47 ,
input [VAR21/8-1:0] VAR51 ,
input [VAR21-1:0] VAR56 ,
output [VAR21-1:0] VAR37 ,
input [15:0] VAR30 ,
input [10:0] VAR38 ,
input [7:0] VAR54 ,
input ... | mit |
shailcoolboy/Warp-Trinity | PlatformSupport/Deprecated/pcores/radio_bridge_v1_04_a/hdl/verilog/radio_bridge.v | 6,499 | module MODULE1
(
VAR15,
VAR59,
VAR20,
VAR25,
VAR4,
VAR30,
VAR73,
VAR77,
VAR81,
VAR53,
VAR11,
VAR22,
VAR13,
VAR41,
VAR48,
VAR75,
VAR34,
VAR28,
VAR44,
VAR58,
VAR9,
VAR17,
VAR23,
VAR8,
VAR57,
VAR49,
VAR10,
VAR74,
VAR33,
VAR21,
VAR66,
VAR29,
VAR47,
VAR56,
VAR39,
VAR54,
VAR40,
VAR69,
VAR62,
VAR36,
VAR1,
VAR50,
VAR43,
VAR83,... | bsd-2-clause |
ShepardSiegel/ocpi | coregen/dram_v6_mig39_2/mig_39_2/example_design/rtl/ui/ui_top.v | 13,780 | module MODULE1 #
(
parameter VAR69 = 100,
parameter VAR25 = 256,
parameter VAR62 = 32,
parameter VAR66 = 3,
parameter VAR71 = 12,
parameter VAR11 = 5,
parameter VAR19 = "VAR9",
parameter VAR43 = "VAR9",
parameter VAR61 = "VAR29",
parameter VAR33 = 4,
parameter VAR49 = 2,
parameter VAR14 = 16,
parameter VAR54 = "VAR47"
... | lgpl-3.0 |
mistryalok/Zedboard | learning/training/Microsystem/les6/ip_repo/myip_1.0/hdl/myip_v1_0_S01_AXI.v | 21,615 | module MODULE1 #
(
parameter integer VAR29 = 1,
parameter integer VAR19 = 32,
parameter integer VAR51 = 6,
parameter integer VAR18 = 0,
parameter integer VAR58 = 0,
parameter integer VAR43 = 0,
parameter integer VAR45 = 0,
parameter integer VAR48 = 0
)
(
input wire VAR47,
input wire VAR16,
input wire [VAR29-1 : 0] VAR7... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/decap/sky130_fd_sc_hs__decap.blackbox.v | 1,155 | module MODULE1 ();
supply1 VAR1;
supply0 VAR2;
endmodule | apache-2.0 |
vad-rulezz/megabot | minsoc/rtl/verilog/ethmac/rtl/verilog/eth_fifo.v | 6,267 | module MODULE1 (VAR16, VAR7, clk, reset, write, read, VAR21,
VAR15, VAR3, VAR20, VAR1, VAR26);
parameter VAR24 = 32;
parameter VAR27 = 8;
parameter VAR9 = 4;
input clk;
input reset;
input write;
input read;
input VAR21;
input [VAR24-1:0] VAR16;
output [VAR24-1:0] VAR7;
output VAR15;
output VAR3;
output VAR20;
output VA... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/or3/sky130_fd_sc_hvl__or3.functional.v | 1,269 | module MODULE1 (
VAR3,
VAR1,
VAR4,
VAR5
);
output VAR3;
input VAR1;
input VAR4;
input VAR5;
wire VAR7;
or VAR2 (VAR7, VAR4, VAR1, VAR5 );
buf VAR6 (VAR3 , VAR7 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nand3b/sky130_fd_sc_hdll__nand3b.behavioral.pp.v | 1,991 | module MODULE1 (
VAR12 ,
VAR6 ,
VAR16 ,
VAR5 ,
VAR4,
VAR3,
VAR7 ,
VAR8
);
output VAR12 ;
input VAR6 ;
input VAR16 ;
input VAR5 ;
input VAR4;
input VAR3;
input VAR7 ;
input VAR8 ;
wire VAR9 ;
wire VAR2 ;
wire VAR10;
not VAR15 (VAR9 , VAR6 );
nand VAR13 (VAR2 , VAR16, VAR9, VAR5 );
VAR14 VAR1 (VAR10, VAR2, VAR4, VAR3);
b... | apache-2.0 |
zeruniverse/pipelined_CPU | .v source code/pipedereg.v | 1,585 | module MODULE1(VAR12,VAR26,VAR7,VAR15,VAR18,VAR1,VAR17,VAR16,VAR23,VAR13,VAR5,VAR25,VAR4,clk,rst,VAR21,VAR8,VAR10,VAR11,VAR22,VAR19,VAR9,VAR3,VAR24,VAR20,VAR2,VAR14,VAR6);
input wire clk, rst,VAR12,VAR26,VAR7,VAR18,VAR13,VAR5;
input wire [3:0] VAR15;
input wire [7:0] VAR25;
input wire [31:0] VAR1,VAR17,VAR16;
input wir... | gpl-3.0 |
leekeith/DEVBOX | Dev_Box_HW/soc_system/synthesis/submodules/soc_system_vga_rgb_resampler.v | 7,603 | module MODULE1 (
clk,
reset,
VAR12,
VAR8,
VAR9,
VAR19,
VAR7,
VAR4,
VAR1,
VAR16,
VAR2,
VAR5,
VAR21,
VAR11
);
parameter VAR3 = 31;
parameter VAR14 = 29;
parameter VAR18 = 1;
parameter VAR6 = 1;
parameter VAR13 = 10'h3FF;
input clk;
input reset;
input [VAR3:0] VAR12;
input VAR8;
input VAR9;
input [VAR18:0] VAR19;
input VA... | gpl-2.0 |
chriswynnyk/american-put-verilog | american_put_stratix/src/addrdecode.v | 6,901 | module MODULE1(
clk,
VAR38,
VAR19,
VAR21,
VAR1,
VAR31,
VAR5,
VAR18,
VAR20,
VAR29,
VAR28,
VAR4,
VAR25,
VAR32,
VAR2,
VAR6,
VAR15,
VAR12,
VAR17,
VAR37,
VAR24,
VAR30,
VAR10,
VAR13,
VAR23,
VAR7,
VAR39,
VAR27,
VAR3,
VAR33,
VAR34,
VAR26,
VAR22,
VAR14,
sel,
VAR35
);
input clk;
input [13:0]VAR38;
output [10:0]VAR19;
output [10:... | apache-2.0 |
bluespec/Flute | src_SSITH_P2/xilinx_ip/hdl/mkBranch_Predictor.v | 24,978 | module MODULE1(VAR71,
VAR122,
VAR51,
VAR14,
VAR16,
VAR91,
VAR47,
VAR80,
VAR24,
VAR60,
VAR61,
VAR54,
VAR130,
VAR126,
VAR87,
VAR132);
input VAR71;
input VAR122;
input VAR51;
output VAR14;
input [63 : 0] VAR16;
input VAR91;
output VAR47;
input VAR80;
input [31 : 0] VAR24;
output [63 : 0] VAR60;
input [63 : 0] VAR61;
input... | apache-2.0 |
Tao-J/nexys3MIPSSoC | alu.v | 1,810 | module MODULE1(
input [31:0] VAR15,
input [31:0] VAR2,
input [2:0] VAR11,
output [31:0] VAR7,
output VAR9,
output reg VAR14
);
wire [31:0] VAR6,VAR4,VAR13,VAR16,VAR3,VAR1;
reg [31:0] VAR10;
parameter VAR8 = 32'h00000001,VAR12=32'h00000000;
assign VAR6 = VAR15&VAR2;
assign VAR4 = VAR15|VAR2;
assign VAR13 = VAR15+VAR2;
a... | gpl-3.0 |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/ip/Gaussian_Filter/acl_fp_log_s5.v | 146,875 | module MODULE1
(
VAR14,
VAR9,
VAR2,
VAR3,
VAR10,
VAR6) ;
input VAR14;
input VAR9;
input VAR2;
input [31:0] VAR3;
input [4:0] VAR10;
output [31:0] VAR6;
tri0 VAR14;
tri1 VAR9;
tri0 VAR2;
reg [0:0] VAR11;
reg [31:0] VAR8;
wire [5:0] VAR12;
wire VAR5;
wire [15:0] VAR1;
wire [191:0] VAR13;
wire [4:0] VAR7;
wire [159:0] VAR... | mit |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_mm_bridge_1/altera_avalon_mm_bridge_171/synth/altera_avalon_mm_bridge.v | 11,685 | module MODULE1
parameter VAR7 = 32,
parameter VAR1 = 8,
parameter VAR16 = 2,
parameter VAR5 = 10,
parameter VAR26 = 1,
parameter VAR23 = 1,
parameter VAR55 = 1,
parameter VAR4 = VAR7 / VAR1
)
(
input clk,
input reset,
output VAR10,
output [VAR7-1:0] VAR42,
output VAR30,
output [VAR16-1:0] VAR12,
input [VAR26-1:0] VAR49... | mit |
DougFirErickson/parallella-hw | fpga/old/projects/parallella_7020_hdmi/parallella_7020_hdmi.srcs/sources_1/imports/parallella_7020_hdmi/system_stub.v | 20,813 | module MODULE1
(
VAR55,
VAR33,
VAR32,
VAR35,
VAR68,
VAR36,
VAR92,
VAR9,
VAR99,
VAR22,
VAR49,
VAR98,
VAR93,
VAR24,
VAR113,
VAR15,
VAR20,
VAR38,
VAR47,
VAR108,
VAR103,
VAR65,
VAR100,
VAR3,
VAR101,
VAR75,
VAR114,
VAR67,
VAR72,
VAR88,
VAR110,
VAR2,
VAR104,
VAR116,
VAR62,
VAR48,
VAR97,
VAR79,
VAR94,
VAR87,
VAR28,
VAR63,
VAR... | gpl-3.0 |
zeruniverse/pipelined_CPU | .v source code/display.v | 1,927 | module MODULE1(
input wire clk,
input wire [15:0] VAR2,output reg [ 3:0] VAR1, output reg [ 7:0] VAR3);reg [3:0] VAR4 = 4'b0;
reg [15:0] VAR5 = 15'b0;
always @(posedge clk) begin
case (VAR5[15:14])
2'b00 : begin
VAR1 <= 4'b1110;
VAR4 <= VAR2[3:0];
end
2'b01 : begin
VAR1 <= 4'b1101;
VAR4 <= VAR2[7:4];
end
2'b10 : begin
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/maj3/sky130_fd_sc_hs__maj3_1.v | 2,047 | module MODULE2 (
VAR4 ,
VAR5 ,
VAR7 ,
VAR2 ,
VAR3,
VAR8
);
output VAR4 ;
input VAR5 ;
input VAR7 ;
input VAR2 ;
input VAR3;
input VAR8;
VAR6 VAR1 (
.VAR4(VAR4),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR8(VAR8)
);
endmodule
module MODULE2 (
VAR4,
VAR5,
VAR7,
VAR2
);
output VAR4;
input VAR5;
input VAR7;
in... | apache-2.0 |
brandonpelfrey/ice40-nes | src/top.v | 3,643 | module MODULE1(
input VAR51,
output [7:0] VAR89,
output VAR14,
output VAR74,
output VAR49,
output VAR59,
output VAR2,
output VAR35,
output VAR15,
input VAR8,
output VAR79,
output VAR63,
output VAR67,
output VAR6,
output VAR40,
output VAR61,
output [1:0] VAR70,
output [11:0] VAR46,
inout [7:0] VAR18
);
wire VAR55;
wire ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a2111oi/sky130_fd_sc_hd__a2111oi_1.v | 2,461 | module MODULE2 (
VAR9 ,
VAR4 ,
VAR6 ,
VAR2 ,
VAR12 ,
VAR1 ,
VAR8,
VAR11,
VAR10 ,
VAR3
);
output VAR9 ;
input VAR4 ;
input VAR6 ;
input VAR2 ;
input VAR12 ;
input VAR1 ;
input VAR8;
input VAR11;
input VAR10 ;
input VAR3 ;
VAR7 VAR5 (
.VAR9(VAR9),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR12(VAR12),
.VAR1(VAR1),
.VAR8(V... | apache-2.0 |
olajep/oh | src/adi/hdl/library/common/ad_tdd_control.v | 23,849 | module MODULE1#(
parameter integer VAR84 = 0,
parameter integer VAR38 = 0) (
input clk,
input rst,
input VAR119,
input VAR16,
input VAR93,
input VAR61,
input [ 7:0] VAR105,
input [23:0] VAR2,
input [23:0] VAR26,
input [23:0] VAR40,
input [23:0] VAR106,
input [23:0] VAR86,
input [23:0] VAR68,
input [23:0] VAR51,
input [... | mit |
deepakcu/maestro | fpga/DE4_Ethernet_0/pll_125_bb.v | 10,984 | module MODULE1 (
VAR2,
VAR1);
input VAR2;
output VAR1;
endmodule | apache-2.0 |
monotone-RK/FACE | IEICE-Trans/data_compression/8-way_2-tree/src/riffa/fifo_packer_64.v | 5,060 | module MODULE1 (
input VAR5,
input VAR23,
input [63:0] VAR11, input [1:0] VAR13, input VAR18, input VAR19, input VAR22, output [63:0] VAR3, output VAR2, output VAR16, output VAR14, output VAR9 );
reg [1:0] VAR7=0, VAR7=0;
reg VAR4=0, VAR4=0;
reg VAR20=0, VAR20=0;
reg VAR6=0, VAR6=0;
reg VAR8=0, VAR8=0;
reg [95:0] VAR1=... | mit |
fpgaminer/sha1_collider | hdl/main_pll.v | 5,684 | module MODULE1
( input VAR3,
output VAR2
);
VAR6 VAR37
(.VAR21 (VAR31),
.VAR29 (VAR3));
wire VAR35;
wire VAR14;
wire [7:0] VAR32;
wire VAR12;
wire VAR20;
wire VAR18;
VAR9
.VAR16 (10),
.VAR30 (20),
.VAR27 ("VAR34"),
.VAR44 (10.0),
.VAR5 ("VAR26"),
.VAR10 ("VAR26"),
.VAR17 ("VAR11"),
.VAR47 (0),
.VAR24 ("VAR34"))
VAR7
(.... | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/sparc/spu/rtl/spu.v | 18,688 | module MODULE1 (VAR29,VAR90,VAR107,VAR12,VAR57,VAR106,
VAR5,
VAR35,
VAR71,
VAR159,
VAR122,
VAR129,
VAR83,
VAR154,
VAR10,
VAR110,
VAR25,
VAR126,
VAR78,
VAR45,
VAR116,
VAR157,
VAR68,
VAR141,
VAR143,
VAR144,
VAR44,
VAR6,
VAR147,
VAR16,
VAR70,
VAR153,
VAR76,
VAR54,
VAR115,
VAR61,
VAR24,
VAR99,
VAR156,
VAR77,
VAR145,
VAR31,... | gpl-2.0 |
secworks/chacha | src/rtl/chacha.v | 9,403 | module MODULE1(
input wire clk,
input wire VAR64,
input wire VAR21,
input wire VAR38,
input wire [7 : 0] addr,
input wire [31 : 0] VAR63,
output wire [31 : 0] VAR20
);
localparam VAR58 = 8'h00;
localparam VAR4 = 8'h01;
localparam VAR36 = 8'h02;
localparam VAR49 = 8'h08;
localparam VAR11 = 0;
localparam VAR5 = 1;
localp... | bsd-2-clause |
zhaishaomin/ring_network-based-multicore- | communication_assist/m_donwload.v | 4,912 | module MODULE1( clk,
rst,
VAR20,
VAR8,
VAR10,
VAR12,
VAR5,
VAR14,
VAR11
);
input clk;
input rst;
input [15:0] VAR20;
input VAR8;
input [1:0] VAR10;
input VAR12;
output VAR5;
output [175:0] VAR14;
output [1:0] VAR11;
reg [1:0] VAR13;
reg [1:0] VAR24;
parameter VAR26=2'b00;
parameter VAR6=2'b01;
parameter VAR22=2'b10;
re... | apache-2.0 |
sh-chris110/chris | FPGA/HPS.bak/Qsys/hps_design/synthesis/submodules/hps_design_pll_0.v | 2,215 | module MODULE1(
input wire VAR59,
input wire rst,
output wire VAR67,
output wire VAR73,
output wire VAR5,
output wire VAR15
);
VAR50 #(
.VAR74("false"),
.VAR27("50.0 VAR3"),
.VAR29("VAR42"),
.VAR65(3),
.VAR4("50.000000 VAR3"),
.VAR70("0 VAR68"),
.VAR44(50),
.VAR21("100.000000 VAR3"),
.VAR33("0 VAR68"),
.VAR35(50),
.VAR... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor3/sky130_fd_sc_lp__nor3_2.v | 2,198 | module MODULE1 (
VAR1 ,
VAR7 ,
VAR4 ,
VAR10 ,
VAR6,
VAR2,
VAR8 ,
VAR3
);
output VAR1 ;
input VAR7 ;
input VAR4 ;
input VAR10 ;
input VAR6;
input VAR2;
input VAR8 ;
input VAR3 ;
VAR9 VAR5 (
.VAR1(VAR1),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR3(VAR3)
);
endmodule
module MODULE... | apache-2.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_11.v | 11,120 | module MODULE5 (
clk,
reset,
VAR47,
VAR28,
VAR8,
VAR24,
VAR1
);
parameter VAR46 = 18;
parameter VAR31 = 11;
parameter VAR67 = 6;
localparam VAR56 = 16;
input clk;
input reset;
input VAR47;
input VAR28;
input [VAR46-1:0] VAR8; output VAR24;
output [VAR46-1:0] VAR1;
localparam VAR7 = 18; localparam VAR4 = 36; localparam ... | mit |
oere/progressive-learning-platform | reference/hw/verilog/inferred_ram.v | 1,548 | module MODULE1(VAR4, VAR6, VAR7, VAR1, VAR8, VAR2, VAR11, VAR3, VAR5, VAR9);
input VAR4, VAR6;
input VAR8;
input VAR7, VAR1;
input [10:0] VAR2, VAR11;
input [31:0] VAR3;
output reg [31:0] VAR5, VAR9;
reg [31:0] VAR10 [2047:0];
always @(posedge VAR4) begin
if (VAR7) begin
if (VAR8) begin
VAR10[VAR2] <= VAR3;
end
VAR5 <=... | gpl-3.0 |
ShepardSiegel/ocpi | coregen/temac_axi_v5_2/example_design/axi_ipif/axi4_lite_ipif_wrapper.v | 9,277 | module MODULE1 #(
parameter VAR74 = 32'h00,
parameter VAR76 = 32'h7FF
) (
input VAR62,
input VAR50,
input [31:0] VAR57,
input VAR14,
output VAR35,
input [31:0] VAR49,
input VAR4,
output VAR59,
output [1:0] VAR6,
output VAR9,
input VAR65,
input [31:0] VAR84,
input VAR34,
output VAR51,
output [31:0] VAR73,
output [1:0] V... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o41a/sky130_fd_sc_hs__o41a_1.v | 2,284 | module MODULE2 (
VAR8 ,
VAR5 ,
VAR7 ,
VAR2 ,
VAR6 ,
VAR9 ,
VAR1,
VAR4
);
output VAR8 ;
input VAR5 ;
input VAR7 ;
input VAR2 ;
input VAR6 ;
input VAR9 ;
input VAR1;
input VAR4;
VAR10 VAR3 (
.VAR8(VAR8),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR4(VAR4)
);
endmodule
module MODULE2 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfrbp/sky130_fd_sc_ls__dfrbp.pp.symbol.v | 1,430 | module MODULE1 (
input VAR2 ,
output VAR1 ,
output VAR7 ,
input VAR9,
input VAR8 ,
input VAR5 ,
input VAR3 ,
input VAR4 ,
input VAR6
);
endmodule | apache-2.0 |
jtillma3/fpga_tutorial | projects/project1/src/avr_interface.v | 3,911 | module MODULE1 #(
parameter VAR6 = 50000000,
parameter VAR25 = 500000
)(
input clk,
input rst,
input VAR15,
output VAR51,
input VAR28,
input VAR33,
input VAR45,
output [3:0] VAR13,
output VAR12,
input VAR10,
input [3:0] VAR53,
output VAR50,
output [9:0] VAR7,
output [3:0] VAR43,
input [7:0] VAR42,
input VAR38,
output V... | mit |
quartushaters/project | M1/Part 1/regFileBoard.v | 1,099 | module MODULE1(
input wire VAR13,
input wire VAR14,
input wire reset,
input wire VAR6,
input wire [4:0] VAR9,
input wire [4:0] VAR1,
input wire [4:0] VAR4,
input wire [31:0] VAR11,
input wire [4:0] VAR7,
input wire [4:0] VAR8,
output reg [31:0] VAR5,
output reg [31:0] VAR10,
output reg [31:0] VAR2,
output reg [31:0] VA... | gpl-2.0 |
hightoon/Sora | FPGA/MIMO/rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/RCB_FRL_TrainingPattern.v | 1,880 | module MODULE1(
input clk,
input rst,
output reg [7:0] VAR1
);
always @ (posedge clk) begin
if(rst) begin
VAR1 <= 8'h00;
end else begin
if(VAR1 == 8'hf4)
VAR1 <= 8'hc2;
end
else
VAR1 <= 8'hf4;
end
end
endmodule | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/xor3/sky130_fd_sc_hdll__xor3.behavioral.v | 1,414 | module MODULE1 (
VAR8,
VAR6,
VAR5,
VAR10
);
output VAR8;
input VAR6;
input VAR5;
input VAR10;
supply1 VAR9;
supply0 VAR7;
supply1 VAR4 ;
supply0 VAR3 ;
wire VAR11;
xor VAR2 (VAR11, VAR6, VAR5, VAR10 );
buf VAR1 (VAR8 , VAR11 );
endmodule | apache-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-xilinx-vc707/mig_interface_model.v | 4,896 | module MODULE1
(
input [27:0] VAR18,
input [2:0] VAR8,
input VAR3,
input [511:0] VAR9,
input VAR33,
input [63:0] VAR28,
input VAR7,
output wire [511:0] VAR30,
output wire VAR22,
output wire VAR14,
output wire VAR11,
output wire VAR1,
output reg VAR32,
output reg VAR10,
output reg VAR15,
input VAR17
);
parameter VAR35 =... | gpl-2.0 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.