repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
bigeagle/riffa | fpga/riffa_hdl/ram_2clk_1w_1r.v | 3,315 | module MODULE1
parameter VAR12 = 32,
parameter VAR2 = 1024
)
(
input VAR3,
input VAR10,
input VAR11,
input [VAR7(VAR2)-1:0] VAR4,
input [VAR7(VAR2)-1:0] VAR6,
input [VAR12-1:0] VAR1,
output [VAR12-1:0] VAR9
);
localparam VAR13 = VAR7(VAR2);
reg [VAR12-1:0] VAR8 [VAR2-1:0];
reg [VAR12-1:0] VAR5;
assign VAR9 = VAR5;
alwa... | bsd-3-clause |
neale/CS-program | 474-VLSI/Lab_ADC/ADC_bb.v | 5,007 | module MODULE1 (
address,
VAR1,
VAR2);
input [10:0] address;
input VAR1;
output [11:0] VAR2;
tri1 VAR1;
endmodule | unlicense |
cr88192/bgbtech_bjx1core | srvcore/ExUop_0.v | 5,674 | module MODULE1(clk);
input clk;
reg[31:0] VAR35; reg[31:0] VAR57;
reg[7:0] VAR19;
reg[6:0] VAR96; reg[6:0] VAR88; reg[6:0] VAR12; reg[31:0] VAR83; reg[11:0] VAR5;
parameter[7:0] VAR64 = 8'h00; parameter[7:0] VAR94 = 8'h01;
parameter[7:0] VAR47 = 8'h02;
parameter[7:0] VAR74 = 8'h03;
parameter[7:0] VAR27 = 8'h04;
paramet... | mit |
alexforencich/xfcp | lib/eth/rtl/ssio_sdr_out_diff.v | 2,947 | module MODULE1 #
(
parameter VAR14 = "VAR27",
parameter VAR4 = "VAR25",
parameter VAR8 = 1
)
(
input wire clk,
input wire [VAR8-1:0] VAR7,
output wire VAR16,
output wire VAR10,
output wire [VAR8-1:0] VAR11,
output wire [VAR8-1:0] VAR15
);
wire VAR13;
wire [VAR8-1:0] VAR6;
VAR17 #(
.VAR14(VAR14),
.VAR4(VAR4),
.VAR8(VAR8... | mit |
mbuesch/pyprofibus | phy_fpga/profibus_phy_mod.v | 30,438 | module MODULE1 (
input clk,
input VAR10,
input [7:0] VAR4,
input VAR6,
output reg VAR7,
output reg [7:0] VAR2,
output reg VAR15,
);
localparam VAR1 = 0;
localparam VAR14 = 1;
localparam VAR11 = 2;
localparam VAR5 = 8'h10;
localparam VAR8 = 8'h68;
localparam VAR3 = 8'hA2;
localparam VAR12 = 8'hDC;
localparam VAR9 = 8'hE... | gpl-2.0 |
BilkentCompGen/GateKeeper | FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/riffa/reorder_queue.v | 12,631 | module MODULE1
parameter VAR76 = 9'd128,
parameter VAR1 = 4'd12,
parameter VAR86 = 512, parameter VAR27 = 5, parameter VAR16 = VAR76/32,
parameter VAR29 = VAR53(VAR16+1),
parameter VAR13 = 2**VAR27,
parameter VAR19 = VAR86/4,
parameter VAR33 = VAR65(VAR19+1),
parameter VAR28 = VAR65(VAR19/VAR16), parameter VAR66 = VAR2... | gpl-3.0 |
mrehkopf/sd2snes | verilog/sd2snes_base/snescmd_buf.v | 10,694 | module MODULE1 (
VAR13,
VAR8,
VAR14,
VAR41,
VAR64,
VAR48,
VAR28,
VAR11,
VAR24);
input [9:0] VAR13;
input [9:0] VAR8;
input VAR14;
input [7:0] VAR41;
input [7:0] VAR64;
input VAR48;
input VAR28;
output [7:0] VAR11;
output [7:0] VAR24;
tri1 VAR14;
tri0 VAR48;
tri0 VAR28;
wire [7:0] VAR59;
wire [7:0] VAR47;
wire [7:0] VAR... | gpl-2.0 |
diegovalverde/papiGB | rtl/gpu_ucode_rom.v | 12,191 | module MODULE1
(
input wire[7:0] VAR46,
output reg [VAR9-1:0] VAR60
);
always @ ( VAR46 )
begin
case ( VAR46 )
0: VAR60 = { VAR18, VAR5, VAR5, VAR5 }; 1: VAR60 = { VAR27, state, VAR3 };
2: VAR60 = { VAR31, VAR37, VAR1, VAR5 }; 3: VAR60 = { VAR31, VAR10, VAR48, VAR5 }; 4: VAR60 = { VAR31, VAR15, VAR43, VAR5}; 5: VAR60 =... | gpl-2.0 |
glocklueng/proxmark3-lcd | fpga/hi_read_tx.v | 2,363 | module MODULE1(
VAR4, VAR11, VAR9,
VAR8, VAR17, VAR19, VAR21, VAR6, VAR5,
VAR18, VAR3,
VAR7, VAR20, VAR13, VAR2,
VAR10, VAR14,
VAR22,
VAR15
);
input VAR4, VAR11, VAR9;
output VAR8, VAR17, VAR19, VAR21, VAR6, VAR5;
input [7:0] VAR18;
output VAR3;
input VAR13;
output VAR7, VAR20, VAR2;
input VAR10, VAR14;
output VAR22;
i... | gpl-2.0 |
olgirard/openmsp430 | core/synthesis/altera/src/megawizard/arria2gx_dmem.v | 7,635 | module MODULE1 (
address,
VAR36,
VAR41,
VAR46,
VAR11,
VAR27,
VAR45);
input [9:0] address;
input [1:0] VAR36;
input VAR41;
input VAR46;
input [15:0] VAR11;
input VAR27;
output [15:0] VAR45;
tri1 [1:0] VAR36;
tri1 VAR41;
tri1 VAR46;
wire [15:0] VAR19;
wire [15:0] VAR45 = VAR19[15:0];
VAR48 VAR31 (
.VAR42 (VAR41),
.VAR44 ... | bsd-3-clause |
monotone-RK/FACE | IEICE-Trans/data_compression/4-way_2-tree/src/ip_pcie/source/PCIeGen2x8If128_pcie_bram_7x.v | 8,976 | module MODULE1
parameter [3:0] VAR17 = 4'h1, parameter [5:0] VAR8 = 6'h08, parameter VAR26 = "VAR3", parameter VAR14 = 0, parameter VAR23 = 0 )
(
input VAR27, input VAR13,
input VAR9, input [12:0] VAR7, input [VAR23 - 1:0] VAR22,
input VAR6, input VAR21, input [12:0] VAR16,
output [VAR23 - 1:0] VAR24 );
localparam VAR1... | mit |
grvmind/amber-cycloneiii | trunk/hw/vlog/ethmac/eth_cop.v | 12,883 | module MODULE1
(
VAR11, VAR58,
VAR34, VAR41, VAR9, VAR43,
VAR30, VAR22, VAR26, VAR35,
VAR29,
VAR27, VAR60, VAR19, VAR21,
VAR33, VAR25, VAR28, VAR24,
VAR56,
VAR50, VAR16, VAR51, VAR14,
VAR3, VAR53, VAR8, VAR6,
VAR5,
VAR45, VAR57, VAR23, VAR37,
VAR4, VAR10, VAR49, VAR47,
VAR2
);
parameter VAR1=1;
input VAR11, VAR58;
inpu... | gpl-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/cmp/rtl/ff_jbi_sc1_2.v | 3,300 | module MODULE1(
VAR21, VAR15, VAR14,
VAR29, VAR28, VAR19,
VAR23, VAR2,
VAR30, VAR4,
VAR16, VAR31, VAR3, VAR20,
VAR18, VAR10, VAR5,
VAR13, VAR8, VAR1, VAR24, VAR12
);
output [31:0] VAR21;
output [31:0] VAR15;
output [6:0] VAR14;
output VAR29;
output VAR28;
output VAR19;
output VAR23;
output VAR2;
output VAR30;
input [31... | gpl-2.0 |
impedimentToProgress/ProbableCause | ddr2/cores/or1200/or1200_cfgr.v | 9,806 | module MODULE1(
VAR20, VAR5
);
input [31:0] VAR20; output [31:0] VAR5;
reg [31:0] VAR5;
always @(VAR20)
if (~|VAR20[31:4])
case(VAR20[3:0]) VAR106: begin
VAR5[VAR22] = VAR30;
VAR5[VAR75] = VAR92;
VAR5[VAR27] = VAR126;
VAR5[VAR102] = VAR98;
end
VAR5[VAR39] = VAR6;
VAR5[VAR87] = VAR18;
VAR5[VAR36] = VAR115;
VAR5[VAR107] ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkdlybuf4s18/sky130_fd_sc_lp__clkdlybuf4s18.behavioral.pp.v | 1,866 | module MODULE1 (
VAR8 ,
VAR5 ,
VAR10,
VAR4,
VAR12 ,
VAR2
);
output VAR8 ;
input VAR5 ;
input VAR10;
input VAR4;
input VAR12 ;
input VAR2 ;
wire VAR6 ;
wire VAR11;
buf VAR1 (VAR6 , VAR5 );
VAR9 VAR7 (VAR11, VAR6, VAR10, VAR4);
buf VAR3 (VAR8 , VAR11 );
endmodule | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/velocityControlHdl_Convert_Data_Type_block1.v | 1,134 | module MODULE1
(
VAR3,
VAR2
);
input signed [35:0] VAR3; output signed [17:0] VAR2;
wire signed [17:0] VAR1;
assign VAR1 = VAR3[35:18];
assign VAR2 = VAR1;
endmodule | gpl-3.0 |
danidim13/labo-digitales | Experimento4Final/Experimento4/Sprite_Controller.v | 1,133 | module MODULE1 # ( parameter VAR5= 32, parameter VAR6=32) (
input wire [9:0] VAR2,
input wire[9:0] VAR11,
input wire VAR9,
input wire VAR7,
input wire [9:0] VAR4,
input wire [9:0] VAR10,
input wire [2:0] VAR8,
input wire [2:0] VAR1 ,
output reg [2:0] VAR3
);
always @ (*)
begin
if(VAR2 <= VAR5 + VAR4 && VAR11 <= VAR6 + ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfbbp/sky130_fd_sc_ls__dfbbp.behavioral.v | 2,671 | module MODULE1 (
VAR3 ,
VAR24 ,
VAR19 ,
VAR20 ,
VAR6 ,
VAR16
);
output VAR3 ;
output VAR24 ;
input VAR19 ;
input VAR20 ;
input VAR6 ;
input VAR16;
supply1 VAR23;
supply0 VAR14;
supply1 VAR15 ;
supply0 VAR28 ;
wire VAR5 ;
wire VAR8 ;
wire VAR13 ;
wire VAR21 ;
wire VAR10;
wire VAR4 ;
reg VAR22 ;
wire VAR1 ;
wire VAR17 ;
... | apache-2.0 |
tloinuy/opencpi-opencv | opencpi/hdl/prims/ocpi/xilinx_v6_pcie_wrapper.v | 15,249 | module MODULE1
(
VAR13, VAR68, VAR27, VAR30,
VAR99, VAR96, VAR41, VAR91,
VAR64, VAR92, VAR80, VAR18, VAR67,
VAR23, VAR59, VAR3, VAR14, VAR19,
VAR60, VAR101, VAR28, VAR50, VAR24,
VAR85, VAR84, VAR10,
VAR22, VAR78,
VAR5, VAR1,
VAR31, VAR87, VAR36,
VAR17, VAR32, VAR46, VAR55,
VAR71, VAR12, VAR20,
VAR15, VAR25, VAR38,
VAR2... | gpl-2.0 |
cr88192/bgbtech_bjx1core | srvcore/ArithAlu.v | 2,546 | module MODULE1(
clk,
VAR22,
VAR4,
VAR11,
VAR6,
VAR14,
VAR9
);
input clk;
input[3:0] VAR22;
input[63:0] VAR4;
input[63:0] VAR11;
output[63:0] VAR6;
input[3:0] VAR14;
output[3:0] VAR9;
parameter[3:0] VAR19 = 4'h00;
parameter[3:0] VAR8 = 4'h01;
parameter[3:0] VAR7 = 4'h02;
parameter[3:0] VAR5 = 4'h03;
parameter[3:0] VAR1 ... | mit |
maltanar/fpga-tidbits | src/main/resources/verilog/Q_srl.v | 11,718 | module MODULE1 (VAR12, reset, VAR5, VAR8, VAR2, VAR13, VAR18, VAR16, VAR3);
parameter VAR24 = 16; parameter VAR4 = 16;
: (((VAR24-1)>>0)==0) ? 0 \
: (((VAR24-1)>>1)==0) ? 1 \
: (((VAR24-1)>>2)==0) ? 2 \
: (((VAR24-1)>>3)==0) ? 3 \
: (((VAR24-1)>>4)==0) ? 4 \
: (((VAR24-1)>>5)==0) ? 5 \
: (((VAR24-1)>>6)==0) ? 6 \
: (((... | bsd-2-clause |
jeffkub/n64-cart-reader | old/fpga/soc_system/soc_system/synthesis/soc_system.v | 50,063 | module MODULE1 (
input wire [15:0] VAR243, output wire [15:0] VAR370, output wire VAR38, output wire VAR152, output wire VAR174, output wire VAR18, output wire VAR52, output wire VAR9, output wire VAR47, input wire VAR247, output wire VAR128, output wire VAR355, output wire VAR135, output wire VAR119, output wire VAR33... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/or2/sky130_fd_sc_ls__or2.pp.symbol.v | 1,257 | module MODULE1 (
input VAR3 ,
input VAR2 ,
output VAR1 ,
input VAR7 ,
input VAR4,
input VAR5,
input VAR6
);
endmodule | apache-2.0 |
aj-michael/Digital-Systems | Pong/Phase4/SheetReader.v | 1,227 | module MODULE1(VAR6, VAR5, VAR1, VAR11, VAR9, VAR8, VAR2, VAR4);
input VAR2, VAR4, VAR6;
output VAR5;
parameter VAR7=4;
input [VAR7-1:0] VAR11;
parameter VAR3=5;
input [VAR3-1:0] VAR1;
output reg [VAR3-1:0] VAR9;
input VAR8;
reg VAR10;
assign VAR5 = ~VAR10;
always@(posedge VAR2 or posedge VAR4)
if (VAR4==1) begin VAR10... | mit |
curtiszimmerman/orp | hardware/mselSoC/src/systems/geophyte/rtl/verilog/wb_rom/rtl/verilog/dp_rom.v | 1,502 | module MODULE1 #(
parameter VAR3 = 5,
parameter VAR10 = ""
) (
input VAR11,
input VAR8,
input [VAR3 - 1:0] VAR7,
output reg [31:0] VAR5,
input VAR6,
input VAR4,
input [VAR3 - 1:0] VAR1,
output reg [31:0] VAR9
);
reg [31:0] VAR2[2**VAR3 - 1:0];
begin
begin | apache-2.0 |
chris-wood/yield | sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_decerr_slave.v | 10,447 | module MODULE1 #
(
parameter integer VAR32 = 1,
parameter integer VAR11 = 32,
parameter integer VAR26 = 1,
parameter integer VAR19 = 1,
parameter integer VAR17 = 0,
parameter integer VAR25 = 2'b11,
parameter integer VAR8 = 0
)
(
input wire VAR29,
input wire VAR30,
input wire [(VAR32-1):0] VAR38,
input wire VAR34,
outpu... | mit |
tnsrb93/G1_RealTimeDCTSteganography | src/ips/decoder_ip_prj/decoder_ip_prj.srcs/sources_1/decoder_axi_modules/decoder_axi_m_v1_0_M00_AXI.v | 23,442 | module MODULE1 #
(
parameter integer VAR70 = 128,
parameter integer VAR36 = 1,
parameter integer VAR30 = 32,
parameter integer VAR18 = 32,
parameter integer VAR2 = 0,
parameter integer VAR7 = 0,
parameter integer VAR73 = 0,
parameter integer VAR82 = 0,
parameter integer VAR84 = 0
)
(
output wire VAR8,
output wire VAR34... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdfstp/sky130_fd_sc_hd__sdfstp.symbol.v | 1,498 | module MODULE1 (
input VAR3 ,
output VAR7 ,
input VAR10,
input VAR1 ,
input VAR5 ,
input VAR4
);
supply1 VAR8;
supply0 VAR6;
supply1 VAR2 ;
supply0 VAR9 ;
endmodule | apache-2.0 |
rkrajnc/minimig-mist | rtl/minimig/paula.v | 9,950 | module MODULE1
(
input clk, input VAR6,
input VAR50,
input VAR8, input reset, input [8:1] VAR70, input [15:0] VAR29, output [15:0] VAR12, output VAR24, input VAR63, input VAR33, input VAR65, input VAR77, input VAR88, input VAR11, input VAR64, input VAR58, output [2:0] VAR53, output [3:0] VAR18, output [3:0] VAR1, outpu... | gpl-3.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_dataflow/bsg_fifo_shift_datapath.v | 1,132 | module MODULE1 #(parameter VAR12( VAR2 )
,parameter VAR12(VAR5 )
,parameter VAR6 = { (VAR2) {1'b0} }
)
(input VAR10
, input [VAR2-1:0] VAR9
, input [VAR5-1:0][1:0] VAR14
, output [VAR2-1:0] VAR1
);
genvar VAR3;
logic [VAR5:0][VAR2-1:0] VAR7, VAR13;
assign VAR7[VAR5] = VAR6;
for (VAR3 = 0; VAR3 < VAR5; VAR3=VAR3+1)
begi... | bsd-3-clause |
ShepardSiegel/ocpi | libsrc/hdl/bsv/bram_patch/BRAM1BE_alt.v | 3,910 | module MODULE1(VAR7,
VAR5,
VAR12,
VAR1,
VAR10,
VAR9
);
parameter VAR4 = 0;
parameter VAR8 = 1;
parameter VAR2 = 1;
parameter VAR15 = 1;
parameter VAR11 = 1;
parameter VAR14 = 1;
input VAR7;
input VAR5;
input [VAR11-1:0] VAR12;
input [VAR8-1:0] VAR1;
input [VAR2-1:0] VAR10;
output [VAR2-1:0] VAR9;
reg [VAR2-1:0] VAR13[0... | lgpl-3.0 |
cafe-alpha/wasca | v12/fpga_firmware/wasca/synthesis/submodules/altera_reset_controller.v | 12,023 | module MODULE1
parameter VAR23 = 6,
parameter VAR77 = 0,
parameter VAR33 = 0,
parameter VAR61 = 0,
parameter VAR28 = 0,
parameter VAR64 = 0,
parameter VAR37 = 0,
parameter VAR30 = 0,
parameter VAR19 = 0,
parameter VAR70 = 0,
parameter VAR29 = 0,
parameter VAR27 = 0,
parameter VAR4 = 0,
parameter VAR39 = 0,
parameter VA... | gpl-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/util_axis_fifo/address_sync.v | 3,981 | module MODULE1 (
input clk,
input VAR14,
input VAR4,
output reg VAR13,
output reg [VAR2-1:0] VAR15,
output reg [VAR2-1:0] VAR3,
output [VAR2:0] VAR1,
output reg VAR9,
input VAR5,
output reg VAR8,
output reg [VAR2-1:0] VAR7,
output [VAR2:0] VAR11
);
parameter VAR2 = 4;
reg [VAR2:0] VAR12 = 2**VAR2;
reg [VAR2:0] VAR10 = ... | gpl-3.0 |
UCR-CS179-SUMMER2014/NES_FPGA | source/etc/hardware/VGA/vga640x480.v | 2,393 | module MODULE1(
VAR10,
VAR14,
VAR3,
VAR4,
VAR5,
VAR7,
VAR6
);
input VAR10; input VAR14;
output VAR3; output VAR4;
output [9:0] VAR5; output [9:0] VAR7;
output VAR6;
localparam VAR2 = 800 , VAR8 = 521 , VAR1 = 144 , VAR13 = 784 ,
VAR11 = 31 , VAR16 = 511 ;
reg [9:0] VAR9, VAR12; reg VAR15;
assign VAR5 = VAR9;
assign VAR... | mit |
monotone-RK/FACE | IEICE-Trans/8-way/src/riffa/offset_to_mask.v | 3,738 | module MODULE1
parameter VAR7 = 4)
(
input VAR6,
input [VAR9(VAR7)-1:0] VAR2,
output [VAR7-1:0] VAR5
);
reg [7:0] VAR4,VAR8;
wire [3:0] VAR1;
assign VAR1 = {VAR6,{{(3-VAR9(VAR7)){1'b0}},VAR2}};
assign VAR5 = (VAR3)? VAR8[7 -: VAR7]: VAR4[VAR7-1:0];
always @(*) begin
VAR4 = 0;
VAR8 = 0;
casex(VAR1)
default: begin
VAR4 =... | mit |
fbalakirev/red-pitaya-notes | cores/axis_timer_v1_0/axis_timer.v | 1,408 | module MODULE1 #
(
parameter integer VAR13 = 64
)
(
input wire VAR3,
input wire VAR7,
input wire VAR6,
input wire [VAR13-1:0] VAR8,
output wire VAR9,
output wire [VAR13-1:0] VAR5,
output wire VAR10,
input wire VAR4
);
reg [VAR13-1:0] VAR11, VAR12;
reg VAR2, VAR1;
wire VAR14;
always @(posedge VAR3)
begin
if(~VAR7)
begin... | mit |
johan92/altera_opencl_sandbox | vector_add/bin_vector_add/iface/ip/Read_Master/MM_to_ST_Adapter.v | 13,852 | module MODULE1 (
clk,
reset,
VAR41,
VAR20,
address,
VAR32,
VAR11,
VAR22,
VAR15,
VAR26,
VAR42,
VAR6,
VAR4,
VAR35
);
parameter VAR2 = 32; parameter VAR17 = 32;
parameter VAR34 = 32;
parameter VAR43 = 2; parameter VAR21 = 5;
parameter VAR7 = 2; parameter VAR27 = 1; parameter VAR5 = 1; parameter VAR13 = 0;
input clk;
input... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a32o/sky130_fd_sc_hdll__a32o_1.v | 2,485 | module MODULE2 (
VAR3 ,
VAR6 ,
VAR8 ,
VAR1 ,
VAR7 ,
VAR2 ,
VAR5,
VAR4,
VAR12 ,
VAR9
);
output VAR3 ;
input VAR6 ;
input VAR8 ;
input VAR1 ;
input VAR7 ;
input VAR2 ;
input VAR5;
input VAR4;
input VAR12 ;
input VAR9 ;
VAR10 VAR11 (
.VAR3(VAR3),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR5(VAR5)... | apache-2.0 |
qmn/riscv-invicta | hardware/src/data_memory.v | 3,504 | module MODULE1 (
input [31:0] VAR11,
input [31:0] VAR2,
input [31:0] addr,
output [31:0] VAR10,
output reg [31:0] VAR12,
output reg [3:0] VAR5,
input [31:0] VAR9,
output reg [31:0] VAR7
);
wire [2:0] VAR3 = VAR11[9:7];
wire [6:0] VAR6 = VAR11[6:0];
assign VAR10 = {addr[31:2], 2'b0};
reg [31:0] VAR1;
always @ begin
case... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o2111a/sky130_fd_sc_ls__o2111a.blackbox.v | 1,394 | module MODULE1 (
VAR6 ,
VAR4,
VAR7,
VAR2,
VAR1,
VAR10
);
output VAR6 ;
input VAR4;
input VAR7;
input VAR2;
input VAR1;
input VAR10;
supply1 VAR5;
supply0 VAR3;
supply1 VAR9 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
Digilent/vivado-library | ip/video_scaler/hdl/verilog/Resize_opr_linearbkb.v | 1,581 | module MODULE1 (VAR9, VAR3, VAR2, VAR8, VAR1, VAR14, VAR5, clk);
parameter VAR10 = 8;
parameter VAR12 = 13;
parameter VAR17 = 4097;
input[VAR12-1:0] VAR9;
input VAR3;
output reg[VAR10-1:0] VAR2;
input[VAR12-1:0] VAR8;
input VAR1;
input[VAR10-1:0] VAR14;
input VAR5;
input clk;
reg [VAR10-1:0] VAR16[0:VAR17-1];
always @(... | mit |
lneuhaus/pyrpl | pyrpl/fpga/rtl/red_pitaya_pid_block.v | 12,335 | module MODULE1 #(
parameter VAR43 = 12 ,
parameter VAR21 = 32 , parameter VAR54 = 10 ,
parameter VAR51 = 24 ,
parameter VAR56 = 0 ,
parameter VAR35 = 4 ,
parameter VAR27 = 5,
parameter VAR20 = 10,
parameter VAR10 = 1
)
(
input VAR40 , input VAR32 , input VAR36 , input signed [ 14-1: 0] VAR53 , output signed [ 14-1: 0] ... | mit |
freecores/verilog_fixed_point_math_library | Tes_add.v | 1,650 | module MODULE1;
reg [31:0] VAR5;
reg [31:0] VAR11;
wire [31:0] VAR8;
VAR6 #(19,32) VAR7 (
.VAR5(VAR5),
.VAR11(VAR11),
.VAR8(VAR8)
);
wire [30:0] VAR4;
wire [30:0] VAR10;
wire [30:0] VAR3;
wire VAR2;
wire VAR9;
wire VAR1;
assign VAR10 = VAR5[30:0];
assign VAR3 = VAR11[30:0];
assign VAR4 = VAR8[30:0];
assign VAR2 = VAR5[... | lgpl-2.1 |
alexforencich/xfcp | lib/eth/example/ADM_PCIE_9V3/fpga_10g/rtl/fpga.v | 25,205 | module MODULE1 (
input wire VAR248,
input wire VAR281,
output wire [1:0] VAR377,
output wire VAR200,
output wire [1:0] VAR115,
input wire [1:0] VAR390,
output wire VAR130,
output wire VAR169,
input wire VAR162,
input wire VAR133,
output wire VAR113,
output wire VAR273,
input wire VAR120,
input wire VAR24,
output wire V... | mit |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/Video_System/synthesis/submodules/Video_System_Pixel_Scaler.v | 8,591 | module MODULE1 (
clk,
reset,
VAR15,
VAR11,
VAR3,
VAR20,
VAR32,
VAR22,
VAR14,
VAR25,
VAR5,
VAR31,
VAR34,
VAR33
);
parameter VAR1 = 29; parameter VAR23 = 1;
parameter VAR26 = 8; parameter VAR12 = 7; parameter VAR24 = 320;
parameter VAR21 = 4'b0000;
parameter VAR17 = 4'b0000;
parameter VAR10 = 8; parameter VAR16 = 320; pa... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfsbp/sky130_fd_sc_ls__sdfsbp.pp.blackbox.v | 1,471 | module MODULE1 (
VAR2 ,
VAR4 ,
VAR3 ,
VAR5 ,
VAR1 ,
VAR6 ,
VAR10,
VAR11 ,
VAR7 ,
VAR8 ,
VAR9
);
output VAR2 ;
output VAR4 ;
input VAR3 ;
input VAR5 ;
input VAR1 ;
input VAR6 ;
input VAR10;
input VAR11 ;
input VAR7 ;
input VAR8 ;
input VAR9 ;
endmodule | apache-2.0 |
which0326/ca_project2 | code/Control.v | 1,681 | module MODULE1(
VAR4,
VAR2,
VAR1,
VAR3
);
input [5:0] VAR4;
output reg VAR2,VAR1;
output reg [7:0] VAR3;
always@(*) begin VAR2 = 0;
VAR1 = 0;
if(VAR4 == 6'b000000)begin
VAR3[0] = 1;
VAR3[1] = 0;
VAR3[2] = 0;
VAR3[3] = 0;
VAR3[4] = 0;
VAR3[6:5] = 2'b10;
VAR3[7] = 1;
end
if(VAR4 == 6'b001000)begin VAR3[0] = 1;
VAR3[1] = ... | cc0-1.0 |
Tao-J/nexys3MIPSSoC | BTN_Anti_jitter.v | 1,237 | module MODULE1(
input wire clk,
input wire [4:0]VAR1,
input wire [7:0]VAR4,
output reg [4:0]VAR2,
output reg [7:0]VAR3
);
reg [31:0] counter;
always @(posedge clk)begin
if (counter > 0)begin
if (counter < 100000) counter <= counter + 1;
end
else begin
counter <= 32'b0;
VAR2 <= VAR1;
VAR3 <= VAR4;
end
end else
if (VAR1 ... | gpl-3.0 |
Blunk-electronic/M-1 | HW/ise/executor_mini/src/scan_clock_timer.v | 10,459 | module MODULE1 (
clk, VAR10, reset, delay, VAR12, VAR11, VAR8, VAR5, VAR19 );
input clk; input VAR10;
input reset;
input [VAR7-1:0] delay; input VAR12;
output reg VAR11;
input VAR8;
input VAR5;
wire [3:0] VAR6;
assign VAR6 = delay[7:4];
wire [3:0] VAR20;
assign VAR20 = delay[3:0];
reg [VAR2-1:0] VAR16;
reg [VAR18-1:0] ... | gpl-2.0 |
cliffordwolf/picorv32 | picosoc/picosoc.v | 6,891 | module MODULE2 (
input clk,
input VAR18,
output VAR31,
input VAR36,
output [ 3:0] VAR28,
output [31:0] VAR79,
output [31:0] VAR42,
input [31:0] VAR64,
input VAR53,
input VAR2,
input VAR6,
output VAR67,
input VAR66,
output VAR82,
output VAR24,
output VAR17,
output VAR47,
output VAR25,
output VAR71,
output VAR65,
output ... | isc |
shailcoolboy/Warp-Trinity | PlatformSupport/Deprecated/pcores/clock_board_config_v1_03_a/hdl/verilog/clock_board_config.v | 27,243 | module MODULE1 (
VAR40,
VAR38,
VAR8,
VAR45,
VAR9,
VAR5,
VAR25,
VAR32,
VAR53,
VAR12,
VAR47
);
parameter VAR41 = 120000000;
parameter VAR13 = 16'h1Aff;
parameter VAR34 = 16'h1Aff;
parameter VAR48 = 16'h01ff; parameter VAR52 = 16'h1eff; parameter VAR63 = 16'h1eff; parameter VAR14 = 16'h01ff;
parameter VAR37 = 16'h02ff; pa... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/or3/sky130_fd_sc_ls__or3.blackbox.v | 1,248 | module MODULE1 (
VAR2,
VAR8,
VAR1,
VAR3
);
output VAR2;
input VAR8;
input VAR1;
input VAR3;
supply1 VAR7;
supply0 VAR6;
supply1 VAR4 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
ffu/DSA-3.2.2 | gr-gpio/src/fpga/lib/tx_chain_dig.v | 1,523 | module MODULE1
(input VAR3,
input reset,
input enable,
input wire [15:0] VAR5,
input wire [15:0] VAR7,
output wire [15:0] VAR2,
output wire [15:0] VAR1,
output wire VAR4,
output wire VAR6
);
assign VAR2 = (enable)?{VAR5[15:1],1'b0}:VAR5;
assign VAR1 = (enable)?{VAR7[15:1],1'b0}:VAR7;
assign VAR4 = (enable)?VAR5[0]:1'b0... | gpl-3.0 |
keith-epidev/VHDL-lib | top/lab_4/part_1/ip/fir/fir_stub.v | 1,399 | module MODULE1(VAR6, VAR5, VAR1, VAR3, VAR2, VAR4)
;
input VAR6;
input VAR5;
output VAR1;
input [15:0]VAR3;
output VAR2;
output [39:0]VAR4;
endmodule | gpl-2.0 |
MartinMosbeck/NoCMonitor | buildCONNECT4x4/mkRouterOutputArbitersStatic.v | 11,922 | module MODULE1(VAR14,
VAR5,
VAR6,
VAR16,
VAR3,
VAR2,
VAR13,
VAR8,
VAR15,
VAR7,
VAR11,
VAR12,
VAR17,
VAR1,
VAR4,
VAR9,
VAR10);
input VAR14;
input VAR5;
input [4 : 0] VAR6;
output [4 : 0] VAR16;
input VAR3;
input [4 : 0] VAR2;
output [4 : 0] VAR13;
input VAR8;
input [4 : 0] VAR15;
output [4 : 0] VAR7;
input VAR11;
input ... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/and3b/sky130_fd_sc_hs__and3b_2.v | 2,091 | module MODULE2 (
VAR3 ,
VAR4 ,
VAR1 ,
VAR2 ,
VAR8,
VAR7
);
output VAR3 ;
input VAR4 ;
input VAR1 ;
input VAR2 ;
input VAR8;
input VAR7;
VAR5 VAR6 (
.VAR3(VAR3),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR7(VAR7)
);
endmodule
module MODULE2 (
VAR3 ,
VAR4,
VAR1 ,
VAR2
);
output VAR3 ;
input VAR4;
input VAR1 ... | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/ASIC_fpaddsub_arch2/integracion_fisica/front_end/db/SINGLE/Add_Subt_syn.v | 19,474 | module MODULE2 ( VAR268, VAR82, VAR312, VAR332, VAR136 );
input [26:0] VAR268;
input [26:0] VAR82;
output [26:0] VAR332;
input VAR312;
output VAR136;
wire VAR253, VAR135, VAR237, VAR251, VAR168, VAR65, VAR24, VAR245, VAR138, VAR19, VAR124, VAR258, VAR311, VAR186, VAR156, VAR296,
VAR187, VAR120, VAR16, VAR130, VAR297, V... | gpl-3.0 |
sergev/vak-opensource | hardware/s3esk-openrisc/or1200/or1200_spram_1024x32_bw.v | 12,985 | module MODULE1(
VAR14, VAR25, VAR24,
clk, rst, VAR38, VAR76, VAR68, addr, VAR50, VAR27
);
input VAR14;
input [VAR35 - 1:0] VAR24; output VAR25;
input clk; input rst; input VAR38; input [3:0] VAR76; input VAR68; input [9:0] addr; input [31:0] VAR50; output [31:0] VAR27;
assign VAR25 = VAR14;
VAR31 VAR37(
VAR28 VAR37(
VA... | apache-2.0 |
eecsninja/duinocube-core | common/registers.v | 5,184 | module MODULE1(reset, clk, en, VAR13, VAR17, VAR11, VAR3);
parameter VAR15=16; parameter VAR4=16; parameter VAR27=VAR7;
input clk; input reset; input en; input [1:0] VAR13;
input [VAR4-1:0] VAR17; output [VAR4-1:0] VAR11;
input [VAR4-1:0] VAR3;
wire VAR18 = VAR13[0];
wire VAR9 = VAR13[1];
genvar VAR1;
generate
if (VAR2... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a32o/sky130_fd_sc_hdll__a32o.behavioral.v | 1,684 | module MODULE1 (
VAR11 ,
VAR12,
VAR6,
VAR17,
VAR1,
VAR14
);
output VAR11 ;
input VAR12;
input VAR6;
input VAR17;
input VAR1;
input VAR14;
supply1 VAR4;
supply0 VAR13;
supply1 VAR2 ;
supply0 VAR8 ;
wire VAR15 ;
wire VAR5 ;
wire VAR16;
and VAR9 (VAR15 , VAR17, VAR12, VAR6 );
and VAR7 (VAR5 , VAR1, VAR14 );
or VAR10 (VAR1... | apache-2.0 |
ptracton/vscale_soc | rtl/wb_riscv_soc_top.v | 5,578 | module MODULE1 (
VAR4,
VAR101, VAR85, VAR57
) ;
parameter VAR51 = "";
input VAR101;
input VAR85;
input VAR57;
output VAR4;
wire VAR25;
wire VAR19;
wire VAR72 = VAR25;
wire VAR39 = VAR19;
VAR54 VAR60(
.VAR89(VAR25),
.VAR111(VAR19),
.VAR101(VAR101),
.VAR85(VAR85)
) ;
wire [23:0] VAR55 = 'b0;
VAR66 VAR13(
.clk(VAR25),
.rs... | mit |
archlabo/Frix | fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/mig/user_design/rtl/controller/mig_7series_v2_0_arb_select.v | 26,779 | module MODULE1 #
(
parameter VAR96 = 100,
parameter VAR85 = "VAR97",
parameter VAR40 = "1T",
parameter VAR101 = 11,
parameter VAR125 = 3,
parameter VAR88 = "8",
parameter VAR7 = 4,
parameter VAR102 = 5,
parameter VAR84 = 5,
parameter VAR136 = 31,
parameter VAR118 = 8,
parameter VAR100 = "VAR6",
parameter VAR60 = "VAR97... | bsd-2-clause |
tugrulyatagan/RISC-processor | xilinx_processor/hazard.v | 1,802 | module MODULE1(
input [2:0] VAR13,
input [2:0] VAR18,
input [2:0] VAR17,
input [2:0] VAR10,
input [2:0] VAR6,
input VAR4,
input VAR3,
input [2:0] VAR12,
input VAR7,
input [2:0] VAR5,
input VAR11,
output reg VAR14,
output reg VAR2,
output reg VAR8,
output reg VAR9,
output reg [1:0] VAR15,
output reg [1:0] VAR1
);
always... | gpl-2.0 |
efabless/openlane | designs/jpeg_encoder/src/dctub.v | 4,690 | module MODULE1(clk, VAR2, VAR22, VAR9, VAR8, VAR10,
VAR4, VAR24, VAR20, VAR7, VAR25, VAR14, VAR23, VAR18);
parameter VAR3 = 16;
parameter VAR5 = 8;
parameter [2:0] VAR6 = 3'h0;
input clk;
input VAR2;
input VAR22; input [2:0] VAR9, VAR8;
input [VAR5:1] VAR10; output [11:0] VAR4, VAR24, VAR20, VAR7, VAR25, VAR14, VAR23, ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_io | cells/top_gpio_ovtv2/sky130_fd_io__top_gpio_ovtv2.pp.symbol.v | 2,930 | module MODULE1 (
input VAR37 ,
output VAR39 ,
input VAR32 ,
output VAR27 ,
input VAR16 ,
inout VAR15 ,
inout VAR6 ,
inout VAR36 ,
inout VAR19 ,
inout VAR7 ,
inout VAR5 ,
input VAR23 ,
input VAR3 ,
input VAR40 ,
input [2:0] VAR31 ,
input VAR26 ,
input VAR33 ,
input VAR12 ,
input VAR22 ,
input VAR2,
input VAR25 ,
input V... | apache-2.0 |
Darkin47/Zynq-TX-UTT | Vivado/Hist_Stretch/Hist_Stretch.srcs/sources_1/bd/design_1/ip/design_1_auto_us_0/synth/design_1_auto_us_0.v | 9,749 | module MODULE1 (
VAR11,
VAR14,
VAR36,
VAR47,
VAR10,
VAR22,
VAR49,
VAR83,
VAR65,
VAR33,
VAR55,
VAR52,
VAR62,
VAR15,
VAR1,
VAR48,
VAR4,
VAR98,
VAR68,
VAR28,
VAR19,
VAR40,
VAR17,
VAR3,
VAR41,
VAR61,
VAR79,
VAR42,
VAR96,
VAR80,
VAR70,
VAR101,
VAR100,
VAR23
);
input wire VAR11;
input wire VAR14;
input wire [31 : 0] VAR36;
i... | gpl-3.0 |
AnAtomInTheUniverse/578_project_col_panic | final_verilog/src/clib/c_shift_reg.v | 2,686 | module MODULE1
(clk, reset, VAR14, VAR2, VAR12);
parameter VAR6 = 32;
parameter VAR15 = 2;
parameter VAR10 = VAR5;
input clk;
input reset;
input VAR14;
input [0:VAR6-1] VAR2;
output [0:VAR6-1] VAR12;
wire [0:VAR6-1] VAR12;
genvar VAR13;
wire [0:(VAR15+1)*VAR6-1] VAR7;
assign VAR7[0:VAR6-1] = VAR2;
generate
for(VAR13 = ... | gpl-2.0 |
andrewandrepowell/axiplasma | hdl/projects/Nexys4/bd/mig_wrap/ip/mig_wrap_mig_7series_0_0/mig_wrap_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_ocd_samp.v | 12,567 | module MODULE1 #
(parameter VAR38 = 4,
parameter VAR18 = 2,
parameter VAR45 = 95,
parameter VAR62 = 100,
parameter VAR63 = "VAR44")
(
VAR34, VAR50, VAR49, VAR65,
VAR26, clk, rst, VAR40,
VAR15, VAR23, VAR46, VAR24,
VAR55
);
function integer VAR17 (input integer VAR14); begin
VAR14 = VAR14 - 1;
for (VAR17=1; VAR14>1; VAR... | mit |
ShepardSiegel/ocpi | coregen/dram_k7_mig11/mig_7series_v1_1/user_design/rtl/phy/phy_top.v | 39,905 | module MODULE1 #
(
parameter VAR222 = 100, parameter VAR256 = "0", parameter VAR121 = 3, parameter VAR94 = "8", parameter VAR122 = "VAR140", parameter VAR166 = 1, parameter VAR258 = 5,
parameter VAR167 = 12, parameter VAR79 = 1, parameter VAR36 = 1, parameter VAR74 = 5,
parameter VAR164 = 8, parameter VAR16 = 64, param... | lgpl-3.0 |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/video_sys/synthesis/submodules/altera_up_video_scaler_shrink.v | 9,488 | module MODULE1 (
clk,
reset,
VAR22,
VAR12,
VAR24,
VAR25,
VAR14,
VAR17,
VAR16,
VAR13,
VAR15,
VAR8
);
parameter VAR4 = 15; parameter VAR26 = 9; parameter VAR6 = 9;
parameter VAR3 = 640;
parameter VAR11 = 4'b0101;
parameter VAR27 = 4'b0000;
input clk;
input reset;
input [VAR4: 0] VAR22;
input VAR12;
input VAR24;
input VAR... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a31o/sky130_fd_sc_hd__a31o.pp.symbol.v | 1,366 | module MODULE1 (
input VAR1 ,
input VAR8 ,
input VAR6 ,
input VAR5 ,
output VAR2 ,
input VAR9 ,
input VAR3,
input VAR7,
input VAR4
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/tapvgnd/sky130_fd_sc_hd__tapvgnd.functional.pp.v | 1,230 | module MODULE1 (
VAR1,
VAR3,
VAR2 ,
VAR4
);
input VAR1;
input VAR3;
input VAR2 ;
input VAR4 ;
endmodule | apache-2.0 |
ychaim/FPGA-Litecoin-Miner | experimental/LX150-SLOWEIGHT-A/salsa_sloweight.v | 8,219 | module MODULE1 (clk, VAR63, VAR109, VAR61, VAR28, VAR46);
input clk;
input [511:0]VAR63;
input [511:0]VAR109;
output [511:0]VAR61; output [511:0]VAR28; output [9:0] VAR46;
wire [9:0] VAR94, VAR54, VAR48, VAR65, VAR9, VAR67, VAR90, VAR49;
reg [511:0]VAR104;
reg [511:0]VAR91;
reg [511:0]VAR15;
reg [511:0]VAR20;
reg [511:... | gpl-3.0 |
jz0229/open-ephys-pcie | kc705-host-firmware/Sources/Verilog/pll_lock_lookup.v | 5,467 | module MODULE1(
input clk,
input [6:0] VAR1,
output reg [39:0] VAR3
);
reg [39:0] VAR2 [0:64];
wire [5:0] addr;
begin
begin | mit |
sergev/vak-opensource | hardware/s3esk-openrisc/or1200/or1200_pic.v | 7,507 | module MODULE1(
clk, rst, VAR4, VAR3, VAR15, VAR18, VAR2,
VAR7, VAR20,
VAR14
);
input clk; input rst; input VAR4; input VAR3; input [31:0] VAR15; input [31:0] VAR18; output [31:0] VAR2; output VAR7; output VAR20;
input [VAR5-1:0] VAR14;
reg [VAR5-1:2] VAR6; else
wire [VAR5-1:2] VAR6; VAR8
reg [VAR5-1:0] VAR16; else
wir... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/a21oi/sky130_fd_sc_hvl__a21oi.blackbox.v | 1,338 | module MODULE1 (
VAR6 ,
VAR7,
VAR5,
VAR3
);
output VAR6 ;
input VAR7;
input VAR5;
input VAR3;
supply1 VAR2;
supply0 VAR4;
supply1 VAR1 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
fpgasystems/caribou | hw/src/nukv/nukv_read_old.v | 4,659 | module MODULE1 #(
parameter VAR3 = 128,
parameter VAR1 = 96,
parameter VAR16 = 32,
parameter VAR19 = 20
)
(
input wire clk,
input wire rst,
input wire [VAR3+VAR1+VAR16-1:0] VAR15,
input wire VAR4,
output wire VAR25,
input wire [VAR3+VAR1+VAR16-1:0] VAR10,
input wire VAR13,
output wire VAR14,
output reg [VAR3+VAR1+VAR16... | gpl-3.0 |
freecores/eco32 | fpga/src/dsk/atactrl.v | 15,192 | module MODULE1 (
input clk, reset,
input VAR58, VAR43,
input [19:2] VAR33,
input [31:0] VAR46,
output [31:0] VAR49,
output VAR51,
output VAR68,
inout [15:0] VAR28,
output [2:0] VAR10,
output VAR13, VAR24,
output VAR52, VAR2,
input VAR29,
input VAR12,
output VAR22,
input VAR18
);
reg VAR19, VAR47;
reg [3:0] VAR38;
wire ... | bsd-2-clause |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/adi_common_v1_00_a/hdl/verilog/up_axis_dma_rx.v | 9,218 | module MODULE1 (
VAR35,
VAR43,
VAR12,
VAR38,
VAR17,
VAR54,
VAR34,
VAR26,
VAR3,
VAR30,
VAR10,
VAR42,
VAR56,
VAR47,
VAR8,
VAR44,
VAR24,
VAR21,
VAR49);
parameter VAR51 = 32'h00050062;
parameter VAR31 = 0;
input VAR35;
output VAR43;
input VAR12;
output VAR38;
output VAR17;
output VAR54;
output [31:0] VAR34;
input VAR26;
in... | mit |
julioamerico/prj_crc_ip | src/SoC/component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vlog/core/coreahblite_addrdec.v | 6,668 | module MODULE1 #(
parameter [2:0]VAR27 = 0,
parameter [0:0]VAR11 = 1,
parameter [15:0]VAR8 = 0,
parameter [16:0]VAR17 = (2**17)-1
)
(
input [31:0] VAR12,
input VAR20,
output wire [16:0] VAR26,
output wire [31:0] VAR9,
output wire VAR22
);
localparam VAR13 = (VAR27 == 1) ? 31 :
(VAR27 == 2) ? 27 :
(VAR27 == 3) ? 23 :
(V... | gpl-3.0 |
johan92/altera_opencl_sandbox | vector_add/bin_vector_add/system/synthesis/submodules/acl_avm_to_ic.v | 3,732 | module MODULE1 #(
parameter integer VAR5 = 256,
parameter integer VAR12 = 256,
parameter integer VAR23 = 6,
parameter integer VAR13 = 32,
parameter integer VAR11 = VAR5 / 8,
parameter integer VAR25 = 1,
parameter VAR8=1 )
(
input logic VAR28,
input logic VAR21,
input logic VAR17,
input logic [VAR12-1:0] VAR2,
input log... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/tapvgnd2/sky130_fd_sc_hd__tapvgnd2.behavioral.v | 1,200 | module MODULE1 ();
supply1 VAR3;
supply0 VAR2;
supply1 VAR1 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
mballance/wb_dma | rtl/wb_dma_rf.v | 63,264 | module MODULE1(clk, rst,
VAR57, VAR271, VAR384, VAR275, VAR323,
VAR326, VAR145,
VAR122, VAR182, VAR167, VAR96, VAR12, VAR121, VAR239, VAR74,
VAR17, VAR180, VAR220, VAR139, VAR304, VAR225, VAR66, VAR146,
VAR157, VAR299, VAR231, VAR155, VAR185, VAR98, VAR347, VAR93,
VAR104, VAR160, VAR84, VAR1, VAR196, VAR224, VAR244, VA... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/bufz/gf180mcu_fd_sc_mcu9t5v0__bufz_2.behavioral.pp.v | 1,236 | module MODULE1( VAR4, VAR5, VAR8, VAR1, VAR6 );
input VAR4, VAR5;
inout VAR1, VAR6;
output VAR8;
VAR2 VAR3(.VAR4(VAR4),.VAR5(VAR5),.VAR8(VAR8),.VAR1(VAR1),.VAR6(VAR6));
VAR2 VAR7(.VAR4(VAR4),.VAR5(VAR5),.VAR8(VAR8),.VAR1(VAR1),.VAR6(VAR6)); | apache-2.0 |
JorisBolsens/PYNQ | Pynq-Z1/vivado/ip/arduino_io_switch_1.0/src/arduino_switch_digital_bit.v | 3,242 | module MODULE1(
input [3:0] VAR16,
input VAR18,
output reg VAR5,
output reg VAR4,
output VAR25,
input VAR20,
input VAR14,
output VAR15,
input VAR6,
input VAR24,
output VAR12,
input VAR9,
input VAR26,
output VAR10,
input VAR22,
input VAR7,
output VAR17,
input VAR2,
input VAR3,
output VAR8,
input VAR1,
input VAR11,
outpu... | bsd-3-clause |
aospan/NetUP_Dual_Universal_CI-fpga | ip_compiler_for_pci_express-library/altpcie_pll_phy5_62p5.v | 18,319 | module MODULE1 (
VAR22,
VAR49,
VAR21,
VAR97,
VAR14,
VAR98);
input VAR22;
input VAR49;
output VAR21;
output VAR97;
output VAR14;
output VAR98;
tri0 VAR22;
wire [5:0] VAR66;
wire VAR77;
wire [0:0] VAR93 = 1'h0;
wire [2:2] VAR36 = VAR66[2:2];
wire [1:1] VAR102 = VAR66[1:1];
wire [0:0] VAR11 = VAR66[0:0];
wire VAR21 = VAR1... | gpl-3.0 |
markusC64/1541ultimate2 | fpga/nios_dut/nios_dut/synthesis/submodules/nios_dut_mm_interconnect_0_avalon_st_adapter_012.v | 6,185 | module MODULE1 #(
parameter VAR4 = 130,
parameter VAR21 = 0,
parameter VAR3 = 130,
parameter VAR13 = 0,
parameter VAR16 = 0,
parameter VAR11 = 0,
parameter VAR9 = 1,
parameter VAR7 = 1,
parameter VAR24 = 0,
parameter VAR14 = 130,
parameter VAR20 = 0,
parameter VAR6 = 1,
parameter VAR18 = 0,
parameter VAR22 = 1,
paramet... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/einvn/sky130_fd_sc_hvl__einvn.pp.blackbox.v | 1,293 | module MODULE1 (
VAR3 ,
VAR6 ,
VAR7,
VAR1,
VAR2,
VAR5 ,
VAR4
);
output VAR3 ;
input VAR6 ;
input VAR7;
input VAR1;
input VAR2;
input VAR5 ;
input VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nor4/sky130_fd_sc_hd__nor4.behavioral.v | 1,425 | module MODULE1 (
VAR6,
VAR8,
VAR3,
VAR11,
VAR1
);
output VAR6;
input VAR8;
input VAR3;
input VAR11;
input VAR1;
supply1 VAR5;
supply0 VAR9;
supply1 VAR2 ;
supply0 VAR7 ;
wire VAR12;
nor VAR10 (VAR12, VAR8, VAR3, VAR11, VAR1 );
buf VAR4 (VAR6 , VAR12 );
endmodule | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_hdmi_rx/axi_hdmi_rx_es.v | 5,944 | module MODULE1 (
VAR20,
VAR17,
VAR12,
VAR28,
VAR19);
parameter VAR27 = 32;
localparam VAR16 = VAR27/8;
input VAR20;
input [(VAR27-1):0] VAR17;
output VAR12;
output VAR28;
output [(VAR27-1):0] VAR19;
reg [(VAR27-1):0] VAR7 = 'd0;
reg VAR13 = 'd0;
reg VAR2 = 'd0;
reg [(VAR27-1):0] VAR24 = 'd0;
reg VAR1 = 'd0;
reg VAR23 =... | gpl-3.0 |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/acme/prj/solution1/impl/verilog/FIFO_image_filter_img_1_cols_V.v | 2,987 | module MODULE2 (
clk,
VAR20,
VAR13,
VAR25,
VAR23);
parameter VAR2 = 32'd12;
parameter VAR6 = 32'd2;
parameter VAR8 = 32'd3;
input clk;
input [VAR2-1:0] VAR20;
input VAR13;
input [VAR6-1:0] VAR25;
output [VAR2-1:0] VAR23;
reg[VAR2-1:0] VAR18 [0:VAR8-1];
integer VAR17;
always @ (posedge clk)
begin
if (VAR13)
begin
for (V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nor3b/sky130_fd_sc_ls__nor3b.pp.blackbox.v | 1,348 | module MODULE1 (
VAR6 ,
VAR8 ,
VAR2 ,
VAR3 ,
VAR1,
VAR7,
VAR5 ,
VAR4
);
output VAR6 ;
input VAR8 ;
input VAR2 ;
input VAR3 ;
input VAR1;
input VAR7;
input VAR5 ;
input VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfxtp/sky130_fd_sc_ls__sdfxtp.behavioral.pp.v | 2,370 | module MODULE1 (
VAR24 ,
VAR2 ,
VAR6 ,
VAR8 ,
VAR1 ,
VAR15,
VAR18,
VAR9 ,
VAR16
);
output VAR24 ;
input VAR2 ;
input VAR6 ;
input VAR8 ;
input VAR1 ;
input VAR15;
input VAR18;
input VAR9 ;
input VAR16 ;
wire VAR4 ;
wire VAR10 ;
reg VAR23 ;
wire VAR5 ;
wire VAR11;
wire VAR22;
wire VAR25;
wire VAR14 ;
wire VAR21 ;
wire V... | apache-2.0 |
alexforencich/verilog-i2c | rtl/i2c_slave.v | 16,537 | module MODULE1 #(
parameter VAR52 = 4
)
(
input wire clk,
input wire rst,
input wire VAR20,
input wire [7:0] VAR49,
input wire VAR62,
output wire VAR21,
input wire VAR45,
output wire [7:0] VAR42,
output wire VAR74,
input wire VAR27,
output wire VAR54,
input wire VAR39,
output wire VAR22,
output wire VAR7,
input wire VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nand2/sky130_fd_sc_hdll__nand2_6.v | 2,113 | module MODULE2 (
VAR4 ,
VAR7 ,
VAR5 ,
VAR9,
VAR8,
VAR3 ,
VAR1
);
output VAR4 ;
input VAR7 ;
input VAR5 ;
input VAR9;
input VAR8;
input VAR3 ;
input VAR1 ;
VAR6 VAR2 (
.VAR4(VAR4),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR1(VAR1)
);
endmodule
module MODULE2 (
VAR4,
VAR7,
VAR5
);
output VAR4;
... | apache-2.0 |
YosysHQ/yosys | techlibs/intel/cycloneive/cells_map.v | 3,437 | module \VAR21 (input VAR1, output VAR14);
VAR6 VAR7 (.VAR22(VAR14), .VAR24(VAR1), .VAR2(1'b0));
endmodule
module \VAR12 (input VAR1, output VAR14);
VAR13 VAR7 (.VAR22(VAR14), .VAR24(VAR1), .VAR23(1'b1));
endmodule
module MODULE3 (VAR19, VAR5);
parameter VAR16 = 0;
parameter VAR8 = 0;
input [VAR16-1:0] VAR19;
output VAR... | isc |
julioamerico/OpenCRC | src/SoC/component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vlog/core/coreahblite_slavestage.v | 8,306 | module MODULE1
(
input VAR46,
input VAR4,
input VAR37,
input VAR33,
output reg VAR23,
output reg [31:0] VAR44,
output reg [2:0] VAR29,
output wire VAR26,
output reg VAR30,
output reg [31:0] VAR15,
output wire VAR10,
output reg VAR20,
input [3:0] VAR2,
input [3:0] VAR42,
input [3:0] VAR21,
output reg [3:0] VAR47,
output... | gpl-3.0 |
ShepardSiegel/ocpi | rtl/mkWsiAdapter32B4B.v | 31,059 | module MODULE1(VAR190,
VAR21,
VAR89,
VAR77,
VAR18,
VAR90,
VAR144,
VAR179,
VAR16,
VAR95,
VAR103,
VAR93,
VAR53,
VAR59,
VAR191,
VAR25,
VAR114,
VAR42,
VAR28,
VAR86,
VAR158,
VAR88);
input VAR190;
input VAR21;
input [2 : 0] VAR89;
input VAR77;
input VAR18;
input [11 : 0] VAR90;
input [255 : 0] VAR144;
input [31 : 0] VAR179;
... | lgpl-3.0 |
rbesenczi/real-time-traffic-analyzer | src/traffic_analyser_Vivado_2014_4/traffic_analyser_Vivaldo_2014_4.srcs/sources_1/bd/design_1/ip/design_1_xbar_0/synth/design_1_xbar_0.v | 14,571 | module MODULE1 (
VAR84,
VAR44,
VAR10,
VAR55,
VAR27,
VAR38,
VAR5,
VAR72,
VAR57,
VAR85,
VAR48,
VAR8,
VAR88,
VAR101,
VAR11,
VAR78,
VAR28,
VAR15,
VAR125,
VAR64,
VAR46,
VAR87,
VAR14,
VAR121,
VAR98,
VAR29,
VAR60,
VAR24,
VAR119,
VAR34,
VAR81,
VAR40,
VAR47,
VAR59,
VAR42,
VAR82,
VAR17,
VAR131,
VAR21,
VAR23
);
input wire VAR84;
... | gpl-3.0 |
htogarcia/Microcontrolador-Calculadora | VGA Mouse/num_5.v | 1,113 | module MODULE1(
input [2:0] VAR7,
output reg [4:0] VAR1
);
parameter [4:0] VAR6 = 5'b11111; parameter [4:0] VAR2 = 5'b00001; parameter [4:0] VAR5 = 5'b01111; parameter [4:0] VAR4 = 5'b10000; parameter [4:0] VAR3 = 5'b10001; parameter [4:0] VAR8 = 5'b01110;
always @ *
begin
case (VAR7)
3'b000:
VAR1 = VAR6;
3'b001:
VAR1 ... | mit |
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