repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdfxtp/sky130_fd_sc_hdll__sdfxtp.functional.pp.v | 1,967 | module MODULE1 (
VAR7 ,
VAR3 ,
VAR17 ,
VAR15 ,
VAR13 ,
VAR9,
VAR5,
VAR6 ,
VAR16
);
output VAR7 ;
input VAR3 ;
input VAR17 ;
input VAR15 ;
input VAR13 ;
input VAR9;
input VAR5;
input VAR6 ;
input VAR16 ;
wire VAR14 ;
wire VAR11;
VAR12 VAR1 (VAR11, VAR17, VAR15, VAR13 );
VAR8 VAR4 VAR2 (VAR14 , VAR11, VAR3, , VAR9, VAR5)... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a211o/sky130_fd_sc_hdll__a211o_4.v | 2,364 | module MODULE1 (
VAR4 ,
VAR6 ,
VAR5 ,
VAR1 ,
VAR3 ,
VAR9,
VAR7,
VAR10 ,
VAR2
);
output VAR4 ;
input VAR6 ;
input VAR5 ;
input VAR1 ;
input VAR3 ;
input VAR9;
input VAR7;
input VAR10 ;
input VAR2 ;
VAR8 VAR11 (
.VAR4(VAR4),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR10(VAR10),
.VAR... | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/cpci/pci_userapp.v | 10,489 | module MODULE1 (
input VAR36,
input VAR45,
input VAR65,
input VAR93,
input VAR64,
input [31:0] VAR51,
inout [31:0] VAR2,
input VAR39,
input VAR84,
output reg VAR78,
output reg VAR1,
input VAR17,
input [7:0] VAR92,
output reg VAR30,
output reg VAR28,
output reg VAR69,
input VAR29,
input VAR80,
input VAR34,
input [3:0] V... | mit |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/fme/fme_interpolator_8x8.v | 47,168 | module MODULE1 (
clk ,
VAR292 ,
VAR191 ,
VAR325 ,
VAR236 ,
VAR439 ,
VAR333 ,
VAR412 ,
VAR220 ,
VAR390 ,
VAR360 ,
VAR187 ,
VAR363 ,
VAR219 ,
VAR320 ,
VAR432 ,
VAR340 ,
VAR388 ,
VAR317 ,
VAR129 ,
VAR69 ,
VAR367 ,
VAR288 ,
VAR201 ,
VAR96 ,
VAR440 ,
VAR377 ,
VAR103 ,
VAR420 ,
VAR209 ,
VAR223 ,
VAR429 ,
VAR339 ,
VAR373 ,
VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o32ai/sky130_fd_sc_ms__o32ai.functional.pp.v | 2,191 | module MODULE1 (
VAR16 ,
VAR9 ,
VAR13 ,
VAR19 ,
VAR17 ,
VAR6 ,
VAR20,
VAR3,
VAR10 ,
VAR4
);
output VAR16 ;
input VAR9 ;
input VAR13 ;
input VAR19 ;
input VAR17 ;
input VAR6 ;
input VAR20;
input VAR3;
input VAR10 ;
input VAR4 ;
wire VAR11 ;
wire VAR7 ;
wire VAR12 ;
wire VAR18;
nor VAR15 (VAR11 , VAR19, VAR9, VAR13 );
no... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o211a/sky130_fd_sc_ms__o211a_1.v | 2,348 | module MODULE1 (
VAR7 ,
VAR9 ,
VAR2 ,
VAR1 ,
VAR11 ,
VAR3,
VAR10,
VAR4 ,
VAR5
);
output VAR7 ;
input VAR9 ;
input VAR2 ;
input VAR1 ;
input VAR11 ;
input VAR3;
input VAR10;
input VAR4 ;
input VAR5 ;
VAR6 VAR8 (
.VAR7(VAR7),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR11(VAR11),
.VAR3(VAR3),
.VAR10(VAR10),
.VAR4(VAR4),
.... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/mux2/gf180mcu_fd_sc_mcu9t5v0__mux2_1.functional.v | 1,043 | module MODULE1( VAR12, VAR6, VAR13, VAR4 );
input VAR4, VAR6, VAR13;
output VAR12;
wire VAR10;
and VAR5( VAR10, VAR4, VAR6 );
wire VAR2;
not VAR9( VAR2, VAR13 );
wire VAR1;
and VAR11( VAR1, VAR2, VAR4 );
wire VAR3;
and VAR8( VAR3, VAR6, VAR13 );
or VAR7( VAR12, VAR10, VAR1, VAR3 );
endmodule | apache-2.0 |
kramble/FPGA-Litecoin-Miner | experimental/LX150-SPLIT/salsaengine.v | 10,997 | module MODULE1 (VAR40, reset, din, dout, VAR45, VAR46, VAR15, VAR59 );
input VAR40, reset, din, VAR45, VAR46;
output reg VAR15 = 1'b0;
output reg VAR59 = 1'b0;
output dout;
parameter VAR8 = 0, VAR54 = 1, VAR19 = 2, VAR21 = 4; reg [2:0] VAR44 = VAR8;
parameter VAR60=0, VAR27=1, VAR26=2, VAR28=4, VAR35=8; reg [3:0] VAR38... | gpl-3.0 |
kyzhai/NUNY | src/hardware/tryagain.v | 6,388 | module MODULE1 (
address,
VAR36,
VAR39);
input [11:0] address;
input VAR36;
output [11:0] VAR39;
tri1 VAR36;
wire [11:0] VAR33;
wire [11:0] VAR39 = VAR33[11:0];
VAR13 VAR20 (
.VAR40 (address),
.VAR50 (VAR36),
.VAR31 (VAR33),
.VAR21 (1'b0),
.VAR42 (1'b0),
.VAR11 (1'b1),
.VAR34 (1'b0),
.VAR7 (1'b0),
.VAR16 (1'b1),
.VAR19... | gpl-2.0 |
shailcoolboy/Warp-Trinity | ResearchApps/PHY/MIMO_OFDM/ConvCoded/fec_encoder.v | 21,494 | module MODULE1 (
clk , VAR50 , VAR7 , VAR17 , VAR42 , VAR87 , VAR83 , VAR34 , VAR54 , VAR38 , VAR19 , VAR21 , VAR98 , VAR53 ) ;
input clk ;
input VAR50 ;
input VAR7 ;
input VAR17 ;
input VAR42 ;
input VAR87 ;
input VAR83 ;
input [7:0] VAR34 ;
input [7:0] VAR54 ;
input [15:0] VAR38 ;
output [15:0] VAR19 ;
output VAR21 ;... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o22a/sky130_fd_sc_ls__o22a.behavioral.pp.v | 2,156 | module MODULE1 (
VAR12 ,
VAR1 ,
VAR10 ,
VAR14 ,
VAR15 ,
VAR16,
VAR13,
VAR19 ,
VAR3
);
output VAR12 ;
input VAR1 ;
input VAR10 ;
input VAR14 ;
input VAR15 ;
input VAR16;
input VAR13;
input VAR19 ;
input VAR3 ;
wire VAR2 ;
wire VAR5 ;
wire VAR17 ;
wire VAR8;
or VAR6 (VAR2 , VAR10, VAR1 );
or VAR18 (VAR5 , VAR15, VAR14 );... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/or2/gf180mcu_fd_sc_mcu7t5v0__or2_2.behavioral.v | 1,173 | module MODULE1( VAR1, VAR5, VAR2 );
input VAR1, VAR5;
output VAR2;
VAR6 VAR3(.VAR1(VAR1),.VAR5(VAR5),.VAR2(VAR2));
VAR6 VAR4(.VAR1(VAR1),.VAR5(VAR5),.VAR2(VAR2)); | apache-2.0 |
vad-rulezz/megabot | minsoc/rtl/verilog/ethmac/rtl/verilog/eth_transmitcontrol.v | 10,426 | module MODULE1 (VAR4, VAR10, VAR2, VAR5, VAR28, VAR18,
VAR14, VAR22, VAR16, VAR1, VAR15,
VAR20, VAR6, VAR23, VAR13, VAR11, VAR21,
VAR24, VAR30, VAR8
);
input VAR4;
input VAR10;
input VAR2;
input VAR5;
input VAR28;
input VAR18;
input VAR14;
input VAR22;
input VAR16;
input VAR1;
input VAR15;
input [15:0] VAR20;
input [47... | gpl-2.0 |
hpeng2/ECE492_Group4_Project | Ryans_stuff/tracking_camera/tracking_camera_system/synthesis/submodules/tracking_camera_system_nios2_qsys_0_jtag_debug_module_sysclk.v | 7,360 | module MODULE1 (
clk,
VAR20,
VAR19,
VAR3,
VAR32,
VAR31,
VAR22,
VAR12,
VAR23,
VAR18,
VAR21,
VAR4,
VAR27,
VAR6,
VAR16,
VAR29,
VAR25,
VAR15,
VAR26
)
;
output [ 37: 0] VAR31;
output VAR22;
output VAR12;
output VAR23;
output VAR18;
output VAR21;
output VAR4;
output VAR27;
output VAR6;
output VAR16;
output VAR29;
output VAR2... | gpl-2.0 |
cfangmeier/VFPIX-telescope-Code | DAQ_Firmware/src/ram/alt_mem_ddrx_addr_cmd_wrap.v | 55,196 | module MODULE1
VAR159 = 2,
VAR202 = 2, VAR69 = 16, VAR135 = 16, VAR122 = 12, VAR157 = 3, VAR91 = 1,
VAR174 = 3,
VAR115 = 2,
VAR178 = 2,
VAR34 = 8,
VAR127 = 4,
VAR50 = 4,
VAR49 = 1,
VAR118 = 2,
VAR33 = 5,
VAR153 = 5,
VAR163 = 5,
VAR54 = 4,
VAR107 = 4,
VAR195 = 2
)
(
VAR212,
VAR86,
VAR70,
VAR44,
VAR37,
VAR171,
VAR150,
VA... | gpl-2.0 |
intelligenttoasters/CPC2.0 | FPGA/Quartus/custom/usb/wrapper/usbHostSlave.v | 19,515 | module MODULE1(
VAR89,
VAR120,
VAR193,
VAR115,
VAR108,
VAR82,
VAR195,
VAR72,
VAR18,
VAR96,
VAR76,
VAR137,
VAR61,
VAR173,
VAR175,
VAR40,
VAR17,
VAR123,
VAR148,
VAR19,
VAR161,
VAR78,
VAR68,
VAR153,
VAR164,
VAR183,
VAR97,
VAR37
);
parameter VAR26 = 64; parameter VAR132 = 6;
parameter VAR146 = 64;
parameter VAR190 = 6;
par... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o21ai/sky130_fd_sc_hs__o21ai.behavioral.v | 1,931 | module MODULE1 (
VAR5 ,
VAR13 ,
VAR7 ,
VAR4 ,
VAR1,
VAR14
);
output VAR5 ;
input VAR13 ;
input VAR7 ;
input VAR4 ;
input VAR1;
input VAR14;
wire VAR10 ;
wire VAR3 ;
wire VAR9;
or VAR11 (VAR10 , VAR7, VAR13 );
nand VAR6 (VAR3 , VAR4, VAR10 );
VAR2 VAR12 (VAR9, VAR3, VAR1, VAR14);
buf VAR8 (VAR5 , VAR9 );
endmodule | apache-2.0 |
kactus2/ipxactexamplelib | tut.fi/cpu.logic/clock/1.0/clock.v | 1,314 | module MODULE1 #(
parameter VAR5 = 2 ) (
output VAR1, output VAR3,
input VAR2, input VAR4 );
assign VAR1 = VAR2;
assign VAR3 = VAR4;
endmodule | mit |
FAST-Switch/fast | lib/hardware/platform/NetMagic08/cdp/ddio_in_1.v | 4,596 | module MODULE1 (
VAR23,
VAR2,
VAR25,
VAR4,
VAR11);
input VAR23;
input VAR2;
input VAR25;
output VAR4;
output VAR11;
tri0 VAR23;
wire [0:0] VAR3;
wire [0:0] VAR1;
wire [0:0] VAR7 = VAR3[0:0];
wire VAR4 = VAR7;
wire [0:0] VAR10 = VAR1[0:0];
wire VAR11 = VAR10;
wire VAR6 = VAR2;
wire VAR9 = VAR6;
VAR21 VAR19 (
.VAR2 (VAR9... | apache-2.0 |
chebykinn/university | circuitry/lab3/src/hdl/dp_memory.v | 2,393 | module MODULE1 #(
parameter VAR18 = 32'h00000fff,
parameter VAR7 = 32'h00000000)(
input wire clk,
input wire rst,
input wire VAR12,
input wire [31:0] VAR17,
output wire [31:0] VAR11,
output VAR13,
input wire VAR16,
input wire VAR24,
input wire [31:0] VAR14,
input wire [31:0] VAR2,
output wire [31:0] VAR1,
input [31:0] ... | mit |
abjordan/RECON2014 | wishbone_uart_tx/tx_port.v | 2,737 | module MODULE1(
input wire VAR1,
input wire VAR14,
output reg VAR13,
input wire [7:0] VAR9,
input wire [3:0] VAR7,
output reg [7:0] VAR16,
input wire VAR11,
input wire VAR3,
output wire dout);
reg [7:0] VAR8;
reg VAR5;
wire VAR2;
reg VAR6;
VAR10 VAR4(
.clk(VAR1),
.rst(VAR14),
.en(VAR5),
.VAR15(VAR8),
.VAR12(VAR2),
.dou... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlxbp/sky130_fd_sc_hs__dlxbp.pp.symbol.v | 1,325 | module MODULE1 (
input VAR4 ,
output VAR3 ,
output VAR5 ,
input VAR1,
input VAR6,
input VAR2
);
endmodule | apache-2.0 |
DreamSourceLab/DSLogic-hdl | src/ipcore_dir/cfifo.v | 13,897 | module MODULE1(
clk,
rst,
din,
VAR312,
VAR190,
dout,
VAR249,
VAR6,
VAR383,
VAR84
);
input clk;
input rst;
input [15 : 0] din;
input VAR312;
input VAR190;
output [15 : 0] dout;
output VAR249;
output VAR6;
output [12 : 0] VAR383;
output VAR84;
VAR338 #(
.VAR47(0),
.VAR41(0),
.VAR10(0),
.VAR56(0),
.VAR266(0),
.VAR385(0),
... | gpl-2.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_059.v | 1,471 | module MODULE1 (
VAR3,
VAR1
);
input [31:0] VAR3;
output [31:0]
VAR1;
wire [31:0]
VAR13,
VAR4,
VAR5,
VAR7,
VAR12,
VAR11,
VAR6,
VAR8;
assign VAR13 = VAR3;
assign VAR11 = VAR13 << 10;
assign VAR4 = VAR13 << 7;
assign VAR5 = VAR13 + VAR4;
assign VAR12 = VAR5 + VAR7;
assign VAR8 = VAR6 << 2;
assign VAR7 = VAR13 << 2;
assig... | mit |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeDE1SoC/Computer_System/synthesis/submodules/altera_up_RGB_to_YCrCb_converter.v | 14,692 | module MODULE1 (
clk,
VAR26,
reset,
VAR7,
VAR56,
VAR60,
VAR47,
VAR34,
VAR8,
VAR42,
VAR15,
VAR66,
VAR20,
VAR2,
VAR18,
VAR24,
VAR25
);
input clk;
input VAR26;
input reset;
input [ 7: 0] VAR7;
input [ 7: 0] VAR56;
input [ 7: 0] VAR60;
input VAR47;
input VAR34;
input VAR8;
input VAR42;
output reg [ 7: 0] VAR15;
output reg ... | mit |
sh-chris110/chris | FPGA/HPS.bak/db/ip/hps_design/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v | 9,229 | module MODULE1(
VAR60,
VAR21,
VAR81,
VAR54,
VAR52,
VAR17,
VAR121,
VAR89,
VAR47,
VAR120,
VAR13,
VAR58,
VAR3,
VAR56,
VAR106,
VAR39,
VAR93,
VAR97,
VAR103,
VAR30,
VAR61,
VAR63,
VAR96,
VAR11,
VAR10,
VAR126,
VAR20,
VAR79,
VAR77
);
parameter VAR23 = "";
parameter VAR84 = "";
parameter VAR69 = "";
parameter VAR122 = "";
parame... | gpl-2.0 |
cafe-alpha/wasca | fpga_firmware/wasca/synthesis/submodules/wasca_mm_interconnect_0_avalon_st_adapter_002.v | 6,152 | module MODULE1 #(
parameter VAR2 = 10,
parameter VAR17 = 0,
parameter VAR5 = 10,
parameter VAR8 = 0,
parameter VAR4 = 0,
parameter VAR6 = 0,
parameter VAR22 = 1,
parameter VAR7 = 1,
parameter VAR19 = 0,
parameter VAR12 = 10,
parameter VAR3 = 0,
parameter VAR9 = 1,
parameter VAR24 = 0,
parameter VAR15 = 1,
parameter VAR... | gpl-2.0 |
fpgaminer/fpgaminer-vanitygen | cores/vanitygen-serial/ff_reduce.v | 2,010 | module MODULE1 (
input clk,
input reset,
input [511:0] VAR2,
output reg VAR9,
output reg [255:0] VAR6
);
reg [3:0] VAR5;
reg [259:0] VAR4;
reg [32:0] VAR11;
reg [64:0] VAR8;
wire [34:0] VAR3 = {VAR11, 2'd0} + {VAR11, 1'd0} + VAR11;
wire [255:0] VAR10 = VAR2[511:256];
reg [255:0] VAR1;
wire [260:0] VAR7 = VAR4 - 256'hFF... | gpl-3.0 |
kyzhai/NUNY | src/hardware/bg1_new.v | 6,392 | module MODULE1 (
address,
VAR37,
VAR14);
input [14:0] address;
input VAR37;
output [11:0] VAR14;
tri1 VAR37;
wire [11:0] VAR20;
wire [11:0] VAR14 = VAR20[11:0];
VAR7 VAR23 (
.VAR31 (address),
.VAR29 (VAR37),
.VAR3 (VAR20),
.VAR35 (1'b0),
.VAR52 (1'b0),
.VAR22 (1'b1),
.VAR12 (1'b0),
.VAR51 (1'b0),
.VAR1 (1'b1),
.VAR25 (... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nand2b/sky130_fd_sc_ls__nand2b.blackbox.v | 1,276 | module MODULE1 (
VAR1 ,
VAR5,
VAR7
);
output VAR1 ;
input VAR5;
input VAR7 ;
supply1 VAR6;
supply0 VAR2;
supply1 VAR4 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
GSejas/Karatsuba_FPU | Resultados/CORDIC/CORDIC_Arch3_Vivado/CORDIC_Arch3_Vivado.srcs/sources_1/imports/Floating-Point-Unit-master/Coprocesador_CORDIC_RTL/sine_cosine_CORDIC/Mux_3x1_b_v2.v | 1,033 | module MODULE1 #(parameter VAR4=32)
(
input wire [1:0] select,
input wire [VAR4-1:0] VAR2,
input wire [VAR4-1:0] VAR5,
input wire [VAR4-1:0] VAR1,
output reg [VAR4-1:0] VAR3
);
always @*
begin
case(select)
2'b00: VAR3 <= {VAR4{1'b0}};
2'b01: VAR3 <= VAR2;
2'b10: VAR3 <= VAR5;
2'b11: VAR3 <= VAR1;
default : VAR3 <= VAR2... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_io | cells/top_power_hvc_wpad/sky130_fd_io__top_power_hvc_wpad.pp.symbol.v | 1,805 | module MODULE1 (
inout VAR4 ,
inout VAR3 ,
inout VAR8 ,
inout VAR10 ,
inout VAR2 ,
inout VAR13 ,
inout VAR15 ,
inout VAR5,
inout VAR16 ,
inout VAR12 ,
inout VAR14 ,
inout VAR11 ,
inout VAR6 ,
inout VAR1 ,
inout VAR7 ,
inout VAR17 ,
inout VAR9
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/ebufn/sky130_fd_sc_lp__ebufn_8.v | 2,148 | module MODULE1 (
VAR1 ,
VAR7 ,
VAR9,
VAR5,
VAR3,
VAR2 ,
VAR6
);
output VAR1 ;
input VAR7 ;
input VAR9;
input VAR5;
input VAR3;
input VAR2 ;
input VAR6 ;
VAR4 VAR8 (
.VAR1(VAR1),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR6(VAR6)
);
endmodule
module MODULE1 (
VAR1 ,
VAR7 ,
VAR9
);
output VAR1 ;... | apache-2.0 |
manu3193/ControladorElevadorTDD | Ascensor.v | 3,775 | module MODULE1( clk,VAR17,VAR42,VAR73,VAR53,VAR43,VAR40,
VAR60,VAR31,VAR22,VAR72,VAR66,VAR64,VAR18,
VAR9,VAR11,VAR59,VAR28,VAR65,VAR32,VAR37,VAR38,VAR10);
wire [1:0] VAR25;
wire VAR44;
wire VAR62;
wire VAR19;
wire VAR45;
wire VAR7;
wire VAR29;
wire VAR12;
wire VAR16;
wire VAR8;
wire VAR71;
VAR51 VAR3(
.VAR4 (VAR25),
.V... | mit |
plindstroem/oh | elink/hdl/erx_protocol.v | 2,835 | module MODULE1 (
VAR18, VAR2, VAR10,
reset, VAR3, clk, VAR1, VAR9, VAR17
);
parameter VAR5 = 32;
parameter VAR4 = 32;
parameter VAR15 = 104;
parameter VAR13 = 12'h800;
input reset;
input VAR3;
input clk;
input [VAR15-1:0] VAR1;
input VAR9;
input VAR17;
output VAR18;
output VAR2;
output [VAR15-1:0] VAR10;
reg [31:0] VAR... | gpl-3.0 |
jotego/jt12 | hdl/jt12_kon.v | 4,156 | module MODULE1(
input rst,
input clk,
input VAR24 ,
input [3:0] VAR31,
input [2:0] VAR15,
input [1:0] VAR22,
input [2:0] VAR26,
input VAR20,
input VAR19,
input VAR8,
output reg VAR33
);
parameter VAR2=6;
wire VAR10;
generate
if(VAR2==6) begin
reg VAR6;
reg [4:0] VAR21;
always @(posedge clk) if( VAR24 ) begin
if(VAR8) b... | gpl-3.0 |
SI-RISCV/e200_opensource | rtl/e203/core/e203_exu_wbck.v | 4,898 | module MODULE1(
input VAR13, output VAR6, input [VAR17-1:0] VAR1,
input [VAR11-1:0] VAR22,
input VAR20, output VAR4, input [VAR9-1:0] VAR24,
input [5-1:0] VAR14,
input [VAR11-1:0] VAR8,
input VAR5,
output VAR30,
output [VAR17-1:0] VAR7,
output [VAR11-1:0] VAR10,
input clk,
input VAR21
);
wire VAR27 = (~VAR20);
wire VAR... | apache-2.0 |
CospanDesign/python | pyqt/syntax-highlighter/wb_gpio.v | 9,363 | module MODULE1#(
parameter VAR28 = 0,
parameter VAR23 = 0,
parameter VAR15 = 0,
parameter VAR30 = 0
)(
input clk,
input rst,
output [31:0] VAR24,
input VAR8,
input VAR3,
input [3:0] VAR10,
input [31:0] VAR37,
input VAR16,
output reg VAR13,
output reg [31:0] VAR40,
input [31:0] VAR4,
output reg VAR34,
output reg [31:0] ... | mit |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src_previous/small_fifo_syn.v | 184,961 | module MODULE2
(
VAR27,
VAR30,
VAR6,
VAR57,
VAR31,
VAR33) ;
input VAR27;
input VAR30;
input VAR6;
output [2:0] VAR57;
input VAR31;
input VAR33;
tri0 VAR27;
tri1 VAR6;
tri0 VAR31;
tri1 VAR33;
wire [0:0] VAR36;
wire [0:0] VAR51;
wire [0:0] VAR16;
wire [0:0] VAR48;
wire [0:0] VAR4;
wire [2:0] VAR37;
wire [2:0] VAR7;
wire ... | mit |
CospanDesign/nysa-artemis-usb2-platform | artemis_usb2/slave/wb_artemis_usb2_platform/rtl/aps.v | 14,776 | module MODULE1 #(
parameter VAR61 = 0, parameter VAR133 = 6,
parameter VAR11 = 4,
parameter VAR6 = 2,
parameter VAR36 = 5,
parameter VAR75 = 1,
parameter VAR137 = 2,
parameter VAR48 = 0 )(
input [1:0] VAR39,
input [1:0] VAR160,
input VAR94,
input VAR73,
input VAR74,
input VAR122,
output VAR131,
output VAR66,
output VAR... | gpl-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_tag/bsg_tag_trace_replay.v | 5,698 | module MODULE1
, parameter VAR29(VAR20 )
, parameter VAR27 = 0
, parameter VAR29(VAR23 )
, parameter VAR29(VAR47 )
, parameter VAR10 = 0)
( input VAR44
, input VAR11
, input VAR24
, output [VAR43-1:0] VAR5
, input [VAR20-1:0] VAR12
, input VAR46
, input [VAR47-1:0] VAR6
, output VAR17
, output VAR8
, output [VAR40(1,VA... | bsd-3-clause |
kyzhai/NUNY | src/hardware/three_new2_bb.v | 5,028 | module MODULE1 (
address,
VAR1,
VAR2);
input [9:0] address;
input VAR1;
output [11:0] VAR2;
tri1 VAR1;
endmodule | gpl-2.0 |
FAST-Switch/fast | lib/hardware/pipeline/IPE_IF_OPENFLOW/mac_sgmii/altera_tse_reset_synchronizer.v | 4,426 | module MODULE1
parameter VAR5 = 1,
parameter VAR2 = 2
)
(
input VAR4 ,
input clk,
output VAR1
);
reg [VAR2-1:0] VAR3;
reg VAR6;
generate if (VAR5) begin
always @(posedge clk or posedge VAR4) begin
if (VAR4) begin
VAR3 <= {VAR2{1'b1}};
VAR6 <= 1'b1;
end
else begin
VAR3[VAR2-2:0] <= VAR3[VAR2-1:1];
VAR3[VAR2-1] <= 0;
VAR... | apache-2.0 |
jouyang3/FMCW | DSP/Radar_DSP/FPGA/magnitude.v | 1,615 | module MODULE2(VAR11, VAR8, VAR6, VAR5, VAR22, VAR2);
input [11:0] VAR11, VAR8, VAR6, VAR5;
output [11:0] VAR22, VAR2;
wire [11:0] VAR1, VAR24, VAR15, VAR23;
wire [11:0] VAR17, VAR14, VAR13, VAR9;
MODULE3 MODULE6 (.in(VAR11), .out(VAR17));
MODULE3 MODULE5 (.in(VAR8), .out(VAR14));
MODULE3 MODULE2 (.in(VAR6), .out(VAR13... | gpl-3.0 |
stpr18/verilog-processor | sys_command.v | 1,317 | module MODULE1(input [47:0] VAR14, input VAR4, input [15:0] VAR15, VAR11, VAR12, VAR1, VAR2, VAR9, VAR3, VAR10, VAR6, flag, input en);
always @(posedge en) begin
case (VAR14[39:36])
end
case (VAR14[35:32])
if (VAR4)
("%VAR8", VAR15);
else
("%VAR8", VAR15[7:0]);
end
if (VAR4)
("%VAR7", VAR15);
else
("%VAR7", VAR15[7:0])... | unlicense |
tmolteno/TART | hardware/FPGA/tart_spi/verilog/fifo/fifo_dc_gray.v | 9,852 | module MODULE1 (
VAR29,
VAR17,
rst,
VAR8,
din,
VAR35,
dout,
VAR38,
VAR6,
VAR19,
VAR31,
VAR25
);
parameter VAR10=16;
parameter VAR34=4;
parameter VAR23=16;
input VAR29, VAR17, rst, VAR8;
input [VAR10-1:0] din;
input VAR35;
output [VAR10-1:0] dout;
input VAR38;
output VAR6;
output VAR19;
output [1:0] VAR31;
output [1:0] ... | lgpl-3.0 |
alexforencich/verilog-ethernet | example/VCU118/fpga_10g/rtl/fpga.v | 34,798 | module MODULE1 (
input wire VAR100,
input wire VAR198,
input wire reset,
input wire VAR97,
input wire VAR359,
input wire VAR296,
input wire VAR49,
input wire VAR219,
input wire [3:0] VAR234,
output wire [7:0] VAR261,
inout wire VAR5,
inout wire VAR141,
output wire VAR54,
output wire VAR6,
input wire VAR173,
input wire ... | mit |
ShepardSiegel/ocpi | coregen/pcie_4243_axi_k7_x4_125/example_design/PIO.v | 5,825 | module MODULE1 #(
parameter VAR5 = 64,
parameter VAR17 = VAR5 / 8, parameter VAR9 = 1
)(
input VAR14,
input VAR24,
input VAR7,
input VAR18,
output [VAR5-1:0] VAR29,
output [VAR17-1:0] VAR10,
output VAR19,
output VAR12,
output VAR4,
input [VAR5-1:0] VAR22,
input [VAR17-1:0] VAR23,
input VAR3,
input VAR21,
output VAR15,
... | lgpl-3.0 |
cpulabs/mist1032isa | src/core/execute/execute_div.v | 2,133 | module MODULE1(
input wire VAR12,
input wire VAR5,
input wire VAR10,
output wire VAR1,
input wire VAR21,
input wire VAR19,
input wire VAR32,
input wire [4:0] VAR29,
input wire [31:0] VAR2,
input wire [31:0] VAR14,
input wire VAR28,
output wire VAR18,
output wire [31:0] VAR17
);
wire VAR34 = VAR21 && (VAR19 || VAR32) &&... | bsd-2-clause |
KorotkiyEugene/Netmaker_vc_router_syn_quartus | NW_vc_input_port.v | 6,020 | module MODULE1(VAR6, VAR2, VAR5, VAR44, select, VAR42, VAR11, VAR33,
VAR16, VAR13,
VAR14, VAR29,
VAR28, VAR40,
VAR37,
VAR22,
clk, VAR20);
parameter VAR3 = 4;
parameter VAR35 = 8;
parameter VAR34 = 0;
parameter VAR36 = 0;
input VAR6, clk, VAR20;
input [VAR3-1:0] VAR2;
input VAR39 VAR5;
output VAR39 VAR42;
output VAR43 V... | gpl-2.0 |
EPiCS/reconos | designs/microblaze_linux_ml605_minimal_14.7/__xps/DDR3_SDRAM/wiredly.v | 5,295 | module MODULE1 # (
parameter VAR11 = 0,
parameter VAR3 = 0,
parameter VAR8 = "VAR13"
)
(
inout VAR6,
inout VAR4,
input reset,
input VAR12
);
reg VAR2;
reg VAR9;
reg VAR10 ;
reg VAR14;
reg VAR5;
assign VAR6 = VAR2;
assign VAR4 = VAR9;
always @
begin
if((VAR5 == 'b1) || (VAR5 == 'b0))
VAR10 <= ~VAR5 ;
end
else
VAR10 <= '... | gpl-2.0 |
Jawanga/ece385final | usb_system/synthesis/submodules/altera_avalon_mm_clock_crossing_bridge.v | 11,534 | module MODULE1
parameter VAR39 = 32,
parameter VAR87 = 8,
parameter VAR17 = 10,
parameter VAR50 = 1,
parameter VAR32 = 4,
parameter VAR71 = 4,
parameter VAR30 = 2,
parameter VAR57 = 2,
parameter VAR9 = VAR39 / VAR87
)
(
input VAR91,
input VAR47,
input VAR75,
input VAR22,
output VAR82,
output [VAR39-1:0] VAR12,
output V... | apache-2.0 |
The-OpenROAD-Project/asap7 | asap7sc6t_26/Verilog/asap7sc6t_CKINVDC_RVT_TT_210930.v | 11,788 | module MODULE1 (VAR2, VAR1);
output VAR2;
input VAR1;
not (VAR2, VAR1); | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nor2/sky130_fd_sc_hd__nor2.functional.pp.v | 1,783 | module MODULE1 (
VAR3 ,
VAR1 ,
VAR10 ,
VAR11,
VAR8,
VAR12 ,
VAR13
);
output VAR3 ;
input VAR1 ;
input VAR10 ;
input VAR11;
input VAR8;
input VAR12 ;
input VAR13 ;
wire VAR9 ;
wire VAR2;
nor VAR6 (VAR9 , VAR1, VAR10 );
VAR5 VAR4 (VAR2, VAR9, VAR11, VAR8);
buf VAR7 (VAR3 , VAR2 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a222oi/sky130_fd_sc_ms__a222oi.behavioral.v | 1,831 | module MODULE1 (
VAR4 ,
VAR20,
VAR15,
VAR19,
VAR12,
VAR7,
VAR8
);
output VAR4 ;
input VAR20;
input VAR15;
input VAR19;
input VAR12;
input VAR7;
input VAR8;
supply1 VAR11;
supply0 VAR10;
supply1 VAR2 ;
supply0 VAR16 ;
wire VAR5 ;
wire VAR17 ;
wire VAR18 ;
wire VAR1;
nand VAR13 (VAR5 , VAR15, VAR20 );
nand VAR3 (VAR17 , ... | apache-2.0 |
jaruiz/ION | src/rtl/mcu.v | 3,149 | module MODULE1 # (
parameter VAR26 = 1024
)
(
input VAR18,
input VAR23,
input [31:0] VAR20,
output reg [31:0] VAR6
);
wire [31:0] VAR9;
wire [ 1:0] VAR2;
reg VAR10;
reg [ 1:0] VAR4;
reg [31:0] VAR3;
wire [31:0] VAR11;
wire [ 1:0] VAR22;
wire [ 2:0] VAR14;
reg VAR7;
reg [ 1:0] VAR27;
reg [31:0] VAR17;
wire [31:0] VAR1;
... | lgpl-3.0 |
danbone/core | riscv_core.v | 3,512 | module MODULE1 (
input clk,
input VAR10,
output [VAR4-1:0] VAR22,
input [VAR11-1:0] VAR16,
output [VAR4-1:0] VAR15,
output VAR29,
output VAR19,
output [(VAR17/8)-1:0] VAR14,
output [VAR17-1:0] VAR27,
input [VAR17-1:0] VAR5,
output VAR13
);
localparam VAR7 = 7'b0010011;
localparam VAR8 = 7'b0110111;
localparam VAR1 = 7'... | mit |
mballance/wb_dma | rtl/wb_dma_ch_rf.v | 16,992 | module MODULE2( clk, rst,
VAR39, VAR76, VAR55, VAR66, VAR86, VAR71,
VAR47, VAR36, VAR2, VAR64, VAR4, int,
VAR73, VAR35, VAR51, VAR54,
VAR8, VAR44,
VAR46, VAR34, VAR69, VAR41,
VAR6, VAR24, VAR45, VAR43,
VAR20, VAR32, VAR1, VAR85,
VAR17, VAR74,
VAR83
);
parameter [4:0] VAR11 = 5'h0; parameter [0:0] VAR52 = 1'b1; paramete... | apache-2.0 |
sharebrained/medusa | hdl/medusa_cape/top.v | 12,376 | module MODULE1 (
input VAR119,
input [23:0] VAR48,
input VAR120,
input VAR43,
input VAR17,
input VAR34,
output [31:0] VAR77,
output [7:0] VAR33,
output VAR51,
input VAR24,
output VAR31,
output VAR63
);
parameter VAR94 = 0,
VAR36 = 1;
parameter VAR72 = VAR36;
wire rst;
VAR130 VAR62 (
.clk(VAR119),
.rst(rst)
);
assign VA... | gpl-2.0 |
BilkentCompGen/GateKeeper | FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/riffa/reorder_queue_output.v | 10,586 | module MODULE1 #(
parameter VAR54 = 9'd128,
parameter VAR5 = 4'd12,
parameter VAR41 = 5, parameter VAR44 = 8, parameter VAR9 = 5, parameter VAR39 = 10, parameter VAR4 = VAR54/32,
parameter VAR51 = VAR7(VAR4),
parameter VAR34 = VAR7(VAR4+1),
parameter VAR53 = 2**VAR41
)
(
input VAR46, input VAR22, output [VAR39-1:0] VAR... | gpl-3.0 |
alonso193/proyecto1 | BloqueDATA.v | 8,639 | module MODULE1(
input wire VAR37,
input wire VAR65,
input wire VAR8,
input wire [15:0] VAR11,
input wire VAR61,
input wire [3:0] VAR45,
input wire VAR51,
input wire VAR41,
input wire VAR16,
input wire [31:0] VAR68,
input wire VAR59,
input wire VAR43,
output wire VAR60,
output wire VAR39,
output wire [31:0] VAR3,
output... | gpl-3.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/adi_common_v1_00_a/hdl/verilog/ad_gt_channel_1.v | 19,987 | module MODULE1 (
rst,
VAR446,
VAR260,
VAR179,
VAR160,
VAR121,
VAR366,
VAR253,
VAR293,
VAR254,
VAR250,
VAR233,
VAR140,
VAR105,
VAR356,
VAR421,
VAR131,
VAR202,
VAR461,
VAR148,
VAR146,
VAR324,
VAR387,
VAR149,
VAR311,
VAR81,
VAR50,
VAR103,
VAR142,
VAR51,
VAR203,
VAR9,
VAR215,
VAR439,
VAR188,
VAR134,
VAR8,
VAR473);
paramete... | mit |
glennchid/font5-firmware | src/verilog/synthesis/LUTCalc.v | 3,389 | module MODULE1(
input clk,
input VAR20,
input [6:0] VAR2,
input [14:0] VAR35,
input VAR16,
output [6:0] VAR41,
input [6:0] VAR24,
input [14:0] VAR18,
input VAR21,
output [6:0] VAR28,
input [6:0] VAR11,
input [14:0] VAR6,
input VAR40,
output [6:0] VAR42,
input [6:0] VAR33,
input [14:0] VAR9,
input VAR27,
output [6:0] VA... | gpl-3.0 |
18545/FPGA | project_1.srcs/sources_1/ip/ila_0/ila_0_stub.v | 1,384 | module MODULE1(clk, VAR1, VAR5, VAR2, VAR4, VAR3)
;
input clk;
output VAR1;
input VAR5;
input VAR2;
output VAR4;
input [0:0]VAR3;
endmodule | mit |
scalable-networks/ext | uhd/fpga/usrp2/control_lib/priority_enc.v | 3,009 | module MODULE1
(input [31:0] in,
output reg [31:0] out);
always @*
casex(in)
32'VAR24 : out <= 31;
32'VAR8 : out <= 30;
32'VAR1 : out <= 29;
32'VAR5 : out <= 28;
32'VAR25 : out <= 27;
32'VAR3 : out <= 26;
32'VAR10 : out <= 25;
32'VAR20 : out <= 24;
32'VAR21 : out <= 23;
32'VAR13 : out <= 22;
32'VAR23 : out <= 21;
32'VA... | gpl-2.0 |
fzyz999/5-stage-MIPS | datapath/muldiv.v | 1,701 | module MODULE1 (VAR7,VAR12,VAR13,VAR14,VAR1,VAR6,VAR2,VAR5,VAR9,clk,rst);
input [31:0] VAR7,VAR12;
input VAR13;
input [1:0] VAR14;
input VAR1,VAR6,clk,rst;
output VAR2;
output [31:0] VAR5,VAR9;
reg [3:0] VAR3;
reg VAR2;
reg [63:0] VAR13;
reg [31:0] VAR7,VAR12;
reg [1:0] VAR14;
wire [63:0] VAR11,VAR16;
assign VAR11=(VAR... | mit |
ShepardSiegel/ocpi | rtl/mkWsiAdapter16B4B.v | 30,668 | module MODULE1(VAR157,
VAR189,
VAR97,
VAR87,
VAR62,
VAR163,
VAR45,
VAR18,
VAR2,
VAR170,
VAR175,
VAR132,
VAR141,
VAR193,
VAR19,
VAR113,
VAR65,
VAR120,
VAR180,
VAR6,
VAR152,
VAR22);
input VAR157;
input VAR189;
input [2 : 0] VAR97;
input VAR87;
input VAR62;
input [11 : 0] VAR163;
input [127 : 0] VAR45;
input [15 : 0] VAR1... | lgpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/addh/gf180mcu_fd_sc_mcu9t5v0__addh_2.functional.pp.v | 1,190 | module MODULE1( VAR3, VAR1, VAR15, VAR6, VAR2, VAR10 );
input VAR1, VAR15;
inout VAR2, VAR10;
output VAR3, VAR6;
and VAR11( VAR3, VAR1, VAR15 );
wire VAR4;
not VAR12( VAR4, VAR15 );
wire VAR13;
and VAR16( VAR13, VAR4, VAR1 );
wire VAR9;
not VAR8( VAR9, VAR1 );
wire VAR14;
and VAR5( VAR14, VAR9, VAR15 );
or VAR7( VAR6, ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/or2/sky130_fd_sc_ms__or2.functional.pp.v | 1,774 | module MODULE1 (
VAR11 ,
VAR10 ,
VAR7 ,
VAR9,
VAR4,
VAR6 ,
VAR12
);
output VAR11 ;
input VAR10 ;
input VAR7 ;
input VAR9;
input VAR4;
input VAR6 ;
input VAR12 ;
wire VAR2 ;
wire VAR13;
or VAR5 (VAR2 , VAR7, VAR10 );
VAR1 VAR3 (VAR13, VAR2, VAR9, VAR4);
buf VAR8 (VAR11 , VAR13 );
endmodule | apache-2.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/riffa2.2/tx_engine_ultrascale.v | 11,826 | module MODULE1
parameter VAR28 = 128,
parameter VAR20 = 1,
parameter VAR80 = 0,
parameter VAR35 = 64
)
(
input VAR32,
input VAR16,
input [VAR50-1:0] VAR36,
input VAR62,
output VAR47,
output VAR41,
output [VAR28-1:0] VAR39,
output [(VAR28/32)-1:0] VAR18,
output [VAR23-1:0] VAR77,
input VAR52,
input [VAR28-1:0] VAR14,
in... | gpl-3.0 |
fbalakirev/red-pitaya-notes | cores/pulse_generator_v1_0/pulse_generator.v | 1,356 | module MODULE1 #
(
parameter VAR8 = "VAR5"
)
(
input wire VAR11,
input wire VAR7,
input wire [95:0] VAR4,
output wire dout
);
reg VAR9, VAR6;
reg [31:0] VAR3, VAR10;
always @(posedge VAR11)
begin
if(~VAR7)
begin
VAR9 <= 1'b0;
VAR3 <= 32'd0;
end
else
begin
VAR9 <= VAR6;
VAR3 <= VAR10;
end
end
always @*
begin
VAR6 = VAR9... | mit |
sukinull/hls_stream | Vivado/example.hls/example.hls.srcs/sources_1/bd/tutorial/ip/tutorial_xbar_0/synth/tutorial_xbar_0.v | 15,855 | module MODULE1 (
VAR69,
VAR9,
VAR95,
VAR20,
VAR83,
VAR17,
VAR28,
VAR81,
VAR78,
VAR19,
VAR109,
VAR39,
VAR64,
VAR126,
VAR10,
VAR102,
VAR119,
VAR35,
VAR72,
VAR62,
VAR65,
VAR76,
VAR98,
VAR120,
VAR112,
VAR40,
VAR103,
VAR94,
VAR43,
VAR38,
VAR22,
VAR123,
VAR18,
VAR29,
VAR99,
VAR24,
VAR105,
VAR37,
VAR63,
VAR91
);
input wire VA... | gpl-2.0 |
ShepardSiegel/ocpi | coregen/temac_axi_v5_2/example_design/clk_wiz.v | 6,984 | module MODULE1
( input VAR66,
input VAR44,
output VAR49,
output VAR58,
output VAR7,
input VAR43,
output VAR17
);
VAR63 VAR79
(.VAR32 (VAR37),
.VAR55 (VAR66),
.VAR81 (VAR44));
wire [15:0] VAR61;
wire VAR36;
wire VAR84;
wire VAR74;
wire VAR38;
wire VAR75;
wire VAR48;
wire VAR15;
wire VAR71;
wire VAR31;
wire VAR14;
wire V... | lgpl-3.0 |
eda-globetrotter/PicenoDecoders | viterbi/syn/src/acs.v | 3,716 | module MODULE1 (VAR4, VAR10, VAR8, VAR1, VAR9, VAR11);
output [3:0] VAR4;
output VAR10;
input [3:0] VAR8;
input [1:0] VAR1;
input [3:0] VAR9;
input [1:0] VAR11;
reg [3:0] VAR4;
reg VAR10;
reg [3:0] VAR5;
reg [3:0] VAR6;
reg [4:0] VAR7;
reg [4:0] VAR3;
parameter VAR2 = 4'd15;
always @ (VAR8 or VAR1)
begin
VAR7 = VAR8 + ... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/sdffrnq/gf180mcu_fd_sc_mcu9t5v0__sdffrnq_4.behavioral.pp.v | 18,378 | module MODULE1( VAR214, VAR185, VAR150, VAR104, VAR35, VAR97, VAR189, VAR67 );
input VAR104, VAR150, VAR35, VAR214, VAR185;
inout VAR189, VAR67;
output VAR97;
reg VAR61;
VAR163 VAR275(.VAR214(VAR214),.VAR185(VAR185),.VAR150(VAR150),.VAR104(VAR104),.VAR35(VAR35),.VAR97(VAR97),.VAR189(VAR189),.VAR67(VAR67),.VAR61(VAR61))... | apache-2.0 |
twlostow/dsi-shield | hdl/rtl/dsi_core/dsi_utils.v | 6,820 | module MODULE4
(
input [23:0] VAR14,
output [7:0] VAR2
);
assign VAR2[0]=^{VAR14[2:0], VAR14[5:4], VAR14[7], VAR14[11:10], VAR14[13], VAR14[16], VAR14[23:20]};
assign VAR2[1]=^{VAR14[1:0], VAR14[4:3], VAR14[6], VAR14[8], VAR14[10], VAR14[12], VAR14[14], VAR14[17], VAR14[23:20]};
assign VAR2[2]=^{VAR14[0], VAR14[3:2], V... | lgpl-3.0 |
tta/gnuradio-tta | gr-sounder/src/fpga/lib/sounder.v | 3,516 | module MODULE1(VAR1, VAR36, VAR3, VAR14,
VAR24, VAR18, VAR32,
VAR4,VAR45,
VAR9, VAR52,VAR31);
input VAR1; input [6:0] VAR36; input [31:0] VAR3; input VAR14;
output VAR24; output [13:0] VAR18; output [13:0] VAR32;
output VAR9; input [15:0] VAR4; input [15:0] VAR45; output [15:0] VAR52; output [15:0] VAR31;
wire reset;
w... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfbbn/sky130_fd_sc_hs__sdfbbn.functional.v | 2,584 | module MODULE1 (
VAR12 ,
VAR23 ,
VAR19 ,
VAR22 ,
VAR6 ,
VAR3 ,
VAR5 ,
VAR24,
VAR21 ,
VAR15
);
output VAR12 ;
output VAR23 ;
input VAR19 ;
input VAR22 ;
input VAR6 ;
input VAR3 ;
input VAR5 ;
input VAR24;
input VAR21 ;
input VAR15 ;
wire VAR18 ;
wire VAR2 ;
wire VAR13 ;
wire VAR20 ;
wire VAR4;
not VAR8 (VAR18 , VAR24 );... | apache-2.0 |
r2apu/Labo_Digitales | L2/codigo/gIMUL.v | 1,733 | module MODULE1 (
input wire VAR12,VAR3,VAR10,
output wire VAR19 ,
output wire VAR4
);
assign {VAR4,VAR19} = VAR12 + VAR3 + VAR10;
endmodule
module MODULE3 # (parameter VAR2 = 8)(
input wire [VAR2-1:0] VAR18,VAR13,
output wire [(2*VAR2)-1:0] VAR6
);
wire[(VAR2-1):0] VAR7[(VAR2-1):0];
wire [(VAR2-2):0] VAR17[(VAR2-1):0];... | gpl-3.0 |
carstenbru/fpga-log | spartanmc/hardware/motor_dummy_control/src/motor_dummy_control.v | 4,397 | module MODULE1 #(parameter VAR16 = 10'h0,
parameter VAR4 = 16000000,
parameter VAR24 = 100,
parameter VAR38 = 100,
parameter VAR36 = 5000,
parameter VAR27 = "VAR30",
parameter VAR5 = 128) (
input wire VAR13, input wire [17:0] VAR26, output wire [17:0] VAR20, input wire [9:0] VAR2, input wire VAR35, input wire VAR1,
inp... | gpl-3.0 |
m-labs/milkymist | cores/pfpu/rtl/pfpu_seq.v | 2,291 | module MODULE1(
input VAR8,
input VAR10,
output reg VAR7,
input VAR5,
input VAR12,
input VAR9,
output reg VAR13,
output reg VAR14,
input VAR11,
output reg VAR1,
output reg VAR15,
input VAR18,
output reg VAR16
);
reg [1:0] state;
reg [1:0] VAR6;
parameter VAR4 = 2'd0;
parameter VAR3 = 2'd1;
parameter VAR2 = 2'd2;
parame... | lgpl-3.0 |
Franderg/Ascensor | bcd_to_display.v | 1,081 | module MODULE1(
input clk,
input rst,
input [3:0] VAR2,
output reg[7:0] VAR1
);
begin
begin
end
begin | gpl-3.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys4/project_1/project_1.srcs/sources_1/imports/sources/or1200/or1200_sb_fifo.v | 9,422 | module MODULE1(
VAR4, VAR22, VAR11, VAR8, VAR6, VAR29, VAR30, VAR19
);
parameter VAR23 = 68;
parameter VAR25 = VAR18;
parameter VAR15 = VAR27;
parameter VAR2 = "VAR7";
input VAR4; input VAR22; input [VAR23-1:0] VAR11; input VAR8; input VAR6; output [VAR23-1:0] VAR29; output VAR30; output VAR19;
VAR26 VAR26 (.din(VAR11[... | gpl-2.0 |
rohit21122012/CPU | ALU/Arith/UnSigned/UAdder/mux.v | 4,830 | module MODULE1(out , VAR1 , VAR6 ,VAR5);
output [31:0] out;
input [31:0] VAR1,VAR6;
input VAR5;
wire VAR3;
wire [31:0] VAR2,VAR4;
not (VAR3,VAR5);
and (VAR2[0] , VAR3 , VAR1[0]);
and (VAR2[1] , VAR3 , VAR1[1]);
and (VAR2[2] , VAR3 , VAR1[2]);
and (VAR2[3] , VAR3 , VAR1[3]);
and (VAR2[4] , VAR3 , VAR1[4]);
and (VAR2[5] ... | mit |
monotone-RK/FACE | MCSoC-15/16-way_2-parallel/ise/ipcore_dir/dram/user_design/rtl/ecc/mig_7series_v1_9_ecc_gen.v | 7,915 | module MODULE1
parameter VAR9 = 72,
parameter VAR13 = 8,
parameter VAR6 = 64
)
(
VAR21
);
function integer VAR10 (input integer VAR5);
integer VAR14;
if (VAR5 == 1) VAR10 = 1;
else begin
VAR10 = 1;
for (VAR14=2; VAR14<=VAR5; VAR14=VAR14+1)
VAR10 = VAR10 * VAR14;
end
endfunction
function integer VAR18 (input integer VAR... | mit |
FAST-Switch/fast | lib/hardware/pipeline/UM_OPENFLOW/UM.v | 8,755 | module MODULE1(
input clk,
input VAR44,
input [5:0] VAR40,
input VAR107,
input [133:0] VAR46,
input VAR104,
input VAR15,
output VAR74,
output VAR66,
output [133:0] VAR52,
output VAR59,
output VAR92,
input VAR73,
input VAR38,
input [133:0] VAR83,
input VAR97,
input VAR70,
output VAR109,
output VAR54,
output [133:0] VAR4... | apache-2.0 |
ncos/Xilinx-Verilog | GYRACC/src/toplevel.v | 5,085 | module MODULE1
(
VAR66,
VAR21,
VAR27,
VAR83,
VAR5,
VAR56,
VAR81,
VAR76,
VAR14,
VAR3,
VAR105,
VAR2,
VAR68,
VAR40,
VAR44,
VAR8,
VAR69,
VAR77,
VAR79,
VAR52,
VAR41,
VAR4,
VAR86,
VAR50,
VAR26,
VAR54,
VAR85,
VAR103,
VAR19,
VAR84,
VAR64,
VAR67,
VAR20,
VAR75,
VAR55,
VAR59,
VAR73,
VAR11,
VAR47,
VAR35,
VAR102,
VAR51,
VAR65,
VAR3... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | models/udp_dff_ps/sky130_fd_sc_hd__udp_dff_ps.blackbox.v | 1,233 | module MODULE1 (
VAR2 ,
VAR3 ,
VAR4,
VAR1
);
output VAR2 ;
input VAR3 ;
input VAR4;
input VAR1;
endmodule | apache-2.0 |
gigglesninja/digital-system-design | Lab4/lab4dpath_part2.v | 1,254 | module MODULE1(VAR8,VAR20,VAR23,VAR3,clk);
input [9:0] VAR8,VAR20,VAR23;
input clk;
output [9:0] VAR3;
wire [11:0] VAR19, VAR10, VAR11, VAR13;
wire [23:0] VAR12, VAR16, VAR7;
reg [9:0] VAR18, VAR14, VAR2, VAR15, VAR4, VAR5;
always @(posedge clk) begin
VAR18 <= VAR8;
VAR14 <= VAR20;
VAR2 <= VAR23;
end
always @(posedge c... | gpl-2.0 |
lvd2/zxevo | unsupported/solegstar/fpga/current/video/video_fetch.v | 2,603 | module MODULE1(
input wire clk,
input wire VAR4, input wire VAR14,
input wire VAR9,
input wire VAR3, input wire VAR5,
output reg VAR10,
input wire [15:0] VAR12, input wire VAR7, output reg VAR2,
output reg [63:0] VAR11
);
reg [3:0] VAR1;
reg [1:0] VAR6; reg VAR13;
reg [15:0] VAR8 [0:3];
always @(posedge clk)
if( VAR3 &... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/sdffrnq/gf180mcu_fd_sc_mcu9t5v0__sdffrnq_2.functional.pp.v | 1,745 | module MODULE1( VAR14, VAR15, VAR25, VAR19, VAR12, VAR22, VAR16, VAR6, VAR8 );
input VAR19, VAR25, VAR12, VAR14, VAR15, VAR16, VAR6, VAR8;
output VAR22;
not VAR13( VAR27, VAR12 );
wire VAR10;
not VAR9( VAR10, VAR25 );
wire VAR7;
not VAR4( VAR7, VAR14 );
wire VAR26;
and VAR20( VAR26, VAR10, VAR7 );
wire VAR18;
not VAR1(... | apache-2.0 |
bunnie/novena-afe-hs-fpga | novena-afe-hs.srcs/sources_1/imports/imports/eim_burstcnt.v | 1,568 | module MODULE1(
input wire VAR15,
input wire [15:0] VAR16, input wire [2:0] VAR9, input wire VAR2, input wire VAR14, input wire VAR8,
output reg [15:0] VAR7
);
reg VAR3;
reg [15:0] VAR12;
reg VAR10;
reg [2:0] VAR6;
reg VAR1;
reg VAR11;
reg [15:0] VAR13;
reg [15:0] VAR4;
reg VAR5;
always @(posedge VAR15) begin
VAR12 <= ... | apache-2.0 |
mamijaz/RISC-V | src/riscv_pipeline/decode/DECODING_STAGE.v | 11,167 | module MODULE1 #(
parameter VAR14 = 32 ,
parameter VAR58 = 32 ,
parameter VAR39 = 5 ,
parameter VAR67 = 5 ,
parameter VAR60 = 3 ,
parameter VAR43 = 2 ,
parameter VAR6 = 3 ,
parameter VAR9 = 1'b1 ,
parameter VAR37 = 1'b0
) (
input VAR41 ,
input VAR22 ,
input VAR5 ,
input [VAR39 - 1 : 0] VAR28 ,
input [VAR58 - 1 : 0] VAR... | bsd-2-clause |
GREO/GNU-Radio | usrp/fpga/sdr_lib/sign_extend.v | 1,138 | module MODULE1 (in,out);
parameter VAR1=0; parameter VAR2=0;
input [VAR1-1:0] in;
output [VAR2-1:0] out;
assign out = {{(VAR2-VAR1){in[VAR1-1]}},in};
endmodule | gpl-3.0 |
Tommydag/CAN-Bus-Controller | Oneshot.v | 1,322 | module MODULE1(
input pulse,
input clk,
input rst,
output reg out
);
VAR6 out = 0;
parameter VAR2 = 2'b00, VAR5 = 2'b01, VAR3 = 2'b10;
reg[1:0] VAR1, VAR4;
always @ (posedge clk or posedge rst) begin
if(rst) begin
VAR4 <= VAR2;
end
else begin
VAR4 <= VAR1;
end
end
always @ (VAR4 or pulse) begin
if(VAR4 == VAR5) begin
V... | mit |
efabless/openlane | designs/usb_cdc_core/src/usbf_sie_tx.v | 9,186 | module MODULE1
(
input VAR3
,input VAR33
,input VAR1
,input VAR17
,input VAR18
,input VAR31
,input [ 7:0] VAR38
,input VAR12
,input VAR36
,input [ 7:0] VAR15
,input VAR40
,output [ 7:0] VAR27
,output VAR24
,output VAR32
,output VAR39
);
localparam VAR6 = 3;
localparam VAR14 = 3'd0;
localparam VAR28 = 3'd1;
localparam V... | apache-2.0 |
fbalakirev/red-pitaya-notes | cores/dna_reader_v1_0/dna_reader.v | 1,838 | module MODULE1
(
input wire VAR4,
input wire VAR18,
output wire [56:0] VAR23
);
localparam integer VAR24 = 16;
localparam integer VAR16 = 57;
reg VAR9, VAR6;
reg VAR5, VAR3;
reg VAR21, VAR14;
reg [VAR24-1:0] VAR22, VAR12;
reg [VAR16-1:0] VAR11, VAR8;
wire VAR17, VAR13;
assign VAR17 = VAR22 < 64*VAR16;
VAR15 VAR2 (
.VAR... | mit |
Darkin47/Zynq-TX-UTT | Vivado_HLS/convolution_2D/solution1/impl/verilog/doImgProc_KERNEL_BUS_s_axi.v | 9,481 | module MODULE1
VAR6 = 5,
VAR36 = 32
)(
input wire VAR67,
input wire VAR62,
input wire VAR24,
input wire [VAR6-1:0] VAR78,
input wire VAR59,
output wire VAR1,
input wire [VAR36-1:0] VAR26,
input wire [VAR36/8-1:0] VAR32,
input wire VAR80,
output wire VAR53,
output wire [1:0] VAR57,
output wire VAR60,
input wire VAR49,
i... | gpl-3.0 |
Saucyz/explode | Hardware/Mod2/nios_system/synthesis/submodules/nios_system_nios2_qsys_0_jtag_debug_module_tck.v | 8,741 | module MODULE1 (
VAR33,
VAR37,
VAR27,
VAR3,
VAR29,
VAR28,
VAR30,
VAR10,
VAR25,
VAR26,
VAR32,
VAR20,
VAR2,
VAR6,
VAR8,
VAR23,
VAR11,
VAR16,
VAR21,
VAR22,
VAR5,
VAR12,
VAR31,
VAR40,
VAR4,
VAR24,
VAR36,
VAR13,
VAR35,
VAR18,
VAR15
)
;
output [ 1: 0] VAR36;
output VAR13;
output [ 37: 0] VAR35;
output VAR18;
output VAR15;
in... | mit |
pemsac/ANN_project | ANN_project.ip_user_repository/UC3M_MISEA_Thesis_feedforward_1_2/hdl/verilog/feedforward_dcmp_64ns_64ns_1_1.v | 2,396 | module MODULE1
VAR8 = 3,
VAR21 = 1,
VAR18 = 64,
VAR41 = 64,
VAR26 = 1
)(
input wire [VAR18-1:0] VAR16,
input wire [VAR41-1:0] VAR35,
input wire [4:0] VAR29,
output wire [VAR26-1:0] dout
);
localparam [4:0]
VAR38 = 5'b00001,
VAR2 = 5'b00010,
VAR12 = 5'b00011,
VAR3 = 5'b00100,
VAR23 = 5'b00101,
VAR30 = 5'b00110,
VAR5 = 5... | gpl-3.0 |
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