Download Amr-HAlahla_Multi-Cycle-RISC-Processor-In-Verilog/candidates/stack_control__stack_control/sim.sh from architect-ubc-capstone/rtl-augmented-v3: direct link, hf CLI and curl.
- Browser
- Download file 460 Bytes
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https://huggingface.co/datasets/architect-ubc-capstone/rtl-augmented-v3/resolve/main/Amr-HAlahla_Multi-Cycle-RISC-Processor-In-Verilog/candidates/stack_control__stack_control/sim.sh
- Command line
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hf download hf://datasets/architect-ubc-capstone/rtl-augmented-v3/Amr-HAlahla_Multi-Cycle-RISC-Processor-In-Verilog/candidates/stack_control__stack_control/sim.sh
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curl -L -o sim.sh https://huggingface.co/datasets/architect-ubc-capstone/rtl-augmented-v3/resolve/main/Amr-HAlahla_Multi-Cycle-RISC-Processor-In-Verilog/candidates/stack_control__stack_control/sim.sh
460 Bytes
| set -euo pipefail | |
| if ! command -v python &>/dev/null; then | |
| _TMPBIN=$(mktemp -d) | |
| ln -s "$(command -v python3)" "$_TMPBIN/python" | |
| export PATH="$_TMPBIN:$PATH" | |
| trap 'rm -rf "$_TMPBIN"' EXIT | |
| fi | |
| SRCDIR="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)" | |
| iverilog -g2012 -o /tmp/sim_stack_control "$SRCDIR/Source Code/ControlUnits/stack_control_tb.v" "$SRCDIR/Source Code/ControlUnits/stack_control.v" | |
| vvp /tmp/sim_stack_control -fst | |