| {"tb_file_path": "Source Code/ALU/alu_tb.v", "simulator": "iverilog", "top_module": "alu", "work_subdir": null, "requires_submodules": false, "compile": {"args": ["-g2012"], "sources": ["Source Code/ALU/alu_tb.v", "Source Code/ALU/alu.v"]}, "run": {"args": ["-fst"]}, "waveform": "wave_alu.fst"} |
| {"tb_file_path": "Source Code/ControlUnits/main_control_tb.v", "simulator": "iverilog", "top_module": "control_unit", "work_subdir": null, "requires_submodules": false, "compile": {"args": ["-g2012"], "sources": ["Source Code/ControlUnits/main_control_tb.v", "Source Code/ControlUnits/main_control.v"]}, "run": {"args": ["-fst"]}, "waveform": "wave_control_unit.fst"} |
| {"tb_file_path": "Source Code/ControlUnits/pc_control_tb.v", "simulator": "iverilog", "top_module": "pc_control", "work_subdir": null, "requires_submodules": false, "compile": {"args": ["-g2012"], "sources": ["Source Code/ControlUnits/pc_control_tb.v", "Source Code/ControlUnits/pc_control.v"]}, "run": {"args": ["-fst"]}, "waveform": "wave_pc_control.fst"} |
| {"tb_file_path": "Source Code/ControlUnits/stack_control_tb.v", "simulator": "iverilog", "top_module": "stack_control", "work_subdir": null, "requires_submodules": false, "compile": {"args": ["-g2012"], "sources": ["Source Code/ControlUnits/stack_control_tb.v", "Source Code/ControlUnits/stack_control.v"]}, "run": {"args": ["-fst"]}, "waveform": "wave_stack_control.fst"} |
| {"tb_file_path": "Source Code/Memory/memory_tb.v", "simulator": "iverilog", "top_module": "memory", "work_subdir": null, "requires_submodules": false, "compile": {"args": ["-g2012"], "sources": ["Source Code/Memory/memory_tb.v", "Source Code/Memory/memory.v"]}, "run": {"args": ["-fst"]}, "waveform": "wave_memory_tb1.fst"} |
| {"tb_file_path": "Source Code/Memory/memory_tb2.v", "simulator": "iverilog", "top_module": "memory", "work_subdir": null, "requires_submodules": false, "compile": {"args": ["-g2012"], "sources": ["Source Code/Memory/memory_tb2.v", "Source Code/Memory/memory.v"]}, "run": {"args": ["-fst"]}, "waveform": "wave_memory_tb2.fst"} |
| {"tb_file_path": "Source Code/extenders/immediate_extender_tb.v", "simulator": "iverilog", "top_module": "immediate_extender", "work_subdir": null, "requires_submodules": false, "compile": {"args": ["-g2012"], "sources": ["Source Code/extenders/immediate_extender_tb.v", "Source Code/extenders/immediate_extender.v"]}, "run": {"args": ["-fst"]}, "waveform": "wave_immediate_extender.fst"} |
| {"tb_file_path": "Source Code/instruction_memory/instruction_memory_tb.v", "simulator": "iverilog", "top_module": "instruction_memory", "work_subdir": null, "requires_submodules": false, "compile": {"args": ["-g2012"], "sources": ["Source Code/instruction_memory/instruction_memory_tb.v", "Source Code/instruction_memory/instruction_memory.v"]}, "run": {"args": ["-fst"]}, "waveform": "wave_instruction_memory.fst"} |
| {"tb_file_path": "Source Code/registers/register_file_tb.v", "simulator": "iverilog", "top_module": "register_file", "work_subdir": null, "requires_submodules": false, "compile": {"args": ["-g2012"], "sources": ["Source Code/registers/register_file_tb.v", "Source Code/registers/register_file.v"]}, "run": {"args": ["-fst"]}, "waveform": "wave_register_file.fst"} |
| {"tb_file_path": "Source Code/stack/stack_memory_tb.v", "simulator": "iverilog", "top_module": "stack_memory", "work_subdir": null, "requires_submodules": false, "compile": {"args": ["-g2012"], "sources": ["Source Code/stack/stack_memory_tb.v", "Source Code/stack/stack_memory.v"]}, "run": {"args": ["-fst"]}, "waveform": "wave_stack_memory.fst"} |
|
|
