Download Amr-HAlahla_Multi-Cycle-RISC-Processor-In-Verilog/source/Source Code/ALU/alu.v from architect-ubc-capstone/rtl-augmented-v3: direct link, hf CLI and curl.
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https://huggingface.co/datasets/architect-ubc-capstone/rtl-augmented-v3/resolve/main/Amr-HAlahla_Multi-Cycle-RISC-Processor-In-Verilog/source/Source%20Code/ALU/alu.v
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hf download 'hf://datasets/architect-ubc-capstone/rtl-augmented-v3/Amr-HAlahla_Multi-Cycle-RISC-Processor-In-Verilog/source/Source Code/ALU/alu.v'
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curl -L -o alu.v https://huggingface.co/datasets/architect-ubc-capstone/rtl-augmented-v3/resolve/main/Amr-HAlahla_Multi-Cycle-RISC-Processor-In-Verilog/source/Source%20Code/ALU/alu.v
414 Bytes
| // buile alu module here | |
| module alu( | |
| input [31:0] a, | |
| input [31:0] b, | |
| input [2:0] op, | |
| output reg [31:0] out | |
| ); | |
| always @(*) begin | |
| case (op) | |
| 3'b000: out = a + b; | |
| 3'b001: out = a - b; | |
| 3'b010: out = a & b; | |
| 3'b011: out = a << b; | |
| 3'b100: out = a >> b; | |
| endcase | |
| end | |
| endmodule | |
| // build alu test bench here | |