Download Amr-HAlahla_Multi-Cycle-RISC-Processor-In-Verilog/testbenches.json from architect-ubc-capstone/rtl-augmented-v3: direct link, hf CLI and curl.
- Browser
- Download file 3.25 kB
-
https://huggingface.co/datasets/architect-ubc-capstone/rtl-augmented-v3/resolve/main/Amr-HAlahla_Multi-Cycle-RISC-Processor-In-Verilog/testbenches.json
- Command line
-
hf download hf://datasets/architect-ubc-capstone/rtl-augmented-v3/Amr-HAlahla_Multi-Cycle-RISC-Processor-In-Verilog/testbenches.json
-
curl -L -o testbenches.json https://huggingface.co/datasets/architect-ubc-capstone/rtl-augmented-v3/resolve/main/Amr-HAlahla_Multi-Cycle-RISC-Processor-In-Verilog/testbenches.json
3.25 kB
| [ | |
| { | |
| "file_path": "Source Code/ALU/alu_tb.v", | |
| "tb_type": "verilog", | |
| "simulator": "icarus", | |
| "makefile_path": null, | |
| "top_module": "alu", | |
| "rtl_files": [ | |
| "Source Code/ALU/alu.v" | |
| ] | |
| }, | |
| { | |
| "file_path": "Source Code/ControlUnits/main_control_tb.v", | |
| "tb_type": "verilog", | |
| "simulator": "icarus", | |
| "makefile_path": null, | |
| "top_module": "control_unit", | |
| "rtl_files": [ | |
| "Source Code/ControlUnits/main_control.v" | |
| ] | |
| }, | |
| { | |
| "file_path": "Source Code/ControlUnits/pc_control_tb.v", | |
| "tb_type": "verilog", | |
| "simulator": "icarus", | |
| "makefile_path": null, | |
| "top_module": "pc_control", | |
| "rtl_files": [ | |
| "Source Code/ControlUnits/pc_control.v" | |
| ] | |
| }, | |
| { | |
| "file_path": "Source Code/ControlUnits/stack_control_tb.v", | |
| "tb_type": "verilog", | |
| "simulator": "icarus", | |
| "makefile_path": null, | |
| "top_module": "stack_control", | |
| "rtl_files": [ | |
| "Source Code/ControlUnits/stack_control.v" | |
| ] | |
| }, | |
| { | |
| "file_path": "Source Code/DataPath/TB.v", | |
| "tb_type": "verilog", | |
| "simulator": "icarus", | |
| "makefile_path": null, | |
| "top_module": "MCRP", | |
| "rtl_files": [ | |
| "Source Code/DataPath/MCRP.v", | |
| "Source Code/ALU/alu.v", | |
| "Source Code/ControlUnits/main_control.v", | |
| "Source Code/ControlUnits/pc_control.v", | |
| "Source Code/ControlUnits/stack_control.v", | |
| "Source Code/Memory/memory.v", | |
| "Source Code/extenders/immediate_extender.v", | |
| "Source Code/extenders/shift_extender.v", | |
| "Source Code/extenders/offset_extednder.v", | |
| "Source Code/instruction_memory/instruction_memory.v", | |
| "Source Code/registers/register_file.v", | |
| "Source Code/stack/stack_memory.v" | |
| ] | |
| }, | |
| { | |
| "file_path": "Source Code/Memory/memory_tb.v", | |
| "tb_type": "verilog", | |
| "simulator": "icarus", | |
| "makefile_path": null, | |
| "top_module": "memory", | |
| "rtl_files": [ | |
| "Source Code/Memory/memory.v" | |
| ] | |
| }, | |
| { | |
| "file_path": "Source Code/Memory/memory_tb2.v", | |
| "tb_type": "verilog", | |
| "simulator": "icarus", | |
| "makefile_path": null, | |
| "top_module": "memory", | |
| "rtl_files": [ | |
| "Source Code/Memory/memory.v" | |
| ] | |
| }, | |
| { | |
| "file_path": "Source Code/extenders/immediate_extender_tb.v", | |
| "tb_type": "verilog", | |
| "simulator": "icarus", | |
| "makefile_path": null, | |
| "top_module": "immediate_extender", | |
| "rtl_files": [ | |
| "Source Code/extenders/immediate_extender.v" | |
| ] | |
| }, | |
| { | |
| "file_path": "Source Code/instruction_memory/instruction_memory_tb.v", | |
| "tb_type": "verilog", | |
| "simulator": "icarus", | |
| "makefile_path": null, | |
| "top_module": "instruction_memory", | |
| "rtl_files": [ | |
| "Source Code/instruction_memory/instruction_memory.v" | |
| ] | |
| }, | |
| { | |
| "file_path": "Source Code/registers/register_file_tb.v", | |
| "tb_type": "verilog", | |
| "simulator": "icarus", | |
| "makefile_path": null, | |
| "top_module": "register_file", | |
| "rtl_files": [ | |
| "Source Code/registers/register_file.v" | |
| ] | |
| }, | |
| { | |
| "file_path": "Source Code/stack/stack_memory_tb.v", | |
| "tb_type": "verilog", | |
| "simulator": "icarus", | |
| "makefile_path": null, | |
| "top_module": "stack_memory", | |
| "rtl_files": [ | |
| "Source Code/stack/stack_memory.v" | |
| ] | |
| } | |
| ] |