https://huggingface.co/datasets/architect-ubc-capstone/rtl-augmented-v3/resolve/main/ayushc13_32-bit-RISC-processor-using-HDL-Verilog/waveform_map.json
hf download hf://datasets/architect-ubc-capstone/rtl-augmented-v3/ayushc13_32-bit-RISC-processor-using-HDL-Verilog/waveform_map.json
curl -L -o waveform_map.json https://huggingface.co/datasets/architect-ubc-capstone/rtl-augmented-v3/resolve/main/ayushc13_32-bit-RISC-processor-using-HDL-Verilog/waveform_map.json
