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9

Publish expected_sets_sve.json: the definition set the SVE tables are scored against

#5
by VanishD - opened
base: refs/heads/main
←
from: refs/pr/5
Discussion Files changed
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Files changed (1) hide show
  1. expected_sets_sve.json +95 -0
expected_sets_sve.json ADDED
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+ {
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+ "ncnn": [
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+ "conv2d_depthwise_fp32_kh3_kw3_sh1_sw1_dh1_dw1_p1",
4
+ "conv2d_depthwise_fp32_kh3_kw3_sh2_sw2_dh1_dw1_p1",
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+ "conv2d_depthwise_fp32_kh5_kw5_sh1_sw1_dh1_dw1_p2",
6
+ "conv2d_depthwise_fp32_kh5_kw5_sh2_sw2_dh1_dw1_p2",
7
+ "conv2d_depthwise_w8a8ch_kh3_kw3_sh1_sw1_dh1_dw1_p1",
8
+ "conv2d_depthwise_w8a8ch_kh3_kw3_sh2_sw2_dh1_dw1_p1",
9
+ "conv2d_depthwise_w8a8ch_kh5_kw5_sh1_sw1_dh1_dw1_p2",
10
+ "conv2d_depthwise_w8a8ch_kh5_kw5_sh2_sw2_dh1_dw1_p2",
11
+ "conv2d_fp32_kh1_kw1_sh1_sw1_dh1_dw1_p0",
12
+ "conv2d_fp32_kh1_kw1_sh2_sw2_dh1_dw1_p0",
13
+ "conv2d_fp32_kh3_kw3_sh1_sw1_dh1_dw1_p1",
14
+ "conv2d_fp32_kh3_kw3_sh2_sw2_dh1_dw1_p1",
15
+ "conv2d_fp32_kh7_kw7_sh2_sw2_dh1_dw1_p3",
16
+ "conv2d_w8a8ch_kh1_kw1_sh1_sw1_dh1_dw1_p0",
17
+ "conv2d_w8a8ch_kh1_kw1_sh2_sw2_dh1_dw1_p0",
18
+ "conv2d_w8a8ch_kh3_kw3_sh1_sw1_dh1_dw1_p1",
19
+ "conv2d_w8a8ch_kh3_kw3_sh2_sw2_dh1_dw1_p1",
20
+ "conv2d_w8a8ch_kh7_kw7_sh2_sw2_dh1_dw1_p3",
21
+ "pooling_fp32_global_avg",
22
+ "pooling_fp32_max_kh2_kw2_sh2_sw2_p0",
23
+ "pooling_fp32_max_kh3_kw3_sh1_sw1_p1",
24
+ "pooling_fp32_max_kh3_kw3_sh2_sw2_p0",
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+ "pooling_fp32_max_kh3_kw3_sh2_sw2_p1"
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+ ],
27
+ "llama.cpp": [
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+ "gemm_bf16_n1024_k2048",
29
+ "gemm_bf16_n1408_k2048",
30
+ "gemm_bf16_n2048_k1024",
31
+ "gemm_bf16_n2048_k1408",
32
+ "gemm_bf16_n2048_k2048",
33
+ "gemm_q4_k_m_n1024_k2048",
34
+ "gemm_q4_k_m_n1408_k2048",
35
+ "gemm_q4_k_m_n2048_k1024",
36
+ "gemm_q4_k_m_n2048_k1536",
37
+ "gemm_q4_k_m_n2048_k2048",
38
+ "gemm_q8_0_n1024_k2048",
39
+ "gemm_q8_0_n1408_k2048",
40
+ "gemm_q8_0_n2048_k1024",
41
+ "gemm_q8_0_n2048_k1408",
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+ "gemm_q8_0_n2048_k2048",
43
+ "gqa_bf16_h32_d128_kvh8",
44
+ "mha_bf16_h16_d128_kvh16",
45
+ "mla_decode_bf16_h16_lora512_rope64_v128",
46
+ "mla_prefill_bf16_h16_qk192_vo128",
47
+ "moe_bf16_e60_k4_d2048_ff1408",
48
+ "moe_bf16_e64_k8_d2048_ff1024",
49
+ "moe_q4_k_m_e60_k4_d2048_ff1536",
50
+ "moe_q4_k_m_e64_k8_d2048_ff1024",
51
+ "moe_q8_0_e60_k4_d2048_ff1408",
52
+ "moe_q8_0_e64_k8_d2048_ff1024",
53
+ "rms_norm_fp32_d2048"
54
+ ],
55
+ "kleidiai": [
56
+ "conv2d_depthwise_f16_nhwc_kh3_kw3_s1_p1",
57
+ "conv2d_depthwise_fp32_nhwc_kh3_kw3_s1_p1",
58
+ "conv2d_f16_nhwc_kh3_kw3_valid_c32_c64",
59
+ "conv2d_fp32_nhwc_kh3_kw3_s1_p1_c32_c64",
60
+ "gemm_bf16_n512_k512",
61
+ "gemm_f16_n512_k512",
62
+ "gemm_fp32_n512_k512",
63
+ "gemm_fp32_sme2_n512_k512",
64
+ "gemm_qs4c32_n256_k512",
65
+ "gemm_qs4cx_sme2_n256_k512"
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+ ],
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+ "simd-loop": [
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+ "loop_001",
69
+ "loop_002",
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+ "loop_003",
71
+ "loop_004",
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+ "loop_008",
73
+ "loop_024",
74
+ "loop_027",
75
+ "loop_028",
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+ "loop_029",
77
+ "loop_033",
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+ "loop_035",
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+ "loop_037",
80
+ "loop_038",
81
+ "loop_103",
82
+ "loop_105",
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+ "loop_108",
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+ "loop_109",
85
+ "loop_110",
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+ "loop_112",
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+ "loop_113",
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+ "loop_114",
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+ "loop_120",
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+ "loop_124",
91
+ "loop_126",
92
+ "loop_127",
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+ "loop_219"
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+ ]
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+ }