SME2 SIMD Loops: loop_216 is ★ under its gemm tolerance; remove loop_032's baseline-sme2

TASKS.md

@@ -1,6 +1,6 @@
 # Tasks and baselines
 
-Every definition in this dataset, with the expert baseline it is scored against on each hardware tier: whether it runs there, and whether it is specialized for that tier. Generated 2026-10-02 from the dataset, the recorded runs and a check of each baseline's code; the SME2 column was updated on 2026-10-20 from a check of every SIMD Loops baseline on M4.
+Every definition in this dataset, with the expert baseline it is scored against on each hardware tier: whether it runs there, and whether it is specialized for that tier. Generated 2026-10-02 from the dataset, the recorded runs and a check of each baseline's code; the SME2 column was updated on 2026-10-20 from a check of every SIMD Loops baseline on M4, and on 2026-10-28 for `loop_216` (tolerance override) and `loop_032` (`baseline-sme2` removed).
 
 | Mark | Meaning |
 |---|---|
@@ -22,10 +22,10 @@ How each source's baseline is chosen and marked is explained under *Notes on the
 |---|---|---|---|---|
 | ncnn | 23 | 0 / 23 / 0 / 0 / 0 | 0 / 23 / 0 / 0 / 0 | 0 / 23 / 0 / 0 / 0 |
 | llama.cpp | 26 | 0 / 26 / 0 / 0 / 0 | 0 / 26 / 0 / 0 / 0 | 0 / 26 / 0 / 0 / 0 |
-| SIMD Loops | 47 | 27 / 0 / 0 / 3 / 17 | 11 / 18 / 0 / 7 / 11 | 6 / 16 / 0 / 10 / 15 |
+| SIMD Loops | 47 | 27 / 0 / 0 / 3 / 17 | 11 / 18 / 0 / 7 / 11 | 7 / 16 / 0 / 8 / 16 |
 | KleidiAI | 10 | 3 / 0 / 0 / 0 / 7 | 0 / 2 / 0 / 0 / 8 | 7 / 0 / 0 / 0 / 3 |
 | e2e (llama.cpp GEMMs) | 18 | 0 / 18 / 0 / 0 / 0 | 0 / 18 / 0 / 0 / 0 | 0 / 18 / 0 / 0 / 0 |
-| **All** | **124** | 30 / 67 / 0 / 3 / 24 | 11 / 87 / 0 / 7 / 19 | 13 / 83 / 0 / 10 / 18 |
+| **All** | **124** | 30 / 67 / 0 / 3 / 24 | 11 / 87 / 0 / 7 / 19 | 14 / 83 / 0 / 8 / 19 |
 
 ## ncnn (23)
 
@@ -121,7 +121,7 @@ Loops without the Eval set mark are in the dataset but not in the main results.
 | `loop_005` |  | 10 |  |  | — | — | — |
 | `loop_006` |  | 10 |  |  | — | — | — |
 | `loop_010` |  | 10 |  |  | ★ | ✓ | ✗ |
-| `loop_032` |  | 10 |  |  | ✗ | ✗ | ✗ |
+| `loop_032` |  | 10 |  |  | ✗ | ✗ | — |
 | `loop_034` |  | 10 |  |  | — | — | — |
 | `loop_101` |  | 10 |  |  | — | ★ | ✓ |
 | `loop_102` |  | 10 |  |  | — | ★ | — |
@@ -133,7 +133,7 @@ Loops without the Eval set mark are in the dataset but not in the main results.
 | `loop_128` |  | 10 |  |  | — | — | ✗ |
 | `loop_130` |  | 10 |  |  | — | ✗ | — |
 | `loop_135` |  | 10 |  |  | — | ✗ | — |
-| `loop_216` |  | 10 |  |  | — | — | ✗ |
+| `loop_216` |  | 10 |  |  | — | — | ★ |
 | `loop_217` |  | 10 |  |  | — | — | ★ |
 | `loop_218` |  | 10 |  |  | — | — | ★ |
 | `loop_220` |  | 10 |  |  | — | — | ★ |
@@ -198,18 +198,16 @@ These definitions load only with the e2e branch for now (code repo issue #94).
 - `loop_010` (`baseline-sme2` on M4): about 44x slower than the scalar starting point auto-vectorized for M4, so it fails the rule that a baseline be at most 2x slower than that (the scalar loop exits early, while the baseline scans the whole array).
 - `loop_027` (`baseline-sme2` on M4): about 2.3x slower than the scalar starting point auto-vectorized for M4, so it fails the rule that a baseline be at most 2x slower than that.
 - `loop_028` (`baseline-sme2` on M4): about 6.1x slower than the scalar starting point auto-vectorized for M4, so it fails the rule that a baseline be at most 2x slower than that.
-- `loop_032` (`baseline-sme2` on M4): its published baseline was never converted to the M4 form: it is built with `-march=armv9-a+sve2+sme2` and declares `isa_features` `sve2`, `sme2`, which the sme2 tier does not provide, so it never runs on M4 (it crashes with SIGILL; found while regenerating the SME2 baselines, code repo PR #105).
 - `loop_038` (`baseline-sme2` on M4): about 5.0x slower than the scalar starting point auto-vectorized for M4, so it fails the rule that a baseline be at most 2x slower than that.
 - `loop_114` (`baseline-sme2` on M4): about 3.3x slower than the scalar starting point auto-vectorized for M4, so it fails the rule that a baseline be at most 2x slower than that.
 - `loop_127` (`baseline-sme2` on M4): about 5.3x slower than the scalar starting point auto-vectorized for M4, so it fails the rule that a baseline be at most 2x slower than that (the first evaluations of the earlier M4 agent runs gave 4.6x).
 - `loop_128` (`baseline-sme2` on M4): 2.01x slower than the scalar starting point auto-vectorized for M4, so it fails the rule that a baseline be at most 2x slower than that, just over the limit.
-- `loop_216` (`baseline-sme2` on M4): wrong results on 2 of 10 workloads at the default tolerance (1 of 256 outputs, up to 1.4e-3 relative). It is an FP32 GEMV with reductions of up to 522k terms; the scalar starting point fails the same outputs with the same values, and both pass under the tolerance used for `gemm` definitions, so the fix is a tolerance override for this definition.
 
 ## Notes on the baselines
 
 - **ncnn** → `baseline-ncnn-arm`, the upstream ncnn kernel, the same on every tier. ncnn is built with its SVE options off, so this is NEON code everywhere: ✓, never ★.
 - **llama.cpp and e2e** → `baseline-llamacpp-arm`, the ggml CPU kernel built natively on each machine. Which kernels reach ggml's SVE code has not been checked, so these are ✓; ggml's KleidiAI path is off. ggml picks its kernel by op, data type and CPU features, not by shape, so a cell with no recorded run is ✓ when the same op and data type ran on that machine (8 llama.cpp definitions on Graviton4). e2e has recorded runs only on Graviton4 and is ✓ on Graviton3 and M4 for the same reason (q4_K ran on both in the llama.cpp set; q5_K and q6_K have not).
-- **SIMD Loops** → one hand-written Arm baseline per tier. `baseline-sve2` uses SVE2-only instructions in some loops (★) and is SVE code in the rest (✓). Of the 32 `baseline-sme2`, 25 are SVE code run in streaming mode (`__arm_locally_streaming`, tag `sme2-kernel:streaming-sve`) and 7 use ZA (tag `sme2-kernel:za`: the matrix loops 216–221 and 223). Streaming SVE counts as ✓, not ★, because it uses nothing SME adds (ZA, outer products, SME2 multi-vector instructions); the ZA ones are ★. All 32 were run on M4 on 2026-10-20 (3 passes on every workload, code at main bc8c53d): 30 pass every workload, `loop_032` cannot run there and `loop_216` fails 2 workloads; the 2x check against the auto-vectorized starting point flags 8 more. All of these are ✗, see the notes below.
+- **SIMD Loops** → one hand-written Arm baseline per tier. `baseline-sve2` uses SVE2-only instructions in some loops (★) and is SVE code in the rest (✓). Of the 31 `baseline-sme2`, 24 are SVE code run in streaming mode (`__arm_locally_streaming`, tag `sme2-kernel:streaming-sve`) and 7 use ZA (tag `sme2-kernel:za`: the matrix loops 216–221 and 223). Streaming SVE counts as ✓, not ★, because it uses nothing SME adds (ZA, outer products, SME2 multi-vector instructions); the ZA ones are ★. All were run on M4 on 2026-10-20 (3 passes on every workload, code at main bc8c53d): 30 pass every workload; the 2x check against the auto-vectorized starting point flags 8 of them, which are ✗ (see the notes above). `loop_216` failed 2 workloads at the default tolerance (1 of 256 outputs, up to 1.4e-3 relative: float32 accumulation over up to 522k terms, which the scalar starting point shares); it passes every workload under the `gemm` tolerance its definition now has (code repo PRs #111, #115) and is well inside the 2x rule (code repo PR #111), so it is ★. `loop_032` has no SME2 code upstream: under `-mcpu=apple-m4` its source falls back to NEON, which streaming mode rejects on M4, so its `baseline-sme2` was removed (—).
 - **KleidiAI** → `baseline-kleidiai-arm`: each kernel uses either an SVE micro-kernel (Graviton tiers) or an SME2 one (M4), not both.
 
 The SVE2 column of SIMD Loops (including the notes on ✗) and of the KleidiAI SVE kernels comes from running each baseline directly on a Graviton4 (c8g) on 2026-10-02. On 2026-10-03 the SIMD Loops and KleidiAI baselines were also checked on Graviton3 and Graviton4 against the inclusion rule that a baseline be at most 2x slower than the scalar starting point auto-vectorized for that machine; every failure is in the notes on ✗.

definitions/simd-loop/loop_032.json

@@ -3,8 +3,7 @@
   "op_type": "loop_032",
   "description": "Solve a step of a banded linear system with non-unit-strided coefficient access",
   "tags": [
-    "simd-loop",
-    "sme2-kernel:streaming-sve"
+    "simd-loop"
   ],
   "axes": {
     "N": {

solutions/simd-loop/baseline-sme2/loop_032/baseline-sme2_loop_032.json

@@ -1,44 +0,0 @@
-{
-  "name": "baseline-sme2_loop_032",
-  "definition": "loop_032",
-  "dataset": "simd-loop",
-  "author": "baseline-sme2",
-  "spec": {
-    "language": "cpp",
-    "target_hardware": [
-      "aarch64"
-    ],
-    "entry_point": "kernel.cpp::inner_loop_032",
-    "dependencies": [],
-    "isa_features": [
-      "sve2",
-      "sme2"
-    ],
-    "compile_flags": [
-      "-O3",
-      "-std=c++14",
-      "-march=armv9-a+sve2+sme2",
-      "-Wno-c++11-narrowing"
-    ],
-    "link_flags": []
-  },
-  "sources": [
-    {
-      "path": "loop_032.h",
-      "content": "// Auto-generated by scripts/gen_simd_loop_harness.py \u2014 do not hand-edit.\n#pragma once\n#include <stdint.h>\n\nstruct loop_032_data {\n    double *a;\n    double *b;\n    int n;\n    double res;\n};\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\nint armbench_entry_loop_032(void *a, void *b, int64_t n, void *res_out);\n#ifdef __cplusplus\n}\n#endif\n"
-    },
-    {
-      "path": "loop_032.cpp",
-      "content": "// Auto-generated by scripts/gen_simd_loop_harness.py \u2014 do not hand-edit.\n#include \"loop_032.h\"\n#include <cassert>\n#include <limits>\n\n#include <arm_sme.h>\n#define SC_SVE_LOOP_ATTR __arm_locally_streaming\n#define S_LOOP_ATTR __arm_locally_streaming __arm_new(\"za\", \"zt0\")\n#define NS_SVE_LOOP_ATTR\n#define SC_SVE_ATTR __arm_streaming_compatible\n#define S_SVE_ATTR __arm_streaming\n#define SC_SVE_ZT0_ATTR __arm_streaming_compatible __arm_inout(\"zt0\") __arm_preserves(\"za\")\n#define SME_ZA_ZT0_ATTR __arm_streaming __arm_inout(\"za\", \"zt0\")\n#define SME_ZA_ATTR __arm_streaming __arm_inout(\"za\") __arm_preserves(\"zt0\")\nstatic inline uint32_t get_sme_vl(void) {\n  uint64_t svl = 0; asm volatile(\"rdsvl %[svl], #8\" : [svl] \"+r\"(svl) : :);\n  return (uint32_t)svl;\n}\nextern \"C\" void inner_loop_032(struct loop_032_data *data) SC_SVE_ATTR;\nNS_SVE_LOOP_ATTR static void __attribute__((noinline)) _armbench_call_032(struct loop_032_data *d) { inner_loop_032(d); }\n\nextern \"C\" int armbench_entry_loop_032(void *a, void *b, int64_t n, void *res_out) {\n    if (n < 0 || n > std::numeric_limits<int>::max()) return -1;\n    struct loop_032_data data;\n    data.a = static_cast<double *>(a);\n    data.b = static_cast<double *>(b);\n    data.n = static_cast<int>(n);\n    data.res = 0.0;\n    _armbench_call_032(&data);\n    *static_cast<double *>(res_out) = data.res;\n    return 0;\n}\n"
-    },
-    {
-      "path": "kernel.cpp",
-      "content": "#include \"loop_032.h\"\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include <stdio.h>\n#include <limits.h>\n#include <assert.h>\n#include <math.h>\n#include <arm_sve.h>\n#define restrict __restrict\n#include <arm_sme.h>\n#define SC_SVE_LOOP_ATTR __arm_locally_streaming\n#define S_LOOP_ATTR __arm_locally_streaming __arm_new(\"za\", \"zt0\")\n#define NS_SVE_LOOP_ATTR\n#define SC_SVE_ATTR __arm_streaming_compatible\n#define S_SVE_ATTR __arm_streaming\n#define SC_SVE_ZT0_ATTR __arm_streaming_compatible __arm_inout(\"zt0\") __arm_preserves(\"za\")\n#define SME_ZA_ZT0_ATTR __arm_streaming __arm_inout(\"za\", \"zt0\")\n#define SME_ZA_ATTR __arm_streaming __arm_inout(\"za\") __arm_preserves(\"zt0\")\nstatic inline uint32_t get_sme_vl(void) {\n  uint64_t svl = 0; asm volatile(\"rdsvl %[svl], #8\" : [svl] \"+r\"(svl) : :);\n  return (uint32_t)svl;\n}\n#define NOINLINE __attribute__((noinline))\n#define FOR_COND(P, S, I, N) svptest_first(svptrue_b##S(), P = svwhilelt_b##S(I, N))\n#define FOR_LOOP(T, I, M, N, P, S, W) for (T I = M; FOR_COND(P, S, I, N); I += svcnt##W())\n#define FOR_LOOP_8(T, I, M, N, P)  FOR_LOOP(T, I, M, N, P, 8, b)\n#define FOR_LOOP_16(T, I, M, N, P) FOR_LOOP(T, I, M, N, P, 16, h)\n#define FOR_LOOP_32(T, I, M, N, P) FOR_LOOP(T, I, M, N, P, 32, w)\n#define FOR_LOOP_64(T, I, M, N, P) FOR_LOOP(T, I, M, N, P, 64, d)\nstatic inline uint32_t get_sve_vl(void) SC_SVE_ATTR {\n  uint64_t vl = 0; asm volatile(\"incb %[vl], all, mul #8\" : [vl] \"+r\"(vl) : :);\n  return (uint32_t)vl;\n}\nstatic inline uint32_t get_vl(void) { return get_sme_vl(); }\n// common/helpers.h: 64-byte-aligned scratch. Only reached when the harness\n// hands a kernel a NULL scratch buffer (it never does \u2014 every scratch field is\n// bound), so a plain aligned malloc stands in for Arm's arena allocator.\nstatic inline void *alloc_64b(uint64_t size, const char *name) {\n  void *p = NULL; (void)name;\n  if (posix_memalign(&p, 64, size ? size : 64) != 0) abort();\n  return p;\n}\n#define ALLOC_64B(P, S, N) P = (__typeof__(P))alloc_64b((S) * sizeof((P)[0]), N)\n\nextern \"C\" void inner_loop_032(struct loop_032_data * input) {\n  double *a = input->a;\n  double *b = input->b;\n  int n = input->n;\n  double res = 0.0;\n  int64_t lw = 0;\n  int64_t lmt = (n - 4) / 5;\n  asm volatile(\n      \"       mov     z0.d, #0                              \\n\"\n      \"       index   z4.d, #4, #5                          \\n\"\n      \"       whilele p0.d, xzr, %[lmt]                     \\n\"\n      \"1:     ld1d    {z2.d}, p0/z, [%[a], %[lw], lsl #3]   \\n\"\n      \"       incd    %[lw]                                 \\n\"\n      \"       ld1d    {z1.d}, p0/z, [%[b], z4.d, lsl #3]    \\n\"\n      \"       incb    %[b], all, mul #5                     \\n\"\n      \"       fmls    z0.d, p0/m, z1.d, z2.d                \\n\"\n      \"       whilele p0.d, %[lw], %[lmt]                   \\n\"\n      \"       b.any   1b                                    \\n\"\n      \"       ptrue   p0.d                                  \\n\"\n      \"       faddv   %d[res], p0, z0.d                     \\n\"\n      : [a] \"+&r\"(a), [b] \"+&r\"(b), [res] \"+&w\"(res), [lw] \"+&r\"(lw)\n      : [lmt] \"r\"(lmt)\n      : \"v0\", \"v1\", \"v2\", \"v3\", \"v4\", \"p0\", \"cc\", \"memory\");\n  input->res = res;\n}\n"
-    },
-    {
-      "path": "sme_abi_stub.cpp",
-      "content": "// Minimal SME ABI support routines (see scripts/gen_simd_loop_harness.py).\nextern \"C\" {\n__attribute__((naked)) void __arm_tpidr2_save(void) { __asm__ volatile(\"ret\"); }\n__attribute__((naked)) void __arm_tpidr2_restore(void *) { __asm__ volatile(\"ret\"); }\n__attribute__((naked)) void __arm_za_disable(void) { __asm__ volatile(\"smstop za\\n ret\"); }\n__attribute__((naked)) void __arm_sme_state(void) { __asm__ volatile(\"mrs x0, svcr\\n mrs x1, tpidr2_el0\\n ret\"); }\n}\n"
-    }
-  ],
-  "description": "Arm hand-written SVE kernel for loop_032 (sme2 tier expert ceiling)."
-}