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guychuk
/
kernel-opt-rl

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vllm
b466fbacd2ff68f0ed46a47f2551455ccbe76cef
2026-10-15T23:22:31-05:00
61,895
https://github.com/vllm-project/vllm/pull/61895
[ROCm][Perf] Any-shape low-latency MoE router GEMM on MI355 (#61895)
[ROCm][Perf] Any-shape low-latency MoE router GEMM on MI355 (#61895) Signed-off-by: Andreas Karatzas <akaratza@amd.com> Co-authored-by: Claude <noreply@anthropic.com>
vllm/model_executor/layers/fused_moe/router/rocm_fp32_router_gemm.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Low-token FP32 router GEMM for gfx950.""" import torch from vllm.platforms import current_platform from vllm.platforms.rocm import on_gfx950 from vllm.triton_utils import tl, triton _MAX_TOKENS = 32 ROCM_FP3...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Low-token router GEMM with FP32 output for gfx950 (FP32 or BF16 weights).""" import torch from vllm.platforms import current_platform from vllm.platforms.rocm import on_gfx950 from vllm.triton_utils import tl...
--- vllm/model_executor/layers/fused_moe/router/rocm_fp32_router_gemm.py +++ vllm/model_executor/layers/fused_moe/router/rocm_fp32_router_gemm.py @@ -1,6 +1,6 @@ # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project -"""Low-token FP32 router GEMM for gfx950.""" +""...
66
39
2
[]
[ "MI355", "ROCM" ]
[]
Optimize this triton kernel file from vllm (vllm/model_executor/layers/fused_moe/router/rocm_fp32_router_gemm.py). Goal: [ROCm][Perf] Any-shape low-latency MoE router GEMM on MI355 Target hardware: MI355, ROCM Target models: unspecified Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrigh...
## Overview On MI355 (gfx950), the MoE router GEMM now has a low-latency kernel for **any** router shape (fp32 or bf16 weights, fp32 output, M ≤ 32), matching the CuTeDSL `ll_fp32w` / `ll_bf16` router kernels from #44343 and #50174. Previously only five hard-coded `(hidden_size, num_experts)` shapes had a fast path;...
[{"scope": "e2e", "hardware": "MI355", "model": "ERNIE-4.5-21B-A3B", "shape": "fp32 2560\u00d764", "batch_size": 1, "metric": "decode throughput", "unit": "%", "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 1.141, "speedup": 1.141}, {"scope": "e2e", "hardware": "MI355", "model": "ERNIE...
2.585
1.043
vllm
e711723352670e811b0e904300d771471e28930d
2026-10-15T16:51:57-05:00
58,800
https://github.com/vllm-project/vllm/pull/58800
[ROCm] gfx1250 optimizations and model enablement (#58800)
[ROCm] gfx1250 optimizations and model enablement (#58800) Signed-off-by: jpvillam <juan.villamizar@amd.com> Signed-off-by: Jaden Mathias <jaden.mathias@amd.com> Signed-off-by: Juan Villamizar <jpvillam@amd.com> Signed-off-by: jpvillam <jpvillam@amd.com> Signed-off-by: Omar Muhammad <omar.muhammad@amd.com> Signed-off-...
vllm/model_executor/layers/quantization/utils/mxfp4_utils.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project from typing import Any import torch from vllm.logger import init_logger from vllm.platforms import current_platform from vllm.triton_utils import tl, triton from vllm.utils.import_utils import get_triton_kernels...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project from typing import Any import torch from vllm.logger import init_logger from vllm.platforms import current_platform from vllm.triton_utils import tl, triton from vllm.utils.import_utils import get_triton_kernels...
--- vllm/model_executor/layers/quantization/utils/mxfp4_utils.py +++ vllm/model_executor/layers/quantization/utils/mxfp4_utils.py @@ -11,6 +11,14 @@ from vllm.utils.torch_utils import direct_register_custom_op, is_torch_equal_or_newer logger = init_logger(__name__) + + +def should_use_gfx1250_mx_scale_swizzle() -> ...
28
0
10
[]
[ "GFX1250", "ROCM" ]
[]
Optimize this triton kernel file from vllm (vllm/model_executor/layers/quantization/utils/mxfp4_utils.py). Goal: [ROCm] gfx1250 optimizations and model enablement Target hardware: GFX1250, ROCM Target models: unspecified Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright...
## Purpose Enables and optimizes gfx1250 (ROCm) for gpt-oss-120b, DeepSeek-R1-0528, DeepSeek-V4-Flash and MiniMax-M3 (MXFP4). Every change is limited to gfx1250; other ROCm and CUDA paths behave as before. - **MoE:** new AITER Triton/Gluon W4A4 MXFP4 expert (`aiter_mxfp4_w4a4_moe.py`), with its own backend enum...
[]
null
null
vllm
82b9ccaa798eeec73f40ea7766d4044cfeaaff32
2026-10-16T03:09:07+08:00
61,773
https://github.com/vllm-project/vllm/pull/61773
[Perf][MoE] Skip the TRTLLM fp8-block activation-scale transpose copy (#61773)
[Perf][MoE] Skip the TRTLLM fp8-block activation-scale transpose copy (#61773) Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
vllm/model_executor/layers/fused_moe/utils.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project import functools from collections.abc import Iterable from math import prod from typing import TYPE_CHECKING import torch import torch.nn.functional as F from torch import nn import vllm.envs as envs from vllm i...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project import functools from collections.abc import Iterable from math import prod from typing import TYPE_CHECKING import torch import torch.nn.functional as F from torch import nn import vllm.envs as envs from vllm i...
--- vllm/model_executor/layers/fused_moe/utils.py +++ vllm/model_executor/layers/fused_moe/utils.py @@ -325,6 +325,7 @@ A_scale: torch.Tensor | None, per_act_token: bool, block_shape: list[int] | None = None, + is_scale_transposed: bool = False, ) -> tuple[torch.Tensor, torch.Tensor]: """Perform...
8
2
4
[]
[]
[]
Optimize this triton kernel file from vllm (vllm/model_executor/layers/fused_moe/utils.py). Goal: [Perf][MoE] Skip the TRTLLM fp8-block activation-scale transpose copy Target hardware: unspecified Target models: unspecified Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyri...
## Overview Skip the per-layer `a1q_scale.t().contiguous()` copy between per-token-group FP8 quantization and the FlashInfer TRTLLM fp8-block MoE experts by emitting the scales in the layout the experts consume. This is pure plumbing on top of the quant kernel's existing `column_major_scales` mode — no kernel change...
[{"scope": "e2e", "hardware": "4xGB300", "model": "Qwen3.8-Flash-Next-FP8", "shape": null, "batch_size": 4, "metric": "TPOT p50", "unit": "ms", "higher_is_better": false, "baseline": 5.115, "optimized": 4.99, "stated_speedup": null, "speedup": 1.0251}, {"scope": "e2e", "hardware": "4xGB300", "model": "Qwen3.8-Flash-Nex...
null
1.0251
vllm
c825e1d235896694ca50160286440859ed46d7d3
2026-10-15T09:02:53-07:00
58,737
https://github.com/vllm-project/vllm/pull/58737
[Perf] Fuse the mamba align block-table gather into one Triton kernel, 7 kernels -> 1, 6x speedup on all shapes for this kernel (#58737)
[Perf] Fuse the mamba align block-table gather into one Triton kernel, 7 kernels -> 1, 6x speedup on all shapes for this kernel (#58737) Signed-off-by: lifulu <fululi12@amd.com> Signed-off-by: lifulu <lifulu@users.noreply.github.com> Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com> Co-authored-by: li...
vllm/v1/attention/backends/utils.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project import math from collections import defaultdict from collections.abc import Callable, Iterable, Sequence from dataclasses import dataclass, field, fields from typing import ( TYPE_CHECKING, Any, Protoc...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project import math from collections import defaultdict from collections.abc import Callable, Iterable, Sequence from dataclasses import dataclass, field, fields from typing import ( TYPE_CHECKING, Any, Protoc...
--- vllm/v1/attention/backends/utils.py +++ vllm/v1/attention/backends/utils.py @@ -18,6 +18,7 @@ from vllm.config import CacheConfig, VllmConfig, get_layers_from_vllm_config from vllm.config.cache import _layout_from_name +from vllm.triton_utils import tl, triton from vllm.utils.gpu_sync_debug import gpu_sync_all...
124
12
1
[ "mamba" ]
[]
[ "6x" ]
Optimize this triton kernel file from vllm (vllm/v1/attention/backends/utils.py). Goal: [Perf] Fuse the mamba align block-table gather into one Triton kernel, 7 kernels -> 1, 6x speedup on all shapes for this kernel Target hardware: unspecified Target models: mamba Current file: ```python # SPDX-License-Identifier: A...
> [!IMPORTANT] > **Scope: this is a kernel-level microbenchmark, not an end-to-end throughput claim.** > The numbers below are measured on the isolated kernel, both versions in the same process. Against a multi-millisecond decode step a > change of this size sits inside run-to-run variation (~1% on a conc=1 arm), so > ...
[{"scope": "kernel", "hardware": "MI355X", "model": null, "shape": "num_reqs=1,spec_blocks=7", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 10.81, "optimized": 1.78, "stated_speedup": 6.06, "speedup": 6.073}, {"scope": "kernel", "hardware": "MI355X", "model": null, "shape":...
6.084
null
vllm
7c3f7e5500c85aacb72aab50bd1ce05485b1d73a
2026-10-14T13:15:58-07:00
61,039
https://github.com/vllm-project/vllm/pull/61039
[Perf][DSv4.1] Length-aware candidate block selection in the decode indexer (#61039)
[Perf][DSv4.1] Length-aware candidate block selection in the decode indexer (#61039) Signed-off-by: Juntian Liu <Juntianl777@gmail.com>
vllm/model_executor/layers/sparse_attn_indexer.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Custom Sparse Attention Indexer layers.""" import torch import torch.distributed as dist import vllm.envs as envs from vllm import _custom_ops as ops from vllm._aiter_ops import rocm_aiter_ops from vllm.compi...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Custom Sparse Attention Indexer layers.""" import torch import torch.distributed as dist import vllm.envs as envs from vllm import _custom_ops as ops from vllm._aiter_ops import rocm_aiter_ops from vllm.compi...
--- vllm/model_executor/layers/sparse_attn_indexer.py +++ vllm/model_executor/layers/sparse_attn_indexer.py @@ -877,20 +877,20 @@ padded_q_scale, decode_weights = mqa_logits_mx_inputs( padded_q_quant_cast, padded_q_scale, weights[:num_padded_tokens] ) - # SM100 deco...
14
14
1
[ "deepseek" ]
[]
[]
Optimize this triton kernel file from vllm (vllm/model_executor/layers/sparse_attn_indexer.py). Goal: [Perf][DSv4.1] Length-aware candidate block selection in the decode indexer Target hardware: unspecified Target models: deepseek Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText:...
## Purpose DeepSeek-V4.1's decode indexer writes its logits into a `[rows, max_model_len]` buffer, a width that must stay static for CUDA graphs (1M with the default `max_model_len`). Each row only holds its own context, but `select_candidate_blocks` scored every block of the full width and then ran `torch.topk(2048)`...
[{"scope": "kernel", "hardware": "GB300", "model": "DeepSeek-V4.1-Flash", "shape": "rows=384, max_model_len=1048576, candidate_blocks=2048, block_size=8", "batch_size": 384, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 847.8, "optimized": 42.9, "stated_speedup": 19.8, "speedup": 19.7622}, {...
10.6092
4.9582
vllm
355553ac22dca4080929ea8f88a446f15df1f3ba
2026-10-15T00:15:51+08:00
58,354
https://github.com/vllm-project/vllm/pull/58354
[ROCm][Perf] Drop two dead per-step ops from the AITER sparse MLA metadata build (#58354)
[ROCm][Perf] Drop two dead per-step ops from the AITER sparse MLA metadata build (#58354) Signed-off-by: ZhengGong-amd <zgong@amd.com> Co-authored-by: Cursor <cursoragent@cursor.com>
vllm/v1/attention/backends/mla/rocm_aiter_mla_sparse.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project from dataclasses import dataclass from typing import TYPE_CHECKING, ClassVar import numpy as np import torch from vllm import _custom_ops as ops from vllm._aiter_ops import rocm_aiter_ops from vllm.config impor...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project from dataclasses import dataclass from typing import TYPE_CHECKING, ClassVar import numpy as np import torch from vllm import _custom_ops as ops from vllm._aiter_ops import rocm_aiter_ops from vllm.config impor...
--- vllm/v1/attention/backends/mla/rocm_aiter_mla_sparse.py +++ vllm/v1/attention/backends/mla/rocm_aiter_mla_sparse.py @@ -322,16 +322,15 @@ def generate_sparse_seqlen_triton( - query_lens: torch.Tensor, seq_lens: torch.Tensor, cu_query_lens: torch.Tensor, topk_token: int, num_tokens: int, ...
5
6
1
[]
[ "ROCM" ]
[]
Optimize this triton kernel file from vllm (vllm/v1/attention/backends/mla/rocm_aiter_mla_sparse.py). Goal: [ROCm][Perf] Drop two dead per-step ops from the AITER sparse MLA metadata build Target hardware: ROCM Target models: unspecified Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrig...
## Purpose `ROCMAiterMLASparseMetadataBuilder.build()` runs once per KV-cache group per scheduler step and launches two GPU ops whose results are not needed: 1. **Unused `query_lens`.** `build()` computes `query_start_loc[1:] - query_start_loc[:-1]`, but `generate_sparse_seqlen_triton` only reads its size and device;...
[{"scope": "kernel", "hardware": "MI355X", "model": "GLM-5.3", "shape": null, "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 91.48, "optimized": 80.68, "stated_speedup": null, "speedup": 1.1339}, {"scope": "kernel", "hardware": "MI355X", "model": "GLM-5.3", "shape": null, "ba...
1.128
1.0054
vllm
badfcdbf919532624b2296eeacb85c6dd9fe2e58
2026-10-14T14:49:46+08:00
60,050
https://github.com/vllm-project/vllm/pull/60050
[Perf][GDN] Internal prefill checkpoints for the FlashInfer GDN prefill backend (#60050)
[Perf][GDN] Internal prefill checkpoints for the FlashInfer GDN prefill backend (#60050) Signed-off-by: zjy0516 <riverclouds.zhu@qq.com> Co-authored-by: Claude Opus 5.5 <noreply@anthropic.com>
vllm/model_executor/layers/mamba/checkpoint.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project from abc import ABC, abstractmethod from dataclasses import dataclass, replace import torch from vllm.config import VllmConfig from vllm.utils.math_utils import cdiv from vllm.utils.torch_utils import async_ten...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project from dataclasses import dataclass, replace import torch from vllm.config import VllmConfig from vllm.triton_utils import tl, triton from vllm.utils.math_utils import cdiv from vllm.utils.torch_utils import asyn...
--- vllm/model_executor/layers/mamba/checkpoint.py +++ vllm/model_executor/layers/mamba/checkpoint.py @@ -1,12 +1,12 @@ # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project -from abc import ABC, abstractmethod from dataclasses import dataclass, replace impor...
127
11
5
[ "mamba" ]
[]
[]
Optimize this triton kernel file from vllm (vllm/model_executor/layers/mamba/checkpoint.py). Goal: [Perf][GDN] Internal prefill checkpoints for the FlashInfer GDN prefill backend Target hardware: unspecified Target models: mamba Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: C...
<!-- markdownlint-disable --> ## Overview Internal prefill checkpoints (RFC #52959) for Qwen GDN models (Qwen3-Next, Qwen3.5) on the FlashInfer GDN prefill backend. With prefix caching on (Mamba align mode), a prompt that crosses its cacheable block boundary no longer needs two forward passes: FlashInfer's prefill em...
[{"scope": "e2e", "hardware": "GB200", "model": "Qwen3.5-35B-A3B", "shape": "N=8000", "batch_size": 1, "metric": "TTFT", "unit": "ms", "higher_is_better": false, "baseline": 188.0, "optimized": 150.8, "stated_speedup": null, "speedup": 1.2467}, {"scope": "e2e", "hardware": "GB200", "model": "Qwen3.5-35B-A3B", "shape": ...
null
1.0089
vllm
2308b6f00be1b65c0b9159e922c529ead5299603
2026-10-14T10:48:05+08:00
58,897
https://github.com/vllm-project/vllm/pull/58897
[Perf][MoE] Cheaper triton_kernels 3.8 routing build in the OAI Triton MoE (#58897)
[Perf][MoE] Cheaper triton_kernels 3.8 routing build in the OAI Triton MoE (#58897) Signed-off-by: Zheng Gong <zgong@amd.com> Co-authored-by: Cursor <cursoragent@cursor.com> Co-authored-by: Shanshan Shen <467638484@qq.com>
vllm/model_executor/layers/fused_moe/experts/gpt_oss_triton_kernels_moe.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project import functools import torch import vllm.model_executor.layers.fused_moe.modular_kernel as mk from vllm.logger import init_logger from vllm.model_executor.layers.fused_moe.activation import MoEActivation from ...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project import functools import torch import vllm.model_executor.layers.fused_moe.modular_kernel as mk from vllm.logger import init_logger from vllm.model_executor.layers.fused_moe.activation import MoEActivation from ...
--- vllm/model_executor/layers/fused_moe/experts/gpt_oss_triton_kernels_moe.py +++ vllm/model_executor/layers/fused_moe/experts/gpt_oss_triton_kernels_moe.py @@ -847,6 +847,20 @@ return output_tensor +def _tk38_routing_data( + col_sum: torch.Tensor, + order: torch.Tensor, + flat_w: torch.Tensor, + ...
34
17
1
[]
[]
[]
Optimize this triton kernel file from vllm (vllm/model_executor/layers/fused_moe/experts/gpt_oss_triton_kernels_moe.py). Goal: [Perf][MoE] Cheaper triton_kernels 3.8 routing build in the OAI Triton MoE Target hardware: unspecified Target models: unspecified Current file: ```python # SPDX-License-Identifier: Apache-2....
## Purpose On triton_kernels 3.8, which every ROCm build ships since #50605, the MoE routing metadata is rebuilt in torch with an int64 stable `argsort` and a `scatter_add_` histogram, costing 31–178 µs per MoE layer per step on MI355X / MI325X. - `make_routing_data` sorts the ids in their own dtype and reads per-exp...
[{"scope": "kernel", "hardware": "MI355X", "model": "DeepSeek-V4-Flash", "shape": null, "batch_size": null, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 104, "optimized": 61, "stated_speedup": null, "speedup": 1.7049}, {"scope": "kernel", "hardware": "MI325X", "model": "DeepSeek-V4-Flash", ...
2.8875
1.022
vllm
c19c263ac8ea3fd6e1d2d689f0e4e725855d89cf
2026-10-13T16:06:41-04:00
60,927
https://github.com/vllm-project/vllm/pull/60927
[GLM 5.3 Perf] Handle two elements at the same time for per token group quant, 2.8% E2E ITL improvement (#60927)
[GLM 5.3 Perf] Handle two elements at the same time for per token group quant, 2.8% E2E ITL improvement (#60927) Signed-off-by: yewentao256 <zhyanwentao@126.com>
csrc/quantization/w8a8/fp8/per_token_group_quant.cu
cuda
Apache-2.0
#include <torch/csrc/stable/tensor.h> #include <torch/csrc/stable/ops.h> #include <torch/headeronly/util/Exception.h> #include <torch/headeronly/core/ScalarType.h> #include <cmath> #ifdef USE_ROCM #include <hip/hip_fp8.h> #else #include <cuda_fp8.h> #endif #include "quantization/vectorization.cuh" #include "quan...
#include <torch/csrc/stable/tensor.h> #include <torch/csrc/stable/ops.h> #include <torch/headeronly/util/Exception.h> #include <torch/headeronly/core/ScalarType.h> #include <cmath> #include <type_traits> #ifdef USE_ROCM #include <hip/hip_fp8.h> #else #include <cuda_bf16.h> #include <cuda_fp8.h> #endif #include...
--- csrc/quantization/w8a8/fp8/per_token_group_quant.cu +++ csrc/quantization/w8a8/fp8/per_token_group_quant.cu @@ -4,10 +4,12 @@ #include <torch/headeronly/core/ScalarType.h> #include <cmath> +#include <type_traits> #ifdef USE_ROCM #include <hip/hip_fp8.h> #else + #include <cuda_bf16.h> #include <cuda_f...
55
26
1
[ "glm" ]
[]
[]
Optimize this cuda kernel file from vllm (csrc/quantization/w8a8/fp8/per_token_group_quant.cu). Goal: [GLM 5.3 Perf] Handle two elements at the same time for per token group quant, 2.8% E2E ITL improvement Target hardware: unspecified Target models: glm Current file: ```cuda #include <torch/csrc/stable/tensor.h> #inc...
## Overview Handle two elements at the same time for per token group quant Using specific instruction __nv_fp8x2_e4m3, __hmin2 etc to get additional perf ## Test ```bash vllm serve zai-org/GLM-5.3 \ --trust-remote-code \ -tp 4 \ --load-format fastsafetensors \ --gpu-memory-utilization 0.88 \ --e...
[]
null
null
vllm
e83222396f6c9ceb72f80c0d82782071bbd8317c
2026-10-13T19:21:30+02:00
57,199
https://github.com/vllm-project/vllm/pull/57199
[ROCm][Perf] W4A16: speed up skinny GEMM decode, including speculative batches (#57199)
[ROCm][Perf] W4A16: speed up skinny GEMM decode, including speculative batches (#57199) Signed-off-by: Robert Esclapez Garcia <robert.garcia@amd.com> Co-authored-by: Claude Opus 4.7 <noreply@anthropic.com> Co-authored-by: Douglas Lehr <91553416+dllehr-amd@users.noreply.github.com>
csrc/rocm/skinny_gemms_int4.cu
cuda
Apache-2.0
#include <torch/all.h> #include <ATen/cuda/CUDAContext.h> #include <c10/cuda/CUDAGuard.h> #include <cuda_runtime.h> #include <cuda_fp16.h> #include <cuda_bf16.h> #include <stdexcept> #include <algorithm> #include <utility> // std::in_range #include "core/cuda_compat.h" // Combined RDNA macro (gfx11 + gfx12) - both...
#include <torch/all.h> #include <ATen/cuda/CUDAContext.h> #include <c10/cuda/CUDAGuard.h> #include <cuda_runtime.h> #include <cuda_fp16.h> #include <cuda_bf16.h> #include <stdexcept> #include <algorithm> #include <type_traits> #include <utility> // std::in_range #include "core/cuda_compat.h" // Combined RDNA macro...
--- csrc/rocm/skinny_gemms_int4.cu +++ csrc/rocm/skinny_gemms_int4.cu @@ -8,6 +8,7 @@ #include <stdexcept> #include <algorithm> +#include <type_traits> #include <utility> // std::in_range #include "core/cuda_compat.h" @@ -17,9 +18,26 @@ #define __HIP__GFX1X__ #endif +// The decode tuning and the deep-K r...
446
98
1
[]
[ "ROCM" ]
[]
Optimize this cuda kernel file from vllm (csrc/rocm/skinny_gemms_int4.cu). Goal: [ROCm][Perf] W4A16: speed up skinny GEMM decode, including speculative batches Target hardware: ROCM Target models: unspecified Current file: ```cuda #include <torch/all.h> #include <ATen/cuda/CUDAContext.h> #include <c10/cuda/CUDAGuard....
## Summary Tunes the W4A16 skinny GEMM decode path on gfx115x, and stops routing deep-K decode shapes away from it. The kernel compiles for gfx11 and gfx12, and everything here was measured on gfx1151, so **every commit gates itself to gfx115x** -- the tuning and the routing alike. Off gfx115x the kernel runs exactly...
[{"scope": "kernel", "hardware": "gfx1151", "model": null, "shape": "M=43008,K=5376", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 634.8, "optimized": 499.2, "stated_speedup": null, "speedup": 1.2716}, {"scope": "kernel", "hardware": "gfx1151", "model": null, "shape": "M=53...
1.1968
1.1168
vllm
0fae39a0142c5d296f7938fa753e8f00b5d80171
2026-10-13T21:37:10+08:00
61,343
https://github.com/vllm-project/vllm/pull/61343
[Perf] per_token_group_quant_8bit: multiply by reciprocal instead of dividing per element (#61343)
[Perf] per_token_group_quant_8bit: multiply by reciprocal instead of dividing per element (#61343) Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
csrc/quantization/fused_kernels/layernorm_utils.cuh
cuda
Apache-2.0
#pragma once /** * __device__ layernorm utilities. */ #include "quantization/vectorization.cuh" #include "quantization/utils.cuh" #include "quant_conversions.cuh" #include "../../cub_helpers.h" #include "core/cuda_compat.h" namespace vllm { // has_residual must be true, if residual is not a nullptr template <typ...
#pragma once /** * __device__ layernorm utilities. */ #include "quantization/vectorization.cuh" #include "quantization/utils.cuh" #include "quant_conversions.cuh" #include "../../cub_helpers.h" #include "core/cuda_compat.h" namespace vllm { // has_residual must be true, if residual is not a nullptr template <typ...
--- csrc/quantization/fused_kernels/layernorm_utils.cuh +++ csrc/quantization/fused_kernels/layernorm_utils.cuh @@ -516,6 +516,11 @@ q8x4_t<scalar_out_t> out; + // Group quant multiplies by the reciprocal of the scale (one div per + // group), matching per_token_group_quant_8bit. Per-token fp8 must keep ...
7
3
2
[]
[]
[]
Optimize this cuda kernel file from vllm (csrc/quantization/fused_kernels/layernorm_utils.cuh). Goal: [Perf] per_token_group_quant_8bit: multiply by reciprocal instead of dividing per element Target hardware: unspecified Target models: unspecified Current file: ```cuda #pragma once /** * __device__ layernorm utilit...
<!-- markdownlint-disable --> ## Overview Speed up FP8 per-token-group quantization by computing the per-group scale reciprocal once and multiplying, instead of dividing per element. This covers both CUDA group-quant kernels: `per_token_group_quant_8bit` (smem and register-resident schedules) and the fused RMSNorm+gr...
[{"scope": "kernel", "hardware": "GB300", "model": null, "shape": "K=4096,group=128", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 2.3, "optimized": 1.92, "stated_speedup": 1.2, "speedup": 1.1979}, {"scope": "kernel", "hardware": "GB300", "model": null, "shape": "K=4096,gro...
1.2188
1.0162
vllm
0fae39a0142c5d296f7938fa753e8f00b5d80171
2026-10-13T21:37:10+08:00
61,343
https://github.com/vllm-project/vllm/pull/61343
[Perf] per_token_group_quant_8bit: multiply by reciprocal instead of dividing per element (#61343)
[Perf] per_token_group_quant_8bit: multiply by reciprocal instead of dividing per element (#61343) Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
csrc/quantization/w8a8/fp8/per_token_group_quant.cu
cuda
Apache-2.0
#include <torch/csrc/stable/tensor.h> #include <torch/csrc/stable/ops.h> #include <torch/headeronly/util/Exception.h> #include <torch/headeronly/core/ScalarType.h> #include <cmath> #ifdef USE_ROCM #include <hip/hip_fp8.h> #else #include <cuda_fp8.h> #endif #include "quantization/vectorization.cuh" #include "quan...
#include <torch/csrc/stable/tensor.h> #include <torch/csrc/stable/ops.h> #include <torch/headeronly/util/Exception.h> #include <torch/headeronly/core/ScalarType.h> #include <cmath> #ifdef USE_ROCM #include <hip/hip_fp8.h> #else #include <cuda_fp8.h> #endif #include "quantization/vectorization.cuh" #include "quan...
--- csrc/quantization/w8a8/fp8/per_token_group_quant.cu +++ csrc/quantization/w8a8/fp8/per_token_group_quant.cu @@ -78,9 +78,13 @@ const float y_s, const float min_8bit, const float max_8bit) { constexpr int vec_size = 16 / sizeof(T); + // One div.rn per group instead of per element; the register-resident + ...
8
6
2
[]
[]
[]
Optimize this cuda kernel file from vllm (csrc/quantization/w8a8/fp8/per_token_group_quant.cu). Goal: [Perf] per_token_group_quant_8bit: multiply by reciprocal instead of dividing per element Target hardware: unspecified Target models: unspecified Current file: ```cuda #include <torch/csrc/stable/tensor.h> #include <...
<!-- markdownlint-disable --> ## Overview Speed up FP8 per-token-group quantization by computing the per-group scale reciprocal once and multiplying, instead of dividing per element. This covers both CUDA group-quant kernels: `per_token_group_quant_8bit` (smem and register-resident schedules) and the fused RMSNorm+gr...
[{"scope": "kernel", "hardware": "GB300", "model": null, "shape": "K=4096,group=128", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 2.3, "optimized": 1.92, "stated_speedup": 1.2, "speedup": 1.1979}, {"scope": "kernel", "hardware": "GB300", "model": null, "shape": "K=4096,gro...
1.2188
1.0162
vllm
0d2689e0dfd5e9f74f361cab7701df0feee33ef3
2026-10-13T08:25:56+03:00
51,309
https://github.com/vllm-project/vllm/pull/51309
[ROCm][Perf] Skip redundant sparse index remap on non-indexer layers (#51309)
[ROCm][Perf] Skip redundant sparse index remap on non-indexer layers (#51309) Signed-off-by: Sriram Kumar <sriramkumar.kishorekumar@amd.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> Co-authored-by: Douglas Lehr <91553416+dllehr-amd@users.noreply.github.com> Co-authored-by: Andreas ...
vllm/v1/attention/backends/mla/rocm_aiter_mla_sparse.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project from dataclasses import dataclass from typing import TYPE_CHECKING, ClassVar import numpy as np import torch from vllm import _custom_ops as ops from vllm._aiter_ops import rocm_aiter_ops from vllm.config impor...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project from dataclasses import dataclass from typing import TYPE_CHECKING, ClassVar import numpy as np import torch from vllm import _custom_ops as ops from vllm._aiter_ops import rocm_aiter_ops from vllm.config impor...
--- vllm/v1/attention/backends/mla/rocm_aiter_mla_sparse.py +++ vllm/v1/attention/backends/mla/rocm_aiter_mla_sparse.py @@ -401,6 +401,18 @@ return on_mi3xx() +# Indexer writes per shared top-k buffer, in layer construction order. +_INDEX_EPOCHS: dict[int, int] = {} + + +def _index_epoch(buf: object, owns_...
46
16
1
[]
[ "ROCM" ]
[]
Optimize this triton kernel file from vllm (vllm/v1/attention/backends/mla/rocm_aiter_mla_sparse.py). Goal: [ROCm][Perf] Skip redundant sparse index remap on non-indexer layers Target hardware: ROCM Target models: unspecified Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copy...
## Summary With cross-layer index sharing, only some attention layers update the shared top-k buffer. The old path still remapped that buffer on every layer. This PR runs the remap only when the layer owns an indexer. For GLM-5.2 with `index_topk_freq = 4`, this reduces remaps from 78 to 21 per forward pass. ## Safe...
[{"scope": "kernel", "hardware": "MI355X", "model": null, "shape": null, "batch_size": null, "metric": "launches", "unit": null, "higher_is_better": false, "baseline": 139378, "optimized": 37254, "stated_speedup": null, "speedup": 3.7413}, {"scope": "kernel", "hardware": "MI355X", "model": null, "shape": null, "batch_s...
3.7175
1.0063
vllm
50b21a2667b6903d2e0d651aab9f449832e5e1e9
2026-10-12T23:50:28+08:00
49,263
https://github.com/vllm-project/vllm/pull/49263
[Perf] [Feat] [ROCm] Add densemha support to ROCm AITER Sparse MLA (#49263)
[Perf] [Feat] [ROCm] Add densemha support to ROCm AITER Sparse MLA (#49263) Signed-off-by: tjtanaa <tunjian.tan@embeddedllm.com>
vllm/v1/attention/backends/mla/rocm_aiter_mla_sparse.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project from dataclasses import dataclass from typing import TYPE_CHECKING, ClassVar import numpy as np import torch from vllm import _custom_ops as ops from vllm._aiter_ops import rocm_aiter_ops from vllm.config impor...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project from dataclasses import dataclass from typing import TYPE_CHECKING, ClassVar import numpy as np import torch from vllm import _custom_ops as ops from vllm._aiter_ops import rocm_aiter_ops from vllm.config impor...
--- vllm/v1/attention/backends/mla/rocm_aiter_mla_sparse.py +++ vllm/v1/attention/backends/mla/rocm_aiter_mla_sparse.py @@ -12,11 +12,10 @@ from vllm.config import VllmConfig, get_current_vllm_config from vllm.config.cache import CacheDType from vllm.logger import init_logger -from vllm.model_executor.layers.attenti...
110
106
1
[]
[ "ROCM" ]
[]
Optimize this triton kernel file from vllm (vllm/v1/attention/backends/mla/rocm_aiter_mla_sparse.py). Goal: [Perf] [Feat] [ROCm] Add densemha support to ROCm AITER Sparse MLA Target hardware: ROCM Target models: unspecified Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyri...
## What is the feature about? Adds dense MHA for short prefill in the ROCm AITER Sparse MLA backend, following #47327. Prefill at or below the sparse top-k threshold (2,048 tokens for DeepSeek-V3.2) uses dense attention; longer prefill and decode retain sparse MQA. The fused DeepSeek-V3.2 path is integrated so mixed p...
[{"scope": "e2e", "hardware": "gfx950", "model": "DeepSeek-V3.2", "shape": null, "batch_size": 8, "metric": "TTFT", "unit": "ms", "higher_is_better": false, "baseline": 526.61, "optimized": 480.76, "stated_speedup": null, "speedup": 1.0954}, {"scope": "e2e", "hardware": "gfx950", "model": "DeepSeek-V3.2", "shape": null...
null
1.0288
vllm
3e8e1364ff41330fb667b2d76d6645176d61fdd0
2026-10-11T22:43:37+08:00
54,951
https://github.com/vllm-project/vllm/pull/54951
[Perf][GLM-5.3-Flash] Shard long-context indexer prefill rows across TP (#54951)
[Perf][GLM-5.3-Flash] Shard long-context indexer prefill rows across TP (#54951) Signed-off-by: Zheng Cai <8370601+zigzagcai@users.noreply.github.com> Signed-off-by: Zheng Cai <caizheng1993@gmail.com> Signed-off-by: Codex <noreply@openai.com> Co-authored-by: root <root@rjob-fb29567b88fec0a9-88c9a4c797eb2ec1-0.caizheng...
vllm/model_executor/layers/sparse_attn_indexer.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Custom Sparse Attention Indexer layers.""" import torch import torch.distributed as dist import vllm.envs as envs from vllm import _custom_ops as ops from vllm._aiter_ops import rocm_aiter_ops from vllm.compi...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Custom Sparse Attention Indexer layers.""" import torch import torch.distributed as dist import vllm.envs as envs from vllm import _custom_ops as ops from vllm._aiter_ops import rocm_aiter_ops from vllm.compi...
--- vllm/model_executor/layers/sparse_attn_indexer.py +++ vllm/model_executor/layers/sparse_attn_indexer.py @@ -9,8 +9,17 @@ from vllm import _custom_ops as ops from vllm._aiter_ops import rocm_aiter_ops from vllm.compilation.breakable_cudagraph import eager_break_during_capture -from vllm.config import CUDAGraphMod...
111
15
2
[ "glm" ]
[]
[]
Optimize this triton kernel file from vllm (vllm/model_executor/layers/sparse_attn_indexer.py). Goal: [Perf][GLM-5.3-Flash] Shard long-context indexer prefill rows across TP Target hardware: unspecified Target models: glm Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyrigh...
## TL;DR **How it works / why it is faster:** Instead of repeating sparse-indexer prefill MQA scoring and top-k on every TP rank, partition independent query rows into cost-balanced contiguous slices. Each rank scores its rows against the full available key history; `all_gatherv` reassembles the final int32 indices. T...
[{"scope": "e2e", "hardware": "H200", "model": "GLM-5.3-Flash", "shape": "C1", "batch_size": 65536, "metric": "TTFT", "unit": "seconds", "higher_is_better": false, "baseline": 4.782, "optimized": 4.605, "stated_speedup": null, "speedup": 1.0384}, {"scope": "e2e", "hardware": "H200", "model": "GLM-5.3-Flash", "shape": "...
null
1.0279
vllm
3e8e1364ff41330fb667b2d76d6645176d61fdd0
2026-10-11T22:43:37+08:00
54,951
https://github.com/vllm-project/vllm/pull/54951
[Perf][GLM-5.3-Flash] Shard long-context indexer prefill rows across TP (#54951)
[Perf][GLM-5.3-Flash] Shard long-context indexer prefill rows across TP (#54951) Signed-off-by: Zheng Cai <8370601+zigzagcai@users.noreply.github.com> Signed-off-by: Zheng Cai <caizheng1993@gmail.com> Signed-off-by: Codex <noreply@openai.com> Co-authored-by: root <root@rjob-fb29567b88fec0a9-88c9a4c797eb2ec1-0.caizheng...
vllm/v1/attention/backends/mla/indexer.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project from dataclasses import dataclass from typing import Any import numpy as np import torch import vllm.envs as envs from vllm.config import VllmConfig, get_current_vllm_config from vllm.distributed import get_dcp_...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project from dataclasses import dataclass from typing import Any import numpy as np import torch import vllm.envs as envs from vllm.config import CUDAGraphMode, VllmConfig, get_current_vllm_config from vllm.distributed ...
--- vllm/v1/attention/backends/mla/indexer.py +++ vllm/v1/attention/backends/mla/indexer.py @@ -7,7 +7,7 @@ import torch import vllm.envs as envs -from vllm.config import VllmConfig, get_current_vllm_config +from vllm.config import CUDAGraphMode, VllmConfig, get_current_vllm_config from vllm.distributed import get...
73
1
2
[ "glm" ]
[]
[]
Optimize this triton kernel file from vllm (vllm/v1/attention/backends/mla/indexer.py). Goal: [Perf][GLM-5.3-Flash] Shard long-context indexer prefill rows across TP Target hardware: unspecified Target models: glm Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contri...
## TL;DR **How it works / why it is faster:** Instead of repeating sparse-indexer prefill MQA scoring and top-k on every TP rank, partition independent query rows into cost-balanced contiguous slices. Each rank scores its rows against the full available key history; `all_gatherv` reassembles the final int32 indices. T...
[{"scope": "e2e", "hardware": "H200", "model": "GLM-5.3-Flash", "shape": "C1", "batch_size": 65536, "metric": "TTFT", "unit": "seconds", "higher_is_better": false, "baseline": 4.782, "optimized": 4.605, "stated_speedup": null, "speedup": 1.0384}, {"scope": "e2e", "hardware": "H200", "model": "GLM-5.3-Flash", "shape": "...
null
1.0279
vllm
87d9996abe7ae0173fa8c1b6ccc2411041bcac81
2026-10-08T04:37:51+02:00
58,584
https://github.com/vllm-project/vllm/pull/58584
[ROCm][Perf][GLM-5.3-Flash] BF16 splitk kernel for sparse MLA decode (#58584)
[ROCm][Perf][GLM-5.3-Flash] BF16 splitk kernel for sparse MLA decode (#58584) Signed-off-by: simondanielsson <simon.danielsson99@hotmail.com> Co-authored-by: Douglas Lehr <91553416+dllehr-amd@users.noreply.github.com>
vllm/v1/attention/backends/mla/rocm_aiter_mla_sparse.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project from dataclasses import dataclass from typing import TYPE_CHECKING, ClassVar import numpy as np import torch from vllm import _custom_ops as ops from vllm._aiter_ops import rocm_aiter_ops from vllm.config impor...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project from dataclasses import dataclass from typing import TYPE_CHECKING, ClassVar import numpy as np import torch from vllm import _custom_ops as ops from vllm._aiter_ops import rocm_aiter_ops from vllm.config impor...
--- vllm/v1/attention/backends/mla/rocm_aiter_mla_sparse.py +++ vllm/v1/attention/backends/mla/rocm_aiter_mla_sparse.py @@ -37,7 +37,9 @@ ) from vllm.v1.attention.backends.utils import split_decodes_and_prefills from vllm.v1.attention.ops.rocm_aiter_mla_sparse import ( + rocm_sparse_attn_decode_bf16, rocm_sp...
40
13
2
[ "glm" ]
[ "ROCM" ]
[]
Optimize this triton kernel file from vllm (vllm/v1/attention/backends/mla/rocm_aiter_mla_sparse.py). Goal: [ROCm][Perf][GLM-5.3-Flash] BF16 splitk kernel for sparse MLA decode Target hardware: ROCM Target models: glm Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright co...
## Purpose Decode rows in the bf16 sparse MLA path go through the ragged **prefill** kernel, whose grid is `(q_len, heads_blocks)`. GLM-5.3-Flash at TP8 has one head block, so during decode with concurrency 4 launches only 4 workgroups on 256 CUs. Clearly underutilized. This new kernel instead uses splitK+reduce o...
[{"scope": "e2e", "hardware": "MI350", "model": "GLM-5.3-Flash", "shape": "ISL=1K,OSL=1K", "batch_size": 32, "metric": "TPOT", "unit": "ms", "higher_is_better": false, "baseline": 14.35, "optimized": 12.88, "stated_speedup": null, "speedup": 1.1141}, {"scope": "e2e", "hardware": "MI350", "model": "GLM-5.3-Flash", "shap...
2.1829
1.1017
vllm
5ab4e4445bcbe2bf07351b82d1af160234c32273
2026-10-06T18:49:57-05:00
59,128
https://github.com/vllm-project/vllm/pull/59128
[Perf][MoE] Skip padded work in block-FP8 DeepGEMM experts (#59128)
[Perf][MoE] Skip padded work in block-FP8 DeepGEMM experts (#59128) Signed-off-by: Tyler Michael Smith <tlrmchlsmth@gmail.com> Co-authored-by: Codex <noreply@openai.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
vllm/model_executor/layers/fused_moe/deep_gemm_utils.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Taken from https://github.com/ModelTC/LightLLM/blob/8ed97c74c18f11505b048b1ba00ba5c0cef8bff6/lightllm/common/fused_moe/deepep_scatter_gather.py and updated to fit vllm needs and terminology. """ import math i...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Taken from https://github.com/ModelTC/LightLLM/blob/8ed97c74c18f11505b048b1ba00ba5c0cef8bff6/lightllm/common/fused_moe/deepep_scatter_gather.py and updated to fit vllm needs and terminology. """ import math i...
--- vllm/model_executor/layers/fused_moe/deep_gemm_utils.py +++ vllm/model_executor/layers/fused_moe/deep_gemm_utils.py @@ -119,6 +119,7 @@ BLOCK_E: tl.constexpr, BLOCK_EXPERT_NUM: tl.constexpr, ALIGN_M: tl.constexpr, + USE_PSUM_LAYOUT: tl.constexpr, ): cur_expert = tl.program_id(0) @@ -140,20...
38
30
3
[]
[]
[]
Optimize this triton kernel file from vllm (vllm/model_executor/layers/fused_moe/deep_gemm_utils.py). Goal: [Perf][MoE] Skip padded work in block-FP8 DeepGEMM experts Target hardware: unspecified Target models: unspecified Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyrig...
## Purpose Skip padded work in block-FP8 `DeepGemmExperts` on SM90 and SM100-family GPUs. Both grouped GEMMs use DeepGEMM's prefix-sum scheduler, and fused SiLU/SwiGLU activation quantization consumes the same live expert endpoints. This avoids visiting unused padded GEMM tiles and quantizing the full allocated worksp...
[{"scope": "kernel", "hardware": "B200", "model": null, "shape": "N=7168,K=2048,intermediate=2048,top-k=8,experts=32", "batch_size": 16, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 472.176, "optimized": 347.456, "stated_speedup": null, "speedup": 1.359}, {"scope": "kernel", "hardware": "B2...
1.2227
null
vllm
5ab4e4445bcbe2bf07351b82d1af160234c32273
2026-10-06T18:49:57-05:00
59,128
https://github.com/vllm-project/vllm/pull/59128
[Perf][MoE] Skip padded work in block-FP8 DeepGEMM experts (#59128)
[Perf][MoE] Skip padded work in block-FP8 DeepGEMM experts (#59128) Signed-off-by: Tyler Michael Smith <tlrmchlsmth@gmail.com> Co-authored-by: Codex <noreply@openai.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
vllm/model_executor/layers/quantization/utils/fp8_utils.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project # Adapted from https://github.com/sgl-project/sglang/pull/2575 import functools import json import os from collections.abc import Callable, Sequence from typing import Any import torch import vllm.envs as envs ...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project # Adapted from https://github.com/sgl-project/sglang/pull/2575 import functools import json import os from collections.abc import Callable, Sequence from typing import Any import torch import vllm.envs as envs ...
--- vllm/model_executor/layers/quantization/utils/fp8_utils.py +++ vllm/model_executor/layers/quantization/utils/fp8_utils.py @@ -142,6 +142,7 @@ input_ptr, output_q_ptr, output_scale_ptr, + expert_ends_ptr, M, input_stride_m, output_q_stride_m, @@ -158,6 +159,7 @@ PACKS_PER_CTA: t...
130
49
3
[]
[]
[]
Optimize this triton kernel file from vllm (vllm/model_executor/layers/quantization/utils/fp8_utils.py). Goal: [Perf][MoE] Skip padded work in block-FP8 DeepGEMM experts Target hardware: unspecified Target models: unspecified Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copy...
## Purpose Skip padded work in block-FP8 `DeepGemmExperts` on SM90 and SM100-family GPUs. Both grouped GEMMs use DeepGEMM's prefix-sum scheduler, and fused SiLU/SwiGLU activation quantization consumes the same live expert endpoints. This avoids visiting unused padded GEMM tiles and quantizing the full allocated worksp...
[{"scope": "kernel", "hardware": "B200", "model": null, "shape": "N=7168,K=2048,intermediate=2048,top-k=8,experts=32", "batch_size": 16, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 472.176, "optimized": 347.456, "stated_speedup": null, "speedup": 1.359}, {"scope": "kernel", "hardware": "B2...
1.2227
null
vllm
b267fe488102eb26555d553a005127b4a523ff4b
2026-10-06T15:22:33+02:00
56,301
https://github.com/vllm-project/vllm/pull/56301
[ROCm][Perf] W4A16: pad gfx11 weight and activation strides (#56301)
[ROCm][Perf] W4A16: pad gfx11 weight and activation strides (#56301) Signed-off-by: Matthias Gehre <matthias.gehre@amd.com>
csrc/rocm/skinny_gemms_int4.cu
cuda
Apache-2.0
#include <torch/all.h> #include <ATen/cuda/CUDAContext.h> #include <c10/cuda/CUDAGuard.h> #include <cuda_runtime.h> #include <cuda_fp16.h> #include <cuda_bf16.h> #include <stdexcept> #include <algorithm> #include "../cuda_compat.h" #include "dispatch_utils.h" // Combined RDNA macro (gfx11 + gfx12) - both use 32-wid...
#include <torch/all.h> #include <ATen/cuda/CUDAContext.h> #include <c10/cuda/CUDAGuard.h> #include <cuda_runtime.h> #include <cuda_fp16.h> #include <cuda_bf16.h> #include <stdexcept> #include <algorithm> #include <utility> // std::in_range #include "../cuda_compat.h" #include "dispatch_utils.h" // Combined RDNA ma...
--- csrc/rocm/skinny_gemms_int4.cu +++ csrc/rocm/skinny_gemms_int4.cu @@ -8,6 +8,7 @@ #include <stdexcept> #include <algorithm> +#include <utility> // std::in_range #include "../cuda_compat.h" #include "dispatch_utils.h" @@ -121,6 +122,7 @@ // GROUP_SIZE: 0 = per-channel scale [M], >0 = per-group scale [M, /...
33
28
1
[]
[ "ROCM" ]
[]
Optimize this cuda kernel file from vllm (csrc/rocm/skinny_gemms_int4.cu). Goal: [ROCm][Perf] W4A16: pad gfx11 weight and activation strides Target hardware: ROCM Target models: unspecified Current file: ```cuda #include <torch/all.h> #include <ATen/cuda/CUDAContext.h> #include <c10/cuda/CUDAGuard.h> #include <cuda_...
On gfx11 (RDNA3/3.5) a W4A16 GEMM loses a large share of its achievable read bandwidth when an operand's row stride lands on a multiple of 1024 bytes. The rows alias into the same L2/DDR channels and the accesses serialize. Offsetting the stride by one 128 B cache line dodges it. This PR nudges **both** operands off t...
[{"scope": "e2e", "hardware": "AMD Strix Halo (gfx1151)", "model": "Qwen3-8B-quantized.w4a16", "shape": "128/128", "batch_size": 10, "metric": "TTFT", "unit": "ms", "higher_is_better": false, "baseline": 119.99, "optimized": 101.8, "stated_speedup": 1.152, "speedup": 1.1787}, {"scope": "e2e", "hardware": "AMD Strix Hal...
null
1.0298
vllm
8bdd8d847dcbdafd80e666ad7fb797a18da62975
2026-10-02T20:05:27-04:00
57,443
https://github.com/vllm-project/vllm/pull/57443
[GLM 5.3 Perf] Enable fused multi-step decode, 13.3% E2E throughput improvement for concurrency 1 (#57443)
[GLM 5.3 Perf] Enable fused multi-step decode, 13.3% E2E throughput improvement for concurrency 1 (#57443) Signed-off-by: yewentao256 <zhyanwentao@126.com>
vllm/v1/attention/backends/mla/indexer.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project from dataclasses import dataclass from typing import Any import numpy as np import torch import vllm.envs as envs from vllm.config import VllmConfig from vllm.distributed import get_dcp_group, get_pcp_group from...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project from dataclasses import dataclass from typing import Any import numpy as np import torch import vllm.envs as envs from vllm.config import VllmConfig from vllm.distributed import get_dcp_group, get_pcp_group from...
--- vllm/v1/attention/backends/mla/indexer.py +++ vllm/v1/attention/backends/mla/indexer.py @@ -669,6 +669,7 @@ decode: DeepSeekV32IndexerDecodeMetadata | None = None prefill: DeepseekV32IndexerPrefillMetadata | None = None + positions: torch.Tensor | None = None @triton.jit(do_not_specialize=["num_...
63
0
2
[ "glm" ]
[]
[]
Optimize this triton kernel file from vllm (vllm/v1/attention/backends/mla/indexer.py). Goal: [GLM 5.3 Perf] Enable fused multi-step decode, 13.3% E2E throughput improvement for concurrency 1 Target hardware: unspecified Target models: glm Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyr...
## Purpose Enable fused multi-step draft decode for GLM-5.3 Consider K = 5 Before: ```text draft prefill: generate token #0 decode step 1: rebuild metadata decode step 2: rebuild metadata decode step 3: rebuild metadata decode step 4: rebuild metadata ``` After: ```text draft prefill: gene...
[{"scope": "e2e", "hardware": null, "model": "GLM-5.3", "shape": null, "batch_size": 1, "metric": "latency", "unit": "s", "higher_is_better": false, "baseline": 6.68, "optimized": 5.9, "stated_speedup": 1.118, "speedup": 1.1322}, {"scope": "e2e", "hardware": null, "model": "GLM-5.3", "shape": null, "batch_size": 1, "me...
null
1.0188
vllm
9cf087fd14bf2219a24cfc1de728e5cebe5d59d4
2026-10-03T01:09:29+08:00
59,731
https://github.com/vllm-project/vllm/pull/59731
[Perf] Tune MoE weighted-sum kernel launch configuration (#59731)
[Perf] Tune MoE weighted-sum kernel launch configuration (#59731) Signed-off-by: Jinzhen Lin <jinzhen.ljz@antgroup.com> Co-authored-by: Codex <noreply@openai.com> Co-authored-by: Misha Goin <mgoin64@gmail.com>
vllm/model_executor/layers/fused_moe/moe_fused_mul_sum.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project import torch from torch._subclasses.fake_tensor import FakeTensor from vllm.triton_utils import tl, triton @triton.jit def moe_fused_mul_sum_kernel( inputs_ptr, topk_weights_ptr, outputs_ptr, to...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project import torch from torch._subclasses.fake_tensor import FakeTensor from vllm.platforms import current_platform from vllm.triton_utils import tl, triton @triton.jit def moe_fused_mul_sum_kernel( inputs_ptr, ...
--- vllm/model_executor/layers/fused_moe/moe_fused_mul_sum.py +++ vllm/model_executor/layers/fused_moe/moe_fused_mul_sum.py @@ -3,6 +3,7 @@ import torch from torch._subclasses.fake_tensor import FakeTensor +from vllm.platforms import current_platform from vllm.triton_utils import tl, triton @@ -75,11 +76,18 @@...
10
1
1
[]
[]
[]
Optimize this triton kernel file from vllm (vllm/model_executor/layers/fused_moe/moe_fused_mul_sum.py). Goal: [Perf] Tune MoE weighted-sum kernel launch configuration Target hardware: unspecified Target models: unspecified Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyrig...
## Overview Tune CUDA FP16/BF16 `moe_fused_mul_sum` launches: cap `BLOCK_K` at 4096 and use 8 warps on SM75, 16 on newer GPUs. FP32, small hidden sizes, and non-CUDA platforms keep their existing settings. ## Claims - Reduce serial hidden-tile iterations with a small launch-only change; retain the kernel and one-CTA...
[{"scope": "kernel", "hardware": "RTX 2080 Ti (SM75)", "model": null, "shape": "(1, 2, 2048)", "batch_size": 1, "metric": "latency", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 1.36, "speedup": 1.36}, {"scope": "kernel", "hardware": "RTX 2080 Ti (SM75)", "model": null,...
1.32
null
vllm
8486f1ebfe6e39a5513a8636e7f07ed9746f8be5
2026-10-02T09:20:13+05:30
52,162
https://github.com/vllm-project/vllm/pull/52162
[Perf][PCP] Shard decode requests across PCP ranks (#52162)
[Perf][PCP] Shard decode requests across PCP ranks (#52162) Signed-off-by: QiuChunshuo <qiuchunshuo@huawei.com> Co-authored-by: Lucas Wilkinson <LucasWilkinson@users.noreply.github.com>
vllm/model_executor/layers/sparse_attn_indexer.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Custom Sparse Attention Indexer layers.""" import torch import torch.distributed as dist import vllm.envs as envs from vllm import _custom_ops as ops from vllm._aiter_ops import rocm_aiter_ops from vllm.compi...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Custom Sparse Attention Indexer layers.""" import torch import torch.distributed as dist import vllm.envs as envs from vllm import _custom_ops as ops from vllm._aiter_ops import rocm_aiter_ops from vllm.compi...
--- vllm/model_executor/layers/sparse_attn_indexer.py +++ vllm/model_executor/layers/sparse_attn_indexer.py @@ -335,6 +335,7 @@ topk_indices_buffer: torch.Tensor, skip_k_cache_insert: bool, use_pcp: bool, + pcp_shard_decode_requests: bool, dense_mha_metadata_layer_name: LayerNameType, use_fp...
6
0
5
[]
[]
[]
Optimize this triton kernel file from vllm (vllm/model_executor/layers/sparse_attn_indexer.py). Goal: [Perf][PCP] Shard decode requests across PCP ranks Target hardware: unspecified Target models: unspecified Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributor...
## Purpose PCP currently replicates every decode request on every PCP rank. For PCP-only deployments (`DCP == 1`), every rank already has a complete KV-cache replica, so this repeats the same decode computation `pcp_size` times. This PR: - assigns decode-only rows round-robin across PCP ranks on every scheduler step...
[{"scope": "e2e", "hardware": "H20", "model": "DeepSeek-V3.2", "shape": "hit_rate=95%", "batch_size": 128, "metric": "throughput", "unit": "req/s", "higher_is_better": true, "baseline": 2.8343, "optimized": 3.0094, "stated_speedup": null, "speedup": 1.0618}, {"scope": "e2e", "hardware": "H20", "model": "DeepSeek-V3.2",...
null
1.0276
vllm
8486f1ebfe6e39a5513a8636e7f07ed9746f8be5
2026-10-02T09:20:13+05:30
52,162
https://github.com/vllm-project/vllm/pull/52162
[Perf][PCP] Shard decode requests across PCP ranks (#52162)
[Perf][PCP] Shard decode requests across PCP ranks (#52162) Signed-off-by: QiuChunshuo <qiuchunshuo@huawei.com> Co-authored-by: Lucas Wilkinson <LucasWilkinson@users.noreply.github.com>
vllm/v1/attention/backends/mla/indexer.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project from dataclasses import dataclass from typing import Any import numpy as np import torch import vllm.envs as envs from vllm.config import VllmConfig from vllm.distributed import get_dcp_group, get_pcp_group from...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project from dataclasses import dataclass from typing import Any import numpy as np import torch import vllm.envs as envs from vllm.config import VllmConfig from vllm.distributed import get_dcp_group, get_pcp_group from...
--- vllm/v1/attention/backends/mla/indexer.py +++ vllm/v1/attention/backends/mla/indexer.py @@ -1298,17 +1298,6 @@ slot_mapping = common_attn_metadata.slot_mapping block_table = common_attn_metadata.block_table_tensor dcp_local_seq_lens = common_attn_metadata.dcp_local_seq_lens - num_d...
28
11
5
[]
[]
[]
Optimize this triton kernel file from vllm (vllm/v1/attention/backends/mla/indexer.py). Goal: [Perf][PCP] Shard decode requests across PCP ranks Target hardware: unspecified Target models: unspecified Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the...
## Purpose PCP currently replicates every decode request on every PCP rank. For PCP-only deployments (`DCP == 1`), every rank already has a complete KV-cache replica, so this repeats the same decode computation `pcp_size` times. This PR: - assigns decode-only rows round-robin across PCP ranks on every scheduler step...
[{"scope": "e2e", "hardware": "H20", "model": "DeepSeek-V3.2", "shape": "hit_rate=95%", "batch_size": 128, "metric": "throughput", "unit": "req/s", "higher_is_better": true, "baseline": 2.8343, "optimized": 3.0094, "stated_speedup": null, "speedup": 1.0618}, {"scope": "e2e", "hardware": "H20", "model": "DeepSeek-V3.2",...
null
1.0276
vllm
26bfdfb6bc5ef85e2128b9ddcf27c369356edd3b
2026-10-01T10:00:15-07:00
57,978
https://github.com/vllm-project/vllm/pull/57978
[ROCm][Perf] Parallelise AITER MLA page-index expansion over token chunks (#57978)
[ROCm][Perf] Parallelise AITER MLA page-index expansion over token chunks (#57978) Signed-off-by: lifulu <fululi12@amd.com> Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
vllm/v1/attention/backends/mla/rocm_aiter_mla.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project import functools from dataclasses import dataclass from enum import Enum from pathlib import Path from typing import TYPE_CHECKING, ClassVar, Final import torch from vllm import envs from vllm._aiter_ops import...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project import functools from dataclasses import dataclass from enum import Enum from pathlib import Path from typing import TYPE_CHECKING, ClassVar, Final import torch from vllm import envs from vllm._aiter_ops import...
--- vllm/v1/attention/backends/mla/rocm_aiter_mla.py +++ vllm/v1/attention/backends/mla/rocm_aiter_mla.py @@ -1331,10 +1331,17 @@ # to the original _copy_page_indices_kernel). # When kernel_block_size=K>1, block_table entry b covering K tokens # gets expanded to flat indices b*K, ...
44
24
1
[]
[ "ROCM" ]
[]
Optimize this triton kernel file from vllm (vllm/v1/attention/backends/mla/rocm_aiter_mla.py). Goal: [ROCm][Perf] Parallelise AITER MLA page-index expansion over token chunks Target hardware: ROCM Target models: unspecified Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyri...
> [!IMPORTANT] > **Scope: this is a kernel-level microbenchmark, not an end-to-end throughput claim.** > The numbers below are measured from torch-profiler traces on the same build, same shapes. Against a multi-millisecond decode step a > change of this size sits inside run-to-run variation (~1% on a conc=1 arm), so > ...
[{"scope": "kernel", "hardware": "MI355X", "model": null, "shape": "TP8, ~97k-token context", "batch_size": 1, "metric": "latency", "unit": "\u00b5s", "higher_is_better": false, "baseline": 22.4, "optimized": 3.3, "stated_speedup": 6.8, "speedup": 6.7879}, {"scope": "kernel", "hardware": "MI355X", "model": null, "shape...
1.7642
null
vllm
2df122e65e87dc12870ce5f0180b49f012e7a53b
2026-09-30T16:45:00+02:00
58,008
https://github.com/vllm-project/vllm/pull/58008
[ROCm][Perf][GLM-5.3-Flash] "Fit kpool top-k indices to AITER" with a single Triton kernel (#58008)
[ROCm][Perf][GLM-5.3-Flash] "Fit kpool top-k indices to AITER" with a single Triton kernel (#58008) Signed-off-by: simondanielsson <simon.danielsson99@hotmail.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
vllm/v1/attention/backends/mla/rocm_aiter_mla_sparse.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project from dataclasses import dataclass from typing import TYPE_CHECKING, ClassVar import numpy as np import torch from vllm import _custom_ops as ops from vllm._aiter_ops import rocm_aiter_ops from vllm.config impor...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project from dataclasses import dataclass from typing import TYPE_CHECKING, ClassVar import numpy as np import torch from vllm import _custom_ops as ops from vllm._aiter_ops import rocm_aiter_ops from vllm.config impor...
--- vllm/v1/attention/backends/mla/rocm_aiter_mla_sparse.py +++ vllm/v1/attention/backends/mla/rocm_aiter_mla_sparse.py @@ -70,6 +70,50 @@ ) +@triton.jit +def _fit_kpool_indices_kernel( + token_indices_ptr, # int32 [num_tokens, NUM_TOPK_TOKENS + TAIL_WIDTH] + out_ptr, # int32 [num_tokens, NUM_TOPK_TOKE...
67
14
1
[ "glm" ]
[ "ROCM" ]
[]
Optimize this triton kernel file from vllm (vllm/v1/attention/backends/mla/rocm_aiter_mla_sparse.py). Goal: [ROCm][Perf][GLM-5.3-Flash] "Fit kpool top-k indices to AITER" with a single Triton kernel Target hardware: ROCM Target models: glm Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyr...
## Purpose The existing kernel is implemented in pytorch and leads to **18** elementwise kernel launched per forward. We replace it with a single triton kernel. **Perf: -5% ITL, +3-5% out tok/s** ## What it does GLM-5.3-Flash's indexer selects `topk + kpool_tail` tokens, where the tail size is <kpool=4 and depend...
[{"scope": "e2e", "hardware": null, "model": "GLM-5.3-Flash", "shape": "ISL=8K,OSL=1K", "batch_size": 4, "metric": "ITL", "unit": "ms", "higher_is_better": false, "baseline": 14.75, "optimized": 14.01, "stated_speedup": 1.05, "speedup": 1.0528}, {"scope": "e2e", "hardware": null, "model": "GLM-5.3-Flash", "shape": "ISL...
null
1.0517
vllm
93dd80f63639453591e68891614729fb0bd44855
2026-09-30T13:23:42+01:00
54,093
https://github.com/vllm-project/vllm/pull/54093
[CPU] Conv1d optimised kernel for aarch64 (#54093)
[CPU] Conv1d optimised kernel for aarch64 (#54093) Signed-off-by: Anna Mayne <anna.mayne@arm.com> Co-authored-by: Li, Jiang <jiang1.li@intel.com>
csrc/cpu/sgl-kernels/conv.cpp
cpp
Apache-2.0
// Adapted from // https://github.com/sgl-project/sglang/tree/main/sgl-kernel/csrc/cpu // clang-format off #include "common.h" #include "gemm.h" #include "vec.h" namespace { template <typename scalar_t> inline void copy_stub(scalar_t* __restrict__ y, const scalar_t* __restrict__ x, int64_t size) { using Vec = at:...
// Adapted from // https://github.com/sgl-project/sglang/tree/main/sgl-kernel/csrc/cpu // clang-format off #include "common.h" #include "gemm.h" #include "vec.h" namespace { template <typename scalar_t> inline void copy_stub(scalar_t* __restrict__ y, const scalar_t* __restrict__ x, int64_t size) { using Vec = at:...
--- csrc/cpu/sgl-kernels/conv.cpp +++ csrc/cpu/sgl-kernels/conv.cpp @@ -65,6 +65,10 @@ TORCH_CHECK(false, "tinygemm_kernel_nn: scalar path not implemented!"); } }; + +#if defined(ARM_BF16_SUPPORT) +#include "conv_arm.h" +#endif #if defined(CPU_CAPABILITY_AVX512) template <int K, int BLOCK_N, bool has_bias,...
19
7
4
[]
[ "CPU" ]
[]
Optimize this cpp kernel file from vllm (csrc/cpu/sgl-kernels/conv.cpp). Goal: [CPU] Conv1d optimised kernel for aarch64 Target hardware: CPU Target models: unspecified Current file: ```cpp // Adapted from // https://github.com/sgl-project/sglang/tree/main/sgl-kernel/csrc/cpu // clang-format off #include "common.h"...
## Purpose Advanced SIMD implementation for aarch64 of the causal conv1d kernel used in Gated DeltaNets. Includes faster silu implementation with fexp. ## Test Plan Run related tests: ``` python -m pytest \ tests/kernels/mamba/test_causal_conv1d.py \ tests/kernels/mamba/cpu/test_cpu_gdn_ops.py \ tests/kernels/...
[{"scope": "e2e", "hardware": null, "model": "Qwen/Qwen3.5-35B-A3B", "shape": null, "batch_size": 256, "metric": "throughput", "unit": "reqs/s", "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 1.0882, "speedup": 1.0882}, {"scope": "e2e", "hardware": null, "model": "Qwen/Qwen3.5-35B-A3B"...
null
1.0904
vllm
93dd80f63639453591e68891614729fb0bd44855
2026-09-30T13:23:42+01:00
54,093
https://github.com/vllm-project/vllm/pull/54093
[CPU] Conv1d optimised kernel for aarch64 (#54093)
[CPU] Conv1d optimised kernel for aarch64 (#54093) Signed-off-by: Anna Mayne <anna.mayne@arm.com> Co-authored-by: Li, Jiang <jiang1.li@intel.com>
csrc/cpu/torch_bindings.cpp
cpp
Apache-2.0
#include "cache.h" #include "ops.h" #include "core/registration.h" #include <torch/library.h> // Note: overwrite the external definition for sharing same name between // libraries use different ISAs. #define TORCH_EXTENSION_NAME _C void release_dnnl_matmul_handler(int64_t handler); int64_t create_onednn_scaled_mm_h...
#include "cache.h" #include "ops.h" #include "core/registration.h" #include <torch/library.h> // Note: overwrite the external definition for sharing same name between // libraries use different ISAs. #define TORCH_EXTENSION_NAME _C void release_dnnl_matmul_handler(int64_t handler); int64_t create_onednn_scaled_mm_h...
--- csrc/cpu/torch_bindings.cpp +++ csrc/cpu/torch_bindings.cpp @@ -281,14 +281,14 @@ const std::optional<at::Tensor>& query_start_loc, const std::optional<at::Tensor>& cache_indices, const std::optional<at::Tensor>& has_initial_state, bool silu_activation, - int64_t pad_slot_id, bool is_vnni); + i...
29
20
4
[]
[ "CPU" ]
[]
Optimize this cpp kernel file from vllm (csrc/cpu/torch_bindings.cpp). Goal: [CPU] Conv1d optimised kernel for aarch64 Target hardware: CPU Target models: unspecified Current file: ```cpp #include "cache.h" #include "ops.h" #include "core/registration.h" #include <torch/library.h> // Note: overwrite the external de...
## Purpose Advanced SIMD implementation for aarch64 of the causal conv1d kernel used in Gated DeltaNets. Includes faster silu implementation with fexp. ## Test Plan Run related tests: ``` python -m pytest \ tests/kernels/mamba/test_causal_conv1d.py \ tests/kernels/mamba/cpu/test_cpu_gdn_ops.py \ tests/kernels/...
[{"scope": "e2e", "hardware": null, "model": "Qwen/Qwen3.5-35B-A3B", "shape": null, "batch_size": 256, "metric": "throughput", "unit": "reqs/s", "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 1.0882, "speedup": 1.0882}, {"scope": "e2e", "hardware": null, "model": "Qwen/Qwen3.5-35B-A3B"...
null
1.0904
vllm
583637f126a5f5193952a81ca9e0630ae9fc9986
2026-09-30T12:46:28+05:30
53,913
https://github.com/vllm-project/vllm/pull/53913
[CPU][Perf] Add vectorized Sampler Kernel (#53913)
[CPU][Perf] Add vectorized Sampler Kernel (#53913) Signed-off-by: Rehan Khan <Rehan.Khan7@ibm.com> Co-authored-by: Li, Jiang <jiang1.li@intel.com>
csrc/cpu/torch_bindings.cpp
cpp
Apache-2.0
#include "cache.h" #include "ops.h" #include "core/registration.h" #include <torch/library.h> // Note: overwrite the external definition for sharing same name between // libraries use different ISAs. #define TORCH_EXTENSION_NAME _C void release_dnnl_matmul_handler(int64_t handler); int64_t create_onednn_scaled_mm_h...
#include "cache.h" #include "ops.h" #include "core/registration.h" #include <torch/library.h> // Note: overwrite the external definition for sharing same name between // libraries use different ISAs. #define TORCH_EXTENSION_NAME _C void release_dnnl_matmul_handler(int64_t handler); int64_t create_onednn_scaled_mm_h...
--- csrc/cpu/torch_bindings.cpp +++ csrc/cpu/torch_bindings.cpp @@ -392,6 +392,11 @@ const c10::optional<at::Tensor>& D, const c10::optional<at::Tensor>& z, const at::Tensor& cu_seqlens); + +torch::Tensor fused_g...
12
0
1
[]
[ "CPU" ]
[]
Optimize this cpp kernel file from vllm (csrc/cpu/torch_bindings.cpp). Goal: [CPU][Perf] Add vectorized Sampler Kernel Target hardware: CPU Target models: unspecified Current file: ```cpp #include "cache.h" #include "ops.h" #include "core/registration.h" #include <torch/library.h> // Note: overwrite the external de...
## Purpose Add fused CPU sampling kernels (Gumbel-max + greedy argmax) to replace the expensive default random sampling pipeline (softmax → exponential → div → argmax) on CPU backends. Profiling on s390x showed `aten::exponential_()` alone consuming **93% of sampling wall time** (~62ms out of 67ms per step at batch=16...
[{"scope": "kernel", "hardware": "s390x", "model": null, "shape": "vocab=32000", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 1370.7, "optimized": 762.3, "stated_speedup": 1.8, "speedup": 1.7981}, {"scope": "kernel", "hardware": "s390x", "model": null, "shape": "vocab=32000...
1.5182
null
vllm
d86cf91240988310d04f75217a2ea7e76f1db3d6
2026-09-29T08:53:38+02:00
57,531
https://github.com/vllm-project/vllm/pull/57531
[MM][Mistral3] Image preprocessing optimization (#57531)
[MM][Mistral3] Image preprocessing optimization (#57531) Signed-off-by: Jakub Zakrzewski <jzakrzewski@nvidia.com> Co-authored-by: OpenAI Codex <noreply@openai.com> Co-authored-by: OpenAI Codex <codex@openai.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
vllm/model_executor/layers/fusion/mm_input_norm.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Fused Normalisation on the Device. Equivalent to:: output = (input * rescale_factor - image_mean) / image_std This is implemented as a single per-channel affine transform:: output = input * weight[...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Fused Normalisation on the Device. Equivalent to:: output = (input * rescale_factor - image_mean) / image_std This is implemented as a single per-channel affine transform:: output = input * weight[...
--- vllm/model_executor/layers/fusion/mm_input_norm.py +++ vllm/model_executor/layers/fusion/mm_input_norm.py @@ -147,6 +147,11 @@ rescale_factor)`` from the processor config.""" config = get_processor_config(model_config.model, revision=model_config.revision) config = config.get("image_processor", confi...
5
0
1
[ "mistral" ]
[]
[]
Optimize this triton kernel file from vllm (vllm/model_executor/layers/fusion/mm_input_norm.py). Goal: [MM][Mistral3] Image preprocessing optimization Target hardware: unspecified Target models: mistral Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to t...
## Purpose Reduce CPU time spent preprocessing images for HF-format Mistral 3 models. This PR applies two optimizations: - On Transformers 5.15 and newer, call PixtralProcessor without dummy text. Image-only calls are supported there, so tokenizing generated [IMG] placeholders is unnecessary. Older Transformers v...
[{"scope": "e2e", "hardware": "NVIDIA GeForce RTX 3070 Ti", "model": "mistralai/Mistral-Small-3.1-24B-Instruct-2503", "shape": "1540x1540", "batch_size": 1, "metric": "latency", "unit": "ms", "higher_is_better": false, "baseline": 75.1, "optimized": 69.0, "stated_speedup": 1.082, "speedup": 1.0884}, {"scope": "e2e", "h...
3.2709
1.0916
vllm
c8d7a7dd13e2b40c013fb6d46be800937e4335fb
2026-09-27T13:06:23+02:00
58,684
https://github.com/vllm-project/vllm/pull/58684
[Perf][Attention] Remove D2H sync from FlashInfer SM90 sparse MLA plan under async scheduling (#58684)
[Perf][Attention] Remove D2H sync from FlashInfer SM90 sparse MLA plan under async scheduling (#58684) Signed-off-by: NickLucche <nicolo.lucchesi@mistral.ai>
vllm/v1/attention/backends/mla/flashinfer_mla_sparse_sm90.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """FlashInfer sparse MLA backend for SM90 (Hopper) NoPE models. Wraps FlashInfer's ``BatchMLAPagedAttentionWrapper`` (FA2/FA3 paths), which as of FlashInfer 0.6.18 supports ``head_dim_kpe=0`` (GLM-5.3-Flash NoPE ...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """FlashInfer sparse MLA backend for SM90 (Hopper) NoPE models. Wraps FlashInfer's ``BatchMLAPagedAttentionWrapper`` (FA2/FA3 paths), which as of FlashInfer 0.6.18 supports ``head_dim_kpe=0`` (GLM-5.3-Flash NoPE ...
--- vllm/v1/attention/backends/mla/flashinfer_mla_sparse_sm90.py +++ vllm/v1/attention/backends/mla/flashinfer_mla_sparse_sm90.py @@ -17,14 +17,14 @@ CUDA-graph handling: ``plan()`` copies its inputs to host unconditionally, so it must stay outside graph capture. Each metadata builder owns a wrapper, reserved captur...
202
80
1
[ "mistral" ]
[ "SM90" ]
[]
Optimize this triton kernel file from vllm (vllm/v1/attention/backends/mla/flashinfer_mla_sparse_sm90.py). Goal: [Perf][Attention] Remove D2H sync from FlashInfer SM90 sparse MLA plan under async scheduling Target hardware: SM90 Target models: mistral Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SP...
## Purpose With async scheduling, `FLASHINFER_MLA_SPARSE_SM90` did a blocking D2H copy on every metadata build. FlashInfer bakes each row's `kv_len` into its schedule on the host, and `seq_lens_cpu_upper_bound` is optimistic under async spec decode, so the builder copied `positions` / `seq_lens` back to get exact leng...
[{"scope": "e2e", "hardware": "H100", "model": "zai-org/GLM-5.3-Flash", "shape": null, "batch_size": 1, "metric": "TPOT", "unit": "ms", "higher_is_better": false, "baseline": 11.09, "optimized": 6.86, "stated_speedup": null, "speedup": 1.6166}, {"scope": "e2e", "hardware": "H100", "model": "zai-org/GLM-5.3-Flash", "sha...
null
1.2598
vllm
c88f4824fff42794d026348b86f9b78869fa273e
2026-09-25T13:15:18-04:00
58,450
https://github.com/vllm-project/vllm/pull/58450
[GLM5.3 Perf] Optimize glm 5.3 metadata op, 1.6~4.8x kernel level performance improvement (#58450)
[GLM5.3 Perf] Optimize glm 5.3 metadata op, 1.6~4.8x kernel level performance improvement (#58450) Signed-off-by: yewentao256 <zhyanwentao@126.com>
vllm/model_executor/layers/attention/sparse_mla_attention.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Shared MHA implementation and metadata builder for sparse MLA backends.""" import math from dataclasses import dataclass from shutil import which from typing import TYPE_CHECKING, Any, ClassVar, Generic, TypeV...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Shared MHA implementation and metadata builder for sparse MLA backends.""" import math from dataclasses import dataclass from shutil import which from typing import TYPE_CHECKING, Any, ClassVar, Generic, TypeV...
--- vllm/model_executor/layers/attention/sparse_mla_attention.py +++ vllm/model_executor/layers/attention/sparse_mla_attention.py @@ -291,17 +291,7 @@ self, common_attn_metadata: "CommonAttentionMetadata", ) -> torch.Tensor: - num_tokens = common_attn_metadata.num_actual_tokens - st...
1
11
3
[ "glm" ]
[]
[ "4.8x" ]
Optimize this triton kernel file from vllm (vllm/model_executor/layers/attention/sparse_mla_attention.py). Goal: [GLM5.3 Perf] Optimize glm 5.3 metadata op, 1.6~4.8x kernel level performance improvement Target hardware: unspecified Target models: glm Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPD...
## Purpose - Reuse `arrange` - persistent GPU buffer + Triton kernel for `_build_req_id_per_token` ## Test Acc covered by current unit test Perf can be seen in this ai generated script ```py import statistics import time import numpy as np import torch from vllm.utils.torch_utils import np_to_pinned_tensor from...
[{"scope": "kernel", "hardware": "NVIDIA B300 SXM6 AC", "model": null, "shape": "tokens=1,reqs=1", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 22.86, "optimized": 13.3, "stated_speedup": 1.72, "speedup": 1.7188}, {"scope": "kernel", "hardware": "NVIDIA B300 SXM6 AC", "mode...
3.5552
null
vllm
38cc054fc2269941cd35ecdfd198aacbb2eabfb8
2026-09-25T11:19:48-04:00
58,194
https://github.com/vllm-project/vllm/pull/58194
[Perf][Kernel] Vectorized flat abs-max for dynamic per-tensor FP8 quantization (#58194)
[Perf][Kernel] Vectorized flat abs-max for dynamic per-tensor FP8 quantization (#58194) Signed-off-by: Monishver Chandrasekaran <monishverchandrasekaran@gmail.com> Co-authored-by: Claude Fable 5.1 <noreply@anthropic.com> Co-authored-by: Misha Goin <mgoin64@gmail.com>
csrc/libtorch_stable/quantization/w8a8/fp8/common.cu
cuda
Apache-2.0
#include "../../../../quantization/w8a8/fp8/common.cuh" #include "../../../dispatch_utils.h" #include "../../../cub_helpers.h" #include "../../vectorization_utils.cuh" #include "../../../torch_utils.h" #include <torch/csrc/stable/macros.h> namespace vllm { // STRIDE_I_ZERO: true if scale_stride_i == 0 (per-tensor or p...
#include "../../../../quantization/w8a8/fp8/common.cuh" #include "../../../../cuda_compat.h" #include "../../../dispatch_utils.h" #include "../../../cub_helpers.h" #include "../../vectorization_utils.cuh" #include "../../../torch_utils.h" #include <torch/csrc/stable/macros.h> #include <algorithm> namespace vllm { na...
--- csrc/libtorch_stable/quantization/w8a8/fp8/common.cu +++ csrc/libtorch_stable/quantization/w8a8/fp8/common.cu @@ -1,10 +1,59 @@ #include "../../../../quantization/w8a8/fp8/common.cuh" +#include "../../../../cuda_compat.h" #include "../../../dispatch_utils.h" #include "../../../cub_helpers.h" #include "../../vec...
119
35
1
[]
[]
[]
Optimize this cuda kernel file from vllm (csrc/libtorch_stable/quantization/w8a8/fp8/common.cu). Goal: [Perf][Kernel] Vectorized flat abs-max for dynamic per-tensor FP8 quantization Target hardware: unspecified Target models: unspecified Current file: ```cuda #include "../../../../quantization/w8a8/fp8/common.cuh" #i...
## Purpose This PR speeds up the abs-max pass of `dynamic_scaled_fp8_quant` (per-tensor dynamic FP8 quantization) in `csrc/libtorch_stable/quantization/w8a8/fp8/common.cu`. It is the activation quant on every MoE layer of a model served with `--quantization fp8`, and it had never been performance-tuned. I went in aft...
[{"scope": "kernel", "hardware": "H100", "model": null, "shape": "hidden=4096", "batch_size": 16, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 8.21, "optimized": 5.61, "stated_speedup": 1.46, "speedup": 1.4635}, {"scope": "kernel", "hardware": "H100", "model": null, "shape": "hidden=8192", ...
1.5928
1.0227
vllm
f550ad8bf7a3983a16aafd25ad18d8b48f4d5218
2026-09-25T23:11:42+08:00
55,330
https://github.com/vllm-project/vllm/pull/55330
[Kernel][Perf] Register-resident path for per-token-group 8-bit quant (#55330)
[Kernel][Perf] Register-resident path for per-token-group 8-bit quant (#55330) Signed-off-by: chao.huan <chao.huan@nio.com> Co-authored-by: Misha Goin <mgoin64@gmail.com>
csrc/libtorch_stable/quantization/w8a8/fp8/per_token_group_quant.cu
cuda
Apache-2.0
#include <torch/csrc/stable/tensor.h> #include <torch/csrc/stable/ops.h> #include <torch/headeronly/util/Exception.h> #include <torch/headeronly/core/ScalarType.h> #include "libtorch_stable/quantization/w8a8/per_token_group_quant_8bit.h" #include <cmath> #ifdef USE_ROCM #include <hip/hip_fp8.h> #else #include <c...
#include <torch/csrc/stable/tensor.h> #include <torch/csrc/stable/ops.h> #include <torch/headeronly/util/Exception.h> #include <torch/headeronly/core/ScalarType.h> #include "libtorch_stable/quantization/w8a8/per_token_group_quant_8bit.h" #include <cmath> #ifdef USE_ROCM #include <hip/hip_fp8.h> #else #include <c...
--- csrc/libtorch_stable/quantization/w8a8/fp8/per_token_group_quant.cu +++ csrc/libtorch_stable/quantization/w8a8/fp8/per_token_group_quant.cu @@ -169,6 +169,156 @@ #endif } +// Register-resident variant for the unpacked float32 scale layout, mirroring +// per_token_group_quant_8bit_packed_register_kernel below, w...
215
4
1
[]
[]
[]
Optimize this cuda kernel file from vllm (csrc/libtorch_stable/quantization/w8a8/fp8/per_token_group_quant.cu). Goal: [Kernel][Perf] Register-resident path for per-token-group 8-bit quant Target hardware: unspecified Target models: unspecified Current file: ```cuda #include <torch/csrc/stable/tensor.h> #include <torc...
## Summary `per_token_group_quant_8bit` stages every group through shared memory because it reads the group twice: once to reduce absmax, once to quantize. At `group_size` 128 a group of 16-bit input is 256 B, which fits in registers, so both the staging and the `__syncthreads()` separating the two passes are avoidabl...
[{"scope": "kernel", "hardware": "H20-3e (SM90)", "model": null, "shape": "N=1,K=128", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 14.0, "optimized": 5.5, "stated_speedup": 2.54, "speedup": 2.5455}, {"scope": "kernel", "hardware": "H20-3e (SM90)", "model": null, "shape": "...
2.5455
1.0153
vllm
442bd00d9feff7d6a0cebf74248674bad74ec391
2026-09-24T20:27:21-07:00
55,072
https://github.com/vllm-project/vllm/pull/55072
[Perf][Distributed] Add low-SM multimem reduce-scatter for SM100/SM103 (#55072)
[Perf][Distributed] Add low-SM multimem reduce-scatter for SM100/SM103 (#55072) Signed-off-by: Yongye Zhu <zyy1102000@gmail.com> Signed-off-by: Summer Yang <girasoleyang@gmail.com> Co-authored-by: Summer Yang <girasoleyang@gmail.com>
csrc/custom_all_gather_reduce_scatter.cuh
cuda
Apache-2.0
#pragma once #include "custom_collective_common.cuh" namespace vllm { constexpr int kMnnvlLamportAgThreads = 128; constexpr int kMnnvlLamportRsThreads = 256; constexpr int kMnnvlLamportConcurrentPollMaxPacks = 8192; using CopyPack = array_t<uint64_t, 2>; template <int ngpus> __global__ void __launch_bounds__(512, ...
#pragma once #include "custom_collective_common.cuh" namespace vllm { constexpr int kMnnvlLamportAgThreads = 128; constexpr int kMnnvlLamportRsThreads = 256; constexpr int kMnnvlLamportConcurrentPollMaxPacks = 8192; constexpr int kMnnvlMultimemRsThreads = 1024; constexpr int kMnnvlMultimemRsBlockLimit = 8; constexpr...
--- csrc/custom_all_gather_reduce_scatter.cuh +++ csrc/custom_all_gather_reduce_scatter.cuh @@ -7,6 +7,10 @@ constexpr int kMnnvlLamportAgThreads = 128; constexpr int kMnnvlLamportRsThreads = 256; constexpr int kMnnvlLamportConcurrentPollMaxPacks = 8192; +constexpr int kMnnvlMultimemRsThreads = 1024; +constexpr int ...
125
0
5
[]
[ "SM100", "SM103" ]
[]
Optimize this cuda kernel file from vllm (csrc/custom_all_gather_reduce_scatter.cuh). Goal: [Perf][Distributed] Add low-SM multimem reduce-scatter for SM100/SM103 Target hardware: SM100, SM103 Target models: unspecified Current file: ```cuda #pragma once #include "custom_collective_common.cuh" namespace vllm { con...
## Purpose Add a low-SM MNNVL reduce-scatter backend for TP2, TP4, and TP8 MNNVL groups on SM100 or SM103. The kernel uses `multimem.ld_reduce` to reduce across the NVLS multicast mapping and ordinary local stores for each rank-owned output shard. It launches at most 8 CTAs per GPU with 1024 threads and an 8-way vecto...
[{"scope": "e2e", "hardware": "B300", "model": null, "shape": "Input size: 64 MiB", "batch_size": null, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 148.83, "optimized": 137.38, "stated_speedup": null, "speedup": 1.0833}, {"scope": "e2e", "hardware": "B300", "model": null, "shape": "Input s...
null
1.0644
vllm
442bd00d9feff7d6a0cebf74248674bad74ec391
2026-09-24T20:27:21-07:00
55,072
https://github.com/vllm-project/vllm/pull/55072
[Perf][Distributed] Add low-SM multimem reduce-scatter for SM100/SM103 (#55072)
[Perf][Distributed] Add low-SM multimem reduce-scatter for SM100/SM103 (#55072) Signed-off-by: Yongye Zhu <zyy1102000@gmail.com> Signed-off-by: Summer Yang <girasoleyang@gmail.com> Co-authored-by: Summer Yang <girasoleyang@gmail.com>
csrc/custom_all_reduce.cuh
cuda
Apache-2.0
#pragma once #include "custom_collective_common.cuh" namespace vllm { template <typename T, int ngpus> __global__ void __launch_bounds__(512, 1) cross_device_reduce_1stage(RankData* _dp, RankSignals sg, Signal* self_sg, T* __restrict__ result, int rank, int size) { using P = type...
#pragma once #include "custom_collective_common.cuh" namespace vllm { template <typename T, int ngpus> __global__ void __launch_bounds__(512, 1) cross_device_reduce_1stage(RankData* _dp, RankSignals sg, Signal* self_sg, T* __restrict__ result, int rank, int size) { using P = type...
--- csrc/custom_all_reduce.cuh +++ csrc/custom_all_reduce.cuh @@ -339,6 +339,12 @@ void mnnvl_lamport_reduce_scatter(cudaStream_t stream, T* input, T* output, void* local_buffer, uint32_t* epochs, int size, int stage_size_bytes); + template <...
6
0
5
[]
[ "SM100", "SM103" ]
[]
Optimize this cuda kernel file from vllm (csrc/custom_all_reduce.cuh). Goal: [Perf][Distributed] Add low-SM multimem reduce-scatter for SM100/SM103 Target hardware: SM100, SM103 Target models: unspecified Current file: ```cuda #pragma once #include "custom_collective_common.cuh" namespace vllm { template <typename...
## Purpose Add a low-SM MNNVL reduce-scatter backend for TP2, TP4, and TP8 MNNVL groups on SM100 or SM103. The kernel uses `multimem.ld_reduce` to reduce across the NVLS multicast mapping and ordinary local stores for each rank-owned output shard. It launches at most 8 CTAs per GPU with 1024 threads and an 8-way vecto...
[{"scope": "e2e", "hardware": "B300", "model": null, "shape": "Input size: 64 MiB", "batch_size": null, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 148.83, "optimized": 137.38, "stated_speedup": null, "speedup": 1.0833}, {"scope": "e2e", "hardware": "B300", "model": null, "shape": "Input s...
null
1.0644
vllm
442bd00d9feff7d6a0cebf74248674bad74ec391
2026-09-24T20:27:21-07:00
55,072
https://github.com/vllm-project/vllm/pull/55072
[Perf][Distributed] Add low-SM multimem reduce-scatter for SM100/SM103 (#55072)
[Perf][Distributed] Add low-SM multimem reduce-scatter for SM100/SM103 (#55072) Signed-off-by: Yongye Zhu <zyy1102000@gmail.com> Signed-off-by: Summer Yang <girasoleyang@gmail.com> Co-authored-by: Summer Yang <girasoleyang@gmail.com>
csrc/libtorch_stable/custom_all_gather_reduce_scatter.cu
cuda
Apache-2.0
#include "torch_utils.h" #include <torch/csrc/stable/macros.h> #include <torch/csrc/stable/accelerator.h> #include <torch/csrc/stable/tensor.h> #include <torch/headeronly/core/ScalarType.h> #include "custom_all_reduce.cuh" #include "custom_all_gather_reduce_scatter.cuh" namespace vllm { void CustomAllreduce::allgat...
#include "torch_utils.h" #include <torch/csrc/stable/macros.h> #include <torch/csrc/stable/accelerator.h> #include <torch/csrc/stable/tensor.h> #include <torch/headeronly/core/ScalarType.h> #include "custom_all_reduce.cuh" #include "custom_all_gather_reduce_scatter.cuh" namespace vllm { void CustomAllreduce::allgat...
--- csrc/libtorch_stable/custom_all_gather_reduce_scatter.cu +++ csrc/libtorch_stable/custom_all_gather_reduce_scatter.cu @@ -191,6 +191,55 @@ #undef MNNVL_LAMPORT_RS_LAUNCH } +template <typename T> +void CustomAllreduce::mnnvl_multimem_reduce_scatter( + cudaStream_t stream, const T* multicast_input, T* output, ...
108
0
5
[]
[ "SM100", "SM103" ]
[]
Optimize this cuda kernel file from vllm (csrc/libtorch_stable/custom_all_gather_reduce_scatter.cu). Goal: [Perf][Distributed] Add low-SM multimem reduce-scatter for SM100/SM103 Target hardware: SM100, SM103 Target models: unspecified Current file: ```cuda #include "torch_utils.h" #include <torch/csrc/stable/macros....
## Purpose Add a low-SM MNNVL reduce-scatter backend for TP2, TP4, and TP8 MNNVL groups on SM100 or SM103. The kernel uses `multimem.ld_reduce` to reduce across the NVLS multicast mapping and ordinary local stores for each rank-owned output shard. It launches at most 8 CTAs per GPU with 1024 threads and an 8-way vecto...
[{"scope": "e2e", "hardware": "B300", "model": null, "shape": "Input size: 64 MiB", "batch_size": null, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 148.83, "optimized": 137.38, "stated_speedup": null, "speedup": 1.0833}, {"scope": "e2e", "hardware": "B300", "model": null, "shape": "Input s...
null
1.0644
vllm
442bd00d9feff7d6a0cebf74248674bad74ec391
2026-09-24T20:27:21-07:00
55,072
https://github.com/vllm-project/vllm/pull/55072
[Perf][Distributed] Add low-SM multimem reduce-scatter for SM100/SM103 (#55072)
[Perf][Distributed] Add low-SM multimem reduce-scatter for SM100/SM103 (#55072) Signed-off-by: Yongye Zhu <zyy1102000@gmail.com> Signed-off-by: Summer Yang <girasoleyang@gmail.com> Co-authored-by: Summer Yang <girasoleyang@gmail.com>
csrc/libtorch_stable/custom_all_gather_reduce_scatter_ops.cpp
cpp
Apache-2.0
#include "ops.h" #include "core/registration.h" #include <torch/csrc/stable/library.h> STABLE_TORCH_LIBRARY_FRAGMENT(_C_custom_ar, custom_ag_rs) { custom_ag_rs.def( "custom_all_gather(int fa, Tensor inp, Tensor! out, int reg_buffer, " "int reg_buffer_sz_bytes) -> ()"); custom_ag_rs.def( "mnnvl_l...
#include "ops.h" #include "core/registration.h" #include <torch/csrc/stable/library.h> STABLE_TORCH_LIBRARY_FRAGMENT(_C_custom_ar, custom_ag_rs) { custom_ag_rs.def( "custom_all_gather(int fa, Tensor inp, Tensor! out, int reg_buffer, " "int reg_buffer_sz_bytes) -> ()"); custom_ag_rs.def( "mnnvl_l...
--- csrc/libtorch_stable/custom_all_gather_reduce_scatter_ops.cpp +++ csrc/libtorch_stable/custom_all_gather_reduce_scatter_ops.cpp @@ -17,6 +17,10 @@ custom_ag_rs.def( "mnnvl_lamport_reduce_scatter(int fa, Tensor inp, Tensor! out, int " "local_buffer, int epoch_buffer, int stage_sz_bytes) -> ()"); + ...
6
0
5
[]
[ "SM100", "SM103" ]
[]
Optimize this cpp kernel file from vllm (csrc/libtorch_stable/custom_all_gather_reduce_scatter_ops.cpp). Goal: [Perf][Distributed] Add low-SM multimem reduce-scatter for SM100/SM103 Target hardware: SM100, SM103 Target models: unspecified Current file: ```cpp #include "ops.h" #include "core/registration.h" #include ...
## Purpose Add a low-SM MNNVL reduce-scatter backend for TP2, TP4, and TP8 MNNVL groups on SM100 or SM103. The kernel uses `multimem.ld_reduce` to reduce across the NVLS multicast mapping and ordinary local stores for each rank-owned output shard. It launches at most 8 CTAs per GPU with 1024 threads and an 8-way vecto...
[{"scope": "e2e", "hardware": "B300", "model": null, "shape": "Input size: 64 MiB", "batch_size": null, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 148.83, "optimized": 137.38, "stated_speedup": null, "speedup": 1.0833}, {"scope": "e2e", "hardware": "B300", "model": null, "shape": "Input s...
null
1.0644
vllm
442bd00d9feff7d6a0cebf74248674bad74ec391
2026-09-24T20:27:21-07:00
55,072
https://github.com/vllm-project/vllm/pull/55072
[Perf][Distributed] Add low-SM multimem reduce-scatter for SM100/SM103 (#55072)
[Perf][Distributed] Add low-SM multimem reduce-scatter for SM100/SM103 (#55072) Signed-off-by: Yongye Zhu <zyy1102000@gmail.com> Signed-off-by: Summer Yang <girasoleyang@gmail.com> Co-authored-by: Summer Yang <girasoleyang@gmail.com>
csrc/libtorch_stable/ops.h
cpp
Apache-2.0
#pragma once #include <torch/csrc/stable/library.h> #include <torch/csrc/stable/tensor.h> #include <torch/headeronly/util/Exception.h> #include <optional> #include <string> #include <vector> #include <torch/csrc/stable/ops.h> inline torch::stable::Tensor weak_ref_tensor(torch::stable::Tensor& tensor) { // Ensure ...
#pragma once #include <torch/csrc/stable/library.h> #include <torch/csrc/stable/tensor.h> #include <torch/headeronly/util/Exception.h> #include <optional> #include <string> #include <vector> #include <torch/csrc/stable/ops.h> inline torch::stable::Tensor weak_ref_tensor(torch::stable::Tensor& tensor) { // Ensure ...
--- csrc/libtorch_stable/ops.h +++ csrc/libtorch_stable/ops.h @@ -527,6 +527,10 @@ torch::stable::Tensor& out, fptr_t local_buffer, fptr_t epoch_buffer, int64_t stage_sz_bytes); +void mnnvl_multimem_reduce_scatter(f...
4
0
5
[]
[ "SM100", "SM103" ]
[]
Optimize this cpp kernel file from vllm (csrc/libtorch_stable/ops.h). Goal: [Perf][Distributed] Add low-SM multimem reduce-scatter for SM100/SM103 Target hardware: SM100, SM103 Target models: unspecified Current file: ```cpp #pragma once #include <torch/csrc/stable/library.h> #include <torch/csrc/stable/tensor.h> #i...
## Purpose Add a low-SM MNNVL reduce-scatter backend for TP2, TP4, and TP8 MNNVL groups on SM100 or SM103. The kernel uses `multimem.ld_reduce` to reduce across the NVLS multicast mapping and ordinary local stores for each rank-owned output shard. It launches at most 8 CTAs per GPU with 1024 threads and an 8-way vecto...
[{"scope": "e2e", "hardware": "B300", "model": null, "shape": "Input size: 64 MiB", "batch_size": null, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 148.83, "optimized": 137.38, "stated_speedup": null, "speedup": 1.0833}, {"scope": "e2e", "hardware": "B300", "model": null, "shape": "Input s...
null
1.0644
vllm
16070ed7e9b051cb0b1958d4289912157026d2f4
2026-09-25T09:30:32+08:00
58,526
https://github.com/vllm-project/vllm/pull/58526
[Minimax-M3][Perf] Use triton_mrope for vision tower + int64 offset fix for triton_mrope (#58526)
[Minimax-M3][Perf] Use triton_mrope for vision tower + int64 offset fix for triton_mrope (#58526) Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg> Co-authored-by: Kimi <noreply@moonshot.cn> Co-authored-by: Isotr0py <Isotr0py@outlook.com>
vllm/model_executor/layers/rotary_embedding/mrope.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project import numpy as np import torch from vllm.platforms import current_platform from vllm.triton_utils import tl, triton from vllm.utils.torch_utils import direct_register_custom_op from .base import RotaryEmbeddi...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project import numpy as np import torch from vllm.platforms import current_platform from vllm.triton_utils import tl, triton from vllm.utils.torch_utils import direct_register_custom_op from .base import RotaryEmbeddi...
--- vllm/model_executor/layers/rotary_embedding/mrope.py +++ vllm/model_executor/layers/rotary_embedding/mrope.py @@ -20,6 +20,8 @@ cos, sin, num_tokens, + q_token_stride, + k_token_stride, n_qh: tl.constexpr, n_kh: tl.constexpr, hd: tl.constexpr, @@ -39,9 +41,10 @@ # and suppor...
12
7
1
[ "kimi", "minimax", "llava/vlm" ]
[]
[]
Optimize this triton kernel file from vllm (vllm/model_executor/layers/rotary_embedding/mrope.py). Goal: [Minimax-M3][Perf] Use triton_mrope for vision tower + int64 offset fix for triton_mrope Target hardware: unspecified Target models: kimi, minimax, llava/vlm Current file: ```python # SPDX-License-Identifier: Apac...
## Purpose Use triton_mrope for RoPE in vision tower. Also add a custom kernel for RoPE setup, called once per model forward pass, shared across layers, to avoid the storm of ~20 kernels (huge impact as we run M3 vision tower w/o CUDAgraph nor torch.compile) This PR also fixes int64 offset issue with the existing tri...
[{"scope": "kernel", "hardware": "GB300", "model": null, "shape": "Patches=256", "batch_size": null, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 178.6, "optimized": 31.3, "stated_speedup": 5.7, "speedup": 5.7061}, {"scope": "kernel", "hardware": "GB300", "model": null, "shape": "Patches=57...
4.2536
1.0366
vllm
26f49e336a1498300a442a0d95911c11f5284500
2026-09-24T22:42:08+08:00
57,918
https://github.com/vllm-project/vllm/pull/57918
[Perf][Attention] Bound FlashInfer prefill dequantization scratch (#57918)
[Perf][Attention] Bound FlashInfer prefill dequantization scratch (#57918) Signed-off-by: Yueh-Ting Chen <yueh.ting.chen@gmail.com>
vllm/v1/attention/backends/flashinfer.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Attention layer with FlashInfer.""" from dataclasses import dataclass, replace from enum import Enum from functools import partial from typing import ClassVar import numpy as np import torch from flashinfer i...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Attention layer with FlashInfer.""" from dataclasses import dataclass, replace from enum import Enum from functools import partial from typing import ClassVar import numpy as np import torch from flashinfer i...
--- vllm/v1/attention/backends/flashinfer.py +++ vllm/v1/attention/backends/flashinfer.py @@ -1563,8 +1563,30 @@ qo_indptr_prefill_cpu[1:] - qo_indptr_prefill_cpu[:-1] ) max_q_len_prefill = int(query_lens_prefill_cpu.max().item()) + prefill_block_tab...
23
1
1
[]
[]
[]
Optimize this triton kernel file from vllm (vllm/v1/attention/backends/flashinfer.py). Goal: [Perf][Attention] Bound FlashInfer prefill dequantization scratch Target hardware: unspecified Target models: unspecified Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contr...
## Purpose The FlashInfer TRTLLM prefill fallback for BF16/FP16 queries with FP8 KV allocates temporary dequantized pages for every block-table entry, including unused columns. Bound the prefill block table using host sequence-length bounds before dequantization. This includes cached prefixes and preserves the contig...
[]
null
null
vllm
b715699df45f091325b307c0f5ac874010fbb23e
2026-09-23T19:11:57+03:00
50,212
https://github.com/vllm-project/vllm/pull/50212
[ROCm][Perf] Extend QK-norm/RoPE/KV-cache fusion to MRoPE (#50212)
[ROCm][Perf] Extend QK-norm/RoPE/KV-cache fusion to MRoPE (#50212) Signed-off-by: Vorapol Assavasangthong <Vorapol.Assavasangthong@amd.com> Co-authored-by: Santosh Hiremath <Santosh.Hiremath@amd.com> Co-authored-by: Douglas Lehr <91553416+dllehr-amd@users.noreply.github.com>
vllm/model_executor/layers/rotary_embedding/mrope.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project import numpy as np import torch from vllm.platforms import current_platform from vllm.triton_utils import tl, triton from .base import RotaryEmbeddingBase from .yarn_scaling_rope import YaRNScalingRotaryEmbedd...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project import numpy as np import torch from vllm.platforms import current_platform from vllm.triton_utils import tl, triton from vllm.utils.torch_utils import direct_register_custom_op from .base import RotaryEmbeddi...
--- vllm/model_executor/layers/rotary_embedding/mrope.py +++ vllm/model_executor/layers/rotary_embedding/mrope.py @@ -7,6 +7,7 @@ from vllm.platforms import current_platform from vllm.triton_utils import tl, triton +from vllm.utils.torch_utils import direct_register_custom_op from .base import RotaryEmbeddingBas...
86
0
3
[]
[ "ROCM" ]
[]
Optimize this triton kernel file from vllm (vllm/model_executor/layers/rotary_embedding/mrope.py). Goal: [ROCm][Perf] Extend QK-norm/RoPE/KV-cache fusion to MRoPE Target hardware: ROCM Target models: unspecified Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contribu...
## Summary Extend the existing `QkNormRopeKvCacheFusionPass` to support Qwen3-VL 3D MRoPE. For eligible decode ranges, it replaces two Q/K RMSNorm launches, MRoPE, and the unified FP8 KV-cache update with one AITER attention-prologue kernel: **three fewer GPU launches per layer**. This is a model-agnostic compile-pas...
[{"scope": "e2e", "hardware": "MI355X", "model": "Qwen3-VL-30B", "shape": null, "batch_size": 4, "metric": "throughput", "unit": "tok/s", "higher_is_better": true, "baseline": 538.78, "optimized": 623.68, "stated_speedup": 1.1576, "speedup": 1.1576}, {"scope": "e2e", "hardware": "MI355X", "model": "Qwen3-VL-30B", "shap...
null
1.0474
vllm
1904ed9402ce81e7db4391841c2205bf785380d9
2026-09-23T16:39:27+08:00
58,225
https://github.com/vllm-project/vllm/pull/58225
[Perf][ROCm][Attention] Narrow the Triton prefill-attention KV tile on RDNA3/RDNA4 (#58225)
[Perf][ROCm][Attention] Narrow the Triton prefill-attention KV tile on RDNA3/RDNA4 (#58225) Signed-off-by: Jipeng Li <jipengli@amd.com> Co-authored-by: GitHub Copilot CLI <noreply@github.com> Co-authored-by: Andreas Karatzas <akaratza@amd.com>
vllm/v1/attention/ops/triton_prefill_attention.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project # Adapted from # https://github.com/sgl-project/sglang/blob/97cb762bb65ebf05025eb342de03c184660427a3/python/sglang/srt/layers/attention/triton_ops/prefill_attention.py # Changes: # - Add support for sliding windo...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project # Adapted from # https://github.com/sgl-project/sglang/blob/97cb762bb65ebf05025eb342de03c184660427a3/python/sglang/srt/layers/attention/triton_ops/prefill_attention.py # Changes: # - Add support for sliding windo...
--- vllm/v1/attention/ops/triton_prefill_attention.py +++ vllm/v1/attention/ops/triton_prefill_attention.py @@ -30,6 +30,16 @@ from vllm.platforms import current_platform from vllm.triton_utils import tl, triton from vllm.utils.math_utils import RCP_LN2 + + +def _prefer_narrow_kv_tile() -> bool: + """RDNA3/RDNA4 ...
15
1
1
[]
[ "ROCM" ]
[]
Optimize this triton kernel file from vllm (vllm/v1/attention/ops/triton_prefill_attention.py). Goal: [Perf][ROCm][Attention] Narrow the Triton prefill-attention KV tile on RDNA3/RDNA4 Target hardware: ROCM Target models: unspecified Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightTe...
## Purpose Addresses #58060. On RDNA3/RDNA4, `context_attention_fwd` in `vllm/v1/attention/ops/triton_prefill_attention.py` launches `_fwd_kernel` with a 128x128 tile for bf16/fp16, which is slow on these GPUs. This PR narrows only the KV tile (`BLOCK_N`) to 32 when `on_gfx1x()` is true. `BLOCK_M`, `num_warps` and `nu...
[{"scope": "kernel", "hardware": "gfx1100", "model": null, "shape": null, "batch_size": null, "metric": "speedup", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 2.56, "speedup": 2.56}, {"scope": "kernel", "hardware": "gfx1100", "model": null, "shape": null, "batch_size":...
2.43
1.11
vllm
68363d64ec476bbbf5025b30ced0f6a2425b1291
2026-09-22T09:38:16+03:00
47,842
https://github.com/vllm-project/vllm/pull/47842
[ROCm][Perf] Avoid extra reshape kernel in Qwen GDN output norm (#47842)
[ROCm][Perf] Avoid extra reshape kernel in Qwen GDN output norm (#47842) Signed-off-by: Mikko Tukiainen <Mikko.Tukiainen@amd.com> Co-authored-by: Cursor <cursoragent@cursor.com>
vllm/model_executor/layers/mamba/gdn/qwen_gdn_linear_attn.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Inference-only Qwen3-Next/Qwen3.5 model.""" import os from typing import Literal import torch from einops import rearrange from torch import nn from vllm import _custom_ops as ops from vllm import envs from ...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Inference-only Qwen3-Next/Qwen3.5 model.""" import os from typing import Literal import torch from einops import rearrange from torch import nn from vllm import _custom_ops as ops from vllm import envs from ...
--- vllm/model_executor/layers/mamba/gdn/qwen_gdn_linear_attn.py +++ vllm/model_executor/layers/mamba/gdn/qwen_gdn_linear_attn.py @@ -852,13 +852,8 @@ The RMSNormGated + quant sequence is eligible for fusion by the compilation pass when fuse_norm_quant is enabled. """ - z_shape_og = z....
3
23
1
[ "qwen", "mamba" ]
[ "ROCM" ]
[]
Optimize this triton kernel file from vllm (vllm/model_executor/layers/mamba/gdn/qwen_gdn_linear_attn.py). Goal: [ROCm][Perf] Avoid extra reshape kernel in Qwen GDN output norm Target hardware: ROCM Target models: qwen, mamba Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copy...
## Purpose Removes an extra Inductor-generated reshape/copy kernel, by reworking Qwen GDN `_output_projection` method. `RMSNormGated` logic now directly produces the flattened `[num_tokens, hidden]` tensor consumed by `out_proj` which allows Inductor to pick. ## Test Plan Run existing RMSNormGated tests, performan...
[{"scope": "e2e", "hardware": "MI355X", "model": "Qwen3.8-2.4T-A95B-Quark-MXFP4", "shape": "ISL=1024,OSL=1024", "batch_size": 4, "metric": "Output tok/s", "unit": "tok/s", "higher_is_better": true, "baseline": 250.6, "optimized": 252.7, "stated_speedup": null, "speedup": 1.0084}, {"scope": "e2e", "hardware": "MI355X", ...
null
1.0047
vllm
a369a7becc20c6c4dda601aedef51b8cc8387971
2026-09-21T17:24:25-07:00
57,458
https://github.com/vllm-project/vllm/pull/57458
[Perf][Attention] Reduce GLM sparse MLA preparation overhead (#57458)
[Perf][Attention] Reduce GLM sparse MLA preparation overhead (#57458) Signed-off-by: Summer Yang <girasoleyang@gmail.com> Co-authored-by: Codex <noreply@openai.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> Co-authored-by: Jiangyun Zhu <riverclouds.zhu@qq.com>
vllm/v1/attention/backends/mla/sparse_utils.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Utility functions for sparse MLA backends.""" from dataclasses import dataclass from typing import Any import numpy as np import torch from vllm.config import VllmConfig from vllm.distributed import get_dcp_...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Utility functions for sparse MLA backends.""" from dataclasses import dataclass from typing import Any import numpy as np import torch from vllm.config import VllmConfig from vllm.distributed import get_dcp_...
--- vllm/v1/attention/backends/mla/sparse_utils.py +++ vllm/v1/attention/backends/mla/sparse_utils.py @@ -86,7 +86,7 @@ @staticmethod @triton.jit(do_not_specialize=["max_num_blocks_per_req", "workspace_rank_stride"]) - def kernel( + def sparse_mla_index_remap_kernel( req_id_ptr, # int32 [num...
72
18
3
[ "glm" ]
[]
[]
Optimize this triton kernel file from vllm (vllm/v1/attention/backends/mla/sparse_utils.py). Goal: [Perf][Attention] Reduce GLM sparse MLA preparation overhead Target hardware: unspecified Target models: glm Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors...
## Purpose Reduce query packing and sparse-index preparation overhead around FlashInfer NoPE MLA attention. The three commits: 1. Reuse a contiguous NoPE query when its rotary tail is empty, avoiding a redundant `torch.cat` before FP8 quantization. Preserve concatenation for nonempty rotary dimensions and strided qu...
[{"scope": "e2e", "hardware": "GB300", "model": null, "shape": "32768 queries \u00d7 8 heads \u00d7 512 dimensions, capacity 2176", "batch_size": 32768, "metric": "latency", "unit": "ms", "higher_is_better": false, "baseline": 518.25, "optimized": 507.61, "stated_speedup": null, "speedup": 1.021}, {"scope": "e2e", "har...
2.4352
1.0191
vllm
97dc6b19d2fe92b794b49e684677a2e1a8b2c540
2026-09-21T00:08:43-07:00
57,885
https://github.com/vllm-project/vllm/pull/57885
[Perf][Attention] Avoid redundant sparse attention metadata operations (#57885)
[Perf][Attention] Avoid redundant sparse attention metadata operations (#57885) Signed-off-by: Woosuk Kwon <woosuk@inferact.ai> Co-authored-by: OpenAI Codex <noreply@openai.com>
vllm/v1/attention/backends/mla/indexer.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project from dataclasses import dataclass from typing import Any import numpy as np import torch import vllm.envs as envs from vllm.config import VllmConfig from vllm.distributed import get_dcp_group, get_pcp_group from...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project from dataclasses import dataclass from typing import Any import numpy as np import torch import vllm.envs as envs from vllm.config import VllmConfig from vllm.distributed import get_dcp_group, get_pcp_group from...
--- vllm/v1/attention/backends/mla/indexer.py +++ vllm/v1/attention/backends/mla/indexer.py @@ -1261,7 +1261,6 @@ assert num_decode_tokens + num_prefill_tokens == num_tokens compressed_slot_mapping = slot_mapping - compressed_seq_lens = seq_lens indexer_block_table = block_table ...
3
2
2
[]
[]
[]
Optimize this triton kernel file from vllm (vllm/v1/attention/backends/mla/indexer.py). Goal: [Perf][Attention] Avoid redundant sparse attention metadata operations Target hardware: unspecified Target models: unspecified Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright...
## Purpose Sparse attention metadata preparation launches unnecessary GPU work on every decode step. Write SWA token validity directly into its persistent buffer, and compute compressed prefill sequence lengths only when the batch contains prefills. For the tested DSV4.1 TP4 configuration, this eliminates four validi...
[{"scope": "e2e", "hardware": "4x GB200", "model": "DeepSeek-V4.1-Flash", "shape": "TP4", "batch_size": 8, "metric": "Mean TPOT", "unit": "ms", "higher_is_better": false, "baseline": 4.467, "optimized": 4.457, "stated_speedup": null, "speedup": 1.0022}, {"scope": "e2e", "hardware": "4x GB200", "model": "DeepSeek-V4.1-F...
null
1.0022
vllm
97dc6b19d2fe92b794b49e684677a2e1a8b2c540
2026-09-21T00:08:43-07:00
57,885
https://github.com/vllm-project/vllm/pull/57885
[Perf][Attention] Avoid redundant sparse attention metadata operations (#57885)
[Perf][Attention] Avoid redundant sparse attention metadata operations (#57885) Signed-off-by: Woosuk Kwon <woosuk@inferact.ai> Co-authored-by: OpenAI Codex <noreply@openai.com>
vllm/v1/attention/backends/mla/sparse_swa.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project from dataclasses import dataclass, field from typing import Any, ClassVar, cast import torch from vllm.config import CacheConfig, VllmConfig, get_current_vllm_config from vllm.model_executor.layers.attention_lay...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project from dataclasses import dataclass, field from typing import Any, ClassVar, cast import torch from vllm.config import CacheConfig, VllmConfig, get_current_vllm_config from vllm.model_executor.layers.attention_lay...
--- vllm/v1/attention/backends/mla/sparse_swa.py +++ vllm/v1/attention/backends/mla/sparse_swa.py @@ -613,7 +613,7 @@ ) is_valid_token = self.is_valid_token[: slot_mapping.shape[0]] - is_valid_token.copy_(slot_mapping >= 0) + torch.ge(slot_mapping, 0, out=is_valid_token) if re...
1
1
2
[]
[]
[]
Optimize this triton kernel file from vllm (vllm/v1/attention/backends/mla/sparse_swa.py). Goal: [Perf][Attention] Avoid redundant sparse attention metadata operations Target hardware: unspecified Target models: unspecified Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyri...
## Purpose Sparse attention metadata preparation launches unnecessary GPU work on every decode step. Write SWA token validity directly into its persistent buffer, and compute compressed prefill sequence lengths only when the batch contains prefills. For the tested DSV4.1 TP4 configuration, this eliminates four validi...
[{"scope": "e2e", "hardware": "4x GB200", "model": "DeepSeek-V4.1-Flash", "shape": "TP4", "batch_size": 8, "metric": "Mean TPOT", "unit": "ms", "higher_is_better": false, "baseline": 4.467, "optimized": 4.457, "stated_speedup": null, "speedup": 1.0022}, {"scope": "e2e", "hardware": "4x GB200", "model": "DeepSeek-V4.1-F...
null
1.0022
vllm
1b9fa3eaa8ff23d1a583f2f77dd2b33c9f896ee8
2026-09-20T18:20:55+08:00
57,534
https://github.com/vllm-project/vllm/pull/57534
[Perf][GLM] Fuse the kpool tail slot mapping into one Triton kernel (#57534)
[Perf][GLM] Fuse the kpool tail slot mapping into one Triton kernel (#57534) Signed-off-by: Jared Wen <jaredwen@inferact.ai> Co-authored-by: Claude Fable 5.1 <noreply@anthropic.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
vllm/v1/attention/backends/mla/indexer.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project from dataclasses import dataclass from typing import Any import numpy as np import torch import vllm.envs as envs from vllm.config import VllmConfig from vllm.distributed import get_dcp_group, get_pcp_group from...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project from dataclasses import dataclass from typing import Any import numpy as np import torch import vllm.envs as envs from vllm.config import VllmConfig from vllm.distributed import get_dcp_group, get_pcp_group from...
--- vllm/v1/attention/backends/mla/indexer.py +++ vllm/v1/attention/backends/mla/indexer.py @@ -634,6 +634,38 @@ prefill: DeepseekV32IndexerPrefillMetadata | None = None +@triton.jit(do_not_specialize=["num_reqs", "num_actual_tokens", "num_tokens"]) +def _kpool_tail_slot_mapping_kernel( + slot_mapping_ptr, ...
57
2
1
[ "glm" ]
[]
[]
Optimize this triton kernel file from vllm (vllm/v1/attention/backends/mla/indexer.py). Goal: [Perf][GLM] Fuse the kpool tail slot mapping into one Triton kernel Target hardware: unspecified Target models: glm Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributo...
## Purpose GLM-5.3-Flash sparse-MLA models keep a one-block-per-request circular tail cache (kpool). Every decode step — twice per step with MTP, once for the target model and once for the drafter — `KpoolTailMetadataBuilder.build()` maps each token to its request's tail ring with a chain of small torch ops (`arange...
[{"scope": "kernel", "hardware": "GB300", "model": null, "shape": "decode bs=1 (2 tok, MTP k=1)", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 157, "optimized": 38, "stated_speedup": null, "speedup": 4.1316}, {"scope": "kernel", "hardware": "GB300", "model": null, "shape": ...
7.6061
1.0143
vllm
92b40f5a144763c8b2ef6ebe848793de634ada05
2026-09-20T05:25:13+01:00
56,045
https://github.com/vllm-project/vllm/pull/56045
[CPU][Perf] refactor paged attention for Arm CPUs (#56045)
[CPU][Perf] refactor paged attention for Arm CPUs (#56045) Signed-off-by: Fadi Arafeh <fadi.arafeh@arm.com> Co-authored-by: Codex <noreply@openai.com> Co-authored-by: Li, Jiang <jiang1.li@intel.com>
csrc/cpu/cpu_attn_impl.hpp
cpp
Apache-2.0
#ifndef CPU_ATTN_HPP #define CPU_ATTN_HPP #include <type_traits> #include <cstddef> #if defined(__APPLE__) #include <sys/sysctl.h> #endif #include "cpu/cpu_arch_macros.h" #include "cpu/utils.hpp" namespace cpu_attention { enum class ISA { AMX, VEC, VEC16, NEON, VXE, RVV, VSX, AMX_FP8 }; // Mirrors csrc/attention...
#ifndef CPU_ATTN_HPP #define CPU_ATTN_HPP #include <type_traits> #include <cstddef> #if defined(__APPLE__) #include <sys/sysctl.h> #endif #include "cpu/cpu_arch_macros.h" #include "cpu/utils.hpp" namespace cpu_attention { enum class ISA { AMX, VEC, VEC16, NEON, VXE, RVV, VSX, AMX_FP8 }; // Mirrors csrc/attention...
--- csrc/cpu/cpu_attn_impl.hpp +++ csrc/cpu/cpu_attn_impl.hpp @@ -956,6 +956,28 @@ std::printf("%s", ss.str().c_str()); } +// This allows us to store probabilities in a packed format +// for GEMM implementations that need packed A. +template <typename attention_impl_t, typename = void> +struct ProbabilityTokenSto...
36
13
4
[]
[ "CPU" ]
[]
Optimize this cpp kernel file from vllm (csrc/cpu/cpu_attn_impl.hpp). Goal: [CPU][Perf] refactor paged attention for Arm CPUs Target hardware: CPU Target models: unspecified Current file: ```cpp #ifndef CPU_ATTN_HPP #define CPU_ATTN_HPP #include <type_traits> #include <cstddef> #if defined(__APPLE__) #include <sy...
## Purpose Previous implementation left performance on the table. This impl provides: - faster GEMM kernels - faster kv cache packing - prepack Q during copy - adds interface allowing attention impl to write softmax probabilities directly in a packed format - enable "NEON" ISA for block_size % 16 - up to 25% faster...
[]
null
null
vllm
92b40f5a144763c8b2ef6ebe848793de634ada05
2026-09-20T05:25:13+01:00
56,045
https://github.com/vllm-project/vllm/pull/56045
[CPU][Perf] refactor paged attention for Arm CPUs (#56045)
[CPU][Perf] refactor paged attention for Arm CPUs (#56045) Signed-off-by: Fadi Arafeh <fadi.arafeh@arm.com> Co-authored-by: Codex <noreply@openai.com> Co-authored-by: Li, Jiang <jiang1.li@intel.com>
csrc/cpu/cpu_attn_neon.hpp
cpp
Apache-2.0
#ifndef CPU_ATTN_NEON_HPP #define CPU_ATTN_NEON_HPP #include "cpu_attn_impl.hpp" #include <arm_neon.h> #include <type_traits> #ifdef ARM_BF16_SUPPORT #include "cpu_attn_neon_bfmmla.hpp" #endif namespace cpu_attention { namespace { #define BLOCK_SIZE_ALIGNMENT 32 #define HEAD_SIZE_ALIGNMENT 32 #define MAX_Q_HEAD_NU...
#ifndef CPU_ATTN_NEON_HPP #define CPU_ATTN_NEON_HPP #include "cpu_attn_impl.hpp" #include <arm_neon.h> #include <type_traits> #ifdef ARM_BF16_SUPPORT #include "cpu_attn_neon_bfmmla.hpp" #endif namespace cpu_attention { namespace { #define BLOCK_SIZE_ALIGNMENT 16 #define HEAD_SIZE_ALIGNMENT 32 #define MAX_Q_HEAD_NU...
--- csrc/cpu/cpu_attn_neon.hpp +++ csrc/cpu/cpu_attn_neon.hpp @@ -11,7 +11,7 @@ namespace { -#define BLOCK_SIZE_ALIGNMENT 32 +#define BLOCK_SIZE_ALIGNMENT 16 #define HEAD_SIZE_ALIGNMENT 32 #define MAX_Q_HEAD_NUM_PER_ITER 16 @@ -387,7 +387,7 @@ }; #ifdef ARM_BF16_SUPPORT -// For BF16 on Arm, reuse the BFMML...
2
2
4
[]
[ "CPU" ]
[]
Optimize this cpp kernel file from vllm (csrc/cpu/cpu_attn_neon.hpp). Goal: [CPU][Perf] refactor paged attention for Arm CPUs Target hardware: CPU Target models: unspecified Current file: ```cpp #ifndef CPU_ATTN_NEON_HPP #define CPU_ATTN_NEON_HPP #include "cpu_attn_impl.hpp" #include <arm_neon.h> #include <type_trai...
## Purpose Previous implementation left performance on the table. This impl provides: - faster GEMM kernels - faster kv cache packing - prepack Q during copy - adds interface allowing attention impl to write softmax probabilities directly in a packed format - enable "NEON" ISA for block_size % 16 - up to 25% faster...
[]
null
null
vllm
fbe8a157fbdd4b2f813ae6395397232de97d5c5d
2026-09-19T16:05:04+03:00
53,623
https://github.com/vllm-project/vllm/pull/53623
[ROCm][Perf] Enable the AITER GDN decode fast path for flat qkvz layouts (#53623)
[ROCm][Perf] Enable the AITER GDN decode fast path for flat qkvz layouts (#53623) Signed-off-by: Mikko Tukiainen <Mikko.Tukiainen@amd.com> Co-authored-by: Cursor <cursoragent@cursor.com> Co-authored-by: TJian <tunjian.tan@embeddedllm.com>
vllm/model_executor/layers/mamba/gdn/qwen_gdn_linear_attn.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Inference-only Qwen3-Next/Qwen3.5 model.""" import os from typing import Literal import torch from einops import rearrange from torch import nn from vllm import _custom_ops as ops from vllm import envs from ...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Inference-only Qwen3-Next/Qwen3.5 model.""" import os from typing import Literal import torch from einops import rearrange from torch import nn from vllm import _custom_ops as ops from vllm import envs from ...
--- vllm/model_executor/layers/mamba/gdn/qwen_gdn_linear_attn.py +++ vllm/model_executor/layers/mamba/gdn/qwen_gdn_linear_attn.py @@ -399,6 +399,7 @@ self.key_dim = self.head_k_dim * self.num_k_heads self.value_dim = self.head_v_dim * self.num_v_heads self.gqa_interleaved_layout = gqa_interle...
6
8
1
[ "qwen", "mamba" ]
[ "ROCM" ]
[]
Optimize this triton kernel file from vllm (vllm/model_executor/layers/mamba/gdn/qwen_gdn_linear_attn.py). Goal: [ROCm][Perf] Enable the AITER GDN decode fast path for flat qkvz layouts Target hardware: ROCM Target models: qwen, mamba Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightT...
## Purpose `_forward_core_rocm` currently gates the AITER GDN decode fast path on `self.gqa_interleaved_layout`, so only Qwen3-Next takes it and flat-layout models (e.g. Qwen3.5, Qwen3.8) fall through to the generic path. #42880 added that guard because the fused reshape+conv kernel only understood Qwen3-Next's pack...
[{"scope": "e2e", "hardware": "MI355X", "model": "amd/Qwen3.8-2.4T-A95B-Quark-MXFP4", "shape": "ISL=1024,OSL=1024", "batch_size": 4, "metric": "throughput", "unit": "tok/s", "higher_is_better": true, "baseline": 250.6, "optimized": 258.6, "stated_speedup": 1.032, "speedup": 1.0319}, {"scope": "e2e", "hardware": "MI355X...
1.9395
1.0228
vllm
975dca5bb5db302077674cfa9afe851ee700ad73
2026-09-16T14:03:57+01:00
57,140
https://github.com/vllm-project/vllm/pull/57140
[Perf][GDN] Scatter mixed speculative outputs into the caller buffer (#57140)
[Perf][GDN] Scatter mixed speculative outputs into the caller buffer (#57140) Signed-off-by: Arpan Tripathi <tripathiarpan20@gmail.com> Signed-off-by: zjy0516 <riverclouds.zhu@qq.com> Co-authored-by: Xavier Lyu <9938360+xavierlyu@users.noreply.github.com> Co-authored-by: Bohdan Podziubanchuk <114604629+Danbog32@users....
vllm/model_executor/layers/mamba/gdn/qwen_gdn_linear_attn.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Inference-only Qwen3-Next/Qwen3.5 model.""" import os from typing import Literal import torch from einops import rearrange from torch import nn from vllm import _custom_ops as ops from vllm import envs from ...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Inference-only Qwen3-Next/Qwen3.5 model.""" import os from typing import Literal import torch from einops import rearrange from torch import nn from vllm import _custom_ops as ops from vllm import envs from ...
--- vllm/model_executor/layers/mamba/gdn/qwen_gdn_linear_attn.py +++ vllm/model_executor/layers/mamba/gdn/qwen_gdn_linear_attn.py @@ -1575,14 +1575,10 @@ # 3. Merge core attention output if spec_sequence_masks is not None and core_attn_out_non_spec is not None: - merged_out = torch.empty(...
4
8
1
[ "qwen", "mamba" ]
[]
[]
Optimize this triton kernel file from vllm (vllm/model_executor/layers/mamba/gdn/qwen_gdn_linear_attn.py). Goal: [Perf][GDN] Scatter mixed speculative outputs into the caller buffer Target hardware: unspecified Target models: qwen, mamba Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrig...
## Purpose Mixed speculative/non-speculative Qwen GDN batches currently allocate `merged_out`, scatter both output partitions into it, and copy the complete tensor into `core_attn_out`. This change scatters directly into the caller's buffer, removing one output-sized allocation and the final full-output copy while pre...
[{"scope": "kernel", "hardware": "H100", "model": null, "shape": "N=32, 32 value heads \u00d7 128 dimensions", "batch_size": 32, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 35.05, "optimized": 17.95, "stated_speedup": null, "speedup": 1.9526}, {"scope": "kernel", "hardware": "H100", "model...
1.4407
1.0032
vllm
6ecd97f1b7fb13991065370f6d6be3dffe9fe1db
2026-09-16T12:34:55+08:00
56,441
https://github.com/vllm-project/vllm/pull/56441
[Perf][DSpark] Add KV-only context insertion across V4.1 cache formats (#56441)
[Perf][DSpark] Add KV-only context insertion across V4.1 cache formats (#56441) Signed-off-by: 0z5a <0z5a@users.noreply.github.com> Signed-off-by: Yongye Zhu <yongye@inferact.ai> Co-authored-by: 0z5a <0z5a@users.noreply.github.com> Co-authored-by: Codex <noreply@openai.com> Co-authored-by: Yongye Zhu <zyy1102000@gmail...
csrc/libtorch_stable/fused_deepseek_v4_qnorm_rope_kv_insert_kernel.cu
cuda
Apache-2.0
/* * SPDX-License-Identifier: Apache-2.0 * SPDX-FileCopyrightText: Copyright contributors to the vLLM project * * Horizontally-fused DeepseekV4-MLA kernel: * - Q side: optional per-head RMSNorm + GPT-J RoPE on last ROPE_DIM * - KV side: GPT-J RoPE on last ROPE_DIM + UE8M0 FP8 quant on NoPE + paged * ...
/* * SPDX-License-Identifier: Apache-2.0 * SPDX-FileCopyrightText: Copyright contributors to the vLLM project * * Horizontally-fused DeepseekV4-MLA kernel: * - Q side: optional per-head RMSNorm + GPT-J RoPE on last ROPE_DIM * - KV side: GPT-J RoPE on last ROPE_DIM + UE8M0 FP8 quant on NoPE + paged * ...
--- csrc/libtorch_stable/fused_deepseek_v4_qnorm_rope_kv_insert_kernel.cu +++ csrc/libtorch_stable/fused_deepseek_v4_qnorm_rope_kv_insert_kernel.cu @@ -657,7 +657,12 @@ config.attrs = attrs; config.numAttrs = (sm_version >= 90) ? 1 : 0; - if (num_tokens_full < NUM_TOKEN_CUTOFF) { + // The reduced grid pays of...
86
1
3
[ "deepseek" ]
[]
[]
Optimize this cuda kernel file from vllm (csrc/libtorch_stable/fused_deepseek_v4_qnorm_rope_kv_insert_kernel.cu). Goal: [Perf][DSpark] Add KV-only context insertion across V4.1 cache formats Target hardware: unspecified Target models: deepseek Current file: ```cuda /* * SPDX-License-Identifier: Apache-2.0 * SPDX-Fi...
Replace the DeepSeek-V4.1 DSpark context insertion call's unused query allocation and query work with a KV-only wrapper. Dispatch the existing CUDA KV math with zero query heads for packed uint8 `fp8_ds_mla`, BF16 and ordinary FP8 e4m3fn caches. Keep projection, `kv_norm`, scheduling and acceptance logic unchanged. Val...
[{"scope": "e2e", "hardware": "H100", "model": "DeepSeek-V4.1-Flash", "shape": null, "batch_size": 16, "metric": "throughput", "unit": "tok/s", "higher_is_better": true, "baseline": 12.8313, "optimized": 14.7392, "stated_speedup": 1.1487, "speedup": 1.1487}, {"scope": "e2e", "hardware": "H100", "model": "DeepSeek-V4.1-...
3.5178
1.1382
vllm
6ecd97f1b7fb13991065370f6d6be3dffe9fe1db
2026-09-16T12:34:55+08:00
56,441
https://github.com/vllm-project/vllm/pull/56441
[Perf][DSpark] Add KV-only context insertion across V4.1 cache formats (#56441)
[Perf][DSpark] Add KV-only context insertion across V4.1 cache formats (#56441) Signed-off-by: 0z5a <0z5a@users.noreply.github.com> Signed-off-by: Yongye Zhu <yongye@inferact.ai> Co-authored-by: 0z5a <0z5a@users.noreply.github.com> Co-authored-by: Codex <noreply@openai.com> Co-authored-by: Yongye Zhu <zyy1102000@gmail...
csrc/libtorch_stable/ops.h
cpp
Apache-2.0
#pragma once #include <torch/csrc/stable/library.h> #include <torch/csrc/stable/tensor.h> #include <torch/headeronly/util/Exception.h> #include <optional> #include <string> #include <vector> #include <torch/csrc/stable/ops.h> inline torch::stable::Tensor weak_ref_tensor(torch::stable::Tensor& tensor) { // Ensure ...
#pragma once #include <torch/csrc/stable/library.h> #include <torch/csrc/stable/tensor.h> #include <torch/headeronly/util/Exception.h> #include <optional> #include <string> #include <vector> #include <torch/csrc/stable/ops.h> inline torch::stable::Tensor weak_ref_tensor(torch::stable::Tensor& tensor) { // Ensure ...
--- csrc/libtorch_stable/ops.h +++ csrc/libtorch_stable/ops.h @@ -258,6 +258,13 @@ torch::stable::Tensor& cos_sin_cache, bool is_neox, torch::stable::Tensor& position_ids, int64_t forced_token_heads_per_warp); + +void fused_deepseek_v4_kv_rope_i...
7
0
3
[]
[]
[]
Optimize this cpp kernel file from vllm (csrc/libtorch_stable/ops.h). Goal: [Perf][DSpark] Add KV-only context insertion across V4.1 cache formats Target hardware: unspecified Target models: unspecified Current file: ```cpp #pragma once #include <torch/csrc/stable/library.h> #include <torch/csrc/stable/tensor.h> #in...
Replace the DeepSeek-V4.1 DSpark context insertion call's unused query allocation and query work with a KV-only wrapper. Dispatch the existing CUDA KV math with zero query heads for packed uint8 `fp8_ds_mla`, BF16 and ordinary FP8 e4m3fn caches. Keep projection, `kv_norm`, scheduling and acceptance logic unchanged. Val...
[{"scope": "e2e", "hardware": "H100", "model": "DeepSeek-V4.1-Flash", "shape": null, "batch_size": 16, "metric": "throughput", "unit": "tok/s", "higher_is_better": true, "baseline": 12.8313, "optimized": 14.7392, "stated_speedup": 1.1487, "speedup": 1.1487}, {"scope": "e2e", "hardware": "H100", "model": "DeepSeek-V4.1-...
3.5178
1.1382
vllm
6ecd97f1b7fb13991065370f6d6be3dffe9fe1db
2026-09-16T12:34:55+08:00
56,441
https://github.com/vllm-project/vllm/pull/56441
[Perf][DSpark] Add KV-only context insertion across V4.1 cache formats (#56441)
[Perf][DSpark] Add KV-only context insertion across V4.1 cache formats (#56441) Signed-off-by: 0z5a <0z5a@users.noreply.github.com> Signed-off-by: Yongye Zhu <yongye@inferact.ai> Co-authored-by: 0z5a <0z5a@users.noreply.github.com> Co-authored-by: Codex <noreply@openai.com> Co-authored-by: Yongye Zhu <zyy1102000@gmail...
csrc/libtorch_stable/torch_bindings.cpp
cpp
Apache-2.0
#include "ops.h" #include "cuda_utils.h" #include "core/registration.h" #include <torch/csrc/stable/library.h> // Register ops with STABLE_TORCH_LIBRARY for libtorch stable ABI compatibility. // Note: We register under namespace "_C" so ops are accessible as // torch.ops._C.<op_name> for compatibility with existing c...
#include "ops.h" #include "cuda_utils.h" #include "core/registration.h" #include <torch/csrc/stable/library.h> // Register ops with STABLE_TORCH_LIBRARY for libtorch stable ABI compatibility. // Note: We register under namespace "_C" so ops are accessible as // torch.ops._C.<op_name> for compatibility with existing c...
--- csrc/libtorch_stable/torch_bindings.cpp +++ csrc/libtorch_stable/torch_bindings.cpp @@ -426,6 +426,12 @@ "int forced_token_heads_per_warp=-1) -> ()"); ops.def( + "fused_deepseek_v4_kv_rope_insert(" + "Tensor kv, Tensor! k_cache, Tensor slot_mapping, Tensor position_ids, " + "Tensor cos_si...
8
0
3
[]
[]
[]
Optimize this cpp kernel file from vllm (csrc/libtorch_stable/torch_bindings.cpp). Goal: [Perf][DSpark] Add KV-only context insertion across V4.1 cache formats Target hardware: unspecified Target models: unspecified Current file: ```cpp #include "ops.h" #include "cuda_utils.h" #include "core/registration.h" #include...
Replace the DeepSeek-V4.1 DSpark context insertion call's unused query allocation and query work with a KV-only wrapper. Dispatch the existing CUDA KV math with zero query heads for packed uint8 `fp8_ds_mla`, BF16 and ordinary FP8 e4m3fn caches. Keep projection, `kv_norm`, scheduling and acceptance logic unchanged. Val...
[{"scope": "e2e", "hardware": "H100", "model": "DeepSeek-V4.1-Flash", "shape": null, "batch_size": 16, "metric": "throughput", "unit": "tok/s", "higher_is_better": true, "baseline": 12.8313, "optimized": 14.7392, "stated_speedup": 1.1487, "speedup": 1.1487}, {"scope": "e2e", "hardware": "H100", "model": "DeepSeek-V4.1-...
3.5178
1.1382
vllm
c6fa1f05d1bc627171c3a58c05f23a1c41202ac1
2026-09-15T17:15:59-04:00
56,346
https://github.com/vllm-project/vllm/pull/56346
[Perf][Kernel] Add sampled filtering for persistent top-k (#56346)
[Perf][Kernel] Add sampled filtering for persistent top-k (#56346) Signed-off-by: mgoin <mgoin64@gmail.com> Co-authored-by: OpenAI Codex <noreply@openai.com>
csrc/libtorch_stable/persistent_topk.cuh
cuda
Apache-2.0
/* * Persistent TopK Scheduler for DSA Indexer */ #ifndef PERSISTENT_TOPK_CUH_ #define PERSISTENT_TOPK_CUH_ #include <cuda.h> #include <cuda_fp16.h> #include <cuda_runtime.h> #include <cub/cub.cuh> #include <cstdint> #include "topk_histogram_4096.cuh" namespace vllm { namespace persistent { // ==================...
/* * Persistent TopK Scheduler for DSA Indexer */ #ifndef PERSISTENT_TOPK_CUH_ #define PERSISTENT_TOPK_CUH_ #include <cuda.h> #include <cuda_fp16.h> #include <cuda_runtime.h> #include <cub/cub.cuh> #include <cstdint> #include "topk_histogram_4096.cuh" namespace vllm { namespace persistent { // ==================...
--- csrc/libtorch_stable/persistent_topk.cuh +++ csrc/libtorch_stable/persistent_topk.cuh @@ -1030,41 +1030,34 @@ constexpr size_t FILTERED_TOPK_SMEM_DYNAMIC = sizeof(int) * 2 * FILTERED_TOPK_SMEM_INPUT_SIZE; // 128KB -/*! - * \brief Filtered Top-K kernel for ragged sequences. - * - * \tparam DType Data type (...
54
36
2
[]
[]
[]
Optimize this cuda kernel file from vllm (csrc/libtorch_stable/persistent_topk.cuh). Goal: [Perf][Kernel] Add sampled filtering for persistent top-k Target hardware: unspecified Target models: unspecified Current file: ```cuda /* * Persistent TopK Scheduler for DSA Indexer */ #ifndef PERSISTENT_TOPK_CUH_ #define P...
## Purpose Speed up long FP32 sparse-indexer decode top-k with sampling inspired by [DeepSelect](https://github.com/deepseek-ai/DeepSelect). A coalesced sample estimates a cutoff, survivors are compacted in shared memory, and exact FP32 selection finishes on those candidates. Too few or too many candidates trigger exa...
[{"scope": "e2e", "hardware": "B300", "model": "DeepSeek-V4-Flash-0731", "shape": "k=2048, valid_length=128K", "batch_size": 1024, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 316.58, "optimized": 207.06, "stated_speedup": null, "speedup": 1.5289}, {"scope": "e2e", "hardware": "B300", "mode...
null
1.733
vllm
c6fa1f05d1bc627171c3a58c05f23a1c41202ac1
2026-09-15T17:15:59-04:00
56,346
https://github.com/vllm-project/vllm/pull/56346
[Perf][Kernel] Add sampled filtering for persistent top-k (#56346)
[Perf][Kernel] Add sampled filtering for persistent top-k (#56346) Signed-off-by: mgoin <mgoin64@gmail.com> Co-authored-by: OpenAI Codex <noreply@openai.com>
csrc/libtorch_stable/topk.cu
cuda
Apache-2.0
// Persistent TopK kernel for DeepSeek V3 sparse attention indexer. // See persistent_topk.cuh for kernel implementation. #include <cuda_runtime.h> #include <algorithm> #include "ops.h" #include "torch_utils.h" #ifndef USE_ROCM #include "persistent_topk.cuh" #endif namespace { #ifndef USE_ROCM template <int TopK...
// Persistent TopK kernel for DeepSeek V3 sparse attention indexer. // See persistent_topk.cuh for kernel implementation. #include <cuda_runtime.h> #include <algorithm> #include "ops.h" #include "torch_utils.h" #ifndef USE_ROCM #include "persistent_topk.cuh" #include "sampled_topk.cuh" #endif namespace { #ifnd...
--- csrc/libtorch_stable/topk.cu +++ csrc/libtorch_stable/topk.cu @@ -9,6 +9,7 @@ #ifndef USE_ROCM #include "persistent_topk.cuh" + #include "sampled_topk.cuh" #endif namespace { @@ -36,7 +37,22 @@ max_smem_per_block = device_prop->sharedMemPerBlockOptin; } - if (num_rows > 32 && max_smem_per_bloc...
17
1
2
[]
[]
[]
Optimize this cuda kernel file from vllm (csrc/libtorch_stable/topk.cu). Goal: [Perf][Kernel] Add sampled filtering for persistent top-k Target hardware: unspecified Target models: unspecified Current file: ```cuda // Persistent TopK kernel for DeepSeek V3 sparse attention indexer. // See persistent_topk.cuh for kern...
## Purpose Speed up long FP32 sparse-indexer decode top-k with sampling inspired by [DeepSelect](https://github.com/deepseek-ai/DeepSelect). A coalesced sample estimates a cutoff, survivors are compacted in shared memory, and exact FP32 selection finishes on those candidates. Too few or too many candidates trigger exa...
[{"scope": "e2e", "hardware": "B300", "model": "DeepSeek-V4-Flash-0731", "shape": "k=2048, valid_length=128K", "batch_size": 1024, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 316.58, "optimized": 207.06, "stated_speedup": null, "speedup": 1.5289}, {"scope": "e2e", "hardware": "B300", "mode...
null
1.733
vllm
dffbb714e4e8e4b95ccc888df98d47c7d2cef78d
2026-09-15T14:34:24-04:00
56,743
https://github.com/vllm-project/vllm/pull/56743
[ROCm][Perf] Optimize DSV4.1 K=512 decode top-k on gfx950 (#56743)
[ROCm][Perf] Optimize DSV4.1 K=512 decode top-k on gfx950 (#56743) Signed-off-by: fai <fangzhouai@gmail.com>
csrc/libtorch_stable/sampler.cu
cuda
Apache-2.0
#include "../cuda_compat.h" #include "dispatch_utils.h" #include "torch_utils.h" #include <cstring> #ifndef USE_ROCM #include <cub/cub.cuh> #else #include <hipcub/hipcub.hpp> #endif namespace vllm { template <typename scalar_t> __global__ void apply_repetition_penalties_kernel( scalar_t* __restrict__ logits...
#include "../cuda_compat.h" #include "dispatch_utils.h" #include "torch_utils.h" #include <cstring> #ifndef USE_ROCM #include <cub/cub.cuh> #else #include <hipcub/hipcub.hpp> #endif namespace vllm { template <typename scalar_t> __global__ void apply_repetition_penalties_kernel( scalar_t* __restrict__ logits...
--- csrc/libtorch_stable/sampler.cu +++ csrc/libtorch_stable/sampler.cu @@ -154,7 +154,8 @@ } template <int step, int kNumThreadsPerBlock, int kNumBins, int kNumFinalItems, - bool multipleBlocksPerRow, bool mergeBlocks, typename SmemFinalType, + bool multipleBlocksPerRow, bool mergeBlocks, + ...
205
58
2
[ "deepseek" ]
[ "GFX950", "ROCM" ]
[]
Optimize this cuda kernel file from vllm (csrc/libtorch_stable/sampler.cu). Goal: [ROCm][Perf] Optimize DSV4.1 K=512 decode top-k on gfx950 Target hardware: GFX950, ROCM Target models: deepseek Current file: ```cuda #include "../cuda_compat.h" #include "dispatch_utils.h" #include "torch_utils.h" #include <cstring> ...
## Purpose Part of #56506. DeepSeek-V4.1-Flash uses K=512 for decode indexer top-k, which misses the existing gfx950 tuning and falls back to the generic 10-split kernel. Add a ROCm/gfx950-only K=512 path for up to 384 rows and 1M columns. It selects active splits from device sequence lengths so FULL graph replay rem...
[{"scope": "e2e", "hardware": "gfx950", "model": "DeepSeek-V4.1", "shape": "K=512", "batch_size": null, "metric": "speedup", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 2.31, "speedup": 2.31}, {"scope": "e2e", "hardware": "gfx950", "model": "DeepSeek-V4.1", "shape": "K...
2.7607
2.067
vllm
dc2e8f1157173d0f0fc09712f6897e9f6eee52a0
2026-09-14T11:40:25+02:00
54,965
https://github.com/vllm-project/vllm/pull/54965
[ROCm][Perf] W4A16: keep skinny GEMM zero-points packed 4-bit (#54965)
[ROCm][Perf] W4A16: keep skinny GEMM zero-points packed 4-bit (#54965) Signed-off-by: Matthias Gehre <matthias.gehre@amd.com>
csrc/rocm/skinny_gemms_int4.cu
cuda
Apache-2.0
#include <torch/all.h> #include <ATen/cuda/CUDAContext.h> #include <c10/cuda/CUDAGuard.h> #include <cuda_runtime.h> #include <cuda_fp16.h> #include <cuda_bf16.h> #include <stdexcept> #include <algorithm> #include "../cuda_compat.h" #include "dispatch_utils.h" // Combined RDNA macro (gfx11 + gfx12) - both use 32-wid...
#include <torch/all.h> #include <ATen/cuda/CUDAContext.h> #include <c10/cuda/CUDAGuard.h> #include <cuda_runtime.h> #include <cuda_fp16.h> #include <cuda_bf16.h> #include <stdexcept> #include <algorithm> #include "../cuda_compat.h" #include "dispatch_utils.h" // Combined RDNA macro (gfx11 + gfx12) - both use 32-wid...
--- csrc/rocm/skinny_gemms_int4.cu +++ csrc/rocm/skinny_gemms_int4.cu @@ -100,6 +100,18 @@ __device__ inline unsigned int min__(uint32_t a, uint32_t b) { return min(a, b); +} + +// Reads row `row` of packed zero points [M/8, num_groups] uint32. +// +// The parameters must be signed and the indexing must use shift...
41
18
2
[]
[ "ROCM" ]
[]
Optimize this cuda kernel file from vllm (csrc/rocm/skinny_gemms_int4.cu). Goal: [ROCm][Perf] W4A16: keep skinny GEMM zero-points packed 4-bit Target hardware: ROCM Target models: unspecified Current file: ```cuda #include <torch/all.h> #include <ATen/cuda/CUDAContext.h> #include <c10/cuda/CUDAGuard.h> #include <cud...
## Purpose `RDNAHybridW4A16LinearKernel` expanded the asymmetric zero-points to the activation dtype at load time (e.g. bf16 instead of int4), costing 4x the DRAM traffic. This PR keeps them in the packed form (8x int4 inside an int32). ### Performance | Model | Metric | before | after | delta | | --- | --- | --- |...
[{"scope": "e2e", "hardware": null, "model": "cyankiwi/gemma-4-31B-it-AWQ-4bit", "shape": null, "batch_size": null, "metric": "Median TPOT", "unit": "ms", "higher_is_better": false, "baseline": 76.37, "optimized": 56.2, "stated_speedup": null, "speedup": 1.3589}, {"scope": "e2e", "hardware": null, "model": "cyankiwi/ge...
null
1.0404
vllm
dc2e8f1157173d0f0fc09712f6897e9f6eee52a0
2026-09-14T11:40:25+02:00
54,965
https://github.com/vllm-project/vllm/pull/54965
[ROCm][Perf] W4A16: keep skinny GEMM zero-points packed 4-bit (#54965)
[ROCm][Perf] W4A16: keep skinny GEMM zero-points packed 4-bit (#54965) Signed-off-by: Matthias Gehre <matthias.gehre@amd.com>
csrc/rocm/torch_bindings.cpp
cpp
Apache-2.0
#include "core/registration.h" #include "rocm/ops.h" // Note on op signatures: // The X_meta signatures are for the meta functions corresponding to op X. // They must be kept in sync with the signature for X. Generally, only // functions that return Tensors require a meta function. // // See the following links for de...
#include "core/registration.h" #include "rocm/ops.h" // Note on op signatures: // The X_meta signatures are for the meta functions corresponding to op X. // They must be kept in sync with the signature for X. Generally, only // functions that return Tensors require a meta function. // // See the following links for de...
--- csrc/rocm/torch_bindings.cpp +++ csrc/rocm/torch_bindings.cpp @@ -31,7 +31,8 @@ rocm_ops.impl("wvSplitK", torch::kCUDA, &wvSplitK); // W4A16 grouped skinny GEMM: packed int4 weights, per-group scales, - // optional zero points for asymmetric quantization + // optional zero points [M/8, K/group_size] int32...
2
1
2
[]
[ "ROCM" ]
[]
Optimize this cpp kernel file from vllm (csrc/rocm/torch_bindings.cpp). Goal: [ROCm][Perf] W4A16: keep skinny GEMM zero-points packed 4-bit Target hardware: ROCM Target models: unspecified Current file: ```cpp #include "core/registration.h" #include "rocm/ops.h" // Note on op signatures: // The X_meta signatures are...
## Purpose `RDNAHybridW4A16LinearKernel` expanded the asymmetric zero-points to the activation dtype at load time (e.g. bf16 instead of int4), costing 4x the DRAM traffic. This PR keeps them in the packed form (8x int4 inside an int32). ### Performance | Model | Metric | before | after | delta | | --- | --- | --- |...
[{"scope": "e2e", "hardware": null, "model": "cyankiwi/gemma-4-31B-it-AWQ-4bit", "shape": null, "batch_size": null, "metric": "Median TPOT", "unit": "ms", "higher_is_better": false, "baseline": 76.37, "optimized": 56.2, "stated_speedup": null, "speedup": 1.3589}, {"scope": "e2e", "hardware": null, "model": "cyankiwi/ge...
null
1.0404
vllm
238cb2b191630e8b02965adc772e3236d26936fe
2026-09-14T17:36:39+08:00
55,738
https://github.com/vllm-project/vllm/pull/55738
[Perf][GLM-5.3-Flash] Dense/masked-MHA sparse prefill for the NoPE (256, 0, 256) layout + skip the NoPE K concat (#55738)
[Perf][GLM-5.3-Flash] Dense/masked-MHA sparse prefill for the NoPE (256, 0, 256) layout + skip the NoPE K concat (#55738) Signed-off-by: Jared Wen <jaredwen@inferact.ai> Signed-off-by: Jared Wen <w13431838023@gmail.com> Co-authored-by: Claude Fable 5.1 <noreply@anthropic.com> Co-authored-by: mergify[bot] <37929162+mer...
vllm/model_executor/layers/attention/sparse_mla_attention.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Shared MHA implementation and metadata builder for sparse MLA backends.""" import math from dataclasses import dataclass from shutil import which from typing import TYPE_CHECKING, Any, ClassVar, Generic, TypeV...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Shared MHA implementation and metadata builder for sparse MLA backends.""" import math from dataclasses import dataclass from shutil import which from typing import TYPE_CHECKING, Any, ClassVar, Generic, TypeV...
--- vllm/model_executor/layers/attention/sparse_mla_attention.py +++ vllm/model_executor/layers/attention/sparse_mla_attention.py @@ -111,6 +111,8 @@ if model_dims not in ( (128, 512, 128, 64, 128), (64, 512, 192, 64, 256), + # GLM-5.3-Flash: NoPE, qk_head_dim 256 == the (192, 64, 256) ker...
2
0
3
[ "glm" ]
[]
[]
Optimize this triton kernel file from vllm (vllm/model_executor/layers/attention/sparse_mla_attention.py). Goal: [Perf][GLM-5.3-Flash] Dense/masked-MHA sparse prefill for the NoPE (256, 0, 256) layout + skip the NoPE K concat Target hardware: unspecified Target models: glm Current file: ```python # SPDX-License-Ident...
## Purpose One of three independent GLM-5.3-Flash perf PRs On main, GLM-5.3-Flash's MLA layout (qk_nope 256, qk_rope 0, v 256) is unknown to the FlashAttention prefill backend and to the masked-MHA allow-list, so `MLACommonImpl` logs `No MLA prefill backend supports this model` and **every prefill token goes through...
[{"scope": "e2e", "hardware": "4x GB300", "model": "GLM-5.3-Flash", "shape": "N=2048", "batch_size": 8, "metric": "TTFT", "unit": "ms", "higher_is_better": false, "baseline": 395, "optimized": 361, "stated_speedup": null, "speedup": 1.0942}, {"scope": "e2e", "hardware": "4x GB300", "model": "GLM-5.3-Flash", "shape": "N...
null
1.0143
vllm
78e84261ab2ffb691a8079d698d1f3f96ecb7635
2026-09-14T16:42:15+09:00
48,498
https://github.com/vllm-project/vllm/pull/48498
[Performance] Add Triton kernel for Gemma3n sparse GELU (#48498)
[Performance] Add Triton kernel for Gemma3n sparse GELU (#48498) Signed-off-by: BWAAEEEK <jooho414@gmail.com> Co-authored-by: Andreas Karatzas <akaratza@amd.com> Co-authored-by: Cyrus Leung <tlleungac@connect.ust.hk>
vllm/model_executor/layers/activation.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Custom activation functions.""" import math import torch import torch.nn as nn import torch.nn.functional as F from vllm.logger import init_logger from vllm.model_executor.custom_op import CustomOp from vllm...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Custom activation functions.""" import math import torch import torch.nn as nn import torch.nn.functional as F from vllm import ir from vllm.logger import init_logger from vllm.model_executor.custom_op impor...
--- vllm/model_executor/layers/activation.py +++ vllm/model_executor/layers/activation.py @@ -8,6 +8,7 @@ import torch.nn as nn import torch.nn.functional as F +from vllm import ir from vllm.logger import init_logger from vllm.model_executor.custom_op import CustomOp from vllm.platforms import CpuArchEnum, curre...
6
18
3
[ "gemma" ]
[]
[]
Optimize this triton kernel file from vllm (vllm/model_executor/layers/activation.py). Goal: [Performance] Add Triton kernel for Gemma3n sparse GELU Target hardware: unspecified Target models: gemma Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the v...
## Purpose This PR adds a dedicated Triton provider for Gemma3n's `gelu_and_mul_sparse` activation. The kernel fuses per-row mean and variance, Gaussian thresholding, tanh GELU, and gated multiplication, avoiding the multi-kernel native/Inductor path. It also: - registers `gelu_and_mul_sparse` with vLLM IR and route...
[{"scope": "kernel", "hardware": "A100", "model": null, "shape": null, "batch_size": null, "metric": "speedup", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 1.022, "speedup": 1.022}, {"scope": "kernel", "hardware": "B200", "model": null, "shape": null, "batch_size": nul...
2.49
1.0049
vllm
fa008bdccf10f2f31f84553112a227cf1b8947d7
2026-09-13T15:44:37+08:00
56,464
https://github.com/vllm-project/vllm/pull/56464
[Perf][Kernel] Integrate DeepSelect TopK for the DSA sparse indexer (#56464)
[Perf][Kernel] Integrate DeepSelect TopK for the DSA sparse indexer (#56464) Signed-off-by: zjy0516 <riverclouds.zhu@qq.com> Signed-off-by: Roger Wang <hey@rogerw.io> Co-authored-by: Kimi Code <noreply@moonshot.ai> Co-authored-by: Roger Wang <hey@rogerw.io>
vllm/model_executor/layers/sparse_attn_indexer.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Custom Sparse Attention Indexer layers.""" import torch import torch.distributed as dist import vllm.envs as envs from vllm import _custom_ops as ops from vllm._aiter_ops import rocm_aiter_ops from vllm.compi...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Custom Sparse Attention Indexer layers.""" import torch import torch.distributed as dist import vllm.envs as envs from vllm import _custom_ops as ops from vllm._aiter_ops import rocm_aiter_ops from vllm.compi...
--- vllm/model_executor/layers/sparse_attn_indexer.py +++ vllm/model_executor/layers/sparse_attn_indexer.py @@ -19,6 +19,10 @@ ) from vllm.model_executor.kernels.attention.dsa.candidate_blocks import ( select_candidate_blocks as _select_candidate_blocks, +) +from vllm.model_executor.layers.indexer_topk import ( ...
18
52
1
[ "kimi" ]
[]
[]
Optimize this triton kernel file from vllm (vllm/model_executor/layers/sparse_attn_indexer.py). Goal: [Perf][Kernel] Integrate DeepSelect TopK for the DSA sparse indexer Target hardware: unspecified Target models: kimi Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright c...
## What Integrate [DeepSeek DeepSelect](https://github.com/deepseek-ai/DeepSelect) (MIT) — a high-performance TopK kernel library for DeepSeek Sparse Attention — into vLLM via CMake FetchContent, and make **every** decode top-k implementation on the DSA sparse indexer path explicitly selectable, with a measured auto h...
[{"scope": "kernel", "hardware": "NVIDIA GB200", "model": "DeepSeek-V4.1-Flash", "shape": "bs=256,kv=1M", "batch_size": 256, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 616, "optimized": 191, "stated_speedup": null, "speedup": 3.2251}, {"scope": "kernel", "hardware": "NVIDIA GB200", "model...
2.3625
null
vllm
c2ea9f1a5f10caec36eac91c461fcec6564f5394
2026-09-12T23:27:08-04:00
56,478
https://github.com/vllm-project/vllm/pull/56478
[Kernel][Perf][Quantization] Fix odd-row performance cliff in per-token-group quantization (#56478)
[Kernel][Perf][Quantization] Fix odd-row performance cliff in per-token-group quantization (#56478) Signed-off-by: Ayushman Singh <ayush1399@users.noreply.github.com> Co-authored-by: Ayushman Singh <ayush1399@users.noreply.github.com>
csrc/libtorch_stable/quantization/w8a8/fp8/per_token_group_quant.cu
cuda
Apache-2.0
#include <torch/csrc/stable/tensor.h> #include <torch/csrc/stable/ops.h> #include <torch/headeronly/util/Exception.h> #include <torch/headeronly/core/ScalarType.h> #include "libtorch_stable/quantization/w8a8/per_token_group_quant_8bit.h" #include <cmath> #ifdef USE_ROCM #include <hip/hip_fp8.h> #else #include <c...
#include <torch/csrc/stable/tensor.h> #include <torch/csrc/stable/ops.h> #include <torch/headeronly/util/Exception.h> #include <torch/headeronly/core/ScalarType.h> #include "libtorch_stable/quantization/w8a8/per_token_group_quant_8bit.h" #include <cmath> #ifdef USE_ROCM #include <hip/hip_fp8.h> #else #include <c...
--- csrc/libtorch_stable/quantization/w8a8/fp8/per_token_group_quant.cu +++ csrc/libtorch_stable/quantization/w8a8/fp8/per_token_group_quant.cu @@ -96,7 +96,8 @@ } template <typename T, typename DST_DTYPE, bool IS_COLUMN_MAJOR = false, - bool SCALE_UE8M0 = false, typename scale_packed_t = float> + ...
91
61
1
[]
[]
[]
Optimize this cuda kernel file from vllm (csrc/libtorch_stable/quantization/w8a8/fp8/per_token_group_quant.cu). Goal: [Kernel][Perf][Quantization] Fix odd-row performance cliff in per-token-group quantization Target hardware: unspecified Target models: unspecified Current file: ```cuda #include <torch/csrc/stable/ten...
## Purpose Avoid the odd-row performance cliff in per-token-group 8-bit quantization while preserving the existing launch policy for even row counts. We identified this while investigating unexpectedly poor TPOT (time per output token) with Gemma 4 31B FP8 at TP8 on H100. The reproduction traced about 35 ms of extra ...
[{"scope": "kernel", "hardware": "H100", "model": null, "shape": "M=32767,K=128", "batch_size": 32767, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 41.76, "optimized": 10.45, "stated_speedup": null, "speedup": 3.9962}, {"scope": "kernel", "hardware": "H100", "model": null, "shape": "M=32767...
1.3332
null
vllm
13e221f8308416564a446909c2fd4805c78fbb8a
2026-09-12T07:20:04-07:00
56,562
https://github.com/vllm-project/vllm/pull/56562
[Perf] Fuse DSV4.1 input metadata preparation with Triton (#56562)
[Perf] Fuse DSV4.1 input metadata preparation with Triton (#56562)
vllm/v1/attention/backends/mla/indexer.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project from dataclasses import dataclass from typing import Any import torch import vllm.envs as envs from vllm.config import VllmConfig from vllm.distributed import get_dcp_group, get_pcp_group from vllm.logger import...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project from dataclasses import dataclass from typing import Any import torch import vllm.envs as envs from vllm.config import VllmConfig from vllm.distributed import get_dcp_group, get_pcp_group from vllm.logger import...
--- vllm/v1/attention/backends/mla/indexer.py +++ vllm/v1/attention/backends/mla/indexer.py @@ -960,28 +960,6 @@ self.global_decode_seq_lens_buffer[actual_expanded:num_decode_tokens] = 0 return self.global_decode_seq_lens_buffer[:num_decode_tokens] - def _build_varlen_decode_indices( - sel...
69
52
2
[ "deepseek" ]
[]
[]
Optimize this triton kernel file from vllm (vllm/v1/attention/backends/mla/indexer.py). Goal: [Perf] Fuse DSV4.1 input metadata preparation with Triton Target hardware: unspecified Target models: deepseek Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to...
## Purpose DSV4.1 prepares token-to-request mappings and flattened indexer decode metadata with chains of PyTorch operations on every model step. Replace those operations with Triton kernels that write directly into the existing buffers: - Build token-to-request mappings from device query boundaries, including zero-l...
[{"scope": "kernel", "hardware": "NVIDIA GB200", "model": "deepseek-ai/DeepSeek-V4.1-Flash", "shape": null, "batch_size": 16, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 168.29, "optimized": 118.21, "stated_speedup": 1.42, "speedup": 1.4237}, {"scope": "kernel", "hardware": "NVIDIA GB200",...
3.0415
1.0284
vllm
8a7f98c8c3ae409df6130995e364393ead5dbc24
2026-09-11T15:05:22-04:00
53,280
https://github.com/vllm-project/vllm/pull/53280
[Kernel][MoE] Optimize batched_moe_align_block_size with cooperative writes (#53280)
[Kernel][MoE] Optimize batched_moe_align_block_size with cooperative writes (#53280) Signed-off-by: mgoin <mgoin64@gmail.com>
csrc/libtorch_stable/moe/moe_align_sum_kernels.cu
cuda
Apache-2.0
#include <array> #include <cub/cub.cuh> #include <cuda_runtime.h> #include <torch/csrc/stable/macros.h> #include <torch/csrc/stable/accelerator.h> #include <torch/csrc/stable/ops.h> #include <torch/csrc/stable/tensor.h> #include <torch/headeronly/core/ScalarType.h> #include "../../cuda_compat.h" #include "libtorch_st...
#include <array> #include <cub/cub.cuh> #include <cuda_runtime.h> #include <torch/csrc/stable/macros.h> #include <torch/csrc/stable/accelerator.h> #include <torch/csrc/stable/ops.h> #include <torch/csrc/stable/tensor.h> #include <torch/headeronly/core/ScalarType.h> #include "../../cuda_compat.h" #include "libtorch_st...
--- csrc/libtorch_stable/moe/moe_align_sum_kernels.cu +++ csrc/libtorch_stable/moe/moe_align_sum_kernels.cu @@ -23,20 +23,18 @@ // Note num_threads needs to be 1024 for BlockScan Reduction in the kernel. static constexpr int32_t num_threads = 1024; static constexpr int32_t num_blocks = 1; +template <bool cooperative...
62
20
1
[]
[]
[]
Optimize this cuda kernel file from vllm (csrc/libtorch_stable/moe/moe_align_sum_kernels.cu). Goal: [Kernel][MoE] Optimize batched_moe_align_block_size with cooperative writes Target hardware: unspecified Target models: unspecified Current file: ```cuda #include <array> #include <cub/cub.cuh> #include <cuda_runtime....
## Summary - parallelize batched MoE token and block-ID output writes across cooperative thread groups - retain the original serial specialization for small capacities and high batch counts - expand correctness coverage and add a batched alignment benchmark matrix The production caller is currently `BatchedMarlinExpe...
[{"scope": "kernel", "hardware": "NVIDIA H200", "model": null, "shape": null, "batch_size": null, "metric": "speedup", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 1.1, "speedup": 1.1}, {"scope": "kernel", "hardware": "NVIDIA H200", "model": null, "shape": null, "batch_...
4.55
null
vllm
1e1060f9988fa188fd243c093610889594ba18fd
2026-09-11T11:16:57-04:00
55,356
https://github.com/vllm-project/vllm/pull/55356
[Kimi Perf] Group fp8 mla cahche insertion, 4~6x kernel level performance improvement for small batch (#55356)
[Kimi Perf] Group fp8 mla cahche insertion, 4~6x kernel level performance improvement for small batch (#55356) Signed-off-by: yewentao256 <zhyanwentao@126.com>
csrc/libtorch_stable/cache_kernels.cu
cuda
Apache-2.0
#include "torch_utils.h" #include "dispatch_utils.h" #include "../cuda_utils.h" #include "../cuda_compat.h" #include "quantization/vectorization_utils.cuh" #include "concat_mla_q.cuh" #if !defined(USE_ROCM) && defined(ENABLE_NVFP4_SM100) && ENABLE_NVFP4_SM100 #include "nvfp4_ds_mla_cache.h" #endif #ifdef USE_ROCM...
#include "torch_utils.h" #include "dispatch_utils.h" #include "../cuda_utils.h" #include "../cuda_compat.h" #include "quantization/vectorization_utils.cuh" #include "concat_mla_q.cuh" #if !defined(USE_ROCM) && defined(ENABLE_NVFP4_SM100) && ENABLE_NVFP4_SM100 #include "nvfp4_ds_mla_cache.h" #endif #ifdef USE_ROCM...
--- csrc/libtorch_stable/cache_kernels.cu +++ csrc/libtorch_stable/cache_kernels.cu @@ -456,14 +456,14 @@ // Grouped variant of concat_and_cache_mla: inserts the context K/V for every // draft layer in a single launch. Grid is (num_tokens, num_layers); each layer // reads its own cache base pointer from kv_cache_ptr...
92
25
3
[ "kimi" ]
[]
[ "6x" ]
Optimize this cuda kernel file from vllm (csrc/libtorch_stable/cache_kernels.cu). Goal: [Kimi Perf] Group fp8 mla cahche insertion, 4~6x kernel level performance improvement for small batch Target hardware: unspecified Target models: kimi Current file: ```cuda #include "torch_utils.h" #include "dispatch_utils.h" #in...
## Purpose Group fp8 mla cahche insertion Before: ```bash CUDA launch 1：layer 0 CUDA launch 2：layer 1 CUDA launch 3：layer 2 CUDA launch 4：layer 3 CUDA launch 5：layer 4 ``` Now ```bash One grouped kernel launch ├─ token 0, layer 0 ├─ token 0, layer 1 ├─ ... └─ ... ``` So basically combining 5 layers togeth...
[{"scope": "kernel", "hardware": null, "model": null, "shape": "tokens=1", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 101.38, "optimized": 15.91, "stated_speedup": 6.37, "speedup": 6.3721}, {"scope": "kernel", "hardware": null, "model": null, "shape": "tokens=2", "batch_s...
5.9679
null
vllm
1e1060f9988fa188fd243c093610889594ba18fd
2026-09-11T11:16:57-04:00
55,356
https://github.com/vllm-project/vllm/pull/55356
[Kimi Perf] Group fp8 mla cahche insertion, 4~6x kernel level performance improvement for small batch (#55356)
[Kimi Perf] Group fp8 mla cahche insertion, 4~6x kernel level performance improvement for small batch (#55356) Signed-off-by: yewentao256 <zhyanwentao@126.com>
csrc/libtorch_stable/ops.h
cpp
Apache-2.0
#pragma once #include <torch/csrc/stable/library.h> #include <torch/csrc/stable/tensor.h> #include <torch/headeronly/util/Exception.h> #include <optional> #include <string> #include <vector> #include <torch/csrc/stable/ops.h> inline torch::stable::Tensor weak_ref_tensor(torch::stable::Tensor& tensor) { // Ensure ...
#pragma once #include <torch/csrc/stable/library.h> #include <torch/csrc/stable/tensor.h> #include <torch/headeronly/util/Exception.h> #include <optional> #include <string> #include <vector> #include <torch/csrc/stable/ops.h> inline torch::stable::Tensor weak_ref_tensor(torch::stable::Tensor& tensor) { // Ensure ...
--- csrc/libtorch_stable/ops.h +++ csrc/libtorch_stable/ops.h @@ -654,12 +654,12 @@ const std::string& kv_cache_dtype, torch::stable::Tensor& scale); -void concat_and_cache_mla_grouped(torch::stable::Tensor& kv_c, - torch::stable::...
6
6
3
[ "kimi" ]
[]
[ "6x" ]
Optimize this cpp kernel file from vllm (csrc/libtorch_stable/ops.h). Goal: [Kimi Perf] Group fp8 mla cahche insertion, 4~6x kernel level performance improvement for small batch Target hardware: unspecified Target models: kimi Current file: ```cpp #pragma once #include <torch/csrc/stable/library.h> #include <torch/c...
## Purpose Group fp8 mla cahche insertion Before: ```bash CUDA launch 1：layer 0 CUDA launch 2：layer 1 CUDA launch 3：layer 2 CUDA launch 4：layer 3 CUDA launch 5：layer 4 ``` Now ```bash One grouped kernel launch ├─ token 0, layer 0 ├─ token 0, layer 1 ├─ ... └─ ... ``` So basically combining 5 layers togeth...
[{"scope": "kernel", "hardware": null, "model": null, "shape": "tokens=1", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 101.38, "optimized": 15.91, "stated_speedup": 6.37, "speedup": 6.3721}, {"scope": "kernel", "hardware": null, "model": null, "shape": "tokens=2", "batch_s...
5.9679
null
vllm
1e1060f9988fa188fd243c093610889594ba18fd
2026-09-11T11:16:57-04:00
55,356
https://github.com/vllm-project/vllm/pull/55356
[Kimi Perf] Group fp8 mla cahche insertion, 4~6x kernel level performance improvement for small batch (#55356)
[Kimi Perf] Group fp8 mla cahche insertion, 4~6x kernel level performance improvement for small batch (#55356) Signed-off-by: yewentao256 <zhyanwentao@126.com>
csrc/libtorch_stable/torch_bindings.cpp
cpp
Apache-2.0
#include "ops.h" #include "cuda_utils.h" #include "core/registration.h" #include <torch/csrc/stable/library.h> // Register ops with STABLE_TORCH_LIBRARY for libtorch stable ABI compatibility. // Note: We register under namespace "_C" so ops are accessible as // torch.ops._C.<op_name> for compatibility with existing c...
#include "ops.h" #include "cuda_utils.h" #include "core/registration.h" #include <torch/csrc/stable/library.h> // Register ops with STABLE_TORCH_LIBRARY for libtorch stable ABI compatibility. // Note: We register under namespace "_C" so ops are accessible as // torch.ops._C.<op_name> for compatibility with existing c...
--- csrc/libtorch_stable/torch_bindings.cpp +++ csrc/libtorch_stable/torch_bindings.cpp @@ -976,14 +976,16 @@ " str kv_cache_dtype," " Tensor scale) -> ()"); - // Grouped concat_and_cache_mla across all layers (bf16 only). Each - // layer's cache base pointer is...
5
3
3
[ "kimi" ]
[]
[ "6x" ]
Optimize this cpp kernel file from vllm (csrc/libtorch_stable/torch_bindings.cpp). Goal: [Kimi Perf] Group fp8 mla cahche insertion, 4~6x kernel level performance improvement for small batch Target hardware: unspecified Target models: kimi Current file: ```cpp #include "ops.h" #include "cuda_utils.h" #include "core/r...
## Purpose Group fp8 mla cahche insertion Before: ```bash CUDA launch 1：layer 0 CUDA launch 2：layer 1 CUDA launch 3：layer 2 CUDA launch 4：layer 3 CUDA launch 5：layer 4 ``` Now ```bash One grouped kernel launch ├─ token 0, layer 0 ├─ token 0, layer 1 ├─ ... └─ ... ``` So basically combining 5 layers togeth...
[{"scope": "kernel", "hardware": null, "model": null, "shape": "tokens=1", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 101.38, "optimized": 15.91, "stated_speedup": 6.37, "speedup": 6.3721}, {"scope": "kernel", "hardware": null, "model": null, "shape": "tokens=2", "batch_s...
5.9679
null
vllm
e3f755b732316df4db8437dcb973b9fa28bfd656
2026-09-11T09:21:14+01:00
55,352
https://github.com/vllm-project/vllm/pull/55352
[CPU] Speedup LM Head on Arm CPUs (#55352)
[CPU] Speedup LM Head on Arm CPUs (#55352) Signed-off-by: Fadi Arafeh <fadi.arafeh@arm.com> Co-authored-by: Li, Jiang <jiang1.li@intel.com>
csrc/cpu/dnnl_helper.cpp
cpp
Apache-2.0
#include <list> #include <optional> #include "common/memory_desc.hpp" #include "common/memory.hpp" #include "cpu/utils.hpp" #include "cpu/dnnl_helper.h" static dnnl::engine& default_engine() { static dnnl::engine engine(dnnl::engine::kind::cpu, 0); return engine; } static dnnl::stream& default_stream() { stat...
#include <list> #include <optional> #include "common/memory_desc.hpp" #include "common/memory.hpp" #include "cpu/utils.hpp" #include "cpu/dnnl_helper.h" static dnnl::engine& default_engine() { static dnnl::engine engine(dnnl::engine::kind::cpu, 0); return engine; } static dnnl::stream& default_stream() { stat...
--- csrc/cpu/dnnl_helper.cpp +++ csrc/cpu/dnnl_helper.cpp @@ -172,7 +172,8 @@ size_t operator()( const MatMulPrimitiveHandler::ClassMatmulCacheKey& val) const { return hash<dnnl_dim_t>()(val.b_n_size) ^ hash<dnnl_dim_t>()(val.b_k_size) ^ - hash<int>()(static_cast<int>(val.b_type)); + ...
7
4
3
[]
[ "CPU" ]
[]
Optimize this cpp kernel file from vllm (csrc/cpu/dnnl_helper.cpp). Goal: [CPU] Speedup LM Head on Arm CPUs Target hardware: CPU Target models: unspecified Current file: ```cpp #include <list> #include <optional> #include "common/memory_desc.hpp" #include "common/memory.hpp" #include "cpu/utils.hpp" #include "cpu/d...
## Purpose LM Head takes around 11-14% of runtime for quantized models These layers currently fallback to a sub-optimal kernel in ACL. The most optimal kernel only supports bf16 src and wei tensors with fp32 dst. We fix this by doing the oneDNN matmul with bf16:bf16:f32 problem desc on AArch64 for BF16 layers with ...
[]
null
null
vllm
e3f755b732316df4db8437dcb973b9fa28bfd656
2026-09-11T09:21:14+01:00
55,352
https://github.com/vllm-project/vllm/pull/55352
[CPU] Speedup LM Head on Arm CPUs (#55352)
[CPU] Speedup LM Head on Arm CPUs (#55352) Signed-off-by: Fadi Arafeh <fadi.arafeh@arm.com> Co-authored-by: Li, Jiang <jiang1.li@intel.com>
csrc/cpu/dnnl_helper.h
cpp
Apache-2.0
#ifndef DNNL_HELPER_H #define DNNL_HELPER_H #include <optional> #include <cassert> #include "oneapi/dnnl/dnnl.hpp" namespace c10 { struct BFloat16; struct Half; } // namespace c10 namespace dnnl { namespace impl { struct memory_storage_t; struct matmul_pd_t; struct matmul_desc_t; } // namespace impl } // namespa...
#ifndef DNNL_HELPER_H #define DNNL_HELPER_H #include <optional> #include <cassert> #include "oneapi/dnnl/dnnl.hpp" namespace c10 { struct BFloat16; struct Half; } // namespace c10 namespace dnnl { namespace impl { struct memory_storage_t; struct matmul_pd_t; struct matmul_desc_t; } // namespace impl } // namespa...
--- csrc/cpu/dnnl_helper.h +++ csrc/cpu/dnnl_helper.h @@ -176,6 +176,7 @@ dnnl_dim_t b_n_size; dnnl_dim_t b_k_size; dnnl::memory::data_type b_type; + dnnl::memory::data_type c_type; friend bool operator==(const ClassMatmulCacheKey& l, const ClassMatmulCacheKey& r); @...
3
0
3
[]
[ "CPU" ]
[]
Optimize this cpp kernel file from vllm (csrc/cpu/dnnl_helper.h). Goal: [CPU] Speedup LM Head on Arm CPUs Target hardware: CPU Target models: unspecified Current file: ```cpp #ifndef DNNL_HELPER_H #define DNNL_HELPER_H #include <optional> #include <cassert> #include "oneapi/dnnl/dnnl.hpp" namespace c10 { struct BF...
## Purpose LM Head takes around 11-14% of runtime for quantized models These layers currently fallback to a sub-optimal kernel in ACL. The most optimal kernel only supports bf16 src and wei tensors with fp32 dst. We fix this by doing the oneDNN matmul with bf16:bf16:f32 problem desc on AArch64 for BF16 layers with ...
[]
null
null
vllm
e3f755b732316df4db8437dcb973b9fa28bfd656
2026-09-11T09:21:14+01:00
55,352
https://github.com/vllm-project/vllm/pull/55352
[CPU] Speedup LM Head on Arm CPUs (#55352)
[CPU] Speedup LM Head on Arm CPUs (#55352) Signed-off-by: Fadi Arafeh <fadi.arafeh@arm.com> Co-authored-by: Li, Jiang <jiang1.li@intel.com>
csrc/cpu/dnnl_kernels.cpp
cpp
Apache-2.0
#include "cpu_types.hpp" #include "dnnl_helper.h" namespace { template <typename scalar_t> struct KernelVecType { using load_vec_type = void; using cvt_vec_type = void; }; template <> struct KernelVecType<float> { using load_vec_type = vec_op::FP32Vec16; using cvt_vec_type = vec_op::FP32Vec16; }; template <>...
#include "cpu_types.hpp" #include "dnnl_helper.h" namespace { template <typename scalar_t> struct KernelVecType { using load_vec_type = void; using cvt_vec_type = void; }; template <> struct KernelVecType<float> { using load_vec_type = vec_op::FP32Vec16; using cvt_vec_type = vec_op::FP32Vec16; }; template <>...
--- csrc/cpu/dnnl_kernels.cpp +++ csrc/cpu/dnnl_kernels.cpp @@ -513,6 +513,17 @@ args.ab_type = get_dnnl_type<scalar_t>(); }); +#ifdef VLLM_USE_ACL + // TODO(fadara01): this is a hot-fix, remove once problem is addressed in the + // AArch64 stack. hy...
27
3
3
[]
[ "CPU" ]
[]
Optimize this cpp kernel file from vllm (csrc/cpu/dnnl_kernels.cpp). Goal: [CPU] Speedup LM Head on Arm CPUs Target hardware: CPU Target models: unspecified Current file: ```cpp #include "cpu_types.hpp" #include "dnnl_helper.h" namespace { template <typename scalar_t> struct KernelVecType { using load_vec_type = v...
## Purpose LM Head takes around 11-14% of runtime for quantized models These layers currently fallback to a sub-optimal kernel in ACL. The most optimal kernel only supports bf16 src and wei tensors with fp32 dst. We fix this by doing the oneDNN matmul with bf16:bf16:f32 problem desc on AArch64 for BF16 layers with ...
[]
null
null
vllm
9163190dda009a310d8c175d63860ac7c671ca90
2026-09-10T15:14:22-07:00
56,098
https://github.com/vllm-project/vllm/pull/56098
[ROCm][Bugfix][Perf] Tune multi-stream shared experts use; wvSplitKrc fixes (#56098)
[ROCm][Bugfix][Perf] Tune multi-stream shared experts use; wvSplitKrc fixes (#56098) Signed-off-by: Matthew Wong <Matthew.Wong2@amd.com> Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
csrc/rocm/skinny_gemms.cu
cuda
Apache-2.0
#include <torch/all.h> #include <ATen/cuda/CUDAContext.h> #include <c10/cuda/CUDAGuard.h> #include <cuda_runtime.h> #include <cuda_fp16.h> #include <cuda_bf16.h> #include <stdexcept> #include <algorithm> #include "../cuda_compat.h" #include "dispatch_utils.h" #include "quantization/w8a8/fp8/common.cuh" #include "cor...
#include <torch/all.h> #include <ATen/cuda/CUDAContext.h> #include <c10/cuda/CUDAGuard.h> #include <cuda_runtime.h> #include <cuda_fp16.h> #include <cuda_bf16.h> #include <stdexcept> #include <algorithm> #include <map> #include <mutex> #include <utility> #include "../cuda_compat.h" #include "dispatch_utils.h" #inclu...
--- csrc/rocm/skinny_gemms.cu +++ csrc/rocm/skinny_gemms.cu @@ -8,11 +8,19 @@ #include <stdexcept> #include <algorithm> +#include <map> +#include <mutex> +#include <utility> #include "../cuda_compat.h" #include "dispatch_utils.h" #include "quantization/w8a8/fp8/common.cuh" #include "core/batch_invariant.hpp" ...
216
32
4
[]
[ "ROCM" ]
[]
Optimize this cuda kernel file from vllm (csrc/rocm/skinny_gemms.cu). Goal: [ROCm][Bugfix][Perf] Tune multi-stream shared experts use; wvSplitKrc fixes Target hardware: ROCM Target models: unspecified Current file: ```cuda #include <torch/all.h> #include <ATen/cuda/CUDAContext.h> #include <c10/cuda/CUDAGuard.h> #inc...
After https://github.com/vllm-project/vllm/pull/55099, multi-stream performance in ROCm has markedly improved and allows new use-cases. In particular, the regime in which multi-stream shared-experts decode (implemented in https://github.com/vllm-project/vllm/pull/52033) brings performance advantages has shifted. ## P...
[{"scope": "e2e", "hardware": "gfx950", "model": "Qwen3.5-35B-A3B", "shape": "ISL 1024 / OSL 256", "batch_size": 1, "metric": "throughput", "unit": "tok/s", "higher_is_better": true, "baseline": 158.0, "optimized": 177.4, "stated_speedup": 1.123, "speedup": 1.1228}, {"scope": "e2e", "hardware": "gfx950", "model": "Qwen...
null
1.045
vllm
6ee5bb0a0b3e32dd1a6d9fddb61b50905ccdd6e0
2026-09-10T08:43:00-07:00
54,889
https://github.com/vllm-project/vllm/pull/54889
[DCP][Kernel][Perf] Fuse the empty-shard LSE mask into the A2A pack kernel (#54889)
[DCP][Kernel][Perf] Fuse the empty-shard LSE mask into the A2A pack kernel (#54889) Signed-off-by: Rita Brugarolas Brufau <rita.brugarolasbrufau@amd.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
vllm/v1/attention/ops/dcp.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """MLA DCP collective selection and direct symmetric-memory implementations.""" from __future__ import annotations import functools from collections.abc import Callable from dataclasses import dataclass from typ...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """MLA DCP collective selection and direct symmetric-memory implementations.""" from __future__ import annotations import functools from collections.abc import Callable from dataclasses import dataclass from typ...
--- vllm/v1/attention/ops/dcp.py +++ vllm/v1/attention/ops/dcp.py @@ -45,13 +45,18 @@ # LSE/output combine -def mask_dcp_empty_shards_( - lse: torch.Tensor, +def _validate_dcp_empty_shard_args( seq_lens: torch.Tensor | None, query_start_loc: torch.Tensor | None, -) -> None: +) -> bool: + """Validat...
62
5
1
[]
[]
[]
Optimize this triton kernel file from vllm (vllm/v1/attention/ops/dcp.py). Goal: [DCP][Kernel][Perf] Fuse the empty-shard LSE mask into the A2A pack kernel Target hardware: unspecified Target models: unspecified Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contribu...
# [DCP][Kernel] Fuse the empty-shard LSE mask into the A2A pack kernel ## Purpose Under DCP, every MLA layer calls `mask_dcp_empty_shards_` (`vllm/v1/attention/ops/dcp.py`) immediately before packing the partial attention output and LSE for the all-to-all combine. It sets the LSE of rows whose request holds no local ...
[{"scope": "kernel", "hardware": "MI355X", "model": null, "shape": null, "batch_size": null, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 35.0, "optimized": 1.23, "stated_speedup": null, "speedup": 28.4553}, {"scope": "kernel", "hardware": "MI355X", "model": null, "shape": null, "batch_size...
14.6512
1.0211
vllm
9521c60bdc0ccd1264961c284c64f4873335aed1
2026-09-10T15:37:54+08:00
54,038
https://github.com/vllm-project/vllm/pull/54038
[ROCm][Perf] Kimi-K3 Fused kernels for KDA prefill reland (#54038)
[ROCm][Perf] Kimi-K3 Fused kernels for KDA prefill reland (#54038) Signed-off-by: kliuae <kuanfu.liu@embeddedllm.com> Signed-off-by: tjtanaa <tunjian.tan@embeddedllm.com> Signed-off-by: kliuae <17350011+kliuae@users.noreply.github.com> Co-authored-by: Claude <noreply@anthropic.com> Co-authored-by: TJian <tunjian.tan@e...
csrc/libtorch_stable/ops.h
cpp
Apache-2.0
#pragma once #include <torch/csrc/stable/library.h> #include <torch/csrc/stable/tensor.h> #include <torch/headeronly/util/Exception.h> #include <optional> #include <string> #include <vector> #include <torch/csrc/stable/ops.h> inline torch::stable::Tensor weak_ref_tensor(torch::stable::Tensor& tensor) { // Ensure ...
#pragma once #include <torch/csrc/stable/library.h> #include <torch/csrc/stable/tensor.h> #include <torch/headeronly/util/Exception.h> #include <optional> #include <string> #include <vector> #include <torch/csrc/stable/ops.h> inline torch::stable::Tensor weak_ref_tensor(torch::stable::Tensor& tensor) { // Ensure ...
--- csrc/libtorch_stable/ops.h +++ csrc/libtorch_stable/ops.h @@ -404,6 +404,39 @@ torch::stable::Tensor const& norm_weight, torch::stable::Tensor& out, double scale, double norm_eps, const std::string& output_gate_activation); +#endif + +#ifdef VLLM_ENABLE_FUSED_KDA_CHUNK +void fused_kda_prologue( + tor...
33
0
2
[ "kimi" ]
[ "ROCM" ]
[]
Optimize this cpp kernel file from vllm (csrc/libtorch_stable/ops.h). Goal: [ROCm][Perf] Kimi-K3 Fused kernels for KDA prefill reland Target hardware: ROCM Target models: kimi Current file: ```cpp #pragma once #include <torch/csrc/stable/library.h> #include <torch/csrc/stable/tensor.h> #include <torch/headeronly/uti...
## Purpose #52606 added a KDA prefill fusion path for ROCm's gfx950, but was reverted in #53294 as its builds failed on gfx90a. This PR adds back the fused path, and guards the kernel builds on gfx950. This PR also adds a few optimizations to further improve the prefill performance, achieving ~5% TTFT reduction comp...
[{"scope": "e2e", "hardware": "MI355X", "model": "moonshotai/Kimi-K3", "shape": "ISL=8192,OSL=1024", "batch_size": 8, "metric": "throughput", "unit": "tokens/s", "higher_is_better": true, "baseline": 2505.59, "optimized": 2526.15, "stated_speedup": null, "speedup": 1.0082}, {"scope": "e2e", "hardware": "MI355X", "model...
null
1.0242
vllm
9521c60bdc0ccd1264961c284c64f4873335aed1
2026-09-10T15:37:54+08:00
54,038
https://github.com/vllm-project/vllm/pull/54038
[ROCm][Perf] Kimi-K3 Fused kernels for KDA prefill reland (#54038)
[ROCm][Perf] Kimi-K3 Fused kernels for KDA prefill reland (#54038) Signed-off-by: kliuae <kuanfu.liu@embeddedllm.com> Signed-off-by: tjtanaa <tunjian.tan@embeddedllm.com> Signed-off-by: kliuae <17350011+kliuae@users.noreply.github.com> Co-authored-by: Claude <noreply@anthropic.com> Co-authored-by: TJian <tunjian.tan@e...
csrc/libtorch_stable/torch_bindings.cpp
cpp
Apache-2.0
#include "ops.h" #include "cuda_utils.h" #include "core/registration.h" #include <torch/csrc/stable/library.h> // Register ops with STABLE_TORCH_LIBRARY for libtorch stable ABI compatibility. // Note: We register under namespace "_C" so ops are accessible as // torch.ops._C.<op_name> for compatibility with existing c...
#include "ops.h" #include "cuda_utils.h" #include "core/registration.h" #include <torch/csrc/stable/library.h> // Register ops with STABLE_TORCH_LIBRARY for libtorch stable ABI compatibility. // Note: We register under namespace "_C" so ops are accessible as // torch.ops._C.<op_name> for compatibility with existing c...
--- csrc/libtorch_stable/torch_bindings.cpp +++ csrc/libtorch_stable/torch_bindings.cpp @@ -535,6 +535,26 @@ "Tensor! state, Tensor output_gate, Tensor norm_weight, Tensor! out, " "float scale, float norm_eps=1e-5, " "str output_gate_activation='silu') -> ()"); +#endif + +#ifdef VLLM_ENABLE_FUSED_K...
25
0
2
[ "kimi" ]
[ "ROCM" ]
[]
Optimize this cpp kernel file from vllm (csrc/libtorch_stable/torch_bindings.cpp). Goal: [ROCm][Perf] Kimi-K3 Fused kernels for KDA prefill reland Target hardware: ROCM Target models: kimi Current file: ```cpp #include "ops.h" #include "cuda_utils.h" #include "core/registration.h" #include <torch/csrc/stable/library...
## Purpose #52606 added a KDA prefill fusion path for ROCm's gfx950, but was reverted in #53294 as its builds failed on gfx90a. This PR adds back the fused path, and guards the kernel builds on gfx950. This PR also adds a few optimizations to further improve the prefill performance, achieving ~5% TTFT reduction comp...
[{"scope": "e2e", "hardware": "MI355X", "model": "moonshotai/Kimi-K3", "shape": "ISL=8192,OSL=1024", "batch_size": 8, "metric": "throughput", "unit": "tokens/s", "higher_is_better": true, "baseline": 2505.59, "optimized": 2526.15, "stated_speedup": null, "speedup": 1.0082}, {"scope": "e2e", "hardware": "MI355X", "model...
null
1.0242
vllm
7e917606504f48f22491eb9d04ce50c28618d45f
2026-09-09T23:39:12-07:00
54,855
https://github.com/vllm-project/vllm/pull/54855
[ROCm][Perf] Route large DSV4 sparse prefill to AITER OPUS (#54855)
[ROCm][Perf] Route large DSV4 sparse prefill to AITER OPUS (#54855) Signed-off-by: jiacao-amd <jiahui.cao@amd.com> Co-authored-by: OpenAI Codex <codex@openai.com> Co-authored-by: Claude <noreply@anthropic.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
vllm/v1/attention/ops/rocm_aiter_mla_sparse.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project import functools import importlib import math from collections.abc import Callable from importlib.util import find_spec import torch import torch.nn.functional as F import vllm.envs as envs from vllm.compilation...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project import functools import importlib import math from collections.abc import Callable from importlib.util import find_spec import torch import torch.nn.functional as F import vllm.envs as envs from vllm.compilation...
--- vllm/v1/attention/ops/rocm_aiter_mla_sparse.py +++ vllm/v1/attention/ops/rocm_aiter_mla_sparse.py @@ -13,6 +13,7 @@ from vllm.compilation.breakable_cudagraph import eager_break_during_capture from vllm.config import CUDAGraphMode from vllm.forward_context import get_forward_context +from vllm.logger import init_...
107
0
1
[ "deepseek" ]
[ "ROCM" ]
[]
Optimize this triton kernel file from vllm (vllm/v1/attention/ops/rocm_aiter_mla_sparse.py). Goal: [ROCm][Perf] Route large DSV4 sparse prefill to AITER OPUS Target hardware: ROCM Target models: deepseek Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to ...
## Purpose Route eligible large DeepSeek V4 sparse-MLA prefill calls on gfx950 to AITER's `pa_sparse_prefill_opus` kernel while keeping the existing Triton implementations as the fallback. ### End-to-end throughput(8k/1k) | Max concurrency | Baseline total tok/s | OPUS total tok/s | Gain | |---:|---:|---:|---:| | 1 ...
[{"scope": "e2e", "hardware": "AMD Instinct MI355X", "model": "DeepSeek-V4-Pro FP4", "shape": "8k/1k", "batch_size": 1, "metric": "throughput", "unit": "tok/s", "higher_is_better": true, "baseline": 797.73, "optimized": 864.7, "stated_speedup": 1.084, "speedup": 1.084}, {"scope": "e2e", "hardware": "AMD Instinct MI355X...
null
1.0255
vllm
cc4210f6719e3285fdfe4da862ae04c8dbb77ab1
2026-09-09T22:33:12+08:00
55,899
https://github.com/vllm-project/vllm/pull/55899
[Perf] Improve BF16x3 router GEMM accuracy and make it default on sm100 (#55899)
[Perf] Improve BF16x3 router GEMM accuracy and make it default on sm100 (#55899) Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg> Co-authored-by: OpenAI Codex <noreply@openai.com> Co-authored-by: Jee Jee Li <pandaleefree@gmail.com>
vllm/model_executor/layers/fused_moe/router/bf16x3_router_gemm_cutedsl.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """CuteDSL BF16x3 router GEMM. Computes ``X @ W.T`` for BF16 ``X`` with shape ``[N, K]`` and FP32 router weights ``W`` with shape ``[M, K]`` by decomposing each FP32 weight value into three BF16 residual terms in...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """CuteDSL BF16x3 router GEMM. Computes ``X @ W.T`` for BF16 ``X`` with shape ``[N, K]`` and FP32 router weights ``W`` with shape ``[M, K]`` by decomposing each FP32 weight value into three BF16 residual terms in...
--- vllm/model_executor/layers/fused_moe/router/bf16x3_router_gemm_cutedsl.py +++ vllm/model_executor/layers/fused_moe/router/bf16x3_router_gemm_cutedsl.py @@ -6,6 +6,10 @@ weights ``W`` with shape ``[M, K]`` by decomposing each FP32 weight value into three BF16 residual terms inside the kernel, then accumulating the...
257
64
2
[]
[ "SM100" ]
[]
Optimize this triton kernel file from vllm (vllm/model_executor/layers/fused_moe/router/bf16x3_router_gemm_cutedsl.py). Goal: [Perf] Improve BF16x3 router GEMM accuracy and make it default on sm100 Target hardware: SM100 Target models: unspecified Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-F...
## Purpose Follow up on #47973. This only concerns router GEMM with FP32 weights i.e. BF16xFP32->FP32 This PR adds master rmem accumulator for long accumulation chain, restoring accuracy against FP32, hence making BF16x3 GEMM suitable as FP32 GEMM replacement whenever the kernel is supported (sm100 family). Custom op...
[{"scope": "kernel", "hardware": "GB300", "model": "Minimax M3", "shape": "hidden_size=6144, num_experts=128", "batch_size": 64, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 9.41, "optimized": 8.1, "stated_speedup": null, "speedup": 1.1617}, {"scope": "kernel", "hardware": "GB300", "model":...
1.0247
null
vllm
1b2c591cd0c3bb5a85ac7f3d6cbaa2fa7df6bc7d
2026-09-08T10:25:42-07:00
55,031
https://github.com/vllm-project/vllm/pull/55031
[Bugfix] speedup nvfp4 kv for FMHA (#55031)
[Bugfix] speedup nvfp4 kv for FMHA (#55031) Signed-off-by: Shiyang Chen <shiychen@nvidia.com> Co-authored-by: Cyrus Leung <tlleungac@connect.ust.hk>
vllm/v1/attention/backends/flashinfer.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Attention layer with FlashInfer.""" from dataclasses import dataclass, replace from enum import Enum from functools import partial from typing import ClassVar import numpy as np import torch from flashinfer i...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Attention layer with FlashInfer.""" from dataclasses import dataclass, replace from enum import Enum from functools import partial from typing import ClassVar import numpy as np import torch from flashinfer i...
--- vllm/v1/attention/backends/flashinfer.py +++ vllm/v1/attention/backends/flashinfer.py @@ -1884,6 +1884,14 @@ return self.cache_config.get_resolved_kv_cache_layout() def fused_output_quant_supported(self, quant_key: QuantKey): + if quant_key == kNvfp4Dynamic and self.is_kvcache_nvfp4: + ...
12
4
1
[]
[]
[]
Optimize this triton kernel file from vllm (vllm/v1/attention/backends/flashinfer.py). Goal: [Bugfix] speedup nvfp4 kv for FMHA Target hardware: unspecified Target models: unspecified Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """...
Do not do type conversion inside copy_. Guard NVFP4 output fusion when the KV cache is NVFP4. Usage: ``` vllm serve <model> --kv-cache-dtype nvfp4 \ --compilation-config '{"pass_config": {"fuse_attn_quant": true}}' ``` AttnQuantFusionPass fuses the attention output quant so the trtllm-gen FMHA writes FP8/NVFP4...
[{"scope": "e2e", "hardware": null, "model": "Qwen3-32B", "shape": "64 Q / 8 KV heads, head_dim=128, KV block size=32", "batch_size": 4, "metric": "latency", "unit": "ms", "higher_is_better": false, "baseline": 390.8, "optimized": 362.6, "stated_speedup": null, "speedup": 1.0778}, {"scope": "e2e", "hardware": null, "mo...
null
1.1022
vllm
f6326f53bda46898a331c2d24500332c285d9a2b
2026-09-08T14:26:03+02:00
55,715
https://github.com/vllm-project/vllm/pull/55715
[Perf][GDN] Enable the FlashInfer GDN prefill kernel on SM12x (#55715)
[Perf][GDN] Enable the FlashInfer GDN prefill kernel on SM12x (#55715) Signed-off-by: Stefano Castagnetta <scastagnetta@nvidia.com>
vllm/model_executor/layers/mamba/gdn/qwen_gdn_linear_attn.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Inference-only Qwen3-Next/Qwen3.5 model.""" import os from typing import Literal import torch from einops import rearrange from torch import nn from vllm import _custom_ops as ops from vllm import envs from ...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Inference-only Qwen3-Next/Qwen3.5 model.""" import os from typing import Literal import torch from einops import rearrange from torch import nn from vllm import _custom_ops as ops from vllm import envs from ...
--- vllm/model_executor/layers/mamba/gdn/qwen_gdn_linear_attn.py +++ vllm/model_executor/layers/mamba/gdn/qwen_gdn_linear_attn.py @@ -100,8 +100,9 @@ * ``requested in ["flashinfer", "auto"]``; * ``platform == cuda``; * one of the following: - - Hopper (SM90) — no further constraints; - - Blackw...
10
2
1
[ "qwen", "mamba" ]
[]
[]
Optimize this triton kernel file from vllm (vllm/model_executor/layers/mamba/gdn/qwen_gdn_linear_attn.py). Goal: [Perf][GDN] Enable the FlashInfer GDN prefill kernel on SM12x Target hardware: unspecified Target models: qwen, mamba Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText:...
## Purpose FlashInfer's GDN prefill kernel is never used on SM12x, so consumer and SoC Blackwell (RTX PRO 6000, RTX 5090, DGX Spark GB10) silently runs the Triton/FLA fallback for every linear-attention layer. On Qwen3.5/3.6/3.8 that is 3 of every 4 layers. `_resolve_gdn_prefill_backend()` only sets `supports_flashin...
[{"scope": "kernel", "hardware": "DGX Spark GB10", "model": "Qwen3.8-27B", "shape": "seqlen=1024,linear_num_key_heads=16,linear_num_value_heads=48,linear_key_head_dim=128", "batch_size": null, "metric": "latency", "unit": "ms", "higher_is_better": false, "baseline": 1.166, "optimized": 0.305, "stated_speedup": 3.83, "s...
4.2191
1.0596
vllm
25047604fe5518ecb99929edc3fe2f5e76bc9f4a
2026-09-08T19:58:26+08:00
55,808
https://github.com/vllm-project/vllm/pull/55808
[ROCm][Perf] Remove AITER paged-MQA outputs guard for DeepSeek-V4 (#55808)
[ROCm][Perf] Remove AITER paged-MQA outputs guard for DeepSeek-V4 (#55808) Signed-off-by: Shanshan Shen <87969357+shen-shanshan@users.noreply.github.com>
vllm/v1/attention/ops/rocm_aiter_mla_sparse.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project import functools import importlib import math from collections.abc import Callable from importlib.util import find_spec import torch import torch.nn.functional as F import vllm.envs as envs from vllm.compilation...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project import functools import importlib import math from collections.abc import Callable from importlib.util import find_spec import torch import torch.nn.functional as F import vllm.envs as envs from vllm.compilation...
--- vllm/v1/attention/ops/rocm_aiter_mla_sparse.py +++ vllm/v1/attention/ops/rocm_aiter_mla_sparse.py @@ -657,7 +657,6 @@ KVBlockSize=block_size, WavePerEU=2, ) - out_logits.nan_to_num_(float("-inf")) return out_logits deepgemm_fp8_paged_mq...
0
1
1
[ "deepseek" ]
[ "ROCM" ]
[]
Optimize this triton kernel file from vllm (vllm/v1/attention/ops/rocm_aiter_mla_sparse.py). Goal: [ROCm][Perf] Remove AITER paged-MQA outputs guard for DeepSeek-V4 Target hardware: ROCM Target models: deepseek Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contribut...
## Purpose To fix https://github.com/Fangzhou-Ai/vllm/issues/13, https://github.com/vllm-project/vllm/pull/49714 added an additional element-wise kernel after `deepgemm_fp8_paged_mqa_logits`, which could introduce costs. <img width="1909" height="310" alt="Snipaste_2026-09-08_14-14-51" src="https://github.com/user-at...
[{"scope": "e2e", "hardware": null, "model": "DeepSeek-V4", "shape": null, "batch_size": 1, "metric": "output token throughput", "unit": "tok/s", "higher_is_better": true, "baseline": 62.04, "optimized": 62.03, "stated_speedup": null, "speedup": 0.9998}, {"scope": "e2e", "hardware": null, "model": "DeepSeek-V4", "shape...
null
1.0041
vllm
8277c42e4c74c5dd604f29b6d938a3456658f247
2026-09-04T17:17:01-07:00
55,202
https://github.com/vllm-project/vllm/pull/55202
[Perf] Ensure async h2d copies are pinned in more places (#55202)
[Perf] Ensure async h2d copies are pinned in more places (#55202)
vllm/v1/attention/backends/flashinfer.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Attention layer with FlashInfer.""" from dataclasses import dataclass, replace from enum import Enum from functools import partial from typing import ClassVar import numpy as np import torch from flashinfer i...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Attention layer with FlashInfer.""" from dataclasses import dataclass, replace from enum import Enum from functools import partial from typing import ClassVar import numpy as np import torch from flashinfer i...
--- vllm/v1/attention/backends/flashinfer.py +++ vllm/v1/attention/backends/flashinfer.py @@ -15,6 +15,7 @@ BatchPrefillWithPagedKVCacheWrapper, BatchPrefillWithRaggedKVCacheWrapper, MultiLevelCascadeAttentionWrapper, + get_seq_lens, ) from flashinfer.decode import fast_decode_plan, trtllm_batch_dec...
34
1
5
[]
[]
[]
Optimize this triton kernel file from vllm (vllm/v1/attention/backends/flashinfer.py). Goal: [Perf] Ensure async h2d copies are pinned in more places Target hardware: unspecified Target models: unspecified Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors t...
Follow-on from https://github.com/vllm-project/vllm/pull/54660. Address more places where async h2d copies are made from paged memory CPU tensors, which could cause a stall harming cpu/gpu overlap, which were exposed via https://github.com/vllm-project/vllm/pull/53491.
[]
null
null
vllm
8277c42e4c74c5dd604f29b6d938a3456658f247
2026-09-04T17:17:01-07:00
55,202
https://github.com/vllm-project/vllm/pull/55202
[Perf] Ensure async h2d copies are pinned in more places (#55202)
[Perf] Ensure async h2d copies are pinned in more places (#55202)
vllm/v1/attention/backends/rocm_aiter_fa.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Attention layer with AiterFlashAttention.""" from dataclasses import dataclass, replace from typing import ClassVar import torch from vllm._aiter_ops import rocm_aiter_ops from vllm.config import ( VllmC...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Attention layer with AiterFlashAttention.""" from dataclasses import dataclass, replace from typing import ClassVar import torch from vllm._aiter_ops import rocm_aiter_ops from vllm.config import ( VllmC...
--- vllm/v1/attention/backends/rocm_aiter_fa.py +++ vllm/v1/attention/backends/rocm_aiter_fa.py @@ -21,7 +21,11 @@ from vllm.utils.gpu_sync_debug import gpu_sync_allowed from vllm.utils.math_utils import cdiv from vllm.utils.platform_utils import num_compute_units -from vllm.utils.torch_utils import get_dtype_size, ...
10
5
5
[]
[]
[]
Optimize this triton kernel file from vllm (vllm/v1/attention/backends/rocm_aiter_fa.py). Goal: [Perf] Ensure async h2d copies are pinned in more places Target hardware: unspecified Target models: unspecified Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributor...
Follow-on from https://github.com/vllm-project/vllm/pull/54660. Address more places where async h2d copies are made from paged memory CPU tensors, which could cause a stall harming cpu/gpu overlap, which were exposed via https://github.com/vllm-project/vllm/pull/53491.
[]
null
null
vllm
9509fc8ae61a8eb871a984e759a6d228c930df80
2026-09-03T15:39:58-07:00
54,896
https://github.com/vllm-project/vllm/pull/54896
[Perf][Kimi-K3] Cut MLA decode concat/cache epilogue latency (#54896)
[Perf][Kimi-K3] Cut MLA decode concat/cache epilogue latency (#54896) Signed-off-by: Yongye Zhu <zyy1102000@gmail.com> Co-authored-by: Claude Fable 5 <noreply@anthropic.com>
csrc/libtorch_stable/fused_kimi_k3_mla_key_concat_kv_cache_kernel.cu
cuda
Apache-2.0
/* * SPDX-License-Identifier: Apache-2.0 * SPDX-FileCopyrightText: Copyright contributors to the vLLM project * * Fused Kimi-K3 MLA prefill + decode epilogues with optional RoPE. * * Prefill: runs after the q_b_proj / kv_b_proj GEMMs, one launch per token * slice. Decode: runs after BMM1 (q_nope x W_UK) right be...
/* * SPDX-License-Identifier: Apache-2.0 * SPDX-FileCopyrightText: Copyright contributors to the vLLM project * * Fused Kimi-K3 MLA prefill + decode epilogues with optional RoPE. * * Prefill: runs after the q_b_proj / kv_b_proj GEMMs, one launch per token * slice. Decode: runs after BMM1 (q_nope x W_UK) right be...
--- csrc/libtorch_stable/fused_kimi_k3_mla_key_concat_kv_cache_kernel.cu +++ csrc/libtorch_stable/fused_kimi_k3_mla_key_concat_kv_cache_kernel.cu @@ -102,6 +102,9 @@ constexpr int kVHeadDim = 128; // V constexpr int kCacheEntry = kKvLoraRank + kQkRopeHeadDim; // 576 constexpr int kVe...
98
36
1
[ "kimi" ]
[]
[]
Optimize this cuda kernel file from vllm (csrc/libtorch_stable/fused_kimi_k3_mla_key_concat_kv_cache_kernel.cu). Goal: [Perf][Kimi-K3] Cut MLA decode concat/cache epilogue latency Target hardware: unspecified Target models: kimi Current file: ```cuda /* * SPDX-License-Identifier: Apache-2.0 * SPDX-FileCopyrightText...
## Purpose Reduce the latency of the fused Kimi-K3 MLA decode q-concat + latent cache insert kernel, which sits between the absorbed-q BMM and the decode FMHA on every full-attention layer. Three changes, all inside `fused_kimi_k3_mla_key_concat_kv_cache_kernel.cu`: 1. **Warps-per-row split, chosen from the token co...
[{"scope": "kernel", "hardware": "B300", "model": "Kimi-K3", "shape": null, "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 2.95, "optimized": 2.06, "stated_speedup": null, "speedup": 1.432}, {"scope": "e2e", "hardware": "B300", "model": "Kimi-K3", "shape": null, "batch_size":...
1.432
1.004
vllm
a56654d6de060495ff2db3b1d9ff0b187084d1a9
2026-09-02T15:22:40-04:00
54,565
https://github.com/vllm-project/vllm/pull/54565
[K3 Perf] Enable DSV3 GEMM for inner-contiguous and row-strided tensors, 12%~81% kernel performance improvement (#54565)
[K3 Perf] Enable DSV3 GEMM for inner-contiguous and row-strided tensors, 12%~81% kernel performance improvement (#54565) Signed-off-by: yewentao256 <zhyanwentao@126.com>
csrc/libtorch_stable/dsv3_fused_a_gemm.cu
cuda
Apache-2.0
/* * Adapted from * https://github.com/sgl-project/sglang/blob/main/sgl-kernel/csrc/gemm/dsv3_fused_a_gemm.cu * which was adapted from * https://github.com/NVIDIA/TensorRT-LLM/blob/619709fc33bd5dc268f19d6a741fe7ed51c0f8f5/cpp/tensorrt_llm/kernels/dsv3MinLatencyKernels/dsv3FusedAGemm.cu * * Copyright (c) 2019-2024...
/* * Adapted from * https://github.com/sgl-project/sglang/blob/main/sgl-kernel/csrc/gemm/dsv3_fused_a_gemm.cu * which was adapted from * https://github.com/NVIDIA/TensorRT-LLM/blob/619709fc33bd5dc268f19d6a741fe7ed51c0f8f5/cpp/tensorrt_llm/kernels/dsv3MinLatencyKernels/dsv3FusedAGemm.cu * * Copyright (c) 2019-2024...
--- csrc/libtorch_stable/dsv3_fused_a_gemm.cu +++ csrc/libtorch_stable/dsv3_fused_a_gemm.cu @@ -326,7 +326,7 @@ #endif } - __device__ void issue_mainloop() { + __device__ void issue_mainloop(int row_stride) { #if defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 900 cudaGridDependencySynchronize(); #pragma un...
35
27
1
[ "deepseek" ]
[]
[]
Optimize this cuda kernel file from vllm (csrc/libtorch_stable/dsv3_fused_a_gemm.cu). Goal: [K3 Perf] Enable DSV3 GEMM for inner-contiguous and row-strided tensors, 12%~81% kernel performance improvement Target hardware: unspecified Target models: deepseek Current file: ```cuda /* * Adapted from * https://github.co...
## Summary Enable DSV3 GEMM for inner-contiguous and row-strided tensors They previously fell back to `F.linear`/NVJet because they were not fully contiguous. This PR fixes the issue ## Test Acc covered in unit test Perf can be seen in this AI generated script ```py import torch import torch.nn.functional as F ...
[{"scope": "kernel", "hardware": "NVIDIA B300 SXM6 AC", "model": null, "shape": "M=1,N=1536,K=128,row_width=6288,offset=6144", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 2.129, "optimized": 1.116, "stated_speedup": null, "speedup": 1.9077}, {"scope": "kernel", "hardware":...
1.8106
null
vllm
a566ea7e8f5975b4d38c0092d7adb0acbda3a890
2026-09-01T20:37:09-07:00
54,660
https://github.com/vllm-project/vllm/pull/54660
[Perf] Avoid more h2d copies from non-pinned tensors (#54660)
[Perf] Avoid more h2d copies from non-pinned tensors (#54660) Signed-off-by: Nick Hill <nickhill123@gmail.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
vllm/v1/attention/backends/flashinfer.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Attention layer with FlashInfer.""" from dataclasses import dataclass, replace from enum import Enum from functools import partial from typing import ClassVar import numpy as np import torch from flashinfer i...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Attention layer with FlashInfer.""" from dataclasses import dataclass, replace from enum import Enum from functools import partial from typing import ClassVar import numpy as np import torch from flashinfer i...
--- vllm/v1/attention/backends/flashinfer.py +++ vllm/v1/attention/backends/flashinfer.py @@ -1569,6 +1569,17 @@ prefill_start : num_reqs + 1 ] assert paged_kv_indptr_prefill_cpu.shape[0] == num_prefills + 1 + # plan() copies these to the GPU with no...
23
4
1
[]
[]
[]
Optimize this triton kernel file from vllm (vllm/v1/attention/backends/flashinfer.py). Goal: [Perf] Avoid more h2d copies from non-pinned tensors Target hardware: unspecified Target models: unspecified Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to th...
Follow-on from https://github.com/vllm-project/vllm/pull/54299. Address more places where async h2d copies are made from paged memory CPU tensors, which could cause a stall harming cpu/gpu overlap, which were exposed via https://github.com/vllm-project/vllm/pull/53491.
[]
null
null
vllm
514c7314a06be9e43d00d3f126a5aaa54211274f
2026-09-01T18:49:07+02:00
53,568
https://github.com/vllm-project/vllm/pull/53568
[Perf][Kernel] Initialize NVFP4 padding in quant kernel (#53568)
[Perf][Kernel] Initialize NVFP4 padding in quant kernel (#53568) Signed-off-by: LopezCastroRoberto <rocastro@redhat.com> Co-authored-by: Codex <codex@openai.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
csrc/libtorch_stable/quantization/fp4/nvfp4_quant_kernels.cu
cuda
Apache-2.0
/* * Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless requi...
/* * Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless requi...
--- csrc/libtorch_stable/quantization/fp4/nvfp4_quant_kernels.cu +++ csrc/libtorch_stable/quantization/fp4/nvfp4_quant_kernels.cu @@ -36,7 +36,7 @@ namespace vllm { // Use UE4M3 by default. -template <class Type, bool UE8M0_SF = false> +template <class Type, bool UE8M0_SF = false, bool PADDED_OUTPUT = false> __glo...
49
20
1
[]
[]
[]
Optimize this cuda kernel file from vllm (csrc/libtorch_stable/quantization/fp4/nvfp4_quant_kernels.cu). Goal: [Perf][Kernel] Initialize NVFP4 padding in quant kernel Target hardware: unspecified Target models: unspecified Current file: ```cuda /* * Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved. * *...
## Purpose Follow-up to #49775 and #45739. #45739 used a separate `torch.zeros` allocation to initialize padded NVFP4 scales. This PR moves the required initialization into the CUDA quantization kernel, allowing the wrapper to safely use `torch.empty` and avoid the extra zero-fill launch. It also: - Preserves a spe...
[{"scope": "kernel", "hardware": "NVIDIA B300", "model": "Llama 3.3 70B", "shape": "N=8192,K=28672", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 3.133, "optimized": 1.912, "stated_speedup": 1.639, "speedup": 1.6386}, {"scope": "kernel", "hardware": "NVIDIA B300", "model": ...
1.2308
null
vllm
d6d665854314f0aa90ad6ef32a3382136c71314c
2026-08-31T16:18:12-07:00
54,261
https://github.com/vllm-project/vllm/pull/54261
[Kimi-K3][Perf] Make native CUDA AttnRes the SM100 default (#54261)
[Kimi-K3][Perf] Make native CUDA AttnRes the SM100 default (#54261) Signed-off-by: Yongye Zhu <zyy1102000@gmail.com>
csrc/libtorch_stable/kimi_k3/attn_res_kernel.cu
cuda
Apache-2.0
/* * Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved. */ // Production AttnRes forward for Blackwell (SM100). // // Warp-specialized online softmax + residual + RMSNorm: // - 1 producer warp issues cp.async.bulk row loads into shared memory. // - 8 consumer warps compute reductions and output. // -...
/* * Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved. */ // Production AttnRes forward for Blackwell (SM100). // // Warp-specialized online softmax + residual + RMSNorm: // - 1 producer warp issues cp.async.bulk row loads into shared memory. // - 8 consumer warps compute reductions and output. // -...
--- csrc/libtorch_stable/kimi_k3/attn_res_kernel.cu +++ csrc/libtorch_stable/kimi_k3/attn_res_kernel.cu @@ -10,7 +10,7 @@ // - Q=res_weight*rms_weight remains in registers across persistent tokens. // - V rows are converted once and cached as FP32 in TMEM between passes. // -// Integration contract: Kimi K3 H=71...
104
77
3
[ "kimi" ]
[ "SM100" ]
[]
Optimize this cuda kernel file from vllm (csrc/libtorch_stable/kimi_k3/attn_res_kernel.cu). Goal: [Kimi-K3][Perf] Make native CUDA AttnRes the SM100 default Target hardware: SM100 Target models: kimi Current file: ```cuda /* * Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved. */ // Production AttnRes fo...
## Purpose Make the native CUDA Kimi-K3 AttnRes implementation the default for dense `hidden_size=7168` inputs on SM100. This PR: - extends the existing register/TMEM kernel to cover block counts 0 through 8, optional prefix addition, optional output normalization, and block-bank writes; - uses the existing sour...
[{"scope": "kernel", "hardware": "NVIDIA B300 SXM6 AC", "model": "Kimi-K3", "shape": "hidden_size=7168", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 10.24, "optimized": 8.19, "stated_speedup": 1.25, "speedup": 1.2503}, {"scope": "kernel", "hardware": "NVIDIA B300 SXM6 AC",...
1.4478
null
vllm
d6d665854314f0aa90ad6ef32a3382136c71314c
2026-08-31T16:18:12-07:00
54,261
https://github.com/vllm-project/vllm/pull/54261
[Kimi-K3][Perf] Make native CUDA AttnRes the SM100 default (#54261)
[Kimi-K3][Perf] Make native CUDA AttnRes the SM100 default (#54261) Signed-off-by: Yongye Zhu <zyy1102000@gmail.com>
csrc/libtorch_stable/ops.h
cpp
Apache-2.0
#pragma once #include <torch/csrc/stable/library.h> #include <torch/csrc/stable/tensor.h> #include <torch/headeronly/util/Exception.h> #include <optional> #include <string> #include <vector> #include <torch/csrc/stable/ops.h> inline torch::stable::Tensor weak_ref_tensor(torch::stable::Tensor& tensor) { // Ensure ...
#pragma once #include <torch/csrc/stable/library.h> #include <torch/csrc/stable/tensor.h> #include <torch/headeronly/util/Exception.h> #include <optional> #include <string> #include <vector> #include <torch/csrc/stable/ops.h> inline torch::stable::Tensor weak_ref_tensor(torch::stable::Tensor& tensor) { // Ensure ...
--- csrc/libtorch_stable/ops.h +++ csrc/libtorch_stable/ops.h @@ -411,13 +411,14 @@ #ifdef VLLM_ENABLE_KIMI_K3_ATTN_RES void kimi_k3_attn_res(torch::stable::Tensor& prefix, - torch::stable::Tensor const& delta, - torch::stable::Tensor const& blocks, + s...
5
4
3
[ "kimi" ]
[ "SM100" ]
[]
Optimize this cpp kernel file from vllm (csrc/libtorch_stable/ops.h). Goal: [Kimi-K3][Perf] Make native CUDA AttnRes the SM100 default Target hardware: SM100 Target models: kimi Current file: ```cpp #pragma once #include <torch/csrc/stable/library.h> #include <torch/csrc/stable/tensor.h> #include <torch/headeronly/u...
## Purpose Make the native CUDA Kimi-K3 AttnRes implementation the default for dense `hidden_size=7168` inputs on SM100. This PR: - extends the existing register/TMEM kernel to cover block counts 0 through 8, optional prefix addition, optional output normalization, and block-bank writes; - uses the existing sour...
[{"scope": "kernel", "hardware": "NVIDIA B300 SXM6 AC", "model": "Kimi-K3", "shape": "hidden_size=7168", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 10.24, "optimized": 8.19, "stated_speedup": 1.25, "speedup": 1.2503}, {"scope": "kernel", "hardware": "NVIDIA B300 SXM6 AC",...
1.4478
null
vllm
d6d665854314f0aa90ad6ef32a3382136c71314c
2026-08-31T16:18:12-07:00
54,261
https://github.com/vllm-project/vllm/pull/54261
[Kimi-K3][Perf] Make native CUDA AttnRes the SM100 default (#54261)
[Kimi-K3][Perf] Make native CUDA AttnRes the SM100 default (#54261) Signed-off-by: Yongye Zhu <zyy1102000@gmail.com>
csrc/libtorch_stable/torch_bindings.cpp
cpp
Apache-2.0
#include "ops.h" #include "cuda_utils.h" #include "core/registration.h" #include <torch/csrc/stable/library.h> // Register ops with STABLE_TORCH_LIBRARY for libtorch stable ABI compatibility. // Note: We register under namespace "_C" so ops are accessible as // torch.ops._C.<op_name> for compatibility with existing c...
#include "ops.h" #include "cuda_utils.h" #include "core/registration.h" #include <torch/csrc/stable/library.h> // Register ops with STABLE_TORCH_LIBRARY for libtorch stable ABI compatibility. // Note: We register under namespace "_C" so ops are accessible as // torch.ops._C.<op_name> for compatibility with existing c...
--- csrc/libtorch_stable/torch_bindings.cpp +++ csrc/libtorch_stable/torch_bindings.cpp @@ -542,9 +542,11 @@ #ifdef VLLM_ENABLE_KIMI_K3_ATTN_RES ops.def( "kimi_k3_attn_res(" - "Tensor! prefix, Tensor delta, Tensor blocks, Tensor norm_weight, " - "Tensor qk_weight, Tensor output_norm_weight, Tensor!...
5
3
3
[ "kimi" ]
[ "SM100" ]
[]
Optimize this cpp kernel file from vllm (csrc/libtorch_stable/torch_bindings.cpp). Goal: [Kimi-K3][Perf] Make native CUDA AttnRes the SM100 default Target hardware: SM100 Target models: kimi Current file: ```cpp #include "ops.h" #include "cuda_utils.h" #include "core/registration.h" #include <torch/csrc/stable/libra...
## Purpose Make the native CUDA Kimi-K3 AttnRes implementation the default for dense `hidden_size=7168` inputs on SM100. This PR: - extends the existing register/TMEM kernel to cover block counts 0 through 8, optional prefix addition, optional output normalization, and block-bank writes; - uses the existing sour...
[{"scope": "kernel", "hardware": "NVIDIA B300 SXM6 AC", "model": "Kimi-K3", "shape": "hidden_size=7168", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 10.24, "optimized": 8.19, "stated_speedup": 1.25, "speedup": 1.2503}, {"scope": "kernel", "hardware": "NVIDIA B300 SXM6 AC",...
1.4478
null
vllm
f5c3cc240bc1fc0519694fe689edb87dee8dfd92
2026-08-31T22:44:38+02:00
53,382
https://github.com/vllm-project/vllm/pull/53382
[Perf][Kernel] Tune cooperative topk for medium batch-sizes (#53382)
[Perf][Kernel] Tune cooperative topk for medium batch-sizes (#53382) Signed-off-by: LopezCastroRoberto <rocastro@redhat.com> Co-authored-by: Codex <codex@openai.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
csrc/libtorch_stable/cooperative_topk.cu
cuda
Apache-2.0
// Cooperative cluster TopK for DeepSeek V3 sparse attention indexer. // See cooperative_topk.cuh for kernel implementation. #include <cuda_runtime.h> #include "torch_utils.h" #ifndef USE_ROCM #include "cooperative_topk.cuh" namespace ct = vllm::cooperative; namespace hist4096 = vllm::topk_histogram_4096; #endif ...
// Cooperative cluster TopK for DeepSeek V3 sparse attention indexer. // See cooperative_topk.cuh for kernel implementation. #include <cuda_runtime.h> #include "torch_utils.h" #ifndef USE_ROCM #include "cooperative_topk.cuh" namespace ct = vllm::cooperative; namespace hist4096 = vllm::topk_histogram_4096; #endif ...
--- csrc/libtorch_stable/cooperative_topk.cu +++ csrc/libtorch_stable/cooperative_topk.cu @@ -16,7 +16,9 @@ void launch_cooperative_cluster(ct::CooperativeTopKParams<TopK>& params, size_t smem, cudaStream_t stream) { auto kernel = []() { - if constexpr (CS == 16) { + if conste...
8
6
3
[]
[]
[]
Optimize this cuda kernel file from vllm (csrc/libtorch_stable/cooperative_topk.cu). Goal: [Perf][Kernel] Tune cooperative topk for medium batch-sizes Target hardware: unspecified Target models: unspecified Current file: ```cuda // Cooperative cluster TopK for DeepSeek V3 sparse attention indexer. // See cooperative_...
Speedups w.r.t. FilteredTopK, which is the backend selected at this moment in MAIN for bs>32 topK=512 | Sequence length | BS=33 | BS=40 | BS=48 | BS=64 | |---|---:|---:|---:|---:| | 64K | 2.33x | 1.82x | 1.79x | 1.82x | | 96K | 2.24x | 1.66x | 1.65x | 1.64x | | 128K | 2.52x | 1.40x | 1.37x | 1.37x | | 160K | 2.71x...
[{"scope": "kernel", "hardware": null, "model": null, "shape": "seq_len=64K, topK=512", "batch_size": 33, "metric": "speedup", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 2.33, "speedup": 2.33}, {"scope": "kernel", "hardware": null, "model": null, "shape": "seq_len=64K...
1.73
null
vllm
f5c3cc240bc1fc0519694fe689edb87dee8dfd92
2026-08-31T22:44:38+02:00
53,382
https://github.com/vllm-project/vllm/pull/53382
[Perf][Kernel] Tune cooperative topk for medium batch-sizes (#53382)
[Perf][Kernel] Tune cooperative topk for medium batch-sizes (#53382) Signed-off-by: LopezCastroRoberto <rocastro@redhat.com> Co-authored-by: Codex <codex@openai.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
csrc/libtorch_stable/cooperative_topk.cuh
cuda
Apache-2.0
/* * Cooperative TopK kernel for DSA Indexer */ #ifndef COOPERATIVE_TOPK_CUH_ #define COOPERATIVE_TOPK_CUH_ #include <cooperative_groups.h> #include <cuda.h> #include <cuda_fp16.h> #include <cuda_runtime.h> #include <cuda/ptx> #include <algorithm> #include <cstdint> #include "topk_histogram_4096.cuh" namespace vl...
/* * Cooperative TopK kernel for DSA Indexer */ #ifndef COOPERATIVE_TOPK_CUH_ #define COOPERATIVE_TOPK_CUH_ #include <cooperative_groups.h> #include <cuda.h> #include <cuda_fp16.h> #include <cuda_runtime.h> #include <cuda/ptx> #include <algorithm> #include <cstdint> #include "topk_histogram_4096.cuh" namespace vl...
--- csrc/libtorch_stable/cooperative_topk.cuh +++ csrc/libtorch_stable/cooperative_topk.cuh @@ -547,7 +547,8 @@ {}; // tracks the parity for mbarrier wait/arrive protocol large_topk<TopK, CS, FusedSmem, true>(in, out, sl, phases, row_tie_ws); } else { - // Two-pass: only CS=4 in practice (CS=8 alwa...
10
1
3
[]
[]
[]
Optimize this cuda kernel file from vllm (csrc/libtorch_stable/cooperative_topk.cuh). Goal: [Perf][Kernel] Tune cooperative topk for medium batch-sizes Target hardware: unspecified Target models: unspecified Current file: ```cuda /* * Cooperative TopK kernel for DSA Indexer */ #ifndef COOPERATIVE_TOPK_CUH_ #define...
Speedups w.r.t. FilteredTopK, which is the backend selected at this moment in MAIN for bs>32 topK=512 | Sequence length | BS=33 | BS=40 | BS=48 | BS=64 | |---|---:|---:|---:|---:| | 64K | 2.33x | 1.82x | 1.79x | 1.82x | | 96K | 2.24x | 1.66x | 1.65x | 1.64x | | 128K | 2.52x | 1.40x | 1.37x | 1.37x | | 160K | 2.71x...
[{"scope": "kernel", "hardware": null, "model": null, "shape": "seq_len=64K, topK=512", "batch_size": 33, "metric": "speedup", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 2.33, "speedup": 2.33}, {"scope": "kernel", "hardware": null, "model": null, "shape": "seq_len=64K...
1.73
null
vllm
f5c3cc240bc1fc0519694fe689edb87dee8dfd92
2026-08-31T22:44:38+02:00
53,382
https://github.com/vllm-project/vllm/pull/53382
[Perf][Kernel] Tune cooperative topk for medium batch-sizes (#53382)
[Perf][Kernel] Tune cooperative topk for medium batch-sizes (#53382) Signed-off-by: LopezCastroRoberto <rocastro@redhat.com> Co-authored-by: Codex <codex@openai.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
vllm/model_executor/layers/sparse_attn_indexer.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Custom Sparse Attention Indexer layers.""" import torch import vllm.envs as envs from vllm import _custom_ops as ops from vllm._aiter_ops import rocm_aiter_ops from vllm.compilation.breakable_cudagraph import...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Custom Sparse Attention Indexer layers.""" import torch import vllm.envs as envs from vllm import _custom_ops as ops from vllm._aiter_ops import rocm_aiter_ops from vllm.compilation.breakable_cudagraph import...
--- vllm/model_executor/layers/sparse_attn_indexer.py +++ vllm/model_executor/layers/sparse_attn_indexer.py @@ -617,7 +617,7 @@ use_cooperative_topk = ( current_platform.is_cuda() and topk_tokens in (512, 1024, 2048) - and num_rows <= 32 + and num_rows <= 64 ...
1
1
3
[]
[]
[]
Optimize this triton kernel file from vllm (vllm/model_executor/layers/sparse_attn_indexer.py). Goal: [Perf][Kernel] Tune cooperative topk for medium batch-sizes Target hardware: unspecified Target models: unspecified Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright co...
Speedups w.r.t. FilteredTopK, which is the backend selected at this moment in MAIN for bs>32 topK=512 | Sequence length | BS=33 | BS=40 | BS=48 | BS=64 | |---|---:|---:|---:|---:| | 64K | 2.33x | 1.82x | 1.79x | 1.82x | | 96K | 2.24x | 1.66x | 1.65x | 1.64x | | 128K | 2.52x | 1.40x | 1.37x | 1.37x | | 160K | 2.71x...
[{"scope": "kernel", "hardware": null, "model": null, "shape": "seq_len=64K, topK=512", "batch_size": 33, "metric": "speedup", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 2.33, "speedup": 2.33}, {"scope": "kernel", "hardware": null, "model": null, "shape": "seq_len=64K...
1.73
null
vllm
129087ddab2b197b067e54e130d2cf5fcb094bd5
2026-08-29T09:14:39-07:00
45,457
https://github.com/vllm-project/vllm/pull/45457
[Perf] Reuse topk SparseMatrix routing metadata in GPT-OSS MoE forward (#45457)
[Perf] Reuse topk SparseMatrix routing metadata in GPT-OSS MoE forward (#45457) Signed-off-by: Shenglei Fu <sfu@confluent.io> Signed-off-by: Shenglei Fu <117230642+ShengleiFu@users.noreply.github.com> Co-authored-by: Claude Fable 5 <noreply@anthropic.com>
vllm/model_executor/layers/fused_moe/experts/gpt_oss_triton_kernels_moe.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project import torch import vllm.model_executor.layers.fused_moe.modular_kernel as mk from vllm.logger import init_logger from vllm.model_executor.layers.fused_moe.activation import MoEActivation from vllm.model_executo...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project import torch import vllm.model_executor.layers.fused_moe.modular_kernel as mk from vllm.logger import init_logger from vllm.model_executor.layers.fused_moe.activation import MoEActivation from vllm.model_executo...
--- vllm/model_executor/layers/fused_moe/experts/gpt_oss_triton_kernels_moe.py +++ vllm/model_executor/layers/fused_moe/experts/gpt_oss_triton_kernels_moe.py @@ -578,13 +578,14 @@ if sm_first: logits = torch.softmax(logits, dim=-1) topk_result = topk_fn(logits, topk, apply_softmax=not sm_...
45
14
1
[ "gpt-oss" ]
[]
[]
Optimize this triton kernel file from vllm (vllm/model_executor/layers/fused_moe/experts/gpt_oss_triton_kernels_moe.py). Goal: [Perf] Reuse topk SparseMatrix routing metadata in GPT-OSS MoE forward Target hardware: unspecified Target models: gpt-oss Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX...
FIX #28986 Supersedes #35619 — thanks @banparth for the earlier exploration of this idea; the routing code has since been restructured, so this reimplements it against the current `experts/gpt_oss_triton_kernels_moe.py`. ## Purpose On the `triton_kernels` v3.6+ path, `topk()` returns a `SparseMatrix` whose construct...
[{"scope": "kernel", "hardware": "RTX 5090 (SM120)", "model": "gpt-oss-20b", "shape": null, "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 458.5, "optimized": 260.3, "stated_speedup": null, "speedup": 1.7614}, {"scope": "kernel", "hardware": "RTX 5090 (SM120)", "model": "gpt-...
1.7614
null
vllm
6c18a5464852d9ddf4c59df8ec278ce1683a917e
2026-08-28T21:06:30-07:00
54,299
https://github.com/vllm-project/vllm/pull/54299
[Perf] Avoid h2d copies from non-pinned CPU tensors (#54299)
[Perf] Avoid h2d copies from non-pinned CPU tensors (#54299) Signed-off-by: Nick Hill <nickhill123@gmail.com>
vllm/v1/attention/backends/flashinfer.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Attention layer with FlashInfer.""" from dataclasses import dataclass, replace from enum import Enum from functools import partial from typing import ClassVar import numpy as np import torch from flashinfer i...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Attention layer with FlashInfer.""" from dataclasses import dataclass, replace from enum import Enum from functools import partial from typing import ClassVar import numpy as np import torch from flashinfer i...
--- vllm/v1/attention/backends/flashinfer.py +++ vllm/v1/attention/backends/flashinfer.py @@ -917,16 +917,15 @@ arch, ) # Preparing persistent buffers - # Since we do not have explicit synchronization in ModelRunnerV2, we do not pin - # reused CPU buffers to avoid a race con...
19
33
2
[]
[ "CPU" ]
[]
Optimize this triton kernel file from vllm (vllm/v1/attention/backends/flashinfer.py). Goal: [Perf] Avoid h2d copies from non-pinned CPU tensors Target hardware: CPU Target models: unspecified Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM pr...
This can cause a stall that impacts overlap of gpu and cpu work. These instances were exposed by https://github.com/vllm-project/vllm/pull/53491.
[]
null
null
vllm
43196f2458bebb822cd825c0370b6f157b66f293
2026-08-28T19:00:46-07:00
54,295
https://github.com/vllm-project/vllm/pull/54295
[Perf][MLA Sparse] Pin req_id_per_token before non_blocking H2D on XPU and ROCm (#54295)
[Perf][MLA Sparse] Pin req_id_per_token before non_blocking H2D on XPU and ROCm (#54295) Signed-off-by: Keyi Li <likey6688@gmail.com> Co-authored-by: Keyi Li <likey6688@gmail.com> Co-authored-by: Claude Opus 4.7 <noreply@anthropic.com>
vllm/v1/attention/backends/mla/rocm_aiter_mla_sparse.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project from dataclasses import dataclass from typing import TYPE_CHECKING, ClassVar import numpy as np import torch from vllm import _custom_ops as ops from vllm._aiter_ops import rocm_aiter_ops from vllm.config impor...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project from dataclasses import dataclass from typing import TYPE_CHECKING, ClassVar import numpy as np import torch from vllm import _custom_ops as ops from vllm._aiter_ops import rocm_aiter_ops from vllm.config impor...
--- vllm/v1/attention/backends/mla/rocm_aiter_mla_sparse.py +++ vllm/v1/attention/backends/mla/rocm_aiter_mla_sparse.py @@ -17,6 +17,7 @@ ) from vllm.platforms import current_platform from vllm.triton_utils import tl, triton +from vllm.utils.torch_utils import np_to_pinned_tensor from vllm.v1.attention.backend impo...
2
1
2
[]
[ "ROCM", "XPU" ]
[]
Optimize this triton kernel file from vllm (vllm/v1/attention/backends/mla/rocm_aiter_mla_sparse.py). Goal: [Perf][MLA Sparse] Pin req_id_per_token before non_blocking H2D on XPU and ROCm Target hardware: ROCM, XPU Target models: unspecified Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCop...
## Summary Route the two `buffer.copy_(torch.from_numpy(...), non_blocking=True)` sites on the sparse-MLA metadata path through `np_to_pinned_tensor` so the copy source is pinned: - `XPUMLASparseMetadataBuilder.build` `req_id_per_token_buffer` - ROCm AITER sparse MLA metadata builder `req_id_per_token_buffer` ## Con...
[]
null
null
vllm
ae5b8e4a8d77a5de404a0cf9a91a56e8c7f2a94e
2026-08-28T15:54:39-07:00
52,849
https://github.com/vllm-project/vllm/pull/52849
[ROCm][PERF] Enable AITER PA gluon decode for MiniMax-M3 MTP and dense layers (#52849)
[ROCm][PERF] Enable AITER PA gluon decode for MiniMax-M3 MTP and dense layers (#52849) Signed-off-by: ukannika <uma.kannikanti@amd.com> Signed-off-by: ykamiset <yaminipreethi.kamisetty@amd.com> Co-authored-by: ykamiset <yaminipreethi.kamisetty@amd.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply....
vllm/v1/attention/backends/rocm_aiter_fa.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Attention layer with AiterFlashAttention.""" from dataclasses import dataclass from typing import ClassVar import torch from vllm._aiter_ops import rocm_aiter_ops from vllm.config import VllmConfig, get_laye...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Attention layer with AiterFlashAttention.""" from dataclasses import dataclass, replace from typing import ClassVar import torch from vllm._aiter_ops import rocm_aiter_ops from vllm.config import ( VllmC...
--- vllm/v1/attention/backends/rocm_aiter_fa.py +++ vllm/v1/attention/backends/rocm_aiter_fa.py @@ -2,13 +2,17 @@ # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Attention layer with AiterFlashAttention.""" -from dataclasses import dataclass +from dataclasses import dataclass, replace from ...
281
63
1
[ "minimax" ]
[ "ROCM" ]
[]
Optimize this triton kernel file from vllm (vllm/v1/attention/backends/rocm_aiter_fa.py). Goal: [ROCm][PERF] Enable AITER PA gluon decode for MiniMax-M3 MTP and dense layers Target hardware: ROCM Target models: minimax Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright c...
## Purpose The gluon paged-attention decode kernel handles multi-token query lengths, so EAGLE3 speculative decoding no longer has to fall back to native vllm unified_attention. ## Test Plan Server cmd to run EAGLE3 speculative decoding ``` export VLLM_ENGINE_READY_TIMEOUT_S=3600 export VLLM_EXECUTE_MODEL_TIMEOUT_S...
[]
null
null
vllm
7d5769b2d9cf1e999e3f2fc2c1da265cf0d5d794
2026-08-28T04:52:45+08:00
53,685
https://github.com/vllm-project/vllm/pull/53685
[Perf][DSv4] Use native CUDA SwiGLU clamp kernel for Humming MoE (throughput +1.40%) (#53685)
[Perf][DSv4] Use native CUDA SwiGLU clamp kernel for Humming MoE (throughput +1.40%) (#53685) Signed-off-by: chaunceyjiang <chaunceyjiang@gmail.com>
vllm/model_executor/layers/fused_moe/utils.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project import functools from collections.abc import Iterable from math import prod from typing import TYPE_CHECKING import torch import torch.nn.functional as F from torch import nn import vllm.envs as envs from vllm i...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project import functools from collections.abc import Iterable from math import prod from typing import TYPE_CHECKING import torch import torch.nn.functional as F from torch import nn import vllm.envs as envs from vllm i...
--- vllm/model_executor/layers/fused_moe/utils.py +++ vllm/model_executor/layers/fused_moe/utils.py @@ -647,6 +647,8 @@ # requires topk_ids. Fall back to the torch implementation otherwise. if topk_ids is not None: _swiglu_limit_pad_aware(output, input, topk_ids, swiglu_limit, expert_map) + elif c...
2
0
1
[ "deepseek" ]
[]
[]
Optimize this triton kernel file from vllm (vllm/model_executor/layers/fused_moe/utils.py). Goal: [Perf][DSv4] Use native CUDA SwiGLU clamp kernel for Humming MoE (throughput +1.40%) Target hardware: unspecified Target models: deepseek Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyright...
## Purpose Use native CUDA SwiGLU clamp kernel for Humming MoE ## Test Plan ``` vllm serve deepseek-ai/DeepSeek-V4-Flash-0731 \ --trust-remote-code --kv-cache-dtype fp8 --block-size 256 \ --enable-expert-parallel --tensor-parallel-size 4 \ --tokenizer-mode deepseek_v4 --tool-call-parser deepseek_v4 \ --enab...
[{"scope": "e2e", "hardware": null, "model": "DeepSeek-V4-Flash-0731", "shape": null, "batch_size": 16, "metric": "throughput", "unit": "tok/s", "higher_is_better": true, "baseline": 661.39, "optimized": 670.64, "stated_speedup": null, "speedup": 1.014}, {"scope": "e2e", "hardware": null, "model": "DeepSeek-V4-Flash-07...
null
1.014
vllm
7156c63bef1f80a2edcc67901fa7ebb3892b4f3d
2026-08-26T05:28:40+02:00
52,980
https://github.com/vllm-project/vllm/pull/52980
[SM100] Hdim 256 optimized (#52980)
[SM100] Hdim 256 optimized (#52980) Signed-off-by: Simon Veitner <sveitner@redhat.com>
vllm/v1/attention/backends/flash_attn.py
cute_dsl
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Attention layer with FlashAttention.""" import copy import functools from dataclasses import dataclass from typing import ClassVar import numpy as np import torch from vllm.model_executor.layers.attention im...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Attention layer with FlashAttention.""" import copy import functools from dataclasses import dataclass from typing import ClassVar import numpy as np import torch from vllm.model_executor.layers.attention im...
--- vllm/v1/attention/backends/flash_attn.py +++ vllm/v1/attention/backends/flash_attn.py @@ -24,11 +24,13 @@ MultipleOf, ) from vllm.v1.attention.backends.fa_utils import ( + FA4_HD256_PAGE_SIZE, flash_attn_supports_kv_cache_dtype, flash_attn_supports_quant_query_input, get_flash_attn_version,...
85
8
3
[]
[ "SM100" ]
[]
Optimize this cute_dsl kernel file from vllm (vllm/v1/attention/backends/flash_attn.py). Goal: [SM100] Hdim 256 optimized Target hardware: SM100 Target models: unspecified Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Attention la...
<!-- markdownlint-disable --> ## Purpose Re-enables FA4 for `head_size=256` on Blackwell, which was temporarily disabled in https://github.com/vllm-project/vllm/pull/52050 because the SM100 2-CTA hd256 kernel rejected `seqused_q/seqused_k` — something vLLM's decoder attention always supplies. That gap is now closed ...
[]
null
null
vllm
07ef21bc69842665cf5056371ea15a6d014f3b05
2026-08-25T09:28:49+08:00
52,676
https://github.com/vllm-project/vllm/pull/52676
[Kernel][Perf] Enable fused QK-norm + partial MRoPE + gate for Qwen3.6 (#52676)
[Kernel][Perf] Enable fused QK-norm + partial MRoPE + gate for Qwen3.6 (#52676) Signed-off-by: kiroxu <148877251+BabyDrangoner@users.noreply.github.com> Co-authored-by: OpenAI Codex <codex@openai.com>
vllm/model_executor/layers/fused_qk_norm_rope.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Fused QK-RMSNorm + (partial) RoPE + gate copy Triton kernel. Currently used by the Qwen3.5 attention path (``attn_output_gate`` with NeoX-style partial RoPE). The unfused reference sequence is ``split -> Gemma...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Fused QK-RMSNorm + (partial) RoPE + gate copy Triton kernel. Currently used by the Qwen3.5 attention path (``attn_output_gate`` with NeoX-style partial RoPE). The unfused reference sequence is ``split -> Gemma...
--- vllm/model_executor/layers/fused_qk_norm_rope.py +++ vllm/model_executor/layers/fused_qk_norm_rope.py @@ -30,16 +30,22 @@ k_out_stride_t, gate_out_stride_t, cache_stride_p, + positions_stride_m, + positions_stride_t, num_q_heads: tl.constexpr, num_kv_heads: tl.constexpr, head_dim...
87
10
1
[ "qwen" ]
[]
[]
Optimize this triton kernel file from vllm (vllm/model_executor/layers/fused_qk_norm_rope.py). Goal: [Kernel][Perf] Enable fused QK-norm + partial MRoPE + gate for Qwen3.6 Target hardware: unspecified Target models: qwen Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright...
## Summary Qwen3.6 vision requests use per-head `[q | gate]`, zero-centered GemmaRMSNorm, and partial interleaved MRoPE. This PR extends the existing fused Q/K norm + RoPE + gate operator to support `[3, M]` T/H/W positions, partial MRoPE, the gated layout, and raw GemmaRMSNorm weights. Unsupported inputs keep the exi...
[{"scope": "kernel", "hardware": null, "model": "Qwen3.6", "shape": "TP1", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 106.71, "optimized": 45.39, "stated_speedup": 2.359, "speedup": 2.351}, {"scope": "kernel", "hardware": null, "model": "Qwen3.6", "shape": "TP1", "batch_s...
2.3548
1.0402