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guychuk
/
kernel-opt-rl

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vllm
7797b6022c129b862e45ae6aed08822e65d1bccb
2026-08-24T23:28:51+08:00
53,247
https://github.com/vllm-project/vllm/pull/53247
[Kernel][Perf] Per-architecture tuned configs for batch-invariant persistent matmul (~3x decode kernels on RTX 4090D/H20) (#53247)
[Kernel][Perf] Per-architecture tuned configs for batch-invariant persistent matmul (~3x decode kernels on RTX 4090D/H20) (#53247) Signed-off-by: LioEinaudi <zhao3024667639@gmail.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
vllm/model_executor/layers/batch_invariant.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project import math import os from collections.abc import Callable from typing import Any import torch import vllm.envs as envs from vllm.platforms import current_platform from vllm.triton_utils import tl, triton from v...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project import math import os from collections.abc import Callable from typing import Any import torch import vllm.envs as envs from vllm.model_executor.layers.batch_invariant_configs import ( _get_matmul_config, ...
--- vllm/model_executor/layers/batch_invariant.py +++ vllm/model_executor/layers/batch_invariant.py @@ -8,6 +8,10 @@ import torch import vllm.envs as envs +from vllm.model_executor.layers.batch_invariant_configs import ( + _get_matmul_config, + resolve_tuned_matmul_configs, +) from vllm.platforms import curr...
6
1
1
[]
[ "H20" ]
[ "3x" ]
Optimize this triton kernel file from vllm (vllm/model_executor/layers/batch_invariant.py). Goal: [Kernel][Perf] Per-architecture tuned configs for batch-invariant persistent matmul (~3x decode kernels on RTX 4090D/H20) Target hardware: H20 Target models: unspecified Current file: ```python # SPDX-License-Identifier:...
## Purpose Add per-architecture-family tuned bf16 launch configurations for the batch-invariant `matmul_kernel_persistent` path on Hopper and Ada. The table covers the five Qwen3-1.7B weight shapes, selects `BLOCK_SIZE_M`, `BLOCK_SIZE_N`, `num_warps`, and `num_stages` by M bucket, and falls back to the existing config...
[{"scope": "kernel", "hardware": "RTX 4090 D", "model": "Qwen3-1.7B", "shape": null, "batch_size": null, "metric": "decode-kernel geomean vs torch.mm", "unit": null, "higher_is_better": true, "baseline": 0.254, "optimized": 0.768, "stated_speedup": 3.02, "speedup": 3.0236}, {"scope": "kernel", "hardware": "H20", "model...
1.9786
1.6141
vllm
9eb9d9d3953959695108600c8ed33d36bc6a1e5f
2026-08-22T13:32:40-04:00
52,789
https://github.com/vllm-project/vllm/pull/52789
[Perf] Support internal prefill checkpoints for Mamba prefix caching, 9%~25% TTFT improvement (#52789)
[Perf] Support internal prefill checkpoints for Mamba prefix caching, 9%~25% TTFT improvement (#52789) Signed-off-by: yewentao256 <zhyanwentao@126.com> Signed-off-by: Ziming Huang <zelda.huanghuang@gmail.com> Signed-off-by: Wentao Ye <44945378+yewentao256@users.noreply.github.com> Co-authored-by: Ziming Huang <zelda.h...
csrc/flashkda_registration.cpp
cpp
Apache-2.0
#include "core/registration.h" #include "flash_kda.h" #include <torch/csrc/stable/library.h> STABLE_TORCH_LIBRARY(_flashkda_C, m) { m.def("get_workspace_size(int T_total, int H, int N=1) -> int"); m.def( "fwd(Tensor q, Tensor k, Tensor v, Tensor g, Tensor beta, float scale, " "Tensor(a!) out, Tensor(c...
#include "core/registration.h" #include "flash_kda.h" #include <torch/csrc/stable/library.h> STABLE_TORCH_LIBRARY(_flashkda_C, m) { m.def("get_workspace_size(int T_total, int H, int N=1) -> int"); m.def( "fwd(Tensor q, Tensor k, Tensor v, Tensor g, Tensor beta, float scale, " "Tensor(a!) out, Tensor(c...
--- csrc/flashkda_registration.cpp +++ csrc/flashkda_registration.cpp @@ -10,7 +10,8 @@ "Tensor(a!) out, Tensor(c!) workspace, Tensor A_log, Tensor dt_bias, " "float lower_bound, " "Tensor? initial_state=None, Tensor(b!)? final_state=None, " - "Tensor? cu_seqlens=None) -> ()"); + "Tensor?...
2
1
1
[ "mamba" ]
[]
[]
Optimize this cpp kernel file from vllm (csrc/flashkda_registration.cpp). Goal: [Perf] Support internal prefill checkpoints for Mamba prefix caching, 9%~25% TTFT improvement Target hardware: unspecified Target models: mamba Current file: ```cpp #include "core/registration.h" #include "flash_kda.h" #include <torch/cs...
## Purpose Mamba prefix caching currently splits a prefill at the last block boundary Let's use a 8k input as an example Before ```bash Model forward (7680 tokens) -> FlashKDA(7680 tokens) -> save checkpoint -> Model forward (320 tokens) -> FlashKDA(320 tokens) ``` Now ```bash Model forward (8000 tokens) -> Flash...
[{"scope": "e2e", "hardware": null, "model": "moonshotai/Kimi-K3", "shape": "prompt_tokens=8000,output_tokens=1000", "batch_size": 1, "metric": "TTFT", "unit": "ms", "higher_is_better": false, "baseline": 435.28, "optimized": 394.19, "stated_speedup": null, "speedup": 1.1042}, {"scope": "e2e", "hardware": null, "model"...
null
1.0398
vllm
fe76112ff2981e9373765d76687d53f94880f38e
2026-08-21T13:00:39-04:00
52,882
https://github.com/vllm-project/vllm/pull/52882
[ROCm][Perf] Optimize DeepSeek V4 C4A top-k with AITER (#52882)
[ROCm][Perf] Optimize DeepSeek V4 C4A top-k with AITER (#52882)
csrc/libtorch_stable/sampler.cu
cuda
Apache-2.0
#include "../cuda_compat.h" #include "dispatch_utils.h" #include "torch_utils.h" #ifndef USE_ROCM #include <cub/cub.cuh> #else #include <hipcub/hipcub.hpp> #endif namespace vllm { template <typename scalar_t> __global__ void apply_repetition_penalties_kernel( scalar_t* __restrict__ logits, // [num_se...
#include "../cuda_compat.h" #include "dispatch_utils.h" #include "torch_utils.h" #include <cstring> #ifndef USE_ROCM #include <cub/cub.cuh> #else #include <hipcub/hipcub.hpp> #endif namespace vllm { template <typename scalar_t> __global__ void apply_repetition_penalties_kernel( scalar_t* __restrict__ logits...
--- csrc/libtorch_stable/sampler.cu +++ csrc/libtorch_stable/sampler.cu @@ -1,6 +1,8 @@ #include "../cuda_compat.h" #include "dispatch_utils.h" #include "torch_utils.h" + +#include <cstring> #ifndef USE_ROCM #include <cub/cub.cuh> @@ -327,11 +329,14 @@ } // Follows half - 11 - 11 - 10 bit iterations +// Ke...
131
10
3
[ "deepseek" ]
[ "ROCM" ]
[]
Optimize this cuda kernel file from vllm (csrc/libtorch_stable/sampler.cu). Goal: [ROCm][Perf] Optimize DeepSeek V4 C4A top-k with AITER Target hardware: ROCM Target models: deepseek Current file: ```cuda #include "../cuda_compat.h" #include "dispatch_utils.h" #include "torch_utils.h" #ifndef USE_ROCM #include <cu...
## Summary This replaces the DeepSeek V4 C4A selector's ROCm top-k bottleneck with a correctness-adapted AITER path for short/medium contexts and a graph-safe tuned native fallback for long contexts on gfx950. - Route C4A prefill/decode top-k through the public AITER v0.1.19 operations. - Convert AITER prefill's pack...
[{"scope": "kernel", "hardware": "gfx950", "model": null, "shape": "context=10K, N=2", "batch_size": 1, "metric": "speedup", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 2.81, "speedup": 2.81}, {"scope": "kernel", "hardware": "gfx950", "model": null, "shape": "context=1...
1.635
1.1216
vllm
fe76112ff2981e9373765d76687d53f94880f38e
2026-08-21T13:00:39-04:00
52,882
https://github.com/vllm-project/vllm/pull/52882
[ROCm][Perf] Optimize DeepSeek V4 C4A top-k with AITER (#52882)
[ROCm][Perf] Optimize DeepSeek V4 C4A top-k with AITER (#52882)
vllm/model_executor/layers/sparse_attn_indexer.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Custom Sparse Attention Indexer layers.""" import torch import vllm.envs as envs from vllm import _custom_ops as ops from vllm._aiter_ops import rocm_aiter_ops from vllm.compilation.breakable_cudagraph import...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Custom Sparse Attention Indexer layers.""" import torch import vllm.envs as envs from vllm import _custom_ops as ops from vllm._aiter_ops import rocm_aiter_ops from vllm.compilation.breakable_cudagraph import...
--- vllm/model_executor/layers/sparse_attn_indexer.py +++ vllm/model_executor/layers/sparse_attn_indexer.py @@ -750,6 +750,7 @@ topk_indices_buffer: torch.Tensor, skip_k_cache_insert: bool = False, use_fp4_cache: bool = False, + compress_ratio: int = 1, ): super().__init_...
3
0
3
[ "deepseek" ]
[ "ROCM" ]
[]
Optimize this triton kernel file from vllm (vllm/model_executor/layers/sparse_attn_indexer.py). Goal: [ROCm][Perf] Optimize DeepSeek V4 C4A top-k with AITER Target hardware: ROCM Target models: deepseek Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to t...
## Summary This replaces the DeepSeek V4 C4A selector's ROCm top-k bottleneck with a correctness-adapted AITER path for short/medium contexts and a graph-safe tuned native fallback for long contexts on gfx950. - Route C4A prefill/decode top-k through the public AITER v0.1.19 operations. - Convert AITER prefill's pack...
[{"scope": "kernel", "hardware": "gfx950", "model": null, "shape": "context=10K, N=2", "batch_size": 1, "metric": "speedup", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 2.81, "speedup": 2.81}, {"scope": "kernel", "hardware": "gfx950", "model": null, "shape": "context=1...
1.635
1.1216
vllm
fe76112ff2981e9373765d76687d53f94880f38e
2026-08-21T13:00:39-04:00
52,882
https://github.com/vllm-project/vllm/pull/52882
[ROCm][Perf] Optimize DeepSeek V4 C4A top-k with AITER (#52882)
[ROCm][Perf] Optimize DeepSeek V4 C4A top-k with AITER (#52882)
vllm/v1/attention/ops/rocm_aiter_mla_sparse.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project import functools import importlib import math from importlib.util import find_spec import torch import torch.nn.functional as F import vllm.envs as envs from vllm.compilation.breakable_cudagraph import eager_bre...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project import functools import importlib import math from collections.abc import Callable from importlib.util import find_spec import torch import torch.nn.functional as F import vllm.envs as envs from vllm.compilation...
--- vllm/v1/attention/ops/rocm_aiter_mla_sparse.py +++ vllm/v1/attention/ops/rocm_aiter_mla_sparse.py @@ -3,6 +3,7 @@ import functools import importlib import math +from collections.abc import Callable from importlib.util import find_spec import torch @@ -10,6 +11,7 @@ import vllm.envs as envs from vllm.comp...
184
21
3
[ "deepseek" ]
[ "ROCM" ]
[]
Optimize this triton kernel file from vllm (vllm/v1/attention/ops/rocm_aiter_mla_sparse.py). Goal: [ROCm][Perf] Optimize DeepSeek V4 C4A top-k with AITER Target hardware: ROCM Target models: deepseek Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the ...
## Summary This replaces the DeepSeek V4 C4A selector's ROCm top-k bottleneck with a correctness-adapted AITER path for short/medium contexts and a graph-safe tuned native fallback for long contexts on gfx950. - Route C4A prefill/decode top-k through the public AITER v0.1.19 operations. - Convert AITER prefill's pack...
[{"scope": "kernel", "hardware": "gfx950", "model": null, "shape": "context=10K, N=2", "batch_size": 1, "metric": "speedup", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 2.81, "speedup": 2.81}, {"scope": "kernel", "hardware": "gfx950", "model": null, "shape": "context=1...
1.635
1.1216
vllm
463aa5e30fe0b51a5d6ef22897962fc1be97cb85
2026-08-22T00:07:13+08:00
52,606
https://github.com/vllm-project/vllm/pull/52606
[ROCm][Perf] Kimi-K3 Fused kernels for KDA prefill (#52606)
[ROCm][Perf] Kimi-K3 Fused kernels for KDA prefill (#52606) Signed-off-by: kliuae <kuanfu.liu@embeddedllm.com> Signed-off-by: tjtanaa <tunjian.tan@embeddedllm.com> Co-authored-by: Claude <noreply@anthropic.com> Co-authored-by: TJian <tunjian.tan@embeddedllm.com>
csrc/libtorch_stable/ops.h
cpp
Apache-2.0
#pragma once #include <torch/csrc/stable/library.h> #include <torch/csrc/stable/tensor.h> #include <torch/headeronly/util/Exception.h> #include <optional> #include <string> #include <vector> #include <torch/csrc/stable/ops.h> inline torch::stable::Tensor weak_ref_tensor(torch::stable::Tensor& tensor) { // Ensure ...
#pragma once #include <torch/csrc/stable/library.h> #include <torch/csrc/stable/tensor.h> #include <torch/headeronly/util/Exception.h> #include <optional> #include <string> #include <vector> #include <torch/csrc/stable/ops.h> inline torch::stable::Tensor weak_ref_tensor(torch::stable::Tensor& tensor) { // Ensure ...
--- csrc/libtorch_stable/ops.h +++ csrc/libtorch_stable/ops.h @@ -404,6 +404,33 @@ torch::stable::Tensor const& norm_weight, torch::stable::Tensor& out, double scale, double norm_eps); +#endif + +#ifdef VLLM_ENABLE_FUSED_KDA_CHUNK +void fused_kda_prologue( + torch::stable::Tensor const& q, torch::stable:...
27
0
2
[ "kimi" ]
[ "ROCM" ]
[]
Optimize this cpp kernel file from vllm (csrc/libtorch_stable/ops.h). Goal: [ROCm][Perf] Kimi-K3 Fused kernels for KDA prefill Target hardware: ROCM Target models: kimi Current file: ```cpp #pragma once #include <torch/csrc/stable/library.h> #include <torch/csrc/stable/tensor.h> #include <torch/headeronly/util/Excep...
## Purpose On ROCm, Kimi-K3's KDA prefill chunk path currently runs a pipeline of nine Triton kernels. This PR adds a fusion path for ROCm that fuses these operations based on the characteristics of their workloads: **Prologue**: The kernel that prepares the chunks leading up to the recurrent state update. It norma...
[{"scope": "kernel", "hardware": "gfx950", "model": "Kimi-K3", "shape": "tokens=1024,seqs=1", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 117.4, "optimized": 60.7, "stated_speedup": 1.93, "speedup": 1.9341}, {"scope": "kernel", "hardware": "gfx950", "model": "Kimi-K3", "sh...
2.1968
1.0373
vllm
463aa5e30fe0b51a5d6ef22897962fc1be97cb85
2026-08-22T00:07:13+08:00
52,606
https://github.com/vllm-project/vllm/pull/52606
[ROCm][Perf] Kimi-K3 Fused kernels for KDA prefill (#52606)
[ROCm][Perf] Kimi-K3 Fused kernels for KDA prefill (#52606) Signed-off-by: kliuae <kuanfu.liu@embeddedllm.com> Signed-off-by: tjtanaa <tunjian.tan@embeddedllm.com> Co-authored-by: Claude <noreply@anthropic.com> Co-authored-by: TJian <tunjian.tan@embeddedllm.com>
csrc/libtorch_stable/torch_bindings.cpp
cpp
Apache-2.0
#include "ops.h" #include "cuda_utils.h" #include "core/registration.h" #include <torch/csrc/stable/library.h> // Register ops with STABLE_TORCH_LIBRARY for libtorch stable ABI compatibility. // Note: We register under namespace "_C" so ops are accessible as // torch.ops._C.<op_name> for compatibility with existing c...
#include "ops.h" #include "cuda_utils.h" #include "core/registration.h" #include <torch/csrc/stable/library.h> // Register ops with STABLE_TORCH_LIBRARY for libtorch stable ABI compatibility. // Note: We register under namespace "_C" so ops are accessible as // torch.ops._C.<op_name> for compatibility with existing c...
--- csrc/libtorch_stable/torch_bindings.cpp +++ csrc/libtorch_stable/torch_bindings.cpp @@ -536,6 +536,23 @@ "Tensor state_indices, Tensor cu_seqlens, Tensor num_accepted_tokens, " "Tensor! state, Tensor output_gate, Tensor norm_weight, Tensor! out, " "float scale, float norm_eps=1e-5) -> ()"); +#e...
22
0
2
[ "kimi" ]
[ "ROCM" ]
[]
Optimize this cpp kernel file from vllm (csrc/libtorch_stable/torch_bindings.cpp). Goal: [ROCm][Perf] Kimi-K3 Fused kernels for KDA prefill Target hardware: ROCM Target models: kimi Current file: ```cpp #include "ops.h" #include "cuda_utils.h" #include "core/registration.h" #include <torch/csrc/stable/library.h> //...
## Purpose On ROCm, Kimi-K3's KDA prefill chunk path currently runs a pipeline of nine Triton kernels. This PR adds a fusion path for ROCm that fuses these operations based on the characteristics of their workloads: **Prologue**: The kernel that prepares the chunks leading up to the recurrent state update. It norma...
[{"scope": "kernel", "hardware": "gfx950", "model": "Kimi-K3", "shape": "tokens=1024,seqs=1", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 117.4, "optimized": 60.7, "stated_speedup": 1.93, "speedup": 1.9341}, {"scope": "kernel", "hardware": "gfx950", "model": "Kimi-K3", "sh...
2.1968
1.0373
vllm
cd7b7c265a30b8c3e5c908d59f4cb0d7dd8f8ff3
2026-08-21T12:07:03-04:00
43,018
https://github.com/vllm-project/vllm/pull/43018
[ROCm] Cpu offload for ROCm 7.13+ to align the hipMemcpyBatchAsync params and perf in 7.14x (#43018)
[ROCm] Cpu offload for ROCm 7.13+ to align the hipMemcpyBatchAsync params and perf in 7.14x (#43018) Signed-off-by: Hongxia Yang <hongxia.yang@amd.com> Co-authored-by: Yifan Qiao <yifanqiao@inferact.ai>
csrc/libtorch_stable/cache_kernels.cu
cuda
Apache-2.0
#include "torch_utils.h" #include "dispatch_utils.h" #include "../cuda_utils.h" #include "../cuda_compat.h" #include "quantization/vectorization_utils.cuh" #include "concat_mla_q.cuh" #ifdef USE_ROCM #include "../quantization/w8a8/fp8/amd/quant_utils.cuh" #else #include "../quantization/w8a8/fp8/nvidia/quant_uti...
#include "torch_utils.h" #include "dispatch_utils.h" #include "../cuda_utils.h" #include "../cuda_compat.h" #include "quantization/vectorization_utils.cuh" #include "concat_mla_q.cuh" #ifdef USE_ROCM #include "../quantization/w8a8/fp8/amd/quant_utils.cuh" #else #include "../quantization/w8a8/fp8/nvidia/quant_uti...
--- csrc/libtorch_stable/cache_kernels.cu +++ csrc/libtorch_stable/cache_kernels.cu @@ -16,6 +16,7 @@ #include <algorithm> #include <cassert> #include <cfloat> +#include <cstdlib> #ifdef USE_ROCM #include <hip/hip_bf16.h> @@ -75,6 +76,31 @@ block_size_in_bytes, memcpy_type, stream); } ...
76
19
1
[]
[ "CPU", "ROCM" ]
[ "7.14x" ]
Optimize this cuda kernel file from vllm (csrc/libtorch_stable/cache_kernels.cu). Goal: [ROCm] Cpu offload for ROCm 7.13+ to align the hipMemcpyBatchAsync params and perf in 7.14x Target hardware: CPU, ROCM Target models: unspecified Current file: ```cuda #include "torch_utils.h" #include "dispatch_utils.h" #include...
## Purpose This is related to the issue: https://github.com/vllm-project/vllm/issues/44341 In a previous enablement PR https://github.com/vllm-project/vllm/pull/40549, we enabled cpu offloading on ROCm, and we noticed the shortcoming of the hipMemcpyBatchAsync API lacked support on numAttrs paramter. This PR is to ...
[{"scope": "kernel", "hardware": "8\u00d7 MI350X, gfx950", "model": null, "shape": "block=4 KiB, direction=store (D\u2192H)", "batch_size": null, "metric": "bandwidth", "unit": "GB/s", "higher_is_better": true, "baseline": 1.6, "optimized": 25.4, "stated_speedup": 15.4, "speedup": 15.875}, {"scope": "kernel", "hardware...
12.1616
null
vllm
bfb6c134997aace3e801c9ae3251728bd5312003
2026-08-20T16:26:24-04:00
52,989
https://github.com/vllm-project/vllm/pull/52989
[Bugfix][MoE] Tune FlashInfer experts to scheduler token limit (#52989)
[Bugfix][MoE] Tune FlashInfer experts to scheduler token limit (#52989) Signed-off-by: mgoin <mgoin64@gmail.com> Co-authored-by: OpenAI Codex <codex@openai.com>
vllm/model_executor/layers/fused_moe/experts/trtllm_lora_moe.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """ LoRA-aware FlashInfer TRT-LLM MoE experts (BF16). Reuses the routed API + ``gemm1_lora_delta`` path from FlashInfer PR #3153: * The W13 (gate_up) LoRA delta is passed directly as ``gemm1_lora_delta`` to ...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """ LoRA-aware FlashInfer TRT-LLM MoE experts (BF16). Reuses the routed API + ``gemm1_lora_delta`` path from FlashInfer PR #3153: * The W13 (gate_up) LoRA delta is passed directly as ``gemm1_lora_delta`` to ...
--- vllm/model_executor/layers/fused_moe/experts/trtllm_lora_moe.py +++ vllm/model_executor/layers/fused_moe/experts/trtllm_lora_moe.py @@ -39,6 +39,7 @@ TopKWeightAndReduceNoOP, ) from vllm.model_executor.layers.fused_moe.utils import ( + fi_moe_largest_bucket, trtllm_moe_pack_topk_ids_weights, ) from...
2
0
5
[]
[]
[]
Optimize this triton kernel file from vllm (vllm/model_executor/layers/fused_moe/experts/trtllm_lora_moe.py). Goal: [Bugfix][MoE] Tune FlashInfer experts to scheduler token limit Target hardware: unspecified Target models: unspecified Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightT...
## Summary - pass vLLM's parallel-aware maximum token bucket to FlashInfer CUTLASS experts - fix the same omitted or hardcoded bound in modular BF16, BF16 LoRA, and MXINT4 expert paths - cover the CUTLASS forwarding behavior with a focused regression assertion ## Root cause These expert paths let FlashInfer use its ...
[]
null
null
vllm
e4d61d0d222ad21437a1507bb34ca7e916aac880
2026-08-19T10:28:52+08:00
52,616
https://github.com/vllm-project/vllm/pull/52616
[CPU] Add AMX-only high-performance MLA backend for DeepSeek V2/V3/R1 (#52616)
[CPU] Add AMX-only high-performance MLA backend for DeepSeek V2/V3/R1 (#52616) Signed-off-by: jiang1.li <jiang1.li@intel.com>
csrc/cpu/torch_bindings.cpp
cpp
Apache-2.0
#include "cache.h" #include "ops.h" #include "core/registration.h" #include <torch/library.h> // Note: overwrite the external definition for sharing same name between // libraries use different ISAs. #define TORCH_EXTENSION_NAME _C void release_dnnl_matmul_handler(int64_t handler); int64_t create_onednn_scaled_mm_h...
#include "cache.h" #include "ops.h" #include "core/registration.h" #include <torch/library.h> // Note: overwrite the external definition for sharing same name between // libraries use different ISAs. #define TORCH_EXTENSION_NAME _C void release_dnnl_matmul_handler(int64_t handler); int64_t create_onednn_scaled_mm_h...
--- csrc/cpu/torch_bindings.cpp +++ csrc/cpu/torch_bindings.cpp @@ -90,6 +90,39 @@ std::vector<int64_t> block_size, const std::optional<at::Tensor>& bias, at::ScalarType out_dtype, bool is_vnni); + +// Adapted from sglang: MLA CPU...
62
0
6
[ "deepseek" ]
[ "CPU" ]
[]
Optimize this cpp kernel file from vllm (csrc/cpu/torch_bindings.cpp). Goal: [CPU] Add AMX-only high-performance MLA backend for DeepSeek V2/V3/R1 Target hardware: CPU Target models: deepseek Current file: ```cpp #include "cache.h" #include "ops.h" #include "core/registration.h" #include <torch/library.h> // Note: ...
## Purpose Add `AMXMLABackend`/`AMXMLAImpl`, a high-performance MLA attention backend for CPU, built on AMX decode/extend/bmm/qkv-proj kernels vendored under `csrc/cpu/sgl-kernels/`. It plugs into the same `MLACommonBackend`/ `MLACommonImpl` abstraction every other concrete MLA backend uses. This is a separate, opt-i...
[]
null
null
vllm
88b2bff2c63d0f28396451f1199d09ee0f3e2d88
2026-08-18T18:56:56+02:00
51,695
https://github.com/vllm-project/vllm/pull/51695
[MOE] Standardize and abstract fused shared expert optimization selection (#51695)
[MOE] Standardize and abstract fused shared expert optimization selection (#51695) Signed-off-by: Felix Marty <Felix.Marty@amd.com>
vllm/model_executor/layers/fused_moe/utils.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project import functools from math import prod from typing import TYPE_CHECKING import torch import torch.nn.functional as F import vllm.envs as envs from vllm import _custom_ops as ops from vllm.logger import init_logg...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project import functools from collections.abc import Iterable from math import prod from typing import TYPE_CHECKING import torch import torch.nn.functional as F from torch import nn import vllm.envs as envs from vllm i...
--- vllm/model_executor/layers/fused_moe/utils.py +++ vllm/model_executor/layers/fused_moe/utils.py @@ -1,15 +1,21 @@ # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project import functools +from collections.abc import Iterable from math import prod from typing i...
85
0
3
[]
[]
[]
Optimize this triton kernel file from vllm (vllm/model_executor/layers/fused_moe/utils.py). Goal: [MOE] Standardize and abstract fused shared expert optimization selection Target hardware: unspecified Target models: unspecified Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Co...
## Disclosure AI assistance was used. The changes were reviewed and tested manually. ## Purpose Standardize fused shared-expert (FSE) detection so model construction and checkpoint loading use the same quantization-compatible decision **throughout all models implementing FSE**. This is e.g. useful for: - `shared_e...
[]
null
null
vllm
cdb8545a91be16f2b80234e0801458ad2a18cf1b
2026-08-18T09:17:40+08:00
52,539
https://github.com/vllm-project/vllm/pull/52539
[Kernel][Perf] Support Qwen head ratios in fused GDN MTP (#52539)
[Kernel][Perf] Support Qwen head ratios in fused GDN MTP (#52539) Signed-off-by: kiroxu <148877251+BabyDrangoner@users.noreply.github.com>
csrc/libtorch_stable/gdn/fused_gdn_decode_kernel.cu
cuda
Apache-2.0
/* * SPDX-License-Identifier: Apache-2.0 * SPDX-FileCopyrightText: Copyright contributors to the vLLM project */ #include <cstdint> #include <cuda_bf16.h> #include <cuda_fp16.h> #include <cuda_runtime.h> #include "../torch_utils.h" #include "../../cuda_compat.h" namespace { template <typename StateT> __device__ ...
/* * SPDX-License-Identifier: Apache-2.0 * SPDX-FileCopyrightText: Copyright contributors to the vLLM project */ #include <cstdint> #include <cuda_bf16.h> #include <cuda_fp16.h> #include <cuda_runtime.h> #include "../torch_utils.h" #include "../../cuda_compat.h" namespace { template <typename StateT> __device__ ...
--- csrc/libtorch_stable/gdn/fused_gdn_decode_kernel.cu +++ csrc/libtorch_stable/gdn/fused_gdn_decode_kernel.cu @@ -146,7 +146,7 @@ return {x, y}; } -template <typename StateT> +template <typename StateT, int ValueHeadsPerKeyHead> __global__ __launch_bounds__(kThreads, 2) void gdn_decode_post_conv_mtp_kernel( ...
50
26
2
[ "qwen" ]
[]
[]
Optimize this cuda kernel file from vllm (csrc/libtorch_stable/gdn/fused_gdn_decode_kernel.cu). Goal: [Kernel][Perf] Support Qwen head ratios in fused GDN MTP Target hardware: unspecified Target models: qwen Current file: ```cuda /* * SPDX-License-Identifier: Apache-2.0 * SPDX-FileCopyrightText: Copyright contribut...
<!-- markdownlint-disable --> ## Summary #51674 added fused GDN MTP verification for `HV/H=8`. An audit of public Qwen GDN configs found production ratios `1/2/3/4/8`, from Qwen3.5 0.8B/2B through Qwen3.6 27B/35B and Qwen3.8 2.4T. This PR: - makes the value-head ratio a compile-time kernel parameter and dispatches ...
[{"scope": "kernel", "hardware": "PRO 6000", "model": null, "shape": "S=2", "batch_size": 1, "metric": "speedup", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 2.4657, "speedup": 2.4657}, {"scope": "kernel", "hardware": "H20", "model": null, "shape": "S=2", "batch_size":...
1.8144
1.1115
vllm
cdb8545a91be16f2b80234e0801458ad2a18cf1b
2026-08-18T09:17:40+08:00
52,539
https://github.com/vllm-project/vllm/pull/52539
[Kernel][Perf] Support Qwen head ratios in fused GDN MTP (#52539)
[Kernel][Perf] Support Qwen head ratios in fused GDN MTP (#52539) Signed-off-by: kiroxu <148877251+BabyDrangoner@users.noreply.github.com>
vllm/model_executor/layers/mamba/gdn/qwen_gdn_linear_attn.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Inference-only Qwen3-Next/Qwen3.5 model.""" import os from typing import Literal import torch from einops import rearrange from torch import nn from vllm import _custom_ops as ops from vllm import envs from ...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Inference-only Qwen3-Next/Qwen3.5 model.""" import os from typing import Literal import torch from einops import rearrange from torch import nn from vllm import _custom_ops as ops from vllm import envs from ...
--- vllm/model_executor/layers/mamba/gdn/qwen_gdn_linear_attn.py +++ vllm/model_executor/layers/mamba/gdn/qwen_gdn_linear_attn.py @@ -1805,7 +1805,8 @@ and attn_metadata.num_spec_decodes > 0 and self.kv_cache[1].dtype in FUSED_GDN_STATE_DTYPES and self.gdn_decode_kernel == "cuda" ...
2
1
2
[ "qwen", "mamba" ]
[]
[]
Optimize this triton kernel file from vllm (vllm/model_executor/layers/mamba/gdn/qwen_gdn_linear_attn.py). Goal: [Kernel][Perf] Support Qwen head ratios in fused GDN MTP Target hardware: unspecified Target models: qwen, mamba Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copy...
<!-- markdownlint-disable --> ## Summary #51674 added fused GDN MTP verification for `HV/H=8`. An audit of public Qwen GDN configs found production ratios `1/2/3/4/8`, from Qwen3.5 0.8B/2B through Qwen3.6 27B/35B and Qwen3.8 2.4T. This PR: - makes the value-head ratio a compile-time kernel parameter and dispatches ...
[{"scope": "kernel", "hardware": "PRO 6000", "model": null, "shape": "S=2", "batch_size": 1, "metric": "speedup", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 2.4657, "speedup": 2.4657}, {"scope": "kernel", "hardware": "H20", "model": null, "shape": "S=2", "batch_size":...
1.8144
1.1115
vllm
75dde08d3fd0cf4217c90e8499881d60fe426aa0
2026-08-17T14:21:32-04:00
51,114
https://github.com/vllm-project/vllm/pull/51114
[Perf][MoE] Optimize deepep_v2 receiver CPU Overhead (#51114)
[Perf][MoE] Optimize deepep_v2 receiver CPU Overhead (#51114) Signed-off-by: Lucas Wilkinson <wilkinson.lucas@gmail.com> Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com> Co-authored-by: Robert Shaw <114415538+robertgshaw2-redhat@users.noreply.github.com>
vllm/model_executor/layers/fused_moe/prepare_finalize/deepep_v2.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project from collections.abc import Callable import deep_ep import torch import vllm.model_executor.layers.fused_moe.modular_kernel as mk from vllm.forward_context import get_forward_context from vllm.model_executor.lay...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project from collections.abc import Callable import deep_ep import torch import vllm.model_executor.layers.fused_moe.modular_kernel as mk from vllm.forward_context import get_forward_context from vllm.model_executor.lay...
--- vllm/model_executor/layers/fused_moe/prepare_finalize/deepep_v2.py +++ vllm/model_executor/layers/fused_moe/prepare_finalize/deepep_v2.py @@ -80,8 +80,22 @@ # DBO microbatching: one handle slot per micro-batch. self.handles: list[deep_ep.EPHandle | None] = [None, None] + # arange(num_loca...
25
16
1
[]
[ "CPU" ]
[]
Optimize this triton kernel file from vllm (vllm/model_executor/layers/fused_moe/prepare_finalize/deepep_v2.py). Goal: [Perf][MoE] Optimize deepep_v2 receiver CPU Overhead Target hardware: CPU Target models: unspecified Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright ...
Optimize away excessive fills in deepep_v2's receiver BEFORE <img width="1571" height="181" alt="Screenshot 2026-08-05 at 12 12 25 AM" src="https://github.com/user-attachments/assets/d98a2c4f-c28e-4baa-8267-8369e025c910" /> AFTER <img width="1316" height="186" alt="Screenshot 2026-08-05 at 12 11 42 AM" src="https:...
[]
null
null
vllm
6914d60b1e1a2594f0066fe81e3684574413fbe7
2026-08-16T19:50:31+03:00
49,544
https://github.com/vllm-project/vllm/pull/49544
[ROCm][Perf] gfx942: use FlyDSL fp8 MQA logits kernel (ROCm/aiter#3913) (#49544)
[ROCm][Perf] gfx942: use FlyDSL fp8 MQA logits kernel (ROCm/aiter#3913) (#49544) Signed-off-by: Aakif Nawaz <aakif.nawaz@amd.com>
vllm/v1/attention/ops/rocm_aiter_mla_sparse.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project import functools import importlib import math from importlib.util import find_spec import torch import torch.nn.functional as F import vllm.envs as envs from vllm.compilation.breakable_cudagraph import eager_bre...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project import functools import importlib import math from importlib.util import find_spec import torch import torch.nn.functional as F import vllm.envs as envs from vllm.compilation.breakable_cudagraph import eager_bre...
--- vllm/v1/attention/ops/rocm_aiter_mla_sparse.py +++ vllm/v1/attention/ops/rocm_aiter_mla_sparse.py @@ -563,21 +563,14 @@ Logits tensor of shape [M, N], dtype `torch.float32`. """ - # TODO(ganyi): Temporarily workaround, will remove the module check and reference - # path after aiter merge this ...
3
10
1
[]
[ "GFX942", "ROCM" ]
[]
Optimize this triton kernel file from vllm (vllm/v1/attention/ops/rocm_aiter_mla_sparse.py). Goal: [ROCm][Perf] gfx942: use FlyDSL fp8 MQA logits kernel (ROCm/aiter#3913) Target hardware: GFX942, ROCM Target models: unspecified Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Co...
On gfx942, replace the vendored Triton `fp8_mqa_logits` with `aiter.ops.flydsl.flydsl_fp8_mqa_logits` from ROCm/aiter#3913. Drop-in replacement (identical args/semantics), gated behind `_ON_GFX942`. gfx950 and other paths are untouched. ## Results: GLM-5.2-FP8, 8× MI325X TP8 ### ISL=128K, OSL=1K, Conc=8 | Metric |...
[{"scope": "e2e", "hardware": "MI325X", "model": "GLM-5.2-FP8", "shape": "ISL=128K,OSL=1K", "batch_size": 8, "metric": "Median TTFT", "unit": "ms", "higher_is_better": false, "baseline": 42839, "optimized": 21871, "stated_speedup": null, "speedup": 1.9587}, {"scope": "e2e", "hardware": "MI325X", "model": "GLM-5.2-FP8",...
null
1.3253
vllm
1be36283678a9a94fc8fdaad6c95c2896d6b4015
2026-08-14T11:44:45+08:00
51,674
https://github.com/vllm-project/vllm/pull/51674
[Kernel][Perf] Add fused CUDA post-conv MTP decode kernel for Qwen3.5 GDN (#51674)
[Kernel][Perf] Add fused CUDA post-conv MTP decode kernel for Qwen3.5 GDN (#51674) Signed-off-by: Jie Fang <jief@nvidia.com> Co-authored-by: OpenAI Codex <codex@openai.com> Co-authored-by: Claude Fable 5 <noreply@anthropic.com>
csrc/libtorch_stable/ops.h
cpp
Apache-2.0
#pragma once #include <torch/csrc/stable/library.h> #include <torch/csrc/stable/tensor.h> #include <torch/headeronly/util/Exception.h> #include <optional> #include <string> #include <vector> #include <torch/csrc/stable/ops.h> inline torch::stable::Tensor weak_ref_tensor(torch::stable::Tensor& tensor) { // Ensure ...
#pragma once #include <torch/csrc/stable/library.h> #include <torch/csrc/stable/tensor.h> #include <torch/headeronly/util/Exception.h> #include <optional> #include <string> #include <vector> #include <torch/csrc/stable/ops.h> inline torch::stable::Tensor weak_ref_tensor(torch::stable::Tensor& tensor) { // Ensure ...
--- csrc/libtorch_stable/ops.h +++ csrc/libtorch_stable/ops.h @@ -400,6 +400,18 @@ torch::stable::Tensor& out, std::optional<double> lower_bound, std::optional<torch::stable::Tensor> output_gate, std::optional<torch::stable::Tensor> norm_weight, double norm_eps); + +void fused_gdn_decode_post_conv_mtp( +...
12
0
3
[ "qwen" ]
[]
[]
Optimize this cpp kernel file from vllm (csrc/libtorch_stable/ops.h). Goal: [Kernel][Perf] Add fused CUDA post-conv MTP decode kernel for Qwen3.5 GDN Target hardware: unspecified Target models: qwen Current file: ```cpp #pragma once #include <torch/csrc/stable/library.h> #include <torch/csrc/stable/tensor.h> #includ...
## Purpose ...
[{"scope": "kernel", "hardware": "B200", "model": "Qwen3.5", "shape": "K=128,V=128,H=4,HV=32", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 20.31, "optimized": 12.19, "stated_speedup": 1.67, "speedup": 1.6661}, {"scope": "kernel", "hardware": "B200", "model": "Qwen3.5", "sh...
1.521
null
vllm
1be36283678a9a94fc8fdaad6c95c2896d6b4015
2026-08-14T11:44:45+08:00
51,674
https://github.com/vllm-project/vllm/pull/51674
[Kernel][Perf] Add fused CUDA post-conv MTP decode kernel for Qwen3.5 GDN (#51674)
[Kernel][Perf] Add fused CUDA post-conv MTP decode kernel for Qwen3.5 GDN (#51674) Signed-off-by: Jie Fang <jief@nvidia.com> Co-authored-by: OpenAI Codex <codex@openai.com> Co-authored-by: Claude Fable 5 <noreply@anthropic.com>
csrc/libtorch_stable/torch_bindings.cpp
cpp
Apache-2.0
#include "ops.h" #include "cuda_utils.h" #include "core/registration.h" #include <torch/csrc/stable/library.h> // Register ops with STABLE_TORCH_LIBRARY for libtorch stable ABI compatibility. // Note: We register under namespace "_C" so ops are accessible as // torch.ops._C.<op_name> for compatibility with existing c...
#include "ops.h" #include "cuda_utils.h" #include "core/registration.h" #include <torch/csrc/stable/library.h> // Register ops with STABLE_TORCH_LIBRARY for libtorch stable ABI compatibility. // Note: We register under namespace "_C" so ops are accessible as // torch.ops._C.<op_name> for compatibility with existing c...
--- csrc/libtorch_stable/torch_bindings.cpp +++ csrc/libtorch_stable/torch_bindings.cpp @@ -532,6 +532,15 @@ "Tensor state_indices, Tensor! state, Tensor! out, " "float? lower_bound=None, Tensor? output_gate=None, " "Tensor? norm_weight=None, float norm_eps=1e-5) -> ()"); +#endif + +#ifdef VLLM_ENA...
14
0
3
[ "qwen" ]
[]
[]
Optimize this cpp kernel file from vllm (csrc/libtorch_stable/torch_bindings.cpp). Goal: [Kernel][Perf] Add fused CUDA post-conv MTP decode kernel for Qwen3.5 GDN Target hardware: unspecified Target models: qwen Current file: ```cpp #include "ops.h" #include "cuda_utils.h" #include "core/registration.h" #include <to...
## Purpose ...
[{"scope": "kernel", "hardware": "B200", "model": "Qwen3.5", "shape": "K=128,V=128,H=4,HV=32", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 20.31, "optimized": 12.19, "stated_speedup": 1.67, "speedup": 1.6661}, {"scope": "kernel", "hardware": "B200", "model": "Qwen3.5", "sh...
1.521
null
vllm
1be36283678a9a94fc8fdaad6c95c2896d6b4015
2026-08-14T11:44:45+08:00
51,674
https://github.com/vllm-project/vllm/pull/51674
[Kernel][Perf] Add fused CUDA post-conv MTP decode kernel for Qwen3.5 GDN (#51674)
[Kernel][Perf] Add fused CUDA post-conv MTP decode kernel for Qwen3.5 GDN (#51674) Signed-off-by: Jie Fang <jief@nvidia.com> Co-authored-by: OpenAI Codex <codex@openai.com> Co-authored-by: Claude Fable 5 <noreply@anthropic.com>
vllm/model_executor/layers/mamba/gdn/qwen_gdn_linear_attn.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Inference-only Qwen3-Next/Qwen3.5 model.""" from typing import Literal import torch from einops import rearrange from torch import nn from vllm import envs from vllm._aiter_ops import rocm_aiter_ops from vll...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Inference-only Qwen3-Next/Qwen3.5 model.""" import os from typing import Literal import torch from einops import rearrange from torch import nn from vllm import _custom_ops as ops from vllm import envs from ...
--- vllm/model_executor/layers/mamba/gdn/qwen_gdn_linear_attn.py +++ vllm/model_executor/layers/mamba/gdn/qwen_gdn_linear_attn.py @@ -2,12 +2,14 @@ # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Inference-only Qwen3-Next/Qwen3.5 model.""" +import os from typing import Literal import tor...
303
4
3
[ "qwen", "mamba" ]
[]
[]
Optimize this triton kernel file from vllm (vllm/model_executor/layers/mamba/gdn/qwen_gdn_linear_attn.py). Goal: [Kernel][Perf] Add fused CUDA post-conv MTP decode kernel for Qwen3.5 GDN Target hardware: unspecified Target models: qwen, mamba Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCo...
## Purpose ...
[{"scope": "kernel", "hardware": "B200", "model": "Qwen3.5", "shape": "K=128,V=128,H=4,HV=32", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 20.31, "optimized": 12.19, "stated_speedup": 1.67, "speedup": 1.6661}, {"scope": "kernel", "hardware": "B200", "model": "Qwen3.5", "sh...
1.521
null
vllm
98f86b9c02329200a0390aecfe598e27928cbf40
2026-08-12T18:04:01-05:00
50,017
https://github.com/vllm-project/vllm/pull/50017
[ROCm] [bugfix] Chunked prefill paged decode masked load perf (#50017)
[ROCm] [bugfix] Chunked prefill paged decode masked load perf (#50017) Signed-off-by: Andy Friedrich <afriedri@amd.com>
vllm/v1/attention/ops/chunked_prefill_paged_decode.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project # Authors: # - Burkhard Ringlein <ngl@zurich.ibm.com> # - Jan van Lunteren <jvl@zurich.ibm.com> # - Chih-Chieh Yang <chih.chieh.yang@ibm.com> # - Thomas Parnell <tpa@zurich.ibm.com> import torch from vllm i...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project # Authors: # - Burkhard Ringlein <ngl@zurich.ibm.com> # - Jan van Lunteren <jvl@zurich.ibm.com> # - Chih-Chieh Yang <chih.chieh.yang@ibm.com> # - Thomas Parnell <tpa@zurich.ibm.com> import torch from vllm i...
--- vllm/v1/attention/ops/chunked_prefill_paged_decode.py +++ vllm/v1/attention/ops/chunked_prefill_paged_decode.py @@ -156,11 +156,6 @@ # Supports non-contiguous mapping # from logical blocks to physical blocks abs_token_idx = start_n + offs_n - # Slots >= seq_len are unwritten KV cac...
34
20
1
[]
[ "ROCM" ]
[]
Optimize this triton kernel file from vllm (vllm/v1/attention/ops/chunked_prefill_paged_decode.py). Goal: [ROCm] [bugfix] Chunked prefill paged decode masked load perf Target hardware: ROCM Target models: unspecified Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright con...
## Purpose Observed 10-15% latency performance regression for serving Qwen/Qwen3-30B-A3B-Thinking-2507; trace revealed that `kernel_paged_attention_2d` was the culprit, taking 1.33x as long on average on v0.25.0 vs v0.24.0. #47305 fixed correctness but introduced performance drop because of universally applied maskin...
[{"scope": "e2e", "hardware": null, "model": "Qwen/Qwen3-30B-A3B-Thinking-2507", "shape": null, "batch_size": 1, "metric": "throughput", "unit": "tok/s", "higher_is_better": true, "baseline": 91.33, "optimized": 97.08, "stated_speedup": null, "speedup": 1.063}, {"scope": "e2e", "hardware": null, "model": "Qwen/Qwen3-30...
null
1.045
vllm
c76a425278bc41e9d661a377d7c166f5be42cf6b
2026-08-10T22:23:43-07:00
51,739
https://github.com/vllm-project/vllm/pull/51739
[Kernel] Optimize long-context MLA cache gathers (#51739)
[Kernel] Optimize long-context MLA cache gathers (#51739) Signed-off-by: Yongye Zhu <zyy1102000@gmail.com> Co-authored-by: OpenAI Codex <noreply@openai.com> Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
csrc/libtorch_stable/cache_kernels.cu
cuda
Apache-2.0
#include "torch_utils.h" #include "dispatch_utils.h" #include "../cuda_utils.h" #include "../cuda_compat.h" #include "quantization/vectorization_utils.cuh" #include "concat_mla_q.cuh" #ifdef USE_ROCM #include "../quantization/w8a8/fp8/amd/quant_utils.cuh" #else #include "../quantization/w8a8/fp8/nvidia/quant_uti...
#include "torch_utils.h" #include "dispatch_utils.h" #include "../cuda_utils.h" #include "../cuda_compat.h" #include "quantization/vectorization_utils.cuh" #include "concat_mla_q.cuh" #ifdef USE_ROCM #include "../quantization/w8a8/fp8/amd/quant_utils.cuh" #else #include "../quantization/w8a8/fp8/nvidia/quant_uti...
--- csrc/libtorch_stable/cache_kernels.cu +++ csrc/libtorch_stable/cache_kernels.cu @@ -1032,83 +1032,121 @@ namespace vllm { -// grid is launched with dimensions (batch, num_splits) +struct GatherPageTask { + int32_t req_id; + int32_t logical_block; + int32_t page_token_begin; + int32_t page_token_end; + int...
337
243
2
[]
[]
[]
Optimize this cuda kernel file from vllm (csrc/libtorch_stable/cache_kernels.cu). Goal: [Kernel] Optimize long-context MLA cache gathers Target hardware: unspecified Target models: unspecified Current file: ```cuda #include "torch_utils.h" #include "dispatch_utils.h" #include "../cuda_utils.h" #include "../cuda_comp...
## Summary - schedule MLA cache gathers by logical cache page instead of independently mapping every output token - flatten page copies/conversions to generate coalesced vector loads and stores, including partial first/last pages and nonzero `seq_starts` - coalesce FP8-to-BF16 stores and tune CTA geometry for long, un...
[{"scope": "kernel", "hardware": "NVIDIA GB300", "model": null, "shape": "60K", "batch_size": null, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 4231.14, "optimized": 19.17, "stated_speedup": 220.7, "speedup": 220.7167}, {"scope": "kernel", "hardware": "NVIDIA GB300", "model": null, "shape"...
1.6807
null
vllm
9e6be4a72bd29ecf2168a41f659aebfe2cdeda4a
2026-08-08T16:32:40-07:00
50,365
https://github.com/vllm-project/vllm/pull/50365
[Perf][Sparse MLA] Drop the atomic contention in the index remap (#50365)
[Perf][Sparse MLA] Drop the atomic contention in the index remap (#50365) Signed-off-by: Nick Hill <nickhill123@gmail.com> Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
vllm/v1/attention/backends/mla/sparse_utils.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Utility functions for sparse MLA backends.""" import torch from vllm.triton_utils import tl, triton # Kernel with prefill workspace support and valid count tracking @triton.jit def _convert_req_index_to_glo...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Utility functions for sparse MLA backends.""" import torch from vllm.triton_utils import tl, triton # Kernel with prefill workspace support and valid count tracking @triton.jit def _convert_req_index_to_glo...
--- vllm/v1/attention/backends/mla/sparse_utils.py +++ vllm/v1/attention/backends/mla/sparse_utils.py @@ -23,6 +23,9 @@ BLOCK_N: tl.constexpr, # tile width along columns HAS_PREFILL: tl.constexpr, COUNT_VALID: tl.constexpr, # whether to count valid indices + # BLOCK_N == NUM_TOPK_TOKENS: one program...
61
16
1
[]
[]
[]
Optimize this triton kernel file from vllm (vllm/v1/attention/backends/mla/sparse_utils.py). Goal: [Perf][Sparse MLA] Drop the atomic contention in the index remap Target hardware: unspecified Target models: unspecified Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright ...
The sparse-MLA index remap splits each 2048-wide row into 16 column tiles. On the valid-count path every tile atomic-adds into the same per-row counter, so the row total is built under 16-way contention -- and the DCP compaction path uses that same counter as an atomic slot allocator. Counting is the only reason the t...
[{"scope": "kernel", "hardware": "GB200", "model": null, "shape": "index_topk=512, 4 tiles", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 2.5, "optimized": 1.67, "stated_speedup": null, "speedup": 1.497}, {"scope": "kernel", "hardware": "GB200", "model": null, "shape": "ind...
2.186
null
vllm
700d39b55813fce6fe5339b334beb55d2a39f598
2026-08-07T21:56:14-07:00
50,949
https://github.com/vllm-project/vllm/pull/50949
[CPU] Optimize routed FP8/MXFP4 MoE GEMM dispatch (#50949)
[CPU] Optimize routed FP8/MXFP4 MoE GEMM dispatch (#50949) Signed-off-by: Li, Tianmu <tianmu.li@intel.com>
csrc/cpu/sgl-kernels/gemm.h
cpp
Apache-2.0
// Adapted from // https://github.com/sgl-project/sglang/tree/main/sgl-kernel/csrc/cpu // clang-format off #pragma once #include "common.h" #include "blas_gemm.h" #if defined(__AVX512F__) && defined(__AVX512BF16__) && defined(__AMX_BF16__) #define CPU_CAPABILITY_AVX512 #endif // amx-bf16 #define TILE_M 16 #define T...
// Adapted from // https://github.com/sgl-project/sglang/tree/main/sgl-kernel/csrc/cpu // clang-format off #pragma once #include "common.h" #include "blas_gemm.h" #if defined(__AVX512F__) && defined(__AVX512BF16__) && defined(__AMX_BF16__) #define CPU_CAPABILITY_AVX512 #endif // amx-bf16 #define TILE_M 16 #define T...
--- csrc/cpu/sgl-kernels/gemm.h +++ csrc/cpu/sgl-kernels/gemm.h @@ -57,6 +57,11 @@ template <> inline bool can_use_brgemm<at::Float8_e4m3fn>(int M) { return brgemm_supported() && M > 4; +} + +template <typename T> +inline bool can_use_brgemm(int M, int N) { + return brgemm_supported() && (can_use_brgemm<T>(M) || ...
5
0
2
[]
[ "CPU" ]
[]
Optimize this cpp kernel file from vllm (csrc/cpu/sgl-kernels/gemm.h). Goal: [CPU] Optimize routed FP8/MXFP4 MoE GEMM dispatch Target hardware: CPU Target models: unspecified Current file: ```cpp // Adapted from // https://github.com/sgl-project/sglang/tree/main/sgl-kernel/csrc/cpu // clang-format off #pragma once ...
## Purpose Remove the fixed global crossover from routed CPU FP8/MXFP4 MoE dispatch so that concentrated moe routing can benefit from brgemm. Select BRGEMM from each expert block's actual `M` and `N` and cover small expert blocks with the existing fixed-row TinyGEMM kernels. Dense and shared-expert dispatch remains u...
[{"scope": "e2e", "hardware": null, "model": "Qwen3-Coder-30B-A3B-Instruct-FP8", "shape": null, "batch_size": 256, "metric": "throughput", "unit": "tok/s", "higher_is_better": true, "baseline": 611.7, "optimized": 975.9, "stated_speedup": 1.5954, "speedup": 1.5954}, {"scope": "e2e", "hardware": null, "model": "GPT-OSS-...
null
1.0865
vllm
700d39b55813fce6fe5339b334beb55d2a39f598
2026-08-07T21:56:14-07:00
50,949
https://github.com/vllm-project/vllm/pull/50949
[CPU] Optimize routed FP8/MXFP4 MoE GEMM dispatch (#50949)
[CPU] Optimize routed FP8/MXFP4 MoE GEMM dispatch (#50949) Signed-off-by: Li, Tianmu <tianmu.li@intel.com>
csrc/cpu/sgl-kernels/moe_fp8.cpp
cpp
Apache-2.0
// Adapted from // https://github.com/sgl-project/sglang/tree/main/sgl-kernel/csrc/cpu // clang-format off #include "common.h" #include "gemm.h" #include "moe.h" template <typename scalar_t, typename packed_t, typename param_t, bool is_mxfp4> void fused_experts_fp_kernel_impl( scalar_t* __restrict__ output, ...
// Adapted from // https://github.com/sgl-project/sglang/tree/main/sgl-kernel/csrc/cpu // clang-format off #include "common.h" #include "gemm.h" #include "moe.h" template <typename scalar_t, typename packed_t, typename param_t, bool is_mxfp4> void fused_experts_fp_kernel_impl( scalar_t* __restrict__ output, ...
--- csrc/cpu/sgl-kernels/moe_fp8.cpp +++ csrc/cpu/sgl-kernels/moe_fp8.cpp @@ -60,9 +60,6 @@ const int64_t stride_e = 2 * N * packed_K; const int64_t stride_n = packed_K; - int64_t avg_M = std::max(int64_t(1), M * topk / E); - const bool use_brgemm = can_use_brgemm<packed_t>(avg_M); - int64_t B_tmp_size_per...
14
5
2
[]
[ "CPU" ]
[]
Optimize this cpp kernel file from vllm (csrc/cpu/sgl-kernels/moe_fp8.cpp). Goal: [CPU] Optimize routed FP8/MXFP4 MoE GEMM dispatch Target hardware: CPU Target models: unspecified Current file: ```cpp // Adapted from // https://github.com/sgl-project/sglang/tree/main/sgl-kernel/csrc/cpu // clang-format off #include...
## Purpose Remove the fixed global crossover from routed CPU FP8/MXFP4 MoE dispatch so that concentrated moe routing can benefit from brgemm. Select BRGEMM from each expert block's actual `M` and `N` and cover small expert blocks with the existing fixed-row TinyGEMM kernels. Dense and shared-expert dispatch remains u...
[{"scope": "e2e", "hardware": null, "model": "Qwen3-Coder-30B-A3B-Instruct-FP8", "shape": null, "batch_size": 256, "metric": "throughput", "unit": "tok/s", "higher_is_better": true, "baseline": 611.7, "optimized": 975.9, "stated_speedup": 1.5954, "speedup": 1.5954}, {"scope": "e2e", "hardware": null, "model": "GPT-OSS-...
null
1.0865
vllm
7b4ed49628abd7860a435d6798feef76a944cb02
2026-08-06T08:53:20-07:00
50,185
https://github.com/vllm-project/vllm/pull/50185
attn_res kernel latency improvements (#50185)
attn_res kernel latency improvements (#50185)
csrc/libtorch_stable/kimi_k3/attn_res_kernel.cu
cuda
Apache-2.0
/* * Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved. */ // Production AttnRes forward for Blackwell (SM100). // // Warp-specialized online softmax + residual + RMSNorm: // - 1 producer warp issues cp.async.bulk row loads into shared memory. // - 8 consumer warps compute reductions and output. // -...
/* * Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved. */ // Production AttnRes forward for Blackwell (SM100). // // Warp-specialized online softmax + residual + RMSNorm: // - 1 producer warp issues cp.async.bulk row loads into shared memory. // - 8 consumer warps compute reductions and output. // -...
--- csrc/libtorch_stable/kimi_k3/attn_res_kernel.cu +++ csrc/libtorch_stable/kimi_k3/attn_res_kernel.cu @@ -91,7 +91,8 @@ "bra WAIT;\n" "DONE:\n" "}\n" ::"r"(barrier_addr), - "r"(phase)); + "r"(phase) + : "memory"); } __device__ __forceinline__ void mbarrier_arrive(uint64_t& barr...
84
39
1
[ "kimi" ]
[]
[]
Optimize this cuda kernel file from vllm (csrc/libtorch_stable/kimi_k3/attn_res_kernel.cu). Goal: attn_res kernel latency improvements Target hardware: unspecified Target models: kimi Current file: ```cuda /* * Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved. */ // Production AttnRes forward for Blackw...
## Purpose A few small improvements to reduce the latency of the attention residual kernel: - Use vectorized loads when populating `q_cache` - Treat `B` and `N` as compile-time constants - Set `NC = 3` for low batch size path - Unroll the main loop over `num_chunks` ## Test Plan ``` pytest -v tests/models/kimi_k3/...
[{"scope": "kernel", "hardware": "GB300", "model": null, "shape": "tokens=1", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 5.23, "optimized": 4.16, "stated_speedup": null, "speedup": 1.2572}, {"scope": "kernel", "hardware": "GB300", "model": null, "shape": "tokens=8", "batc...
1.2163
1.0167
vllm
2dfb8ba59098eb489197e1b4c643addffd51592e
2026-08-06T15:53:17+08:00
50,230
https://github.com/vllm-project/vllm/pull/50230
[Perf][CUDA] Programmatic dependent launch for the DSA decode kernels (#50230)
[Perf][CUDA] Programmatic dependent launch for the DSA decode kernels (#50230) Signed-off-by: Peiyuan Zhou <peiyuanzhou1994@gmail.com> Co-authored-by: Claude <noreply@anthropic.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
csrc/libtorch_stable/quantization/fp4/nvfp4_quant_kernels.cu
cuda
Apache-2.0
/* * Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless requi...
/* * Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless requi...
--- csrc/libtorch_stable/quantization/fp4/nvfp4_quant_kernels.cu +++ csrc/libtorch_stable/quantization/fp4/nvfp4_quant_kernels.cu @@ -49,6 +49,11 @@ static_assert(sizeof(PackedVec) == sizeof(Type) * CVT_FP4_ELTS_PER_THREAD, "Vec size is not matched."); +#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH_...
40
10
1
[]
[]
[]
Optimize this cuda kernel file from vllm (csrc/libtorch_stable/quantization/fp4/nvfp4_quant_kernels.cu). Goal: [Perf][CUDA] Programmatic dependent launch for the DSA decode kernels Target hardware: unspecified Target models: unspecified Current file: ```cuda /* * Copyright (c) 2025, NVIDIA CORPORATION. All rights r...
## What this does Chain the DSA decode kernels with programmatic dependent launch so back-to-back small kernels overlap their launch latency: - the fused norm/rope and fused-q Triton kernels get a `USE_PDL` constexpr with `gdc_wait()` / `gdc_launch_dependents()`, launched with `launch_pdl` - the NVFP4 quant kernels...
[{"scope": "e2e", "hardware": "8\u00d7B300", "model": "nvidia/GLM-5.2-NVFP4", "shape": "MTP=5, 8192 input / 1024 output tokens", "batch_size": 64, "metric": "output tok/s", "unit": "tok/s", "higher_is_better": true, "baseline": 446.7, "optimized": 459.2, "stated_speedup": null, "speedup": 1.028}, {"scope": "e2e", "hard...
null
1.028
vllm
66b3c0e61f1e477820212201adf1ed871df7ee98
2026-08-05T22:33:49+08:00
50,294
https://github.com/vllm-project/vllm/pull/50294
[Kernel][Model] Optimize FA4 mm_prefix range lookup (#50294)
[Kernel][Model] Optimize FA4 mm_prefix range lookup (#50294) Signed-off-by: Juqi Li <2223621784@qq.com> Signed-off-by: Matthew Bonanni <mbonanni@redhat.com> Co-authored-by: Matthew Bonanni <mbonanni@redhat.com> Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com> Co-authored-by: mergify[bot] <37929162+me...
vllm/v1/attention/backends/flash_attn.py
cute_dsl
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Attention layer with FlashAttention.""" import copy from dataclasses import dataclass from typing import ClassVar import numpy as np import torch from vllm.model_executor.layers.attention import Attention fr...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Attention layer with FlashAttention.""" import copy import functools from dataclasses import dataclass from typing import ClassVar import numpy as np import torch from vllm.model_executor.layers.attention im...
--- vllm/v1/attention/backends/flash_attn.py +++ vllm/v1/attention/backends/flash_attn.py @@ -3,6 +3,7 @@ """Attention layer with FlashAttention.""" import copy +import functools from dataclasses import dataclass from typing import ClassVar @@ -12,6 +13,7 @@ from vllm.model_executor.layers.attention import Att...
111
46
3
[]
[]
[]
Optimize this cute_dsl kernel file from vllm (vllm/v1/attention/backends/flash_attn.py). Goal: [Kernel][Model] Optimize FA4 mm_prefix range lookup Target hardware: unspecified Target models: unspecified Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to t...
# [Kernel][Model] Gemma4: optimize FA4 mm_prefix range lookup and CuTe JIT stability ## Motivation Gemma4 multimodal models can use FA4 as the backend for all layers, so that both sliding-attention layers (`head_dim=256`) and global/full layers (`global_head_dim=512`) use one attention backend. This is required for t...
[{"scope": "e2e", "hardware": "H100", "model": "Gemma4 26B A4B MoE", "shape": "batch_max_ranges varies (8-64), avg 48 frames; text avg 885 tokens", "batch_size": 32, "metric": "QPS", "unit": "req/s", "higher_is_better": true, "baseline": 0.103, "optimized": 1.307, "stated_speedup": null, "speedup": 12.6893}, {"scope": ...
null
7.3085
vllm
df71917cf17c97d81f48122e6baa7c13d184ff90
2026-07-31T11:45:58-04:00
49,236
https://github.com/vllm-project/vllm/pull/49236
[DSv4 Perf] Optimize workspace reuse for eager break, 3.9% E2E TTFT improvement. (#49236)
[DSv4 Perf] Optimize workspace reuse for eager break, 3.9% E2E TTFT improvement. (#49236) Signed-off-by: yewentao256 <zhyanwentao@126.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
csrc/libtorch_stable/fused_deepseek_v4_qnorm_rope_kv_insert_kernel.cu
cuda
Apache-2.0
/* * SPDX-License-Identifier: Apache-2.0 * SPDX-FileCopyrightText: Copyright contributors to the vLLM project * * Horizontally-fused DeepseekV4-MLA kernel: * - Q side: per-head RMSNorm (no weight) + GPT-J RoPE on last ROPE_DIM * - KV side: GPT-J RoPE on last ROPE_DIM + UE8M0 FP8 quant on NoPE + paged * ...
/* * SPDX-License-Identifier: Apache-2.0 * SPDX-FileCopyrightText: Copyright contributors to the vLLM project * * Horizontally-fused DeepseekV4-MLA kernel: * - Q side: per-head RMSNorm (no weight) + GPT-J RoPE on last ROPE_DIM * - KV side: GPT-J RoPE on last ROPE_DIM + UE8M0 FP8 quant on NoPE + paged * ...
--- csrc/libtorch_stable/fused_deepseek_v4_qnorm_rope_kv_insert_kernel.cu +++ csrc/libtorch_stable/fused_deepseek_v4_qnorm_rope_kv_insert_kernel.cu @@ -942,9 +942,10 @@ // ──────────────────────────────────────────────────────────────────────────── // Torch op wrapper // ─────────────────────────────────────────────...
24
6
3
[ "deepseek" ]
[]
[]
Optimize this cuda kernel file from vllm (csrc/libtorch_stable/fused_deepseek_v4_qnorm_rope_kv_insert_kernel.cu). Goal: [DSv4 Perf] Optimize workspace reuse for eager break, 3.9% E2E TTFT improvement. Target hardware: unspecified Target models: deepseek Current file: ```cuda /* * SPDX-License-Identifier: Apache-2.0 ...
## Purpose Part of https://github.com/vllm-project/vllm/issues/45861 Optimize workspace reuse for eager break ## Test `vllm serve deepseek-ai/DeepSeek-V4-Flash --tensor-parallel-size 4 --enable-expert-parallel --attention-backend FLASHMLA_SPARSE_DSV4 --attention-config '{"use_fp4_indexer_cache":true}' --k...
[]
null
null
vllm
df71917cf17c97d81f48122e6baa7c13d184ff90
2026-07-31T11:45:58-04:00
49,236
https://github.com/vllm-project/vllm/pull/49236
[DSv4 Perf] Optimize workspace reuse for eager break, 3.9% E2E TTFT improvement. (#49236)
[DSv4 Perf] Optimize workspace reuse for eager break, 3.9% E2E TTFT improvement. (#49236) Signed-off-by: yewentao256 <zhyanwentao@126.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
csrc/libtorch_stable/ops.h
cpp
Apache-2.0
#pragma once #include <torch/csrc/stable/library.h> #include <torch/csrc/stable/tensor.h> #include <torch/headeronly/util/Exception.h> #include <optional> #include <string> #include <vector> #include <torch/csrc/stable/ops.h> inline torch::stable::Tensor weak_ref_tensor(torch::stable::Tensor& tensor) { // Ensure ...
#pragma once #include <torch/csrc/stable/library.h> #include <torch/csrc/stable/tensor.h> #include <torch/headeronly/util/Exception.h> #include <optional> #include <string> #include <vector> #include <torch/csrc/stable/ops.h> inline torch::stable::Tensor weak_ref_tensor(torch::stable::Tensor& tensor) { // Ensure ...
--- csrc/libtorch_stable/ops.h +++ csrc/libtorch_stable/ops.h @@ -265,6 +265,14 @@ torch::stable::Tensor fused_deepseek_v4_qnorm_rope_kv_rope_quant_insert( torch::stable::Tensor const& q_in, torch::stable::Tensor const& kv, torch::stable::Tensor& k_cache, torch::stable::Tensor const& slot_mapping, + torch...
8
0
3
[ "deepseek" ]
[]
[]
Optimize this cpp kernel file from vllm (csrc/libtorch_stable/ops.h). Goal: [DSv4 Perf] Optimize workspace reuse for eager break, 3.9% E2E TTFT improvement. Target hardware: unspecified Target models: deepseek Current file: ```cpp #pragma once #include <torch/csrc/stable/library.h> #include <torch/csrc/stable/tensor...
## Purpose Part of https://github.com/vllm-project/vllm/issues/45861 Optimize workspace reuse for eager break ## Test `vllm serve deepseek-ai/DeepSeek-V4-Flash --tensor-parallel-size 4 --enable-expert-parallel --attention-backend FLASHMLA_SPARSE_DSV4 --attention-config '{"use_fp4_indexer_cache":true}' --k...
[]
null
null
vllm
df71917cf17c97d81f48122e6baa7c13d184ff90
2026-07-31T11:45:58-04:00
49,236
https://github.com/vllm-project/vllm/pull/49236
[DSv4 Perf] Optimize workspace reuse for eager break, 3.9% E2E TTFT improvement. (#49236)
[DSv4 Perf] Optimize workspace reuse for eager break, 3.9% E2E TTFT improvement. (#49236) Signed-off-by: yewentao256 <zhyanwentao@126.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
csrc/libtorch_stable/torch_bindings.cpp
cpp
Apache-2.0
#include "ops.h" #include "cuda_utils.h" #include "core/registration.h" #include <torch/csrc/stable/library.h> // Register ops with STABLE_TORCH_LIBRARY for libtorch stable ABI compatibility. // Note: We register under namespace "_C" so ops are accessible as // torch.ops._C.<op_name> for compatibility with existing c...
#include "ops.h" #include "cuda_utils.h" #include "core/registration.h" #include <torch/csrc/stable/library.h> // Register ops with STABLE_TORCH_LIBRARY for libtorch stable ABI compatibility. // Note: We register under namespace "_C" so ops are accessible as // torch.ops._C.<op_name> for compatibility with existing c...
--- csrc/libtorch_stable/torch_bindings.cpp +++ csrc/libtorch_stable/torch_bindings.cpp @@ -433,6 +433,11 @@ "Tensor q_in, Tensor kv, Tensor! k_cache, " "Tensor slot_mapping, Tensor position_ids, Tensor cos_sin_cache, " "int q_head_padded, float eps, int cache_block_size) -> Tensor"); + ops.def( +...
7
0
3
[ "deepseek" ]
[]
[]
Optimize this cpp kernel file from vllm (csrc/libtorch_stable/torch_bindings.cpp). Goal: [DSv4 Perf] Optimize workspace reuse for eager break, 3.9% E2E TTFT improvement. Target hardware: unspecified Target models: deepseek Current file: ```cpp #include "ops.h" #include "cuda_utils.h" #include "core/registration.h" #...
## Purpose Part of https://github.com/vllm-project/vllm/issues/45861 Optimize workspace reuse for eager break ## Test `vllm serve deepseek-ai/DeepSeek-V4-Flash --tensor-parallel-size 4 --enable-expert-parallel --attention-backend FLASHMLA_SPARSE_DSV4 --attention-config '{"use_fp4_indexer_cache":true}' --k...
[]
null
null
vllm
88bc8fb56f69667bcb67b482ecf729385d7ae972
2026-07-31T15:19:31+05:30
50,219
https://github.com/vllm-project/vllm/pull/50219
[CPU][s390x] Optimize inference perf and add oneDNN INT8 GEMM for s390x (#50219)
[CPU][s390x] Optimize inference perf and add oneDNN INT8 GEMM for s390x (#50219) Signed-off-by: Rehan Khan <Rehan.Khan7@ibm.com> Co-authored-by: Li, Jiang <jiang1.li@intel.com>
csrc/cpu/cpu_arch_macros.h
cpp
Apache-2.0
#ifndef CPU_ARCH_MACROS_H #define CPU_ARCH_MACROS_H // x86_64 #ifdef __x86_64__ #define FAST_SPINNING _mm_pause(); #ifdef __AVX512F__ #define DEFINE_FAST_EXP \ const __m512 vec_factorial_1 = _mm512_set1_ps(0.999999701f); \ const __m512...
#ifndef CPU_ARCH_MACROS_H #define CPU_ARCH_MACROS_H // x86_64 #ifdef __x86_64__ #define FAST_SPINNING _mm_pause(); #ifdef __AVX512F__ #define DEFINE_FAST_EXP \ const __m512 vec_factorial_1 = _mm512_set1_ps(0.999999701f); \ const __m512...
--- csrc/cpu/cpu_arch_macros.h +++ csrc/cpu/cpu_arch_macros.h @@ -183,4 +183,15 @@ #endif // __powerpc__ +// IBM Z (s390x) VXE +#ifdef __s390x__ + // FP32Vec16::exp() in cpu_types_vxe.hpp delegates to FP32Vec8::exp(), which + // implements a vectorised 5-term minimax polynomial using VXE intrinsics. + #define ...
11
0
3
[]
[ "CPU" ]
[]
Optimize this cpp kernel file from vllm (csrc/cpu/cpu_arch_macros.h). Goal: [CPU][s390x] Optimize inference perf and add oneDNN INT8 GEMM for s390x Target hardware: CPU Target models: unspecified Current file: ```cpp #ifndef CPU_ARCH_MACROS_H #define CPU_ARCH_MACROS_H // x86_64 #ifdef __x86_64__ #define FAST_SPINN...
## Purpose Enable s390x specific CPU optimizations: - Wire DEFINE_FAST_EXP for attention softmax via VXE minimax polynomial - Add vectorized reduce_sum/reduce_max using vec_add/vec_max/vec_sld - Add INT8Vec16 for FP32→INT8 packing (vec_cts/vec_packs) - Add FP32Vec16 exp/abs/min/clamp/reduce_min for dnnl_kernels support...
[]
null
null
vllm
88bc8fb56f69667bcb67b482ecf729385d7ae972
2026-07-31T15:19:31+05:30
50,219
https://github.com/vllm-project/vllm/pull/50219
[CPU][s390x] Optimize inference perf and add oneDNN INT8 GEMM for s390x (#50219)
[CPU][s390x] Optimize inference perf and add oneDNN INT8 GEMM for s390x (#50219) Signed-off-by: Rehan Khan <Rehan.Khan7@ibm.com> Co-authored-by: Li, Jiang <jiang1.li@intel.com>
csrc/cpu/cpu_types_vxe.hpp
cpp
Apache-2.0
#ifndef CPU_TYPES_VXE_HPP #define CPU_TYPES_VXE_HPP #include <vecintrin.h> #include <bit> #include <cmath> #include <cstdint> #include <limits> #include <torch/all.h> namespace vec_op { struct fp8_e4m3_tag {}; struct fp8_e5m2_tag {}; #define vec_neg(a) (-(a)) #define vec_add(a, b) ((a) + (b)) #define vec_sub(a, b) ...
#ifndef CPU_TYPES_VXE_HPP #define CPU_TYPES_VXE_HPP #include <vecintrin.h> #include <bit> #include <cmath> #include <cstdint> #include <limits> #include <torch/all.h> namespace vec_op { struct fp8_e4m3_tag {}; struct fp8_e5m2_tag {}; #define vec_neg(a) (-(a)) #define vec_add(a, b) ((a) + (b)) #define vec_sub(a, b) ...
--- csrc/cpu/cpu_types_vxe.hpp +++ csrc/cpu/cpu_types_vxe.hpp @@ -140,9 +140,20 @@ explicit BF16Vec16(const FP32Vec16&); void save(void* ptr) const { - // Save 256 bits in two parts vec_xst(reg.val[0], 0, (signed short*)ptr); vec_xst(reg.val[1], 16, (signed short*)ptr); + } + + void save(void* pt...
150
22
3
[]
[ "CPU" ]
[]
Optimize this cpp kernel file from vllm (csrc/cpu/cpu_types_vxe.hpp). Goal: [CPU][s390x] Optimize inference perf and add oneDNN INT8 GEMM for s390x Target hardware: CPU Target models: unspecified Current file: ```cpp #ifndef CPU_TYPES_VXE_HPP #define CPU_TYPES_VXE_HPP #include <vecintrin.h> #include <bit> #include ...
## Purpose Enable s390x specific CPU optimizations: - Wire DEFINE_FAST_EXP for attention softmax via VXE minimax polynomial - Add vectorized reduce_sum/reduce_max using vec_add/vec_max/vec_sld - Add INT8Vec16 for FP32→INT8 packing (vec_cts/vec_packs) - Add FP32Vec16 exp/abs/min/clamp/reduce_min for dnnl_kernels support...
[]
null
null
vllm
88bc8fb56f69667bcb67b482ecf729385d7ae972
2026-07-31T15:19:31+05:30
50,219
https://github.com/vllm-project/vllm/pull/50219
[CPU][s390x] Optimize inference perf and add oneDNN INT8 GEMM for s390x (#50219)
[CPU][s390x] Optimize inference perf and add oneDNN INT8 GEMM for s390x (#50219) Signed-off-by: Rehan Khan <Rehan.Khan7@ibm.com> Co-authored-by: Li, Jiang <jiang1.li@intel.com>
csrc/cpu/torch_bindings.cpp
cpp
Apache-2.0
#include "cache.h" #include "ops.h" #include "core/registration.h" #include <torch/library.h> // Note: overwrite the external definition for sharing same name between // libraries use different ISAs. #define TORCH_EXTENSION_NAME _C void release_dnnl_matmul_handler(int64_t handler); int64_t create_onednn_scaled_mm_h...
#include "cache.h" #include "ops.h" #include "core/registration.h" #include <torch/library.h> // Note: overwrite the external definition for sharing same name between // libraries use different ISAs. #define TORCH_EXTENSION_NAME _C void release_dnnl_matmul_handler(int64_t handler); int64_t create_onednn_scaled_mm_h...
--- csrc/cpu/torch_bindings.cpp +++ csrc/cpu/torch_bindings.cpp @@ -398,7 +398,7 @@ // Quantization #if defined(__AVX512F__) || defined(__AVX2__) || \ (defined(__aarch64__) && !defined(__APPLE__)) || defined(__powerpc64__) || \ - defined(__riscv_v) + defined(__riscv_v) || de...
1
1
3
[]
[ "CPU" ]
[]
Optimize this cpp kernel file from vllm (csrc/cpu/torch_bindings.cpp). Goal: [CPU][s390x] Optimize inference perf and add oneDNN INT8 GEMM for s390x Target hardware: CPU Target models: unspecified Current file: ```cpp #include "cache.h" #include "ops.h" #include "core/registration.h" #include <torch/library.h> // N...
## Purpose Enable s390x specific CPU optimizations: - Wire DEFINE_FAST_EXP for attention softmax via VXE minimax polynomial - Add vectorized reduce_sum/reduce_max using vec_add/vec_max/vec_sld - Add INT8Vec16 for FP32→INT8 packing (vec_cts/vec_packs) - Add FP32Vec16 exp/abs/min/clamp/reduce_min for dnnl_kernels support...
[]
null
null
vllm
82642d7d6c332fefdec06b260a246bd1a4ebf5ff
2026-07-29T16:45:38-04:00
49,750
https://github.com/vllm-project/vllm/pull/49750
[Perf] RMSNorm uncontiguous support, 1.2~3.1x kernel performance improvement (#49750)
[Perf] RMSNorm uncontiguous support, 1.2~3.1x kernel performance improvement (#49750) Signed-off-by: yewentao256 <zhyanwentao@126.com> Signed-off-by: Wentao Ye <44945378+yewentao256@users.noreply.github.com>
csrc/libtorch_stable/layernorm_kernels.cu
cuda
Apache-2.0
#include <numeric> #include "torch_utils.h" #include "cub_helpers.h" #include "../core/batch_invariant.hpp" #include "type_convert.cuh" #include "dispatch_utils.h" #include "quantization/vectorization_utils.cuh" namespace vllm { // TODO(woosuk): Further optimize this kernel. template <typename scalar_t, int VEC_SIZ...
#include <numeric> #include "torch_utils.h" #include "cub_helpers.h" #include "../core/batch_invariant.hpp" #include "type_convert.cuh" #include "dispatch_utils.h" #include "quantization/vectorization_utils.cuh" namespace vllm { // TODO(woosuk): Further optimize this kernel. template <typename scalar_t, int VEC_SIZ...
--- csrc/libtorch_stable/layernorm_kernels.cu +++ csrc/libtorch_stable/layernorm_kernels.cu @@ -110,7 +110,8 @@ const int64_t input_stride, scalar_t* __restrict__ residual, // [..., hidden_size] const scalar_t* __restrict__ weight, // [hidden_size], null if !HasWeight - const float epsilon, cons...
15
11
1
[]
[]
[ "3.1x" ]
Optimize this cuda kernel file from vllm (csrc/libtorch_stable/layernorm_kernels.cu). Goal: [Perf] RMSNorm uncontiguous support, 1.2~3.1x kernel performance improvement Target hardware: unspecified Target models: unspecified Current file: ```cuda #include <numeric> #include "torch_utils.h" #include "cub_helpers.h" ...
## Purpose Thanks @tlrmchlsmth for the context Part of https://github.com/vllm-project/vllm/issues/46654, mainly optimization for GLM5.2, but found that similar issues appear in a lot of other models so fixed accordingly. ## Test Covered in current unit tests Perf can be seen in this AI generated script ```bash #...
[{"scope": "kernel", "hardware": "NVIDIA B300 SXM6 AC", "model": null, "shape": "hidden_size=7168", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 10.2, "optimized": 8.31, "stated_speedup": 1.23, "speedup": 1.2274}, {"scope": "kernel", "hardware": "NVIDIA B300 SXM6 AC", "mode...
2.1208
null
vllm
05a08148631ab2d852c1984ddb3abebad8039a29
2026-07-28T11:50:10-05:00
49,906
https://github.com/vllm-project/vllm/pull/49906
[ROCm] Fix and optimize GPT-J-style MRoPE (#49906)
[ROCm] Fix and optimize GPT-J-style MRoPE (#49906) Signed-off-by: Andreas Karatzas <akaratza@amd.com>
vllm/model_executor/layers/rotary_embedding/mrope.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project import numpy as np import torch from vllm.triton_utils import tl, triton from .base import RotaryEmbeddingBase from .yarn_scaling_rope import YaRNScalingRotaryEmbedding, yarn_get_mscale @triton.jit def _trit...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project import numpy as np import torch from vllm.platforms import current_platform from vllm.triton_utils import tl, triton from .base import RotaryEmbeddingBase from .yarn_scaling_rope import YaRNScalingRotaryEmbedd...
--- vllm/model_executor/layers/rotary_embedding/mrope.py +++ vllm/model_executor/layers/rotary_embedding/mrope.py @@ -5,6 +5,7 @@ import numpy as np import torch +from vllm.platforms import current_platform from vllm.triton_utils import tl, triton from .base import RotaryEmbeddingBase @@ -24,16 +25,17 @@ r...
99
62
1
[]
[ "ROCM" ]
[]
Optimize this triton kernel file from vllm (vllm/model_executor/layers/rotary_embedding/mrope.py). Goal: [ROCm] Fix and optimize GPT-J-style MRoPE Target hardware: ROCM Target models: unspecified Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM...
- Honor the existing adjacent-pair MRoPE setting instead of hardcoding NeoX pairing. - Use contiguous ROCm loads and stores with register-only split/interleave, preserving the NeoX and non-ROCm launch paths. https://buildkite.com/vllm/amd-ci/builds/11254/list?sid=019f966b-1ec6-4bee-8ce6-acf444a98979&tab=output
[]
null
null
vllm
a89015c6df8eeb37a843b717c97a5be1355de83d
2026-07-27T21:24:42+08:00
48,739
https://github.com/vllm-project/vllm/pull/48739
[Perf] Make merge attention context count a runtime argument (#48739)
[Perf] Make merge attention context count a runtime argument (#48739) Signed-off-by: liminfei-amd <91481003+liminfei-amd@users.noreply.github.com>
vllm/v1/attention/ops/triton_merge_attn_states.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project import torch from vllm.platforms import current_platform from vllm.triton_utils import tl, triton float8_info = torch.finfo(current_platform.fp8_dtype()) def mask_empty_context( lse: torch.Tensor, out...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project import torch from vllm.platforms import current_platform from vllm.triton_utils import tl, triton float8_info = torch.finfo(current_platform.fp8_dtype()) def mask_empty_context( lse: torch.Tensor, out...
--- vllm/v1/attention/ops/triton_merge_attn_states.py +++ vllm/v1/attention/ops/triton_merge_attn_states.py @@ -158,10 +158,10 @@ prefix_head_stride, output_head_stride, output_scale, + prefill_tokens_with_context, head_size, padded_head_size, output_lse is n...
2
2
1
[]
[]
[]
Optimize this triton kernel file from vllm (vllm/v1/attention/ops/triton_merge_attn_states.py). Goal: [Perf] Make merge attention context count a runtime argument Target hardware: unspecified Target models: unspecified Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright c...
## Summary Makes `merge_attn_states_kernel`'s batch-varying `prefill_tokens_with_context` a runtime argument instead of a `tl.constexpr`, preventing a new Triton specialization for each distinct value. Partial fix for #48650. ## Why this is not a duplicate Rechecked on 2026-07-15 immediately before preparing this dr...
[{"scope": "e2e", "hardware": "R9700 (gfx1201)", "model": null, "shape": null, "batch_size": null, "metric": "TTFT", "unit": "ms", "higher_is_better": false, "baseline": 69.78, "optimized": 56.38, "stated_speedup": null, "speedup": 1.2377}, {"scope": "e2e", "hardware": "R9700 (gfx1201)", "model": null, "shape": null, "...
null
1.256
vllm
544cb724c888dda1eff06a02cb0baca783c3dd86
2026-07-26T23:20:14-07:00
48,577
https://github.com/vllm-project/vllm/pull/48577
[CPU][Spec Decode] Optimize GDN conv path for speculative decoding (#48577)
[CPU][Spec Decode] Optimize GDN conv path for speculative decoding (#48577) Signed-off-by: Li, Tianmu <tianmu.li@intel.com> Co-authored-by: Codex <codex@openai.com> Co-authored-by: Li, Jiang <jiang1.li@intel.com>
csrc/cpu/sgl-kernels/conv.cpp
cpp
Apache-2.0
// Adapted from // https://github.com/sgl-project/sglang/tree/main/sgl-kernel/csrc/cpu // clang-format off #include "common.h" #include "gemm.h" #include "vec.h" namespace { template <typename scalar_t> inline void copy_stub(scalar_t* __restrict__ y, const scalar_t* __restrict__ x, int64_t size) { using Vec = at:...
// Adapted from // https://github.com/sgl-project/sglang/tree/main/sgl-kernel/csrc/cpu // clang-format off #include "common.h" #include "gemm.h" #include "vec.h" namespace { template <typename scalar_t> inline void copy_stub(scalar_t* __restrict__ y, const scalar_t* __restrict__ x, int64_t size) { using Vec = at:...
--- csrc/cpu/sgl-kernels/conv.cpp +++ csrc/cpu/sgl-kernels/conv.cpp @@ -451,6 +451,90 @@ }); } +template <typename scalar_t> +void causal_conv1d_update_multi_kernel_impl( + scalar_t* __restrict__ out, + const scalar_t* __restrict__ input, + scalar_t* __restrict__ conv_states, + const scalar_t* __restr...
173
12
3
[]
[ "CPU" ]
[]
Optimize this cpp kernel file from vllm (csrc/cpu/sgl-kernels/conv.cpp). Goal: [CPU][Spec Decode] Optimize GDN conv path for speculative decoding Target hardware: CPU Target models: unspecified Current file: ```cpp // Adapted from // https://github.com/sgl-project/sglang/tree/main/sgl-kernel/csrc/cpu // clang-format...
## Purpose Improve CPU serving performance for Qwen3.5 GDN speculative decoding with MTP by replacing fallback torch conv1d path with cpp implementation when AMX is available. ## Test Plan Perf: Server: ```bash VLLM_CPU_SGL_KERNEL=1 \ vllm serve Qwen/Qwen3.5-9B \ --max-model-len 2048 \ --max-num-seqs 8 \ --li...
[{"scope": "e2e", "hardware": null, "model": "Qwen/Qwen3.5-9B", "shape": null, "batch_size": null, "metric": "throughput", "unit": "tok/s", "higher_is_better": true, "baseline": 70.29, "optimized": 70.16, "stated_speedup": null, "speedup": 0.9982}, {"scope": "e2e", "hardware": null, "model": "Qwen/Qwen3.5-9B", "shape":...
null
1.1725
vllm
544cb724c888dda1eff06a02cb0baca783c3dd86
2026-07-26T23:20:14-07:00
48,577
https://github.com/vllm-project/vllm/pull/48577
[CPU][Spec Decode] Optimize GDN conv path for speculative decoding (#48577)
[CPU][Spec Decode] Optimize GDN conv path for speculative decoding (#48577) Signed-off-by: Li, Tianmu <tianmu.li@intel.com> Co-authored-by: Codex <codex@openai.com> Co-authored-by: Li, Jiang <jiang1.li@intel.com>
csrc/cpu/torch_bindings.cpp
cpp
Apache-2.0
#include "cache.h" #include "ops.h" #include "core/registration.h" #include <torch/library.h> // Note: overwrite the external definition for sharing same name between // libraries use different ISAs. #define TORCH_EXTENSION_NAME _C void release_dnnl_matmul_handler(int64_t handler); int64_t create_onednn_scaled_mm_h...
#include "cache.h" #include "ops.h" #include "core/registration.h" #include <torch/library.h> // Note: overwrite the external definition for sharing same name between // libraries use different ISAs. #define TORCH_EXTENSION_NAME _C void release_dnnl_matmul_handler(int64_t handler); int64_t create_onednn_scaled_mm_h...
--- csrc/cpu/torch_bindings.cpp +++ csrc/cpu/torch_bindings.cpp @@ -147,7 +147,7 @@ at::Tensor causal_conv1d_update_cpu( const at::Tensor& x, const at::Tensor& conv_states, const at::Tensor& weight, const std::optional<at::Tensor>& bias, - bool silu_activation, const std::optional<at::Tensor>& cache_seqle...
3
2
3
[]
[ "CPU" ]
[]
Optimize this cpp kernel file from vllm (csrc/cpu/torch_bindings.cpp). Goal: [CPU][Spec Decode] Optimize GDN conv path for speculative decoding Target hardware: CPU Target models: unspecified Current file: ```cpp #include "cache.h" #include "ops.h" #include "core/registration.h" #include <torch/library.h> // Note: ...
## Purpose Improve CPU serving performance for Qwen3.5 GDN speculative decoding with MTP by replacing fallback torch conv1d path with cpp implementation when AMX is available. ## Test Plan Perf: Server: ```bash VLLM_CPU_SGL_KERNEL=1 \ vllm serve Qwen/Qwen3.5-9B \ --max-model-len 2048 \ --max-num-seqs 8 \ --li...
[{"scope": "e2e", "hardware": null, "model": "Qwen/Qwen3.5-9B", "shape": null, "batch_size": null, "metric": "throughput", "unit": "tok/s", "higher_is_better": true, "baseline": 70.29, "optimized": 70.16, "stated_speedup": null, "speedup": 0.9982}, {"scope": "e2e", "hardware": null, "model": "Qwen/Qwen3.5-9B", "shape":...
null
1.1725
vllm
c314af1abfddff7b6cce9af578be72c496c6a5e4
2026-07-27T06:53:09+01:00
48,637
https://github.com/vllm-project/vllm/pull/48637
[CPU][Perf] INT8 Fused MoE Kernel for Arm CPUs (#48637)
[CPU][Perf] INT8 Fused MoE Kernel for Arm CPUs (#48637) Signed-off-by: Fadi Arafeh <fadi.arafeh@arm.com> Co-authored-by: Li, Jiang <jiang1.li@intel.com>
csrc/cpu/cpu_fused_moe.cpp
cpp
Apache-2.0
#include "cpu/cpu_types.hpp" #include "cpu/utils.hpp" #include "cpu/micro_gemm/cpu_micro_gemm_vec.hpp" #include "cpu/cpu_arch_macros.h" #ifdef CPU_CAPABILITY_AMXBF16 #include "cpu/micro_gemm/cpu_micro_gemm_amx.hpp" #define AMX_DISPATCH(...) \ case cpu_utils::I...
#include "cpu/cpu_types.hpp" #include "cpu/utils.hpp" #include "cpu/cpu_fused_moe_activations.hpp" #include "cpu/micro_gemm/cpu_micro_gemm_vec.hpp" #include "cpu/cpu_arch_macros.h" #ifdef CPU_CAPABILITY_AMXBF16 #include "cpu/micro_gemm/cpu_micro_gemm_amx.hpp" #define AMX_DISPATCH(...) ...
--- csrc/cpu/cpu_fused_moe.cpp +++ csrc/cpu/cpu_fused_moe.cpp @@ -1,5 +1,6 @@ #include "cpu/cpu_types.hpp" #include "cpu/utils.hpp" +#include "cpu/cpu_fused_moe_activations.hpp" #include "cpu/micro_gemm/cpu_micro_gemm_vec.hpp" #include "cpu/cpu_arch_macros.h" @@ -43,193 +44,9 @@ }() namespace { -enum class ...
6
188
6
[]
[ "CPU" ]
[]
Optimize this cpp kernel file from vllm (csrc/cpu/cpu_fused_moe.cpp). Goal: [CPU][Perf] INT8 Fused MoE Kernel for Arm CPUs Target hardware: CPU Target models: unspecified Current file: ```cpp #include "cpu/cpu_types.hpp" #include "cpu/utils.hpp" #include "cpu/micro_gemm/cpu_micro_gemm_vec.hpp" #include "cpu/cpu_arch_...
## Purpose Enable W8A8 (per token input, channelweise weights) MoE checkpoints like `RedHatAI/Qwen3-30B-A3B-Thinking-2507-quantized.w8a8` on Arm CPUs To achieve this, we: - reuse the structure of the existing bf16 grouped gemm kernel in the int8 kernel (I tried to extend the existing bf16 grouped gemm kernel to suppo...
[]
null
null
vllm
c314af1abfddff7b6cce9af578be72c496c6a5e4
2026-07-27T06:53:09+01:00
48,637
https://github.com/vllm-project/vllm/pull/48637
[CPU][Perf] INT8 Fused MoE Kernel for Arm CPUs (#48637)
[CPU][Perf] INT8 Fused MoE Kernel for Arm CPUs (#48637) Signed-off-by: Fadi Arafeh <fadi.arafeh@arm.com> Co-authored-by: Li, Jiang <jiang1.li@intel.com>
csrc/cpu/micro_gemm/cpu_micro_gemm_impl.hpp
cpp
Apache-2.0
#ifndef CPU_MICRO_GEMM_IMPL_HPP #define CPU_MICRO_GEMM_IMPL_HPP #include "cpu/utils.hpp" #include "cpu/cpu_types.hpp" namespace cpu_micro_gemm { #define DEFINE_CPU_MICRO_GEMM_PARAMS \ scalar_t *__restrict__ a_ptr, scalar_t *__restrict__ b_ptr, \ float *__res...
#ifndef CPU_MICRO_GEMM_IMPL_HPP #define CPU_MICRO_GEMM_IMPL_HPP #include "cpu/utils.hpp" #include "cpu/cpu_types.hpp" namespace cpu_micro_gemm { #define DEFINE_CPU_MICRO_GEMM_PARAMS \ scalar_t *__restrict__ a_ptr, scalar_t *__restrict__ b_ptr, \ float *__res...
--- csrc/cpu/micro_gemm/cpu_micro_gemm_impl.hpp +++ csrc/cpu/micro_gemm/cpu_micro_gemm_impl.hpp @@ -30,6 +30,9 @@ TORCH_CHECK(false, "Unimplemented MicroGemm."); } }; + +template <cpu_utils::ISA isa, typename scalar_t> +class MicroGemmINT8; template <int32_t n_size, typename scalar_t> FORCE_INLINE void def...
3
0
6
[]
[ "CPU" ]
[]
Optimize this cpp kernel file from vllm (csrc/cpu/micro_gemm/cpu_micro_gemm_impl.hpp). Goal: [CPU][Perf] INT8 Fused MoE Kernel for Arm CPUs Target hardware: CPU Target models: unspecified Current file: ```cpp #ifndef CPU_MICRO_GEMM_IMPL_HPP #define CPU_MICRO_GEMM_IMPL_HPP #include "cpu/utils.hpp" #include "cpu/cpu_ty...
## Purpose Enable W8A8 (per token input, channelweise weights) MoE checkpoints like `RedHatAI/Qwen3-30B-A3B-Thinking-2507-quantized.w8a8` on Arm CPUs To achieve this, we: - reuse the structure of the existing bf16 grouped gemm kernel in the int8 kernel (I tried to extend the existing bf16 grouped gemm kernel to suppo...
[]
null
null
vllm
c314af1abfddff7b6cce9af578be72c496c6a5e4
2026-07-27T06:53:09+01:00
48,637
https://github.com/vllm-project/vllm/pull/48637
[CPU][Perf] INT8 Fused MoE Kernel for Arm CPUs (#48637)
[CPU][Perf] INT8 Fused MoE Kernel for Arm CPUs (#48637) Signed-off-by: Fadi Arafeh <fadi.arafeh@arm.com> Co-authored-by: Li, Jiang <jiang1.li@intel.com>
csrc/cpu/micro_gemm/cpu_micro_gemm_neon.hpp
cpp
Apache-2.0
#ifndef CPU_MICRO_GEMM_NEON_HPP #define CPU_MICRO_GEMM_NEON_HPP #include <algorithm> #include <cstdint> #include "cpu/micro_gemm/cpu_micro_gemm_impl.hpp" #include <arm_bf16.h> #include <arm_neon.h> namespace cpu_micro_gemm { namespace { constexpr int32_t K = 4; constexpr int32_t Cols = 2; constexpr int32_t TileSi...
// SPDX-License-Identifier: Apache-2.0 // SPDX-FileCopyrightText: Copyright contributors to the vLLM project #ifndef CPU_MICRO_GEMM_NEON_HPP #define CPU_MICRO_GEMM_NEON_HPP #include <algorithm> #include <cstdint> #include "cpu/micro_gemm/cpu_micro_gemm_impl.hpp" #include <arm_bf16.h> #include <arm_neon.h> namespac...
--- csrc/cpu/micro_gemm/cpu_micro_gemm_neon.hpp +++ csrc/cpu/micro_gemm/cpu_micro_gemm_neon.hpp @@ -1,3 +1,6 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: Copyright contributors to the vLLM project + #ifndef CPU_MICRO_GEMM_NEON_HPP #define CPU_MICRO_GEMM_NEON_HPP @@ -16,9 +19,6 @@ constexp...
14
8
6
[]
[ "CPU" ]
[]
Optimize this cpp kernel file from vllm (csrc/cpu/micro_gemm/cpu_micro_gemm_neon.hpp). Goal: [CPU][Perf] INT8 Fused MoE Kernel for Arm CPUs Target hardware: CPU Target models: unspecified Current file: ```cpp #ifndef CPU_MICRO_GEMM_NEON_HPP #define CPU_MICRO_GEMM_NEON_HPP #include <algorithm> #include <cstdint> #in...
## Purpose Enable W8A8 (per token input, channelweise weights) MoE checkpoints like `RedHatAI/Qwen3-30B-A3B-Thinking-2507-quantized.w8a8` on Arm CPUs To achieve this, we: - reuse the structure of the existing bf16 grouped gemm kernel in the int8 kernel (I tried to extend the existing bf16 grouped gemm kernel to suppo...
[]
null
null
vllm
c314af1abfddff7b6cce9af578be72c496c6a5e4
2026-07-27T06:53:09+01:00
48,637
https://github.com/vllm-project/vllm/pull/48637
[CPU][Perf] INT8 Fused MoE Kernel for Arm CPUs (#48637)
[CPU][Perf] INT8 Fused MoE Kernel for Arm CPUs (#48637) Signed-off-by: Fadi Arafeh <fadi.arafeh@arm.com> Co-authored-by: Li, Jiang <jiang1.li@intel.com>
csrc/cpu/torch_bindings.cpp
cpp
Apache-2.0
#include "cache.h" #include "ops.h" #include "core/registration.h" #include <torch/library.h> // Note: overwrite the external definition for sharing same name between // libraries use different ISAs. #define TORCH_EXTENSION_NAME _C void release_dnnl_matmul_handler(int64_t handler); int64_t create_onednn_scaled_mm_h...
#include "cache.h" #include "ops.h" #include "core/registration.h" #include <torch/library.h> // Note: overwrite the external definition for sharing same name between // libraries use different ISAs. #define TORCH_EXTENSION_NAME _C void release_dnnl_matmul_handler(int64_t handler); int64_t create_onednn_scaled_mm_h...
--- csrc/cpu/torch_bindings.cpp +++ csrc/cpu/torch_bindings.cpp @@ -206,6 +206,20 @@ const torch::Tensor& topk_weights, const torch::Tensor& topk_id, const bool skip_weighted, const std::string& act, const std::string& isa); + +void prepack_moe_weight_int8(con...
31
3
6
[]
[ "CPU" ]
[]
Optimize this cpp kernel file from vllm (csrc/cpu/torch_bindings.cpp). Goal: [CPU][Perf] INT8 Fused MoE Kernel for Arm CPUs Target hardware: CPU Target models: unspecified Current file: ```cpp #include "cache.h" #include "ops.h" #include "core/registration.h" #include <torch/library.h> // Note: overwrite the extern...
## Purpose Enable W8A8 (per token input, channelweise weights) MoE checkpoints like `RedHatAI/Qwen3-30B-A3B-Thinking-2507-quantized.w8a8` on Arm CPUs To achieve this, we: - reuse the structure of the existing bf16 grouped gemm kernel in the int8 kernel (I tried to extend the existing bf16 grouped gemm kernel to suppo...
[]
null
null
vllm
dd72658e7db0c6a674f473f6f9f0f5c2ebe7e523
2026-07-24T12:36:27+08:00
48,597
https://github.com/vllm-project/vllm/pull/48597
[Perf][GLM-5.2] Blackwell decode optimizations (#48597)
[Perf][GLM-5.2] Blackwell decode optimizations (#48597) Signed-off-by: Peiyuan Zhou <peiyuanzhou1994@gmail.com> Signed-off-by: zhou <zhou@zhoudeMacBook-Pro.local> Signed-off-by: Stefan Koncarevic <stefan.koncarevic@amd.com> Co-authored-by: Claude <noreply@anthropic.com> Co-authored-by: Giancarlo Delfin <32987265+TheEp...
csrc/libtorch_stable/dsv3_fused_a_gemm.cu
cuda
Apache-2.0
/* * Adapted from * https://github.com/sgl-project/sglang/blob/main/sgl-kernel/csrc/gemm/dsv3_fused_a_gemm.cu * which was adapted from * https://github.com/NVIDIA/TensorRT-LLM/blob/619709fc33bd5dc268f19d6a741fe7ed51c0f8f5/cpp/tensorrt_llm/kernels/dsv3MinLatencyKernels/dsv3FusedAGemm.cu * * Copyright (c) 2019-2024...
/* * Adapted from * https://github.com/sgl-project/sglang/blob/main/sgl-kernel/csrc/gemm/dsv3_fused_a_gemm.cu * which was adapted from * https://github.com/NVIDIA/TensorRT-LLM/blob/619709fc33bd5dc268f19d6a741fe7ed51c0f8f5/cpp/tensorrt_llm/kernels/dsv3MinLatencyKernels/dsv3FusedAGemm.cu * * Copyright (c) 2019-2024...
--- csrc/libtorch_stable/dsv3_fused_a_gemm.cu +++ csrc/libtorch_stable/dsv3_fused_a_gemm.cu @@ -391,7 +391,7 @@ static constexpr int n_iter_cnt = (tile_n + 7) / 8; // Possible to have non-1 n_iter_cnt for ab_swap m16 case. - static_assert(m_iter_cnt == 1); + static_assert(m_iter_cnt == 1 || m_iter_c...
113
37
6
[ "deepseek", "glm" ]
[ "BLACKWELL" ]
[]
Optimize this cuda kernel file from vllm (csrc/libtorch_stable/dsv3_fused_a_gemm.cu). Goal: [Perf][GLM-5.2] Blackwell decode optimizations Target hardware: BLACKWELL Target models: deepseek, glm Current file: ```cuda /* * Adapted from * https://github.com/sgl-project/sglang/blob/main/sgl-kernel/csrc/gemm/dsv3_fused...
# Blackwell decode optimization tracker This pull request is now the tracking page for the focused follow-up work. The original squash merge was reverted by #49768. A checkbox is marked complete only when the corresponding functionality is present on the current `vllm-project/vllm/main` branch. ## Already on `main` ...
[{"scope": "e2e", "hardware": "B300", "model": null, "shape": null, "batch_size": null, "metric": "output tok/s", "unit": "tok/s", "higher_is_better": true, "baseline": 446.7, "optimized": 542.5, "stated_speedup": null, "speedup": 1.2145}, {"scope": "e2e", "hardware": "B300", "model": null, "shape": null, "batch_size":...
null
1.2147
vllm
dd72658e7db0c6a674f473f6f9f0f5c2ebe7e523
2026-07-24T12:36:27+08:00
48,597
https://github.com/vllm-project/vllm/pull/48597
[Perf][GLM-5.2] Blackwell decode optimizations (#48597)
[Perf][GLM-5.2] Blackwell decode optimizations (#48597) Signed-off-by: Peiyuan Zhou <peiyuanzhou1994@gmail.com> Signed-off-by: zhou <zhou@zhoudeMacBook-Pro.local> Signed-off-by: Stefan Koncarevic <stefan.koncarevic@amd.com> Co-authored-by: Claude <noreply@anthropic.com> Co-authored-by: Giancarlo Delfin <32987265+TheEp...
csrc/libtorch_stable/quantization/fp4/nvfp4_quant_kernels.cu
cuda
Apache-2.0
/* * Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless requi...
/* * Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless requi...
--- csrc/libtorch_stable/quantization/fp4/nvfp4_quant_kernels.cu +++ csrc/libtorch_stable/quantization/fp4/nvfp4_quant_kernels.cu @@ -49,6 +49,11 @@ static_assert(sizeof(PackedVec) == sizeof(Type) * CVT_FP4_ELTS_PER_THREAD, "Vec size is not matched."); +#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH_...
42
10
6
[ "glm" ]
[ "BLACKWELL" ]
[]
Optimize this cuda kernel file from vllm (csrc/libtorch_stable/quantization/fp4/nvfp4_quant_kernels.cu). Goal: [Perf][GLM-5.2] Blackwell decode optimizations Target hardware: BLACKWELL Target models: glm Current file: ```cuda /* * Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved. * * Licensed under the...
# Blackwell decode optimization tracker This pull request is now the tracking page for the focused follow-up work. The original squash merge was reverted by #49768. A checkbox is marked complete only when the corresponding functionality is present on the current `vllm-project/vllm/main` branch. ## Already on `main` ...
[{"scope": "e2e", "hardware": "B300", "model": null, "shape": null, "batch_size": null, "metric": "output tok/s", "unit": "tok/s", "higher_is_better": true, "baseline": 446.7, "optimized": 542.5, "stated_speedup": null, "speedup": 1.2145}, {"scope": "e2e", "hardware": "B300", "model": null, "shape": null, "batch_size":...
null
1.2147
vllm
dd72658e7db0c6a674f473f6f9f0f5c2ebe7e523
2026-07-24T12:36:27+08:00
48,597
https://github.com/vllm-project/vllm/pull/48597
[Perf][GLM-5.2] Blackwell decode optimizations (#48597)
[Perf][GLM-5.2] Blackwell decode optimizations (#48597) Signed-off-by: Peiyuan Zhou <peiyuanzhou1994@gmail.com> Signed-off-by: zhou <zhou@zhoudeMacBook-Pro.local> Signed-off-by: Stefan Koncarevic <stefan.koncarevic@amd.com> Co-authored-by: Claude <noreply@anthropic.com> Co-authored-by: Giancarlo Delfin <32987265+TheEp...
csrc/libtorch_stable/torch_bindings.cpp
cpp
Apache-2.0
#include "ops.h" #include "cuda_utils.h" #include "core/registration.h" #include <torch/csrc/stable/library.h> // Register ops with STABLE_TORCH_LIBRARY for libtorch stable ABI compatibility. // Note: We register under namespace "_C" so ops are accessible as // torch.ops._C.<op_name> for compatibility with existing c...
#include "ops.h" #include "cuda_utils.h" #include "core/registration.h" #include <torch/csrc/stable/library.h> // Register ops with STABLE_TORCH_LIBRARY for libtorch stable ABI compatibility. // Note: We register under namespace "_C" so ops are accessible as // torch.ops._C.<op_name> for compatibility with existing c...
--- csrc/libtorch_stable/torch_bindings.cpp +++ csrc/libtorch_stable/torch_bindings.cpp @@ -329,6 +329,10 @@ // BF16/FP32 x FP32 -> FP32 router GEMM for H=3072, E=256, M<=32 (SM90+). // conditionally compiled so impl registration is in source file ops.def("fp32_router_gemm(Tensor! output, Tensor mat_a, Tensor ...
4
0
6
[ "glm" ]
[ "BLACKWELL" ]
[]
Optimize this cpp kernel file from vllm (csrc/libtorch_stable/torch_bindings.cpp). Goal: [Perf][GLM-5.2] Blackwell decode optimizations Target hardware: BLACKWELL Target models: glm Current file: ```cpp #include "ops.h" #include "cuda_utils.h" #include "core/registration.h" #include <torch/csrc/stable/library.h> //...
# Blackwell decode optimization tracker This pull request is now the tracking page for the focused follow-up work. The original squash merge was reverted by #49768. A checkbox is marked complete only when the corresponding functionality is present on the current `vllm-project/vllm/main` branch. ## Already on `main` ...
[{"scope": "e2e", "hardware": "B300", "model": null, "shape": null, "batch_size": null, "metric": "output tok/s", "unit": "tok/s", "higher_is_better": true, "baseline": 446.7, "optimized": 542.5, "stated_speedup": null, "speedup": 1.2145}, {"scope": "e2e", "hardware": "B300", "model": null, "shape": null, "batch_size":...
null
1.2147
vllm
dd72658e7db0c6a674f473f6f9f0f5c2ebe7e523
2026-07-24T12:36:27+08:00
48,597
https://github.com/vllm-project/vllm/pull/48597
[Perf][GLM-5.2] Blackwell decode optimizations (#48597)
[Perf][GLM-5.2] Blackwell decode optimizations (#48597) Signed-off-by: Peiyuan Zhou <peiyuanzhou1994@gmail.com> Signed-off-by: zhou <zhou@zhoudeMacBook-Pro.local> Signed-off-by: Stefan Koncarevic <stefan.koncarevic@amd.com> Co-authored-by: Claude <noreply@anthropic.com> Co-authored-by: Giancarlo Delfin <32987265+TheEp...
vllm/v1/attention/backends/mla/sparse_utils.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Utility functions for sparse MLA backends.""" import torch from vllm.triton_utils import tl, triton # Kernel with prefill workspace support and valid count tracking @triton.jit def _convert_req_index_to_glo...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Utility functions for sparse MLA backends.""" import torch from vllm.triton_utils import tl, triton # Kernel with prefill workspace support and valid count tracking @triton.jit def _convert_req_index_to_glo...
--- vllm/v1/attention/backends/mla/sparse_utils.py +++ vllm/v1/attention/backends/mla/sparse_utils.py @@ -128,6 +128,8 @@ prefill_workspace_request_ids: torch.Tensor | None = None, prefill_workspace_starts: torch.Tensor | None = None, return_valid_counts: bool = False, + out: torch.Tensor | None = Non...
56
4
6
[ "glm" ]
[ "BLACKWELL" ]
[]
Optimize this triton kernel file from vllm (vllm/v1/attention/backends/mla/sparse_utils.py). Goal: [Perf][GLM-5.2] Blackwell decode optimizations Target hardware: BLACKWELL Target models: glm Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM pro...
# Blackwell decode optimization tracker This pull request is now the tracking page for the focused follow-up work. The original squash merge was reverted by #49768. A checkbox is marked complete only when the corresponding functionality is present on the current `vllm-project/vllm/main` branch. ## Already on `main` ...
[{"scope": "e2e", "hardware": "B300", "model": null, "shape": null, "batch_size": null, "metric": "output tok/s", "unit": "tok/s", "higher_is_better": true, "baseline": 446.7, "optimized": 542.5, "stated_speedup": null, "speedup": 1.2145}, {"scope": "e2e", "hardware": "B300", "model": null, "shape": null, "batch_size":...
null
1.2147
vllm
7ca017778fc04cfb1a96080e7c484b1b44fc3a64
2026-07-20T22:21:55+02:00
47,451
https://github.com/vllm-project/vllm/pull/47451
[Feat][Perf] Add new warmup infrastructure for JITs (#47451)
[Feat][Perf] Add new warmup infrastructure for JITs (#47451) Signed-off-by: LopezCastroRoberto <rocastro@redhat.com> Signed-off-by: Roberto L. Castro <38211239+LopezCastroRoberto@users.noreply.github.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
vllm/v1/attention/backends/mla/indexer.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project from dataclasses import dataclass import torch import vllm.envs as envs from vllm.config import VllmConfig from vllm.distributed import get_dcp_group, get_pcp_group from vllm.logger import init_logger from vllm....
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project from dataclasses import dataclass import torch import vllm.envs as envs from vllm.config import VllmConfig from vllm.distributed import get_dcp_group, get_pcp_group from vllm.logger import init_logger from vllm....
--- vllm/v1/attention/backends/mla/indexer.py +++ vllm/v1/attention/backends/mla/indexer.py @@ -8,6 +8,14 @@ from vllm.config import VllmConfig from vllm.distributed import get_dcp_group, get_pcp_group from vllm.logger import init_logger +from vllm.model_executor.warmup.jit_warmup import ( + VllmJitKernel, + W...
215
79
3
[]
[]
[]
Optimize this triton kernel file from vllm (vllm/v1/attention/backends/mla/indexer.py). Goal: [Feat][Perf] Add new warmup infrastructure for JITs Target hardware: unspecified Target models: unspecified Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to th...
## Summary This PR introduces a shared warmup infrastructure for JIT kernels in vLLM. The goal is to provide a standard, extensible way for kernels from different JIT backends, including Triton, CuTeDSL, TileLang, and potential future DSLs, to expose the set of specializations that should be compiled during engine st...
[]
null
null
vllm
7ca017778fc04cfb1a96080e7c484b1b44fc3a64
2026-07-20T22:21:55+02:00
47,451
https://github.com/vllm-project/vllm/pull/47451
[Feat][Perf] Add new warmup infrastructure for JITs (#47451)
[Feat][Perf] Add new warmup infrastructure for JITs (#47451) Signed-off-by: LopezCastroRoberto <rocastro@redhat.com> Signed-off-by: Roberto L. Castro <38211239+LopezCastroRoberto@users.noreply.github.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
vllm/v1/attention/backends/mla/sparse_swa.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project from dataclasses import dataclass, field from typing import ClassVar, cast import torch from vllm.config import CacheConfig, VllmConfig, get_current_vllm_config from vllm.model_executor.layers.attention_layer_ba...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project from dataclasses import dataclass, field from typing import ClassVar, cast import torch from vllm.config import CacheConfig, VllmConfig, get_current_vllm_config from vllm.model_executor.layers.attention_layer_ba...
--- vllm/v1/attention/backends/mla/sparse_swa.py +++ vllm/v1/attention/backends/mla/sparse_swa.py @@ -7,9 +7,14 @@ from vllm.config import CacheConfig, VllmConfig, get_current_vllm_config from vllm.model_executor.layers.attention_layer_base import AttentionLayerBase +from vllm.model_executor.warmup.jit_warmup impor...
108
34
3
[]
[]
[]
Optimize this triton kernel file from vllm (vllm/v1/attention/backends/mla/sparse_swa.py). Goal: [Feat][Perf] Add new warmup infrastructure for JITs Target hardware: unspecified Target models: unspecified Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to...
## Summary This PR introduces a shared warmup infrastructure for JIT kernels in vLLM. The goal is to provide a standard, extensible way for kernels from different JIT backends, including Triton, CuTeDSL, TileLang, and potential future DSLs, to expose the set of specializations that should be compiled during engine st...
[]
null
null
vllm
e94243893dd30256f58644ad4ecf779be757dff8
2026-07-18T18:39:37+02:00
46,832
https://github.com/vllm-project/vllm/pull/46832
[ROCm][DSv3.2][Perf] Cap sparse MLA decode KV-splits with a work-per-split heuristic (#46832)
[ROCm][DSv3.2][Perf] Cap sparse MLA decode KV-splits with a work-per-split heuristic (#46832) Signed-off-by: Frida Andersson <fanderss@amd.com>
vllm/v1/attention/backends/mla/rocm_aiter_mla_sparse.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project from dataclasses import dataclass from typing import TYPE_CHECKING, ClassVar import numpy as np import torch from vllm import _custom_ops as ops from vllm._aiter_ops import rocm_aiter_ops from vllm.config impor...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project from dataclasses import dataclass from typing import TYPE_CHECKING, ClassVar import numpy as np import torch from vllm import _custom_ops as ops from vllm._aiter_ops import rocm_aiter_ops from vllm.config impor...
--- vllm/v1/attention/backends/mla/rocm_aiter_mla_sparse.py +++ vllm/v1/attention/backends/mla/rocm_aiter_mla_sparse.py @@ -369,6 +369,8 @@ self.num_heads = self.model_config.get_num_attention_heads(parallel_config) self.mla_dims = get_mla_dims(self.model_config) self.topk_tokens = vllm_confi...
21
0
1
[ "deepseek" ]
[ "ROCM" ]
[]
Optimize this triton kernel file from vllm (vllm/v1/attention/backends/mla/rocm_aiter_mla_sparse.py). Goal: [ROCm][DSv3.2][Perf] Cap sparse MLA decode KV-splits with a work-per-split heuristic Target hardware: ROCM Target models: deepseek Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyri...
# [ROCm][DSv3.2][Perf] Cap sparse MLA decode KV-splits with a work-per-split heuristic The ROCm aiter sparse-MLA decode backend calls `get_mla_metadata_v1` without `max_split_per_batch`, so aiter defaults to `-1` and splits the decode reduction across every CU (304 on gfx942). The reduce only covers the selected token...
[{"scope": "kernel", "hardware": "gfx942 / MI325X", "model": "DeepSeek-V3.2", "shape": null, "batch_size": null, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 22.136, "optimized": 5.387, "stated_speedup": null, "speedup": 4.1092}, {"scope": "kernel", "hardware": "gfx942 / MI325X", "model": "...
4.1079
1.0431
vllm
da64db78b989d820effd090d8ac4b65ade2cbe4f
2026-07-18T10:26:14+08:00
48,759
https://github.com/vllm-project/vllm/pull/48759
[LoRA] Optimize TrtLlmLoRAExperts (#48759)
[LoRA] Optimize TrtLlmLoRAExperts (#48759) Signed-off-by: Jee Jee Li <jeejeelee@inferact.ai>
vllm/model_executor/layers/fused_moe/experts/trtllm_lora_moe.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """ LoRA-aware FlashInfer TRT-LLM MoE experts (BF16). Reuses the routed API + ``gemm1_lora_delta`` path from FlashInfer PR #3153: * The W13 (gate_up) LoRA delta is passed directly as ``gemm1_lora_delta`` to ...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """ LoRA-aware FlashInfer TRT-LLM MoE experts (BF16). Reuses the routed API + ``gemm1_lora_delta`` path from FlashInfer PR #3153: * The W13 (gate_up) LoRA delta is passed directly as ``gemm1_lora_delta`` to ...
--- vllm/model_executor/layers/fused_moe/experts/trtllm_lora_moe.py +++ vllm/model_executor/layers/fused_moe/experts/trtllm_lora_moe.py @@ -31,6 +31,7 @@ FusedMoEQuantConfig, RoutingMethodType, ) +from vllm.model_executor.layers.fused_moe.experts.lora_context import MoELoRAContext from vllm.model_executor.l...
212
42
2
[]
[]
[]
Optimize this triton kernel file from vllm (vllm/model_executor/layers/fused_moe/experts/trtllm_lora_moe.py). Goal: [LoRA] Optimize TrtLlmLoRAExperts Target hardware: unspecified Target models: unspecified Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors t...
## Purpose part of https://github.com/vllm-project/vllm/pull/47226 ## Test Plan ## Test Result --- <details> <summary> Essential Elements of an Effective PR Description Checklist </summary> - [ ] The purpose of the PR, such as "Fix some issue (link existing issues this PR will resolve)". - [ ] The test plan, such...
[]
null
null
vllm
b5433b6f5079feb32f9f278cf4ae23bd87375148
2026-07-17T16:35:06-04:00
48,660
https://github.com/vllm-project/vllm/pull/48660
[Perf] Optimize dsv4 routing using specialized kernel, 2.94% E2E TPOT improvement (#48660)
[Perf] Optimize dsv4 routing using specialized kernel, 2.94% E2E TPOT improvement (#48660) Signed-off-by: yewentao256 <zhyanwentao@126.com>
csrc/libtorch_stable/moe/topk_softplus_sqrt_kernels.cu
cuda
Apache-2.0
/* * Adapted from * https://github.com/NVIDIA/TensorRT-LLM/blob/v0.7.1/cpp/tensorrt_llm/kernels/mixtureOfExperts/moe_kernels.cu * Copyright (c) 2024, The vLLM team. * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & * AFFILIATES. All rights reserved. SPDX-License-Identifier: Apache-2.0 * * Li...
/* * Adapted from * https://github.com/NVIDIA/TensorRT-LLM/blob/v0.7.1/cpp/tensorrt_llm/kernels/mixtureOfExperts/moe_kernels.cu * Copyright (c) 2024, The vLLM team. * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & * AFFILIATES. All rights reserved. SPDX-License-Identifier: Apache-2.0 * * Li...
--- csrc/libtorch_stable/moe/topk_softplus_sqrt_kernels.cu +++ csrc/libtorch_stable/moe/topk_softplus_sqrt_kernels.cu @@ -70,6 +70,73 @@ return __half2float(value); } } + +#ifndef USE_ROCM +// Adapted from: +// https://github.com/sgl-project/sglang/blob/main/python/sglang/jit_kernel/csrc/deepseek_v4/hash_topk....
78
0
2
[ "deepseek" ]
[]
[]
Optimize this cuda kernel file from vllm (csrc/libtorch_stable/moe/topk_softplus_sqrt_kernels.cu). Goal: [Perf] Optimize dsv4 routing using specialized kernel, 2.94% E2E TPOT improvement Target hardware: unspecified Target models: deepseek Current file: ```cuda /* * Adapted from * https://github.com/NVIDIA/TensorRT...
## Purpose Thanks the context from @zyongye ! ## Test `vllm serve deepseek-ai/DeepSeek-V4-Flash -tp 4 -ep --attention-backend FLASHINFER_MLA_SPARSE_DSV4 --kv-cache-dtype fp8 --tokenizer-mode deepseek_v4 --all2all-backend allgather_reducescatter --port 8003` ### Acc `lm_eval --model local-completion...
[]
null
null
vllm
efed8a1e8345de2b4398a48243301d6a5b1a361e
2026-07-17T13:24:59-04:00
48,788
https://github.com/vllm-project/vllm/pull/48788
[ROCm][Perf][DSV4] Improve sparse decode reduction occupancy on gfx950 (#48788)
[ROCm][Perf][DSV4] Improve sparse decode reduction occupancy on gfx950 (#48788) Signed-off-by: fai <fangzhouai@gmail.com>
vllm/v1/attention/ops/rocm_aiter_mla_sparse.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project import functools import importlib import math from importlib.util import find_spec import torch import torch.nn.functional as F import vllm.envs as envs from vllm.compilation.breakable_cudagraph import eager_bre...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project import functools import importlib import math from importlib.util import find_spec import torch import torch.nn.functional as F import vllm.envs as envs from vllm.compilation.breakable_cudagraph import eager_bre...
--- vllm/v1/attention/ops/rocm_aiter_mla_sparse.py +++ vllm/v1/attention/ops/rocm_aiter_mla_sparse.py @@ -2205,7 +2205,7 @@ num_warps=4, ) - _sparse_attn_decode_reduce_kernel[(num_queries, heads_blocks)]( + _sparse_attn_decode_reduce_kernel[(num_queries, num_heads)]( part_m, part...
2
2
1
[ "deepseek" ]
[ "GFX950", "ROCM" ]
[]
Optimize this triton kernel file from vllm (vllm/v1/attention/ops/rocm_aiter_mla_sparse.py). Goal: [ROCm][Perf][DSV4] Improve sparse decode reduction occupancy on gfx950 Target hardware: GFX950, ROCM Target models: deepseek Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyri...
## Summary The split-K sparse decode reducer currently processes 16 heads per workgroup, which keeps a `[16, COMB_DIM]` FP32 accumulator in each workgroup and limits workgroup-level parallelism. This change processes one head per reducer workgroup. It lowers per-workgroup accumulator/register pressure and exposes up ...
[{"scope": "e2e", "hardware": "MI355X", "model": "DeepSeek-V4-Pro", "shape": null, "batch_size": 4, "metric": "throughput", "unit": "tok/s", "higher_is_better": true, "baseline": 143.56, "optimized": 149.78, "stated_speedup": 1.0434, "speedup": 1.0433}, {"scope": "e2e", "hardware": "MI355X", "model": "DeepSeek-V4-Pro",...
null
1.0476
vllm
f17be06fbe42bab61522868a78d044fd0d2e3547
2026-07-16T18:41:07-04:00
48,143
https://github.com/vllm-project/vllm/pull/48143
[Perf] Optimize `clamp` to `clamp_` (#48143)
[Perf] Optimize `clamp` to `clamp_` (#48143) Signed-off-by: yewentao256 <zhyanwentao@126.com> Signed-off-by: Wentao Ye <44945378+yewentao256@users.noreply.github.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
vllm/v1/attention/backends/rocm_aiter_fa.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Attention layer with AiterFlashAttention.""" from dataclasses import dataclass from typing import ClassVar import torch from vllm._aiter_ops import rocm_aiter_ops from vllm.config import VllmConfig, get_laye...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Attention layer with AiterFlashAttention.""" from dataclasses import dataclass from typing import ClassVar import torch from vllm._aiter_ops import rocm_aiter_ops from vllm.config import VllmConfig, get_laye...
--- vllm/v1/attention/backends/rocm_aiter_fa.py +++ vllm/v1/attention/backends/rocm_aiter_fa.py @@ -593,9 +593,8 @@ chunk_ends = torch.min( computed_kv_lens.unsqueeze(0), chunk_starts + max_context_chunk ) - chunk_seq_lens = (chunk_ends - chunk_starts).clamp( - ...
2
3
4
[]
[]
[]
Optimize this triton kernel file from vllm (vllm/v1/attention/backends/rocm_aiter_fa.py). Goal: [Perf] Optimize `clamp` to `clamp_` Target hardware: unspecified Target models: unspecified Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project...
## Purpose Optimize `clamp` to `clamp_` to reduce additional memory allocation.
[]
null
null
vllm
b8168e33e000df5c60d63d7ca244ba2ca2c34079
2026-07-16T15:28:20+03:00
46,275
https://github.com/vllm-project/vllm/pull/46275
[ROCm][Perf][DSV4] Enable split sparse decode on gfx942 (#46275)
[ROCm][Perf][DSV4] Enable split sparse decode on gfx942 (#46275) Signed-off-by: Tuukka Sarvi <tuukka.sarvi@amd.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
vllm/v1/attention/ops/rocm_aiter_mla_sparse.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project import functools import importlib import math from importlib.util import find_spec import torch import torch.nn.functional as F import vllm.envs as envs from vllm.compilation.breakable_cudagraph import eager_bre...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project import functools import importlib import math from importlib.util import find_spec import torch import torch.nn.functional as F import vllm.envs as envs from vllm.compilation.breakable_cudagraph import eager_bre...
--- vllm/v1/attention/ops/rocm_aiter_mla_sparse.py +++ vllm/v1/attention/ops/rocm_aiter_mla_sparse.py @@ -2104,7 +2104,7 @@ comb_dim = nope_head_dim + rope_head_dim is_fnuz = current_platform.is_fp8_fnuz() - if not _ON_GFX950: # Fallback path for un-tuned architectures. + if not (_ON_GFX942 or _ON_GF...
1
1
1
[ "deepseek" ]
[ "GFX942", "ROCM" ]
[]
Optimize this triton kernel file from vllm (vllm/v1/attention/ops/rocm_aiter_mla_sparse.py). Goal: [ROCm][Perf][DSV4] Enable split sparse decode on gfx942 Target hardware: GFX942, ROCM Target models: deepseek Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributor...
## Purpose Enable the existing split partial/reduce Triton sparse decode path for DeepSeek-V4 sparse MLA decode on AMD gfx942. gfx950 already uses this path. gfx942 currently falls back to the monolithic `_sparse_attn_decode_ragged_kernel`, even though the split path runs correctly on gfx942. This PR extends the tune...
[{"scope": "kernel", "hardware": "MI300X", "model": "DeepSeek-V4", "shape": "MAIN_LEN=80,EXTRA_LEN=32", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 42.754, "optimized": 22.836, "stated_speedup": null, "speedup": 1.8722}, {"scope": "kernel", "hardware": "MI300X", "model": "...
1.7373
1.0337
vllm
3c1bc1fc0dd5384c92d608824f03e6e60e98d592
2026-07-16T08:58:59+08:00
48,519
https://github.com/vllm-project/vllm/pull/48519
[ROCm][Perf] Optimize sparse attention prefill kernel for DeepSeek-V4 (#48519)
[ROCm][Perf] Optimize sparse attention prefill kernel for DeepSeek-V4 (#48519) Signed-off-by: kliuae <kuanfu.liu@embeddedllm.com> Co-authored-by: TJian <tunjian.tan@embeddedllm.com>
vllm/v1/attention/ops/rocm_aiter_mla_sparse.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project import functools import importlib import math from importlib.util import find_spec import torch import torch.nn.functional as F import vllm.envs as envs from vllm.compilation.breakable_cudagraph import eager_bre...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project import functools import importlib import math from importlib.util import find_spec import torch import torch.nn.functional as F import vllm.envs as envs from vllm.compilation.breakable_cudagraph import eager_bre...
--- vllm/v1/attention/ops/rocm_aiter_mla_sparse.py +++ vllm/v1/attention/ops/rocm_aiter_mla_sparse.py @@ -1187,10 +1187,12 @@ kv_len = kv_end - kv_start k_offsets = tl.arange(0, BLOCK_K) + slot = tl.load( + kv_indices_ptr + kv_start + k_offsets, mask=k_offsets < kv_len, other=-1 + ) for k_...
10
3
1
[ "deepseek" ]
[ "ROCM" ]
[]
Optimize this triton kernel file from vllm (vllm/v1/attention/ops/rocm_aiter_mla_sparse.py). Goal: [ROCm][Perf] Optimize sparse attention prefill kernel for DeepSeek-V4 Target hardware: ROCM Target models: deepseek Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contr...
## Purpose This PR optimizes DeepSeek-V4's dedicated sparse attention ragged prefill kernel in ROCm. The optimization speeds up the kernel by ~2x, and in E2E benchmark reduces TTFT by ~10%. In the current upstream ROCm path, this kernel has some slight inefficiencies that can be optimized. Specifically, this PR add...
[{"scope": "kernel", "hardware": null, "model": "DeepSeek-V4-Pro", "shape": "num_heads=16,head_dim=512", "batch_size": 2048, "metric": "latency", "unit": "ms", "higher_is_better": false, "baseline": 0.348, "optimized": 0.19, "stated_speedup": 1.83, "speedup": 1.8316}, {"scope": "kernel", "hardware": null, "model": "Dee...
2.0247
1.1151
vllm
2dab187f756f2c4549fd5e57019413f3415365a4
2026-07-15T19:40:55-04:00
47,463
https://github.com/vllm-project/vllm/pull/47463
[Perf] Optimize `fused_topk_bias` for DSv4, 1.5~2x kernel performance improvement (#47463)
[Perf] Optimize `fused_topk_bias` for DSv4, 1.5~2x kernel performance improvement (#47463) Signed-off-by: yewentao256 <zhyanwentao@126.com>
csrc/libtorch_stable/moe/topk_softplus_sqrt_kernels.cu
cuda
Apache-2.0
/* * Adapted from * https://github.com/NVIDIA/TensorRT-LLM/blob/v0.7.1/cpp/tensorrt_llm/kernels/mixtureOfExperts/moe_kernels.cu * Copyright (c) 2024, The vLLM team. * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & * AFFILIATES. All rights reserved. SPDX-License-Identifier: Apache-2.0 * * Li...
/* * Adapted from * https://github.com/NVIDIA/TensorRT-LLM/blob/v0.7.1/cpp/tensorrt_llm/kernels/mixtureOfExperts/moe_kernels.cu * Copyright (c) 2024, The vLLM team. * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & * AFFILIATES. All rights reserved. SPDX-License-Identifier: Apache-2.0 * * Li...
--- csrc/libtorch_stable/moe/topk_softplus_sqrt_kernels.cu +++ csrc/libtorch_stable/moe/topk_softplus_sqrt_kernels.cu @@ -44,6 +44,12 @@ namespace vllm { namespace moe { +template <typename HashIndType> +__device__ __forceinline__ int64_t load_index_as_int64(const HashIndType* ptr, + ...
68
59
2
[ "deepseek" ]
[]
[ "2x" ]
Optimize this cuda kernel file from vllm (csrc/libtorch_stable/moe/topk_softplus_sqrt_kernels.cu). Goal: [Perf] Optimize `fused_topk_bias` for DSv4, 1.5~2x kernel performance improvement Target hardware: unspecified Target models: deepseek Current file: ```cuda /* * Adapted from * https://github.com/NVIDIA/TensorRT...
## Purpose Part of https://github.com/vllm-project/vllm/issues/45861 ~Originally when `hash_indices_table` is None we will do a redundant `input_tokens.to(dtype=indices_type)` which can be removed.~ We make the conversion inside the kernel to improve performance ## Test Acc covered in current unit test Performanc...
[{"scope": "kernel", "hardware": null, "model": null, "shape": "vocab=163840,experts=512,topk=8,hidden=1", "batch_size": 128, "metric": "latency", "unit": "ms", "higher_is_better": false, "baseline": 0.0311, "optimized": 0.0163, "stated_speedup": 1.91, "speedup": 1.908}, {"scope": "kernel", "hardware": null, "model": n...
1.9046
null
vllm
dcf4072da9aeba343e4189b52a6e8d4228758d2d
2026-07-14T05:48:54+02:00
45,000
https://github.com/vllm-project/vllm/pull/45000
[Perf][ROCm] Fix GDN KKT warmup regression on RDNA by avoiding fp32 tl.dot (#45000)
[Perf][ROCm] Fix GDN KKT warmup regression on RDNA by avoiding fp32 tl.dot (#45000) Signed-off-by: Saeid Rostami <srostami@amd.com> Signed-off-by: nemanjaudovic <nudovic@amd.com>
vllm/model_executor/layers/fla/ops/chunk_scaled_dot_kkt.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project # SPDX-FileCopyrightText: Songlin Yang, Yu Zhang # # This file contains code copied from the flash-linear-attention project. # The original source code was licensed under the MIT license and included # the followi...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project # SPDX-FileCopyrightText: Songlin Yang, Yu Zhang # # This file contains code copied from the flash-linear-attention project. # The original source code was licensed under the MIT license and included # the followi...
--- vllm/model_executor/layers/fla/ops/chunk_scaled_dot_kkt.py +++ vllm/model_executor/layers/fla/ops/chunk_scaled_dot_kkt.py @@ -10,11 +10,22 @@ import torch +from vllm.platforms import current_platform from vllm.triton_utils import tl, triton from .index import prepare_chunk_indices from .op import exp fro...
19
1
1
[]
[ "ROCM" ]
[]
Optimize this triton kernel file from vllm (vllm/model_executor/layers/fla/ops/chunk_scaled_dot_kkt.py). Goal: [Perf][ROCm] Fix GDN KKT warmup regression on RDNA by avoiding fp32 tl.dot Target hardware: ROCM Target models: unspecified Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightT...
## Purpose After this PR: https://github.com/vllm-project/vllm/pull/42076, during running of Qwen3.5-9B model that uses GDN triton kernel on RDNA GPUs, warmup time went from ~150s to ~2400s. The problem was that operands of tl.dot() were casted to fp32, so that operation lowered to software fp32 matmul instead of wmma ...
[{"scope": "e2e", "hardware": "RDNA", "model": "Qwen3.5-9B", "shape": null, "batch_size": null, "metric": "warmup time", "unit": "s", "higher_is_better": false, "baseline": 150, "optimized": 150, "stated_speedup": null, "speedup": 1.0}, {"scope": "e2e", "hardware": "RDNA", "model": null, "shape": null, "batch_size": nu...
null
95.5
vllm
a02984ed471488c0f0e8f73cab21be4325992d4c
2026-07-12T14:14:49+08:00
47,006
https://github.com/vllm-project/vllm/pull/47006
[Perf][Qwen] Replace MOE all-reduce with reduce-scatter (#47006)
[Perf][Qwen] Replace MOE all-reduce with reduce-scatter (#47006) Signed-off-by: gcanlin <canlinguosdu@gmail.com> Signed-off-by: yewentao256 <zhyanwentao@126.com> Co-authored-by: yewentao256 <zhyanwentao@126.com>
vllm/model_executor/layers/mamba/gdn/qwen_gdn_linear_attn.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Inference-only Qwen3-Next/Qwen3.5 model.""" import functools from typing import Literal import torch from einops import rearrange from torch import nn from vllm import envs from vllm._aiter_ops import rocm_a...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Inference-only Qwen3-Next/Qwen3.5 model.""" import functools from typing import Literal import torch from einops import rearrange from torch import nn from vllm import envs from vllm._aiter_ops import rocm_a...
--- vllm/model_executor/layers/mamba/gdn/qwen_gdn_linear_attn.py +++ vllm/model_executor/layers/mamba/gdn/qwen_gdn_linear_attn.py @@ -437,6 +437,7 @@ vllm_config: VllmConfig, prefix: str = "", gqa_interleaved_layout=False, + reduce_results: bool = True, ) -> None: super()...
2
0
1
[ "qwen", "mamba" ]
[]
[]
Optimize this triton kernel file from vllm (vllm/model_executor/layers/mamba/gdn/qwen_gdn_linear_attn.py). Goal: [Perf][Qwen] Replace MOE all-reduce with reduce-scatter Target hardware: unspecified Target models: qwen, mamba Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyr...
## Purpose Need https://github.com/vllm-project/vllm/pull/47070 merged first. Follow https://github.com/vllm-project/vllm/pull/46635. ## Test Plan ``` vllm serve /mnt/data1/huggingface/hub/models--Qwen--Qwen3.5-122B-A10B/snapshots/dc4d348443bc740c68e2d77492492c11606384d5 \ --host 127.0.0.1 \ --port 9256 ...
[]
null
null
vllm
19069bcbd5be607a9c502e007951d8325d6a340e
2026-07-11T21:07:48+08:00
48,335
https://github.com/vllm-project/vllm/pull/48335
FP32 router GEMV optimization (#48335)
FP32 router GEMV optimization (#48335) Signed-off-by: peiyuanz <peiyuanz@inferact.ai> Signed-off-by: Jee Jee Li <jeejeelee@inferact.ai> Co-authored-by: peiyuanz <peiyuanz@inferact.ai> Co-authored-by: Claude <noreply@anthropic.com> Co-authored-by: zhouzhou <zhouzhou@zhouzhoudeMacBook-Pro.local>
csrc/libtorch_stable/fp32_router_gemm.cu
cuda
Apache-2.0
// SPDX-License-Identifier: Apache-2.0 // SPDX-FileCopyrightText: Copyright contributors to the vLLM project // // Router GEMM: activation(T) x weight(fp32) -> fp32, H=3072, E=256, M<=32. // Supports bf16 or fp32 activation; weight is always fp32. // Adapted from dsv3_router_gemm_float_out.cu. #include <cuda_bf16.h> #...
// SPDX-License-Identifier: Apache-2.0 // SPDX-FileCopyrightText: Copyright contributors to the vLLM project // // Router GEMM: activation(T) x weight(fp32) -> fp32, M<=32, for the // supported (E, H) pairs listed at the bottom of this file. // Supports bf16 or fp32 activation; weight is always fp32. // Adapted from ds...
--- csrc/libtorch_stable/fp32_router_gemm.cu +++ csrc/libtorch_stable/fp32_router_gemm.cu @@ -1,12 +1,17 @@ // SPDX-License-Identifier: Apache-2.0 // SPDX-FileCopyrightText: Copyright contributors to the vLLM project // -// Router GEMM: activation(T) x weight(fp32) -> fp32, H=3072, E=256, M<=32. +// Router GEMM: act...
198
75
3
[]
[]
[]
Optimize this cuda kernel file from vllm (csrc/libtorch_stable/fp32_router_gemm.cu). Goal: FP32 router GEMV optimization Target hardware: unspecified Target models: unspecified Current file: ```cuda // SPDX-License-Identifier: Apache-2.0 // SPDX-FileCopyrightText: Copyright contributors to the vLLM project // // Rout...
## Purpose ## Test Plan ## Test Result --- <details> <summary> Essential Elements of an Effective PR Description Checklist </summary> - [ ] The purpose of the PR, such as "Fix some issue (link existing issues this PR will resolve)". - [ ] The test plan, such as providing test command. - [ ] The test results, suc...
[]
null
null
vllm
19069bcbd5be607a9c502e007951d8325d6a340e
2026-07-11T21:07:48+08:00
48,335
https://github.com/vllm-project/vllm/pull/48335
FP32 router GEMV optimization (#48335)
FP32 router GEMV optimization (#48335) Signed-off-by: peiyuanz <peiyuanz@inferact.ai> Signed-off-by: Jee Jee Li <jeejeelee@inferact.ai> Co-authored-by: peiyuanz <peiyuanz@inferact.ai> Co-authored-by: Claude <noreply@anthropic.com> Co-authored-by: zhouzhou <zhouzhou@zhouzhoudeMacBook-Pro.local>
csrc/libtorch_stable/fp32_router_gemm_entry.cu
cuda
Apache-2.0
// SPDX-License-Identifier: Apache-2.0 // SPDX-FileCopyrightText: Copyright contributors to the vLLM project #include <torch/csrc/stable/library.h> #include <torch/csrc/stable/tensor.h> #include <torch/headeronly/core/ScalarType.h> #include "core/registration.h" #include "libtorch_stable/torch_utils.h" #include <cud...
// SPDX-License-Identifier: Apache-2.0 // SPDX-FileCopyrightText: Copyright contributors to the vLLM project #include <torch/csrc/stable/library.h> #include <torch/csrc/stable/tensor.h> #include <torch/headeronly/core/ScalarType.h> #include "core/registration.h" #include "libtorch_stable/torch_utils.h" #include <cud...
--- csrc/libtorch_stable/fp32_router_gemm_entry.cu +++ csrc/libtorch_stable/fp32_router_gemm_entry.cu @@ -25,10 +25,12 @@ static constexpr int FP32_MAX_TOKENS = 32; // Supported (hidden_dim, num_experts) pairs (must match the instantiations in -// fp32_router_gemm.cu): (3072, 256) for MiniMax-M2/M2.5, (6144, 128) f...
8
3
3
[]
[]
[]
Optimize this cuda kernel file from vllm (csrc/libtorch_stable/fp32_router_gemm_entry.cu). Goal: FP32 router GEMV optimization Target hardware: unspecified Target models: unspecified Current file: ```cuda // SPDX-License-Identifier: Apache-2.0 // SPDX-FileCopyrightText: Copyright contributors to the vLLM project #in...
## Purpose ## Test Plan ## Test Result --- <details> <summary> Essential Elements of an Effective PR Description Checklist </summary> - [ ] The purpose of the PR, such as "Fix some issue (link existing issues this PR will resolve)". - [ ] The test plan, such as providing test command. - [ ] The test results, suc...
[]
null
null
vllm
300e33797fac8a949a0ed89fab2633de96e65fa8
2026-07-10T15:37:51+08:00
46,998
https://github.com/vllm-project/vllm/pull/46998
[Perf] fuse more rmsnorm and all-reduce in qwen3.5 (#46998)
[Perf] fuse more rmsnorm and all-reduce in qwen3.5 (#46998) Signed-off-by: zjy0516 <riverclouds.zhu@qq.com>
vllm/model_executor/layers/mamba/gdn/qwen_gdn_linear_attn.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Inference-only Qwen3-Next/Qwen3.5 model.""" import functools from typing import Literal import torch from einops import rearrange from torch import nn from vllm import envs from vllm._aiter_ops import rocm_a...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Inference-only Qwen3-Next/Qwen3.5 model.""" import functools from typing import Literal import torch from einops import rearrange from torch import nn from vllm import envs from vllm._aiter_ops import rocm_a...
--- vllm/model_executor/layers/mamba/gdn/qwen_gdn_linear_attn.py +++ vllm/model_executor/layers/mamba/gdn/qwen_gdn_linear_attn.py @@ -844,17 +844,14 @@ def forward( self, hidden_states: torch.Tensor, - output: torch.Tensor, - ): - self._forward_method(hidden_states, output) + ...
16
20
1
[ "qwen", "mamba" ]
[]
[]
Optimize this triton kernel file from vllm (vllm/model_executor/layers/mamba/gdn/qwen_gdn_linear_attn.py). Goal: [Perf] fuse more rmsnorm and all-reduce in qwen3.5 Target hardware: unspecified Target models: qwen, mamba Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright ...
## Purpose `Qwen3NextDecoderLayer` currently passes a preallocated output buffer into its attention submodules, which write their result via slice assignment: ```python output = torch.empty_like(hidden_states) ... output[:num_tokens], _ = self.out_proj(core_attn_out) # GDN linear attention ``` It prevents all re...
[]
null
null
vllm
b0dec2a11b91711ac1893aa18491a77b0f443644
2026-07-09T22:35:10+03:00
45,149
https://github.com/vllm-project/vllm/pull/45149
[ROCM][DSV32][Perf][MTP] Enable UNIFORM_BATCH CG mode in rocm_aiter_mla_sparse (#45149)
[ROCM][DSV32][Perf][MTP] Enable UNIFORM_BATCH CG mode in rocm_aiter_mla_sparse (#45149) Signed-off-by: Teemu Virolainen <teemu.virolainen@amd.com> Co-authored-by: TJian <tunjian.tan@embeddedllm.com> Co-authored-by: Andreas Karatzas <akaratza@amd.com>
vllm/v1/attention/backends/mla/rocm_aiter_mla_sparse.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project from dataclasses import dataclass from typing import TYPE_CHECKING, ClassVar import numpy as np import torch from vllm import _custom_ops as ops from vllm._aiter_ops import rocm_aiter_ops from vllm.config impor...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project from dataclasses import dataclass from typing import TYPE_CHECKING, ClassVar import numpy as np import torch from vllm import _custom_ops as ops from vllm._aiter_ops import rocm_aiter_ops from vllm.config impor...
--- vllm/v1/attention/backends/mla/rocm_aiter_mla_sparse.py +++ vllm/v1/attention/backends/mla/rocm_aiter_mla_sparse.py @@ -347,9 +347,7 @@ class ROCMAiterMLASparseMetadataBuilder( AttentionMetadataBuilder[ROCMAiterMLASparseMetadata] ): - _cudagraph_support: ClassVar[AttentionCGSupport] = ( - Attention...
4
3
1
[ "deepseek" ]
[ "ROCM" ]
[]
Optimize this triton kernel file from vllm (vllm/v1/attention/backends/mla/rocm_aiter_mla_sparse.py). Goal: [ROCM][DSV32][Perf][MTP] Enable UNIFORM_BATCH CG mode in rocm_aiter_mla_sparse Target hardware: ROCM Target models: deepseek Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightTex...
## Purpose In order to improve performance especially in CPU bound cases when MTP is enabled UNIFORM_BATCH CG mode needs to be enabled in rocm_aiter_mla_sparse.py. It has not been enabled mostly due to testing reasons and lack of focus for MTP. ## Test Plan Extensive testing of DeepSeekV3.2 with MTP on on MI350X and...
[{"scope": "e2e", "hardware": "MI350X", "model": "DeepSeek-V3.2", "shape": null, "batch_size": 32, "metric": "throughput", "unit": "tok/s", "higher_is_better": true, "baseline": 951.02, "optimized": 982.07, "stated_speedup": null, "speedup": 1.0326}, {"scope": "e2e", "hardware": "MI350X", "model": "DeepSeek-V3.2", "sha...
null
1.0347
vllm
d9e57ea82e3e873a74d0ed1c3439fccea2164706
2026-07-08T12:03:34+08:00
46,117
https://github.com/vllm-project/vllm/pull/46117
[ROCm][Perf] MXFP8 dense-linear + grouped-MoE GEMM optimizations for MiniMax-M3 (#46117)
[ROCm][Perf] MXFP8 dense-linear + grouped-MoE GEMM optimizations for MiniMax-M3 (#46117) Signed-off-by: amd-ethany <amd-ethany@users.noreply.github.com> Co-authored-by: amd-ethany <amd-ethany@users.noreply.github.com>
vllm/model_executor/layers/fused_moe/experts/mxfp8_native_moe.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Native MXFP8 (1x32 block, E8M0 scale) MoE for AMD CDNA4 (gfx950) via Triton ``tl.dot_scaled`` (hardware microscaling matmul). The expert GEMMs consume the FP8 E4M3 weights and their E8M0 block scales directly ...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Native MXFP8 (1x32 block, E8M0 scale) MoE for AMD CDNA4 (gfx950) via Triton ``tl.dot_scaled`` (hardware microscaling matmul). The expert GEMMs consume the FP8 E4M3 weights and their E8M0 block scales directly ...
--- vllm/model_executor/layers/fused_moe/experts/mxfp8_native_moe.py +++ vllm/model_executor/layers/fused_moe/experts/mxfp8_native_moe.py @@ -19,7 +19,6 @@ import torch import vllm.model_executor.layers.fused_moe.modular_kernel as mk -from vllm.logger import init_logger from vllm.model_executor.layers.fused_moe.ex...
63
35
1
[ "minimax" ]
[ "ROCM" ]
[]
Optimize this triton kernel file from vllm (vllm/model_executor/layers/fused_moe/experts/mxfp8_native_moe.py). Goal: [ROCm][Perf] MXFP8 dense-linear + grouped-MoE GEMM optimizations for MiniMax-M3 Target hardware: ROCM Target models: minimax Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCop...
## Summary Numerically-equivalent Triton-kernel optimizations for the native MXFP8 path of MiniMax-M3 on AMD MI355X (CDNA4 / gfx950). Math is unchanged (`tl.dot_scaled`, fp32 accumulate; outputs numerically identical to the current kernels, tol 6e-2). **AMD/ROCm-only**: both kernels are gated on `current_platform.is_r...
[{"scope": "e2e", "hardware": "MI355X", "model": "MiniMax-M3", "shape": "ISL=8192,OSL=1024", "batch_size": 1, "metric": "throughput", "unit": "tok/s", "higher_is_better": true, "baseline": 64.8, "optimized": 93.6, "stated_speedup": 1.44, "speedup": 1.4444}, {"scope": "e2e", "hardware": "MI355X", "model": "MiniMax-M3", ...
null
1.3353
vllm
c85d72076ae2263e0634a6bdb7c1b8a4b0cbab11
2026-07-07T15:05:47+05:30
47,321
https://github.com/vllm-project/vllm/pull/47321
[HARDWARE][POWER] optimize math functions of VSX power (#47321)
[HARDWARE][POWER] optimize math functions of VSX power (#47321) Signed-off-by: Akash Kaothalkar <akashkaothalkar@akashs-mbp.bl1-in.ibm.com> Signed-off-by: Akash Kaothalkar <akash.kaothalkar@ibm.com> Signed-off-by: Akash kaothalkar <akash.kaothalkar@ibm.com> Signed-off-by: Rukhaiya <bibirukhaiya123@gmail.com> Co-autho...
csrc/cpu/cpu_attn_vsx.hpp
cpp
Apache-2.0
// SPDX-License-Identifier: Apache-2.0 // SPDX-FileCopyrightText: Copyright contributors to the vLLM project #ifndef CPU_ATTN_VSX_HPP #define CPU_ATTN_VSX_HPP #include "cpu_attn_impl.hpp" #include <altivec.h> #include <type_traits> namespace cpu_attention { namespace { // ppc64le Vector = 16 bytes (128 bits) #defin...
// SPDX-License-Identifier: Apache-2.0 // SPDX-FileCopyrightText: Copyright contributors to the vLLM project #ifndef CPU_ATTN_VSX_HPP #define CPU_ATTN_VSX_HPP #include "cpu_attn_impl.hpp" #include <altivec.h> #include <type_traits> namespace cpu_attention { namespace { // ppc64le Vector = 16 bytes (128 bits) #defin...
--- csrc/cpu/cpu_attn_vsx.hpp +++ csrc/cpu/cpu_attn_vsx.hpp @@ -323,8 +323,6 @@ const int64_t num_blocks_stride, const int64_t cache_head_num_stride, const int64_t block_size, const int64_t block_size_stride, const float k_inv = 0.0f, const float v_inv = 0.0f) { - // k_inv and v_inv are unused o...
0
2
5
[]
[ "CPU" ]
[]
Optimize this cpp kernel file from vllm (csrc/cpu/cpu_attn_vsx.hpp). Goal: [HARDWARE][POWER] optimize math functions of VSX power Target hardware: CPU Target models: unspecified Current file: ```cpp // SPDX-License-Identifier: Apache-2.0 // SPDX-FileCopyrightText: Copyright contributors to the vLLM project #ifndef C...
## Summary Adds PowerPC VSX (Vector Scalar Extension) support to the vLLM CPU attention backend for optimized inference on POWER architecture systems.
[]
null
null
vllm
c85d72076ae2263e0634a6bdb7c1b8a4b0cbab11
2026-07-07T15:05:47+05:30
47,321
https://github.com/vllm-project/vllm/pull/47321
[HARDWARE][POWER] optimize math functions of VSX power (#47321)
[HARDWARE][POWER] optimize math functions of VSX power (#47321) Signed-off-by: Akash Kaothalkar <akashkaothalkar@akashs-mbp.bl1-in.ibm.com> Signed-off-by: Akash Kaothalkar <akash.kaothalkar@ibm.com> Signed-off-by: Akash kaothalkar <akash.kaothalkar@ibm.com> Signed-off-by: Rukhaiya <bibirukhaiya123@gmail.com> Co-autho...
csrc/cpu/cpu_types.hpp
cpp
Apache-2.0
#ifndef CPU_TYPES_HPP #define CPU_TYPES_HPP #if defined(__x86_64__) // x86 implementation #include "cpu_types_x86.hpp" #elif defined(__POWER9_VECTOR__) // ppc implementation #include "cpu_types_vsx.hpp" #elif defined(__s390x__) // s390 implementation #include "cpu_types_vxe.hpp" #elif defined(__aarch64__) ...
#ifndef CPU_TYPES_HPP #define CPU_TYPES_HPP #if defined(__x86_64__) // x86 implementation #include "cpu_types_x86.hpp" #elif defined(__powerpc__) // ppc implementation #include "cpu_types_vsx.hpp" #elif defined(__s390x__) // s390 implementation #include "cpu_types_vxe.hpp" #elif defined(__aarch64__) // a...
--- csrc/cpu/cpu_types.hpp +++ csrc/cpu/cpu_types.hpp @@ -4,7 +4,7 @@ #if defined(__x86_64__) // x86 implementation #include "cpu_types_x86.hpp" -#elif defined(__POWER9_VECTOR__) +#elif defined(__powerpc__) // ppc implementation #include "cpu_types_vsx.hpp" #elif defined(__s390x__)
1
1
5
[]
[ "CPU" ]
[]
Optimize this cpp kernel file from vllm (csrc/cpu/cpu_types.hpp). Goal: [HARDWARE][POWER] optimize math functions of VSX power Target hardware: CPU Target models: unspecified Current file: ```cpp #ifndef CPU_TYPES_HPP #define CPU_TYPES_HPP #if defined(__x86_64__) // x86 implementation #include "cpu_types_x86.hp...
## Summary Adds PowerPC VSX (Vector Scalar Extension) support to the vLLM CPU attention backend for optimized inference on POWER architecture systems.
[]
null
null
vllm
c85d72076ae2263e0634a6bdb7c1b8a4b0cbab11
2026-07-07T15:05:47+05:30
47,321
https://github.com/vllm-project/vllm/pull/47321
[HARDWARE][POWER] optimize math functions of VSX power (#47321)
[HARDWARE][POWER] optimize math functions of VSX power (#47321) Signed-off-by: Akash Kaothalkar <akashkaothalkar@akashs-mbp.bl1-in.ibm.com> Signed-off-by: Akash Kaothalkar <akash.kaothalkar@ibm.com> Signed-off-by: Akash kaothalkar <akash.kaothalkar@ibm.com> Signed-off-by: Rukhaiya <bibirukhaiya123@gmail.com> Co-autho...
csrc/cpu/cpu_types_vsx.hpp
cpp
Apache-2.0
#ifndef CPU_TYPES_VSX_HPP #define CPU_TYPES_VSX_HPP #include <altivec.h> #include <cmath> #include <algorithm> #include <torch/all.h> namespace vec_op { // FP8 tag types for tag dispatch (see cpu_attn_vec.hpp) struct fp8_e4m3_tag {}; struct fp8_e5m2_tag {}; #define VLLM_DISPATCH_CASE_FLOATING_TYPES(...) ...
#ifndef CPU_TYPES_VSX_HPP #define CPU_TYPES_VSX_HPP #include <altivec.h> #include <cmath> #include <algorithm> #include <torch/all.h> namespace vec_op { // FP8 tag types for tag dispatch (see cpu_attn_vec.hpp) struct fp8_e4m3_tag {}; struct fp8_e5m2_tag {}; #define VLLM_DISPATCH_CASE_FLOATING_TYPES(...) ...
--- csrc/cpu/cpu_types_vsx.hpp +++ csrc/cpu/cpu_types_vsx.hpp @@ -344,53 +344,133 @@ return result; } - FP32Vec8 exp() const { - // TODO: Vectorize this - AliasReg ar; - ar.reg = reg; - f32x4x4_t ret; - ret.val[0][0] = std::exp(ar.values[0]); - ret.val[0][1] = std::exp(ar.values[1]); - ...
120
40
5
[]
[ "CPU" ]
[]
Optimize this cpp kernel file from vllm (csrc/cpu/cpu_types_vsx.hpp). Goal: [HARDWARE][POWER] optimize math functions of VSX power Target hardware: CPU Target models: unspecified Current file: ```cpp #ifndef CPU_TYPES_VSX_HPP #define CPU_TYPES_VSX_HPP #include <altivec.h> #include <cmath> #include <algorithm> #inc...
## Summary Adds PowerPC VSX (Vector Scalar Extension) support to the vLLM CPU attention backend for optimized inference on POWER architecture systems.
[]
null
null
vllm
c85d72076ae2263e0634a6bdb7c1b8a4b0cbab11
2026-07-07T15:05:47+05:30
47,321
https://github.com/vllm-project/vllm/pull/47321
[HARDWARE][POWER] optimize math functions of VSX power (#47321)
[HARDWARE][POWER] optimize math functions of VSX power (#47321) Signed-off-by: Akash Kaothalkar <akashkaothalkar@akashs-mbp.bl1-in.ibm.com> Signed-off-by: Akash Kaothalkar <akash.kaothalkar@ibm.com> Signed-off-by: Akash kaothalkar <akash.kaothalkar@ibm.com> Signed-off-by: Rukhaiya <bibirukhaiya123@gmail.com> Co-autho...
csrc/cpu/utils.hpp
cpp
Apache-2.0
#ifndef UTILS_HPP #define UTILS_HPP #include <atomic> #include <string> #include <unistd.h> #include <ATen/cpu/Utils.h> #include "cpu/cpu_types.hpp" namespace cpu_utils { enum class ISA { AMX, VEC, RVV, NEON }; inline ISA get_isa(const std::string& isa) { if (isa == "amx") { return ISA::AMX; } else if (isa ...
#ifndef UTILS_HPP #define UTILS_HPP #include <atomic> #include <string> #include <unistd.h> #include <ATen/cpu/Utils.h> #include "cpu/cpu_types.hpp" namespace cpu_utils { enum class ISA { AMX, VEC, RVV, NEON }; inline ISA get_isa(const std::string& isa) { if (isa == "amx") { return ISA::AMX; } else if (isa ...
--- csrc/cpu/utils.hpp +++ csrc/cpu/utils.hpp @@ -76,14 +76,14 @@ if (l2_cache_size == 0) { l2_cache_size = 256 * 1024; } - return static_cast<int64_t>(l2_cache_size) >> 1; // use 50% of L2 cache + return static_cast<int64_t>(l2_cache_size) >> 1; }(); return size; #else static int64_t ...
2
2
5
[]
[ "CPU" ]
[]
Optimize this cpp kernel file from vllm (csrc/cpu/utils.hpp). Goal: [HARDWARE][POWER] optimize math functions of VSX power Target hardware: CPU Target models: unspecified Current file: ```cpp #ifndef UTILS_HPP #define UTILS_HPP #include <atomic> #include <string> #include <unistd.h> #include <ATen/cpu/Utils.h> #in...
## Summary Adds PowerPC VSX (Vector Scalar Extension) support to the vLLM CPU attention backend for optimized inference on POWER architecture systems.
[]
null
null
vllm
c85d72076ae2263e0634a6bdb7c1b8a4b0cbab11
2026-07-07T15:05:47+05:30
47,321
https://github.com/vllm-project/vllm/pull/47321
[HARDWARE][POWER] optimize math functions of VSX power (#47321)
[HARDWARE][POWER] optimize math functions of VSX power (#47321) Signed-off-by: Akash Kaothalkar <akashkaothalkar@akashs-mbp.bl1-in.ibm.com> Signed-off-by: Akash Kaothalkar <akash.kaothalkar@ibm.com> Signed-off-by: Akash kaothalkar <akash.kaothalkar@ibm.com> Signed-off-by: Rukhaiya <bibirukhaiya123@gmail.com> Co-autho...
vllm/model_executor/layers/activation.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Custom activation functions.""" import math import torch import torch.nn as nn import torch.nn.functional as F from vllm.distributed import ( divide, get_tensor_model_parallel_rank, get_tensor_mo...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Custom activation functions.""" import math import torch import torch.nn as nn import torch.nn.functional as F from vllm.distributed import ( divide, get_tensor_model_parallel_rank, get_tensor_mo...
--- vllm/model_executor/layers/activation.py +++ vllm/model_executor/layers/activation.py @@ -129,10 +129,12 @@ def __init__(self, *, compile_native: bool = True): super().__init__(compile_native=compile_native) - if current_platform.is_cuda_alike() or current_platform.is_xpu(): + if ( + ...
30
8
5
[]
[]
[]
Optimize this triton kernel file from vllm (vllm/model_executor/layers/activation.py). Goal: [HARDWARE][POWER] optimize math functions of VSX power Target hardware: unspecified Target models: unspecified Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to...
## Summary Adds PowerPC VSX (Vector Scalar Extension) support to the vLLM CPU attention backend for optimized inference on POWER architecture systems.
[]
null
null
vllm
066f02ae94c75d7e3ad7f0faaa2df348fce98c8d
2026-07-07T12:08:36+03:00
47,427
https://github.com/vllm-project/vllm/pull/47427
[MoE] FI autotuning: max bucket = max token count [e.g. `DP_size*MNBT`] (#47427)
[MoE] FI autotuning: max bucket = max token count [e.g. `DP_size*MNBT`] (#47427) Signed-off-by: Netanel Haber <58652339+netanel-haber@users.noreply.github.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
vllm/model_executor/layers/fused_moe/utils.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project import functools from math import prod import torch import torch.nn.functional as F from vllm import _custom_ops as ops from vllm.model_executor.layers.quantization.utils.fp8_utils import ( per_token_group_q...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project import functools from math import prod from typing import TYPE_CHECKING import torch import torch.nn.functional as F from vllm import _custom_ops as ops from vllm.model_executor.layers.quantization.utils.fp8_uti...
--- vllm/model_executor/layers/fused_moe/utils.py +++ vllm/model_executor/layers/fused_moe/utils.py @@ -2,6 +2,7 @@ # SPDX-FileCopyrightText: Copyright contributors to the vLLM project import functools from math import prod +from typing import TYPE_CHECKING import torch import torch.nn.functional as F @@ -32,6 +...
21
0
4
[]
[]
[]
Optimize this triton kernel file from vllm (vllm/model_executor/layers/fused_moe/utils.py). Goal: [MoE] FI autotuning: max bucket = max token count [e.g. `DP_size*MNBT`] Target hardware: unspecified Target models: unspecified Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copy...
vLLM does not pass `tune_max_num_tokens` to FlashInfer’s BF16, FP8, and NVFP4 TRT-LLM MoE kernels. FlashInfer therefore ends autotuning at its default maximum bucket of 8192. This can be too low. The estimated maximum token count is: `DP size * max_num_batched_tokens` Larger inputs still run, but use a tactic tuned f...
[{"scope": "e2e", "hardware": "NVIDIA GB200", "model": "Nemotron Ultra NVFP4", "shape": "DP_size*MNBT=4*8192=32768", "batch_size": 128, "metric": "Output TPS", "unit": "tok/s", "higher_is_better": true, "baseline": 1706.8, "optimized": 1751.5, "stated_speedup": 1.0262, "speedup": 1.0262}, {"scope": "e2e", "hardware": "...
null
1.0291
vllm
f70caef48b9263e8f86fdf20a04a4933a5f75083
2026-07-06T11:17:46-04:00
47,474
https://github.com/vllm-project/vllm/pull/47474
[Perf] Cache `token_to_req_indices` for dsv4, 5x~6x kernel performance improvement (#47474)
[Perf] Cache `token_to_req_indices` for dsv4, 5x~6x kernel performance improvement (#47474) Signed-off-by: yewentao256 <zhyanwentao@126.com>
vllm/v1/attention/backends/mla/sparse_swa.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project from dataclasses import dataclass, field from typing import ClassVar, cast import torch from vllm.config import CacheConfig, VllmConfig, get_current_vllm_config from vllm.model_executor.layers.attention_layer_ba...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project from dataclasses import dataclass, field from typing import ClassVar, cast import torch from vllm.config import CacheConfig, VllmConfig, get_current_vllm_config from vllm.model_executor.layers.attention_layer_ba...
--- vllm/v1/attention/backends/mla/sparse_swa.py +++ vllm/v1/attention/backends/mla/sparse_swa.py @@ -399,7 +399,6 @@ For prefill, we use chunked prefill to align with the indexer's chunking. """ - num_reqs = common_attn_metadata.num_reqs seq_lens = common_attn_metadata.seq_lens ...
3
5
2
[ "deepseek" ]
[]
[ "5x", "6x" ]
Optimize this triton kernel file from vllm (vllm/v1/attention/backends/mla/sparse_swa.py). Goal: [Perf] Cache `token_to_req_indices` for dsv4, 5x~6x kernel performance improvement Target hardware: unspecified Target models: deepseek Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightTex...
## Purpose So we save two additional copy from CPU to GPU ## Test ### Acc ```bash vllm serve deepseek-ai/DeepSeek-V4-Flash --trust-remote-code --kv-cache-dtype fp8 --block-size 256 --enable-expert-parallel --tensor-parallel-size 4 --attention_config.use_fp4_indexer_cache=True --moe-backend deep_gemm_m...
[{"scope": "kernel", "hardware": null, "model": null, "shape": "num_reqs=32,query_len=1,pad_tokens=0", "batch_size": 32, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 194.97, "optimized": 32.73, "stated_speedup": null, "speedup": 5.9569}, {"scope": "kernel", "hardware": null, "model": null, ...
5.9796
null
vllm
e433634c781dce7ee55563424b8136ad3495c1be
2026-07-06T13:58:56+08:00
47,538
https://github.com/vllm-project/vllm/pull/47538
[Performance][Hardware][RISC-V] Reduce LMUL pressure in INT4 LUT dequant (#47538)
[Performance][Hardware][RISC-V] Reduce LMUL pressure in INT4 LUT dequant (#47538) Signed-off-by: liutong <liutong@iscas.ac.cn> Co-authored-by: Claude <noreply@anthropic.com>
csrc/cpu/cpu_types_riscv_impl.hpp
cpp
Apache-2.0
#ifndef CPU_TYPES_RISCV_IMPL_HPP #define CPU_TYPES_RISCV_IMPL_HPP // Shared implementation of RVV vector-type wrapper classes. // This file is VLEN-independent: it uses the semantic type names and // RVVI() intrinsic macros from cpu_types_riscv_defs.hpp. // // DO NOT include this file directly; include cpu_types_riscv...
#ifndef CPU_TYPES_RISCV_IMPL_HPP #define CPU_TYPES_RISCV_IMPL_HPP // Shared implementation of RVV vector-type wrapper classes. // This file is VLEN-independent: it uses the semantic type names and // RVVI() intrinsic macros from cpu_types_riscv_defs.hpp. // // DO NOT include this file directly; include cpu_types_riscv...
--- csrc/cpu/cpu_types_riscv_impl.hpp +++ csrc/cpu/cpu_types_riscv_impl.hpp @@ -623,17 +623,30 @@ data.reg, data.reg)) {}; explicit FP32Vec16(const FP32Vec16& data) : reg(data.reg) {}; explicit FP32Vec16(int64_t value, const FP32Vec16& lut) { - const uint64_t q_values = static_cast<uint64_t>(value...
23
10
1
[]
[ "CPU" ]
[]
Optimize this cpp kernel file from vllm (csrc/cpu/cpu_types_riscv_impl.hpp). Goal: [Performance][Hardware][RISC-V] Reduce LMUL pressure in INT4 LUT dequant Target hardware: CPU Target models: unspecified Current file: ```cpp #ifndef CPU_TYPES_RISCV_IMPL_HPP #define CPU_TYPES_RISCV_IMPL_HPP // Shared implementation o...
## Purpose The FP32Vec16(int64_t, FP32Vec16&) LUT constructor extracts 16 four-bit nibble indices from a packed int64 using u64 vectors at LMUL_1024. Using u64 to process an int64 input is natural — on fixed-width SIMD like x86 AVX, element width has no impact on register file pressure. However, RVV's variable-lengt...
[{"scope": "kernel", "hardware": "Spacemit X100", "model": null, "shape": null, "batch_size": null, "metric": "latency", "unit": "ns", "higher_is_better": false, "baseline": 14.2, "optimized": 6.8, "stated_speedup": 2.08, "speedup": 2.0882}]
2.0882
null
vllm
89e99202f285d1dc1168f87f6cc3e26e930970ff
2026-07-01T07:24:40+01:00
44,639
https://github.com/vllm-project/vllm/pull/44639
[CPU][Perf]Added tanh AOR for faster gelu activations. (#44639)
[CPU][Perf]Added tanh AOR for faster gelu activations. (#44639) Signed-off-by: Anna Mayne <anna.mayne@arm.com> Signed-off-by: almayne <anna.mayne@arm.com> Co-authored-by: Li, Jiang <jiang1.li@intel.com>
csrc/cpu/activation.cpp
cpp
Apache-2.0
#include "cpu_types.hpp" namespace { template <typename scalar_t, vec_op::FP32Vec8 (*func)(const vec_op::FP32Vec8&), bool is_gated> void activation_kernel(int num_tokens, int d, scalar_t* __restrict__ input, scalar_t* __restrict__ output) { using scalar_vec_t = vec_op::vec_t<scalar_t...
#include "cpu_types.hpp" namespace { template <typename scalar_t, vec_op::FP32Vec8 (*func)(const vec_op::FP32Vec8&), bool is_gated> void activation_kernel(int num_tokens, int d, scalar_t* __restrict__ input, scalar_t* __restrict__ output) { using scalar_vec_t = vec_op::vec_t<scalar_t...
--- csrc/cpu/activation.cpp +++ csrc/cpu/activation.cpp @@ -126,6 +126,18 @@ }); } +void gelu_tanh(torch::Tensor& out, torch::Tensor& input) { + int num_tokens = input.numel() / input.size(-1); + int d = input.size(-1); + + VLLM_DISPATCH_FLOATING_TYPES(input.scalar_type(), "gelu_tanh_impl", [&] { + CPU_...
12
0
5
[]
[ "CPU" ]
[]
Optimize this cpp kernel file from vllm (csrc/cpu/activation.cpp). Goal: [CPU][Perf]Added tanh AOR for faster gelu activations. Target hardware: CPU Target models: unspecified Current file: ```cpp #include "cpu_types.hpp" namespace { template <typename scalar_t, vec_op::FP32Vec8 (*func)(const vec_op::FP32Vec8&), ...
Co-authored-by: GPT 5.4 ## Purpose Add the Arm Optimised Routine for tanh on SIMD architectures. This is enabled for gelu activations where the tanh approximation is used. ## Test Plan - Add a unit test and ensure it passes. - Compare performance of new implementation and PyTorch's F.gelu(tanh). ## Test Result The ...
[{"scope": "kernel", "hardware": null, "model": null, "shape": "M=4096,N=4096", "batch_size": null, "metric": "speedup", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 1.86, "speedup": 1.86}, {"scope": "kernel", "hardware": null, "model": null, "shape": "M=8192,N=4096", "...
2.116
null
vllm
89e99202f285d1dc1168f87f6cc3e26e930970ff
2026-07-01T07:24:40+01:00
44,639
https://github.com/vllm-project/vllm/pull/44639
[CPU][Perf]Added tanh AOR for faster gelu activations. (#44639)
[CPU][Perf]Added tanh AOR for faster gelu activations. (#44639) Signed-off-by: Anna Mayne <anna.mayne@arm.com> Signed-off-by: almayne <anna.mayne@arm.com> Co-authored-by: Li, Jiang <jiang1.li@intel.com>
csrc/cpu/cpu_types_arm.hpp
cpp
Apache-2.0
#include <cmath> #include <type_traits> #include <arm_neon.h> #include <torch/all.h> #include <ATen/cpu/vec/functional.h> #include <ATen/cpu/vec/vec.h> #if defined(__APPLE__) #include "omp.h" #endif using namespace at::vec; namespace vec_op { struct fp8_e4m3_tag {}; struct fp8_e5m2_tag {}; #define VLLM_DISPATC...
#include <cmath> #include <type_traits> #include <arm_neon.h> #include "cpu/cpu_tanhf_neon.hpp" #include <torch/all.h> #include <ATen/cpu/vec/functional.h> #include <ATen/cpu/vec/vec.h> #if defined(__APPLE__) #include "omp.h" #endif using namespace at::vec; namespace vec_op { struct fp8_e4m3_tag {}; struct fp8...
--- csrc/cpu/cpu_types_arm.hpp +++ csrc/cpu/cpu_types_arm.hpp @@ -2,6 +2,8 @@ #include <type_traits> #include <arm_neon.h> + +#include "cpu/cpu_tanhf_neon.hpp" #include <torch/all.h> #include <ATen/cpu/vec/functional.h> @@ -345,6 +347,10 @@ explicit FP32Vec4(float32x4_t data) : Base(VectorizedT(data)) {}; ...
22
0
5
[]
[ "CPU" ]
[]
Optimize this cpp kernel file from vllm (csrc/cpu/cpu_types_arm.hpp). Goal: [CPU][Perf]Added tanh AOR for faster gelu activations. Target hardware: CPU Target models: unspecified Current file: ```cpp #include <cmath> #include <type_traits> #include <arm_neon.h> #include <torch/all.h> #include <ATen/cpu/vec/function...
Co-authored-by: GPT 5.4 ## Purpose Add the Arm Optimised Routine for tanh on SIMD architectures. This is enabled for gelu activations where the tanh approximation is used. ## Test Plan - Add a unit test and ensure it passes. - Compare performance of new implementation and PyTorch's F.gelu(tanh). ## Test Result The ...
[{"scope": "kernel", "hardware": null, "model": null, "shape": "M=4096,N=4096", "batch_size": null, "metric": "speedup", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 1.86, "speedup": 1.86}, {"scope": "kernel", "hardware": null, "model": null, "shape": "M=8192,N=4096", "...
2.116
null
vllm
89e99202f285d1dc1168f87f6cc3e26e930970ff
2026-07-01T07:24:40+01:00
44,639
https://github.com/vllm-project/vllm/pull/44639
[CPU][Perf]Added tanh AOR for faster gelu activations. (#44639)
[CPU][Perf]Added tanh AOR for faster gelu activations. (#44639) Signed-off-by: Anna Mayne <anna.mayne@arm.com> Signed-off-by: almayne <anna.mayne@arm.com> Co-authored-by: Li, Jiang <jiang1.li@intel.com>
csrc/cpu/torch_bindings.cpp
cpp
Apache-2.0
#include "cache.h" #include "ops.h" #include "core/registration.h" #include <torch/library.h> // Note: overwrite the external definition for sharing same name between // libraries use different ISAs. #define TORCH_EXTENSION_NAME _C void release_dnnl_matmul_handler(int64_t handler); int64_t create_onednn_scaled_mm_h...
#include "cache.h" #include "ops.h" #include "core/registration.h" #include <torch/library.h> // Note: overwrite the external definition for sharing same name between // libraries use different ISAs. #define TORCH_EXTENSION_NAME _C void release_dnnl_matmul_handler(int64_t handler); int64_t create_onednn_scaled_mm_h...
--- csrc/cpu/torch_bindings.cpp +++ csrc/cpu/torch_bindings.cpp @@ -298,6 +298,10 @@ ops.def("gelu_tanh_and_mul(Tensor! out, Tensor input) -> ()"); ops.impl("gelu_tanh_and_mul", torch::kCPU, &gelu_tanh_and_mul); + // GELU tanh implementation. + ops.def("gelu_tanh(Tensor! out, Tensor input) -> ()"); + ops.imp...
4
0
5
[]
[ "CPU" ]
[]
Optimize this cpp kernel file from vllm (csrc/cpu/torch_bindings.cpp). Goal: [CPU][Perf]Added tanh AOR for faster gelu activations. Target hardware: CPU Target models: unspecified Current file: ```cpp #include "cache.h" #include "ops.h" #include "core/registration.h" #include <torch/library.h> // Note: overwrite th...
Co-authored-by: GPT 5.4 ## Purpose Add the Arm Optimised Routine for tanh on SIMD architectures. This is enabled for gelu activations where the tanh approximation is used. ## Test Plan - Add a unit test and ensure it passes. - Compare performance of new implementation and PyTorch's F.gelu(tanh). ## Test Result The ...
[{"scope": "kernel", "hardware": null, "model": null, "shape": "M=4096,N=4096", "batch_size": null, "metric": "speedup", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 1.86, "speedup": 1.86}, {"scope": "kernel", "hardware": null, "model": null, "shape": "M=8192,N=4096", "...
2.116
null
vllm
89e99202f285d1dc1168f87f6cc3e26e930970ff
2026-07-01T07:24:40+01:00
44,639
https://github.com/vllm-project/vllm/pull/44639
[CPU][Perf]Added tanh AOR for faster gelu activations. (#44639)
[CPU][Perf]Added tanh AOR for faster gelu activations. (#44639) Signed-off-by: Anna Mayne <anna.mayne@arm.com> Signed-off-by: almayne <anna.mayne@arm.com> Co-authored-by: Li, Jiang <jiang1.li@intel.com>
csrc/ops.h
cpp
Apache-2.0
#pragma once #include <optional> #include <string> #include <torch/library.h> #include <tuple> #include "core/scalar_type.hpp" #include <vector> // rms_norm and fused_add_rms_norm declarations also exist in // csrc/libtorch_stable/ops.h (torch::stable ABI for CUDA). They remain here // because the CPU build still u...
#pragma once #include <optional> #include <string> #include <torch/library.h> #include <tuple> #include "core/scalar_type.hpp" #include <vector> // rms_norm and fused_add_rms_norm declarations also exist in // csrc/libtorch_stable/ops.h (torch::stable ABI for CUDA). They remain here // because the CPU build still u...
--- csrc/ops.h +++ csrc/ops.h @@ -35,6 +35,8 @@ void gelu_tanh_and_mul(torch::Tensor& out, torch::Tensor& input); +void gelu_tanh(torch::Tensor& out, torch::Tensor& input); + void gelu_new(torch::Tensor& out, torch::Tensor& input); void gelu_fast(torch::Tensor& out, torch::Tensor& input);
2
0
5
[]
[ "CPU" ]
[]
Optimize this cpp kernel file from vllm (csrc/ops.h). Goal: [CPU][Perf]Added tanh AOR for faster gelu activations. Target hardware: CPU Target models: unspecified Current file: ```cpp #pragma once #include <optional> #include <string> #include <torch/library.h> #include <tuple> #include "core/scalar_type.hpp" #inc...
Co-authored-by: GPT 5.4 ## Purpose Add the Arm Optimised Routine for tanh on SIMD architectures. This is enabled for gelu activations where the tanh approximation is used. ## Test Plan - Add a unit test and ensure it passes. - Compare performance of new implementation and PyTorch's F.gelu(tanh). ## Test Result The ...
[{"scope": "kernel", "hardware": null, "model": null, "shape": "M=4096,N=4096", "batch_size": null, "metric": "speedup", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 1.86, "speedup": 1.86}, {"scope": "kernel", "hardware": null, "model": null, "shape": "M=8192,N=4096", "...
2.116
null
vllm
89e99202f285d1dc1168f87f6cc3e26e930970ff
2026-07-01T07:24:40+01:00
44,639
https://github.com/vllm-project/vllm/pull/44639
[CPU][Perf]Added tanh AOR for faster gelu activations. (#44639)
[CPU][Perf]Added tanh AOR for faster gelu activations. (#44639) Signed-off-by: Anna Mayne <anna.mayne@arm.com> Signed-off-by: almayne <anna.mayne@arm.com> Co-authored-by: Li, Jiang <jiang1.li@intel.com>
vllm/model_executor/layers/activation.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Custom activation functions.""" import math import torch import torch.nn as nn import torch.nn.functional as F from vllm.distributed import ( divide, get_tensor_model_parallel_rank, get_tensor_mo...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Custom activation functions.""" import math import torch import torch.nn as nn import torch.nn.functional as F from vllm.distributed import ( divide, get_tensor_model_parallel_rank, get_tensor_mo...
--- vllm/model_executor/layers/activation.py +++ vllm/model_executor/layers/activation.py @@ -313,8 +313,10 @@ def __init__(self): super().__init__() - if current_platform.get_cpu_architecture() == CpuArchEnum.ARM and hasattr( - torch.ops._C, "activation_lut_bf16" + if ( + ...
46
3
5
[]
[ "CPU" ]
[]
Optimize this triton kernel file from vllm (vllm/model_executor/layers/activation.py). Goal: [CPU][Perf]Added tanh AOR for faster gelu activations. Target hardware: CPU Target models: unspecified Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM...
Co-authored-by: GPT 5.4 ## Purpose Add the Arm Optimised Routine for tanh on SIMD architectures. This is enabled for gelu activations where the tanh approximation is used. ## Test Plan - Add a unit test and ensure it passes. - Compare performance of new implementation and PyTorch's F.gelu(tanh). ## Test Result The ...
[{"scope": "kernel", "hardware": null, "model": null, "shape": "M=4096,N=4096", "batch_size": null, "metric": "speedup", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 1.86, "speedup": 1.86}, {"scope": "kernel", "hardware": null, "model": null, "shape": "M=8192,N=4096", "...
2.116
null
vllm
b588f66dc2982fe3228e0aee55b80387d31db2e4
2026-06-27T01:16:20-04:00
46,862
https://github.com/vllm-project/vllm/pull/46862
[GLM5.2 Perf] `fused_indexer_q_rope_quant` triton kernel, 1.9% ~ 3.3% E2E Throughput improvement. (#46862)
[GLM5.2 Perf] `fused_indexer_q_rope_quant` triton kernel, 1.9% ~ 3.3% E2E Throughput improvement. (#46862) Signed-off-by: yewentao256 <zhyanwentao@126.com>
vllm/model_executor/layers/sparse_attn_indexer.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Custom Sparse Attention Indexer layers.""" import torch import vllm.envs as envs from vllm import _custom_ops as ops from vllm._aiter_ops import rocm_aiter_ops from vllm.compilation.breakable_cudagraph import...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Custom Sparse Attention Indexer layers.""" import torch import vllm.envs as envs from vllm import _custom_ops as ops from vllm._aiter_ops import rocm_aiter_ops from vllm.compilation.breakable_cudagraph import...
--- vllm/model_executor/layers/sparse_attn_indexer.py +++ vllm/model_executor/layers/sparse_attn_indexer.py @@ -11,7 +11,11 @@ from vllm.forward_context import get_forward_context from vllm.logger import init_logger from vllm.model_executor.custom_op import CustomOp +from vllm.model_executor.layers.quantization.util...
131
0
1
[ "glm" ]
[]
[]
Optimize this triton kernel file from vllm (vllm/model_executor/layers/sparse_attn_indexer.py). Goal: [GLM5.2 Perf] `fused_indexer_q_rope_quant` triton kernel, 1.9% ~ 3.3% E2E Throughput improvement. Target hardware: unspecified Target models: glm Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-F...
## Purpose We have similar fused kernel in DSv4, this path works for GLM as wel Originally: `Q RoPE -> cat -> FP8 quant -> q_scale fold into weights` Now: `Q RoPE + FP8 quant + q_scale fold into weights` in one triton kernel. ## Test `vllm serve zai-org/GLM-5.2-FP8 --kv-cache-dtype fp8_e4m3 --enable-expert-pa...
[]
null
null
vllm
c2507fb2937aa8c8e74bea15719d04fb6090befe
2026-06-26T10:05:20-04:00
46,545
https://github.com/vllm-project/vllm/pull/46545
[ROCm] [MoE] [Perf] Shared-expert fusion for bias-routed MoE; enable on MiniMax-M3 mxfp8 model (#46545)
[ROCm] [MoE] [Perf] Shared-expert fusion for bias-routed MoE; enable on MiniMax-M3 mxfp8 model (#46545) Signed-off-by: Hongxia Yang <hongxia.yang@amd.com> Co-authored-by: Claude Opus 4.8 <noreply@anthropic.com>
vllm/model_executor/layers/fused_moe/experts/mxfp8_native_moe.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Native MXFP8 (1x32 block, E8M0 scale) MoE for AMD CDNA4 (gfx950) via Triton ``tl.dot_scaled`` (hardware microscaling matmul). The expert GEMMs consume the FP8 E4M3 weights and their E8M0 block scales directly ...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Native MXFP8 (1x32 block, E8M0 scale) MoE for AMD CDNA4 (gfx950) via Triton ``tl.dot_scaled`` (hardware microscaling matmul). The expert GEMMs consume the FP8 E4M3 weights and their E8M0 block scales directly ...
--- vllm/model_executor/layers/fused_moe/experts/mxfp8_native_moe.py +++ vllm/model_executor/layers/fused_moe/experts/mxfp8_native_moe.py @@ -227,10 +227,16 @@ tiles = _mxfp8_moe_tiles(T) block_m = tiles["block_m"] + # Bin by the actual number of expert weight rows. With fused shared experts + # the w...
7
1
4
[ "minimax" ]
[ "ROCM" ]
[]
Optimize this triton kernel file from vllm (vllm/model_executor/layers/fused_moe/experts/mxfp8_native_moe.py). Goal: [ROCm] [MoE] [Perf] Shared-expert fusion for bias-routed MoE; enable on MiniMax-M3 mxfp8 model Target hardware: ROCM Target models: minimax Current file: ```python # SPDX-License-Identifier: Apache-2.0...
## Purpose Perf optimization MiniMax-M3 runs its single shared expert as a separate dense MLP **every MoE layer** (a `gate_up` GEMM + activation + `down` GEMM on a side stream, ×60 layers). Folding it into the routed grouped GEMM removes those per-layer launches, which is the dominant cost at low/medium concurrenc...
[{"scope": "e2e", "hardware": null, "model": "MiniMax-M3", "shape": null, "batch_size": 1, "metric": "throughput", "unit": "tok/s", "higher_is_better": true, "baseline": 59.2, "optimized": 77.0, "stated_speedup": 1.302, "speedup": 1.3007}, {"scope": "e2e", "hardware": null, "model": "MiniMax-M3", "shape": null, "batch_...
null
1.105
vllm
e8e7b592d11d3ea5d5cdb78ee0f1ab4c5b440667
2026-06-25T13:38:28-06:00
46,642
https://github.com/vllm-project/vllm/pull/46642
[Kernel][MoE] Tune block-FP8 fused MoE for low-batch decode (#46642)
[Kernel][MoE] Tune block-FP8 fused MoE for low-batch decode (#46642) Signed-off-by: mgoin <mgoin64@gmail.com>
vllm/model_executor/layers/fused_moe/fused_moe.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Fused MoE Triton kernels.""" import functools import json import os from typing import Any import torch import vllm.envs as envs import vllm.model_executor.layers.fused_moe.modular_kernel as mk from vllm imp...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Fused MoE Triton kernels.""" import functools import json import os from typing import Any import torch import vllm.envs as envs import vllm.model_executor.layers.fused_moe.modular_kernel as mk from vllm imp...
--- vllm/model_executor/layers/fused_moe/fused_moe.py +++ vllm/model_executor/layers/fused_moe/fused_moe.py @@ -1257,19 +1257,38 @@ num_stages_rocm = 2 if dtype == "fp8_w8a8" and block_shape is not None: - # Block-wise quant: tile sizes are constrained by block_shape. - # Use a small M tile fo...
26
7
1
[]
[]
[]
Optimize this triton kernel file from vllm (vllm/model_executor/layers/fused_moe/fused_moe.py). Goal: [Kernel][MoE] Tune block-FP8 fused MoE for low-batch decode Target hardware: unspecified Target models: unspecified Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright co...
## Justification Block-quantized FP8 fused MoE was locked to `BLOCK_SIZE_N = block_shape[0]` (128) at every batch size — in both the runtime heuristic (`get_default_config`) and the tuner search space. At decode the gate-up GEMM is SM-bound: a 128-wide N tile produces too few thread blocks to fill the GPU. This was n...
[{"scope": "kernel", "hardware": "H200", "model": null, "shape": "E=384,N=128", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 42.1, "optimized": 38.2, "stated_speedup": 1.092, "speedup": 1.1021}, {"scope": "kernel", "hardware": "H200", "model": null, "shape": "E=384,N=128", ...
1.0989
null
vllm
77c1d9fe9b2b4f49fe8d98d5da5d9efc1134b9cd
2026-06-25T08:17:46+02:00
40,784
https://github.com/vllm-project/vllm/pull/40784
[ROCm][Perf] Tune wvSplitK on gfx1151 (#40784)
[ROCm][Perf] Tune wvSplitK on gfx1151 (#40784) Signed-off-by: Matthias Gehre <matthias.gehre@amd.com>
csrc/rocm/skinny_gemms.cu
cuda
Apache-2.0
#include <torch/all.h> #include <ATen/cuda/CUDAContext.h> #include <c10/cuda/CUDAGuard.h> #include <cuda_runtime.h> #include <cuda_fp16.h> #include <cuda_bf16.h> #include <stdexcept> #include <algorithm> #include "../cuda_compat.h" #include "dispatch_utils.h" #include "quantization/w8a8/fp8/common.cuh" #include "cor...
#include <torch/all.h> #include <ATen/cuda/CUDAContext.h> #include <c10/cuda/CUDAGuard.h> #include <cuda_runtime.h> #include <cuda_fp16.h> #include <cuda_bf16.h> #include <stdexcept> #include <algorithm> #include "../cuda_compat.h" #include "dispatch_utils.h" #include "quantization/w8a8/fp8/common.cuh" #include "cor...
--- csrc/rocm/skinny_gemms.cu +++ csrc/rocm/skinny_gemms.cu @@ -66,6 +66,15 @@ const auto* dprops = at::cuda::getCurrentDeviceProperties(); const std::string device_arch = dprops->gcnArchName; return device_arch.find("gfx12") != std::string::npos; + }(); + return result; +} + +bool on_gfx1151() { + st...
53
21
1
[]
[ "GFX1151", "ROCM" ]
[]
Optimize this cuda kernel file from vllm (csrc/rocm/skinny_gemms.cu). Goal: [ROCm][Perf] Tune wvSplitK on gfx1151 Target hardware: GFX1151, ROCM Target models: unspecified Current file: ```cuda #include <torch/all.h> #include <ATen/cuda/CUDAContext.h> #include <c10/cuda/CUDAGuard.h> #include <cuda_runtime.h> #includ...
## Summary Tune wvSplitK skinny GEMM kernel for gfx1151. ## Kernel benchmarks **bf16 `wvSplitK` kernel benchmark on Strix Halo (gfx1151, 20 CUs):** - `N=1` average: **+18.7%** bandwidth improvement - `N=2` average: **+19.8%** - `N=3` average: **+15.2%** - `N=4` average: **+13.0%** **fp16 `wvSplitK` kernel benchmar...
[{"scope": "kernel", "hardware": "gfx1151", "model": null, "shape": "N=1", "batch_size": null, "metric": "bandwidth", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 1.187, "speedup": 1.187}, {"scope": "kernel", "hardware": "gfx1151", "model": null, "shape": "N=2", "batch_...
1.152
1.0598
vllm
1273a8f05a1a3fa90c0edfdf1c6c87e70054e680
2026-06-24T18:44:30-07:00
36,559
https://github.com/vllm-project/vllm/pull/36559
[Kernel] Add swap AB optimization to fused_moe_kernel (#36559)
[Kernel] Add swap AB optimization to fused_moe_kernel (#36559) Signed-off-by: Xin Yang <xyangx@amazon.com>
vllm/model_executor/layers/fused_moe/fused_moe.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Fused MoE Triton kernels.""" import functools import json import os from typing import Any import torch import vllm.envs as envs import vllm.model_executor.layers.fused_moe.modular_kernel as mk from vllm imp...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Fused MoE Triton kernels.""" import functools import json import os from typing import Any import torch import vllm.envs as envs import vllm.model_executor.layers.fused_moe.modular_kernel as mk from vllm imp...
--- vllm/model_executor/layers/fused_moe/fused_moe.py +++ vllm/model_executor/layers/fused_moe/fused_moe.py @@ -26,6 +26,7 @@ moe_align_block_size, ) from vllm.model_executor.layers.fused_moe.utils import ( + enable_swap_ab, moe_kernel_quantize_input, ) from vllm.platforms import current_platform @@ -3...
50
15
2
[]
[]
[]
Optimize this triton kernel file from vllm (vllm/model_executor/layers/fused_moe/fused_moe.py). Goal: [Kernel] Add swap AB optimization to fused_moe_kernel Target hardware: unspecified Target models: unspecified Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contribu...
## Purpose This PR add swap AB optimization to `fused_moe_kernel` to make better use of WGMMA. Similar as #20396. For small BLOCK_SIZE_M cases (BLOCK_SIZE_M < 64), change the gemm from `a[M, K] @ b[K, N]-> c[M, N]` to `b[N, K] @ a[K, M] -> c[N, M]`. 2% to 4% e2e output token throughput improvement. ## Test Plan ``...
[{"scope": "kernel", "hardware": "H200", "model": "Qwen/Qwen3-Next-80B-A3B-Instruct-FP8", "shape": "BLOCK_SIZE_M=16,BLOCK_SIZE_N=128,BLOCK_SIZE_K=128,GROUP_SIZE_M=1", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 29.97, "optimized": 26.72, "stated_speedup": null, "speedup": ...
1.022
1.0231
vllm
1273a8f05a1a3fa90c0edfdf1c6c87e70054e680
2026-06-24T18:44:30-07:00
36,559
https://github.com/vllm-project/vllm/pull/36559
[Kernel] Add swap AB optimization to fused_moe_kernel (#36559)
[Kernel] Add swap AB optimization to fused_moe_kernel (#36559) Signed-off-by: Xin Yang <xyangx@amazon.com>
vllm/model_executor/layers/fused_moe/utils.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project from math import prod import torch import torch.nn.functional as F from vllm import _custom_ops as ops from vllm.model_executor.layers.quantization.utils.fp8_utils import ( per_token_group_quant_fp8, ) from ...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project import functools from math import prod import torch import torch.nn.functional as F from vllm import _custom_ops as ops from vllm.model_executor.layers.quantization.utils.fp8_utils import ( per_token_group_q...
--- vllm/model_executor/layers/fused_moe/utils.py +++ vllm/model_executor/layers/fused_moe/utils.py @@ -1,5 +1,6 @@ # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project +import functools from math import prod import torch @@ -446,3 +447,12 @@ up = tor...
10
0
2
[]
[]
[]
Optimize this triton kernel file from vllm (vllm/model_executor/layers/fused_moe/utils.py). Goal: [Kernel] Add swap AB optimization to fused_moe_kernel Target hardware: unspecified Target models: unspecified Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors...
## Purpose This PR add swap AB optimization to `fused_moe_kernel` to make better use of WGMMA. Similar as #20396. For small BLOCK_SIZE_M cases (BLOCK_SIZE_M < 64), change the gemm from `a[M, K] @ b[K, N]-> c[M, N]` to `b[N, K] @ a[K, M] -> c[N, M]`. 2% to 4% e2e output token throughput improvement. ## Test Plan ``...
[{"scope": "kernel", "hardware": "H200", "model": "Qwen/Qwen3-Next-80B-A3B-Instruct-FP8", "shape": "BLOCK_SIZE_M=16,BLOCK_SIZE_N=128,BLOCK_SIZE_K=128,GROUP_SIZE_M=1", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 29.97, "optimized": 26.72, "stated_speedup": null, "speedup": ...
1.022
1.0231
vllm
061043eacac0473769d86a1babb9adeb8402e833
2026-06-24T15:14:35+01:00
46,353
https://github.com/vllm-project/vllm/pull/46353
[CPU][Perf] Accelerate unquantized MoE for AArch64 (#46353)
[CPU][Perf] Accelerate unquantized MoE for AArch64 (#46353) Signed-off-by: Fadi Arafeh <fadi.arafeh@arm.com>
csrc/cpu/cpu_fused_moe.cpp
cpp
Apache-2.0
#include <sleef.h> #include "cpu/cpu_types.hpp" #include "cpu/utils.hpp" #include "cpu/micro_gemm/cpu_micro_gemm_vec.hpp" #include "cpu/cpu_arch_macros.h" #ifdef CPU_CAPABILITY_AMXBF16 #include "cpu/micro_gemm/cpu_micro_gemm_amx.hpp" #define AMX_DISPATCH(...) \ ...
#include "cpu/cpu_types.hpp" #include "cpu/utils.hpp" #include "cpu/micro_gemm/cpu_micro_gemm_vec.hpp" #include "cpu/cpu_arch_macros.h" #ifdef CPU_CAPABILITY_AMXBF16 #include "cpu/micro_gemm/cpu_micro_gemm_amx.hpp" #define AMX_DISPATCH(...) \ case cpu_utils::I...
--- csrc/cpu/cpu_fused_moe.cpp +++ csrc/cpu/cpu_fused_moe.cpp @@ -1,5 +1,3 @@ -#include <sleef.h> - #include "cpu/cpu_types.hpp" #include "cpu/utils.hpp" #include "cpu/micro_gemm/cpu_micro_gemm_vec.hpp" @@ -14,6 +12,18 @@ } #else #define AMX_DISPATCH(...) case cpu_utils::ISA::AMX: +#endif + +#if defined(ARM...
76
14
10
[]
[ "CPU" ]
[]
Optimize this cpp kernel file from vllm (csrc/cpu/cpu_fused_moe.cpp). Goal: [CPU][Perf] Accelerate unquantized MoE for AArch64 Target hardware: CPU Target models: unspecified Current file: ```cpp #include <sleef.h> #include "cpu/cpu_types.hpp" #include "cpu/utils.hpp" #include "cpu/micro_gemm/cpu_micro_gemm_vec.hpp"...
## Purpose Accelerate unquantized MoE for AArch64 - Enable FusedMoE kernel for AArch64 - Implement AdvSIMD BFMMLA interface to accelerate w13 and w2 GEMMs - Extend generic micro kernel interface and MoE kernel to support packing input matrix - Abstract sleef.h includes and tanh symbol for x86 under the AVX vectorize...
[{"scope": "e2e", "hardware": null, "model": "gpt-oss", "shape": null, "batch_size": 256, "metric": "throughput", "unit": "tok/s", "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 2.1, "speedup": 2.1}, {"scope": "e2e", "hardware": null, "model": "gemma4", "shape": null, "batch_size": 256...
null
2.22
vllm
061043eacac0473769d86a1babb9adeb8402e833
2026-06-24T15:14:35+01:00
46,353
https://github.com/vllm-project/vllm/pull/46353
[CPU][Perf] Accelerate unquantized MoE for AArch64 (#46353)
[CPU][Perf] Accelerate unquantized MoE for AArch64 (#46353) Signed-off-by: Fadi Arafeh <fadi.arafeh@arm.com>
csrc/cpu/cpu_types_arm.hpp
cpp
Apache-2.0
#include <cmath> #include <type_traits> #include <arm_neon.h> #include <torch/all.h> #include <ATen/cpu/vec/functional.h> #include <ATen/cpu/vec/vec.h> #if defined(__APPLE__) #include "omp.h" #endif using namespace at::vec; namespace vec_op { struct fp8_e4m3_tag {}; struct fp8_e5m2_tag {}; #define VLLM_DISPATC...
#include <cmath> #include <type_traits> #include <arm_neon.h> #include <torch/all.h> #include <ATen/cpu/vec/functional.h> #include <ATen/cpu/vec/vec.h> #if defined(__APPLE__) #include "omp.h" #endif using namespace at::vec; namespace vec_op { struct fp8_e4m3_tag {}; struct fp8_e5m2_tag {}; #define VLLM_DISPATC...
--- csrc/cpu/cpu_types_arm.hpp +++ csrc/cpu/cpu_types_arm.hpp @@ -497,6 +497,26 @@ reg.val[3] = Vectorized<float>(vcvt_f32_f16(vget_high_f16(v.reg.val[1]))); }; + static FORCE_INLINE void load_even_odd(const float* ptr, FP32Vec16& even, + FP32Vec16& odd) noexcept { + ...
29
0
10
[]
[ "CPU" ]
[]
Optimize this cpp kernel file from vllm (csrc/cpu/cpu_types_arm.hpp). Goal: [CPU][Perf] Accelerate unquantized MoE for AArch64 Target hardware: CPU Target models: unspecified Current file: ```cpp #include <cmath> #include <type_traits> #include <arm_neon.h> #include <torch/all.h> #include <ATen/cpu/vec/functional.h...
## Purpose Accelerate unquantized MoE for AArch64 - Enable FusedMoE kernel for AArch64 - Implement AdvSIMD BFMMLA interface to accelerate w13 and w2 GEMMs - Extend generic micro kernel interface and MoE kernel to support packing input matrix - Abstract sleef.h includes and tanh symbol for x86 under the AVX vectorize...
[{"scope": "e2e", "hardware": null, "model": "gpt-oss", "shape": null, "batch_size": 256, "metric": "throughput", "unit": "tok/s", "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 2.1, "speedup": 2.1}, {"scope": "e2e", "hardware": null, "model": "gemma4", "shape": null, "batch_size": 256...
null
2.22
vllm
061043eacac0473769d86a1babb9adeb8402e833
2026-06-24T15:14:35+01:00
46,353
https://github.com/vllm-project/vllm/pull/46353
[CPU][Perf] Accelerate unquantized MoE for AArch64 (#46353)
[CPU][Perf] Accelerate unquantized MoE for AArch64 (#46353) Signed-off-by: Fadi Arafeh <fadi.arafeh@arm.com>
csrc/cpu/cpu_types_scalar.hpp
cpp
Apache-2.0
#include <cmath> #include <cstdint> #include <cstring> #include <torch/all.h> #include "float_convert.hpp" namespace vec_op { struct fp8_e4m3_tag {}; struct fp8_e5m2_tag {}; #define VLLM_DISPATCH_CASE_FLOATING_TYPES(...) \ AT_DISPATCH_CASE(at::ScalarType::Float, __VA_ARGS__) \ AT_DISPATCH_CASE(at::...
#include <cmath> #include <cstdint> #include <cstring> #include <torch/all.h> #include "float_convert.hpp" namespace vec_op { struct fp8_e4m3_tag {}; struct fp8_e5m2_tag {}; #define VLLM_DISPATCH_CASE_FLOATING_TYPES(...) \ AT_DISPATCH_CASE(at::ScalarType::Float, __VA_ARGS__) \ AT_DISPATCH_CASE(at::...
--- csrc/cpu/cpu_types_scalar.hpp +++ csrc/cpu/cpu_types_scalar.hpp @@ -363,6 +363,13 @@ return FP32Vec16(ret); } + FP32Vec16 tanh() const { + f32x16_t ret; + unroll_loop<int, VEC_ELEM_NUM>( + [&ret, this](int i) { ret.val[i] = std::tanh(reg.val[i]); }); + return FP32Vec16(ret); + } + flo...
7
0
10
[]
[ "CPU" ]
[]
Optimize this cpp kernel file from vllm (csrc/cpu/cpu_types_scalar.hpp). Goal: [CPU][Perf] Accelerate unquantized MoE for AArch64 Target hardware: CPU Target models: unspecified Current file: ```cpp #include <cmath> #include <cstdint> #include <cstring> #include <torch/all.h> #include "float_convert.hpp" namespace v...
## Purpose Accelerate unquantized MoE for AArch64 - Enable FusedMoE kernel for AArch64 - Implement AdvSIMD BFMMLA interface to accelerate w13 and w2 GEMMs - Extend generic micro kernel interface and MoE kernel to support packing input matrix - Abstract sleef.h includes and tanh symbol for x86 under the AVX vectorize...
[{"scope": "e2e", "hardware": null, "model": "gpt-oss", "shape": null, "batch_size": 256, "metric": "throughput", "unit": "tok/s", "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 2.1, "speedup": 2.1}, {"scope": "e2e", "hardware": null, "model": "gemma4", "shape": null, "batch_size": 256...
null
2.22
vllm
061043eacac0473769d86a1babb9adeb8402e833
2026-06-24T15:14:35+01:00
46,353
https://github.com/vllm-project/vllm/pull/46353
[CPU][Perf] Accelerate unquantized MoE for AArch64 (#46353)
[CPU][Perf] Accelerate unquantized MoE for AArch64 (#46353) Signed-off-by: Fadi Arafeh <fadi.arafeh@arm.com>
csrc/cpu/cpu_types_x86.hpp
cpp
Apache-2.0
#ifndef CPU_TYPES_X86_HPP #define CPU_TYPES_X86_HPP #include <immintrin.h> #include <torch/all.h> #ifndef __AVX2__ static_assert(false, "AVX2 must be supported for the current implementation."); #endif namespace vec_op { // Tags for FP8 BF16Vec32 constructors (avoid overload collision with // BF16Vec32(void*)). //...
#ifndef CPU_TYPES_X86_HPP #define CPU_TYPES_X86_HPP #include <immintrin.h> #include <sleef.h> #include <torch/all.h> #ifndef __AVX2__ static_assert(false, "AVX2 must be supported for the current implementation."); #endif namespace vec_op { // Tags for FP8 BF16Vec32 constructors (avoid overload collision with // BF...
--- csrc/cpu/cpu_types_x86.hpp +++ csrc/cpu/cpu_types_x86.hpp @@ -3,6 +3,7 @@ #define CPU_TYPES_X86_HPP #include <immintrin.h> +#include <sleef.h> #include <torch/all.h> #ifndef __AVX2__ @@ -592,6 +593,8 @@ FP32Vec16 abs() const { return FP32Vec16(_mm512_abs_ps(reg)); } + FP32Vec16 tanh() const { return...
9
0
10
[]
[ "CPU" ]
[]
Optimize this cpp kernel file from vllm (csrc/cpu/cpu_types_x86.hpp). Goal: [CPU][Perf] Accelerate unquantized MoE for AArch64 Target hardware: CPU Target models: unspecified Current file: ```cpp #ifndef CPU_TYPES_X86_HPP #define CPU_TYPES_X86_HPP #include <immintrin.h> #include <torch/all.h> #ifndef __AVX2__ stat...
## Purpose Accelerate unquantized MoE for AArch64 - Enable FusedMoE kernel for AArch64 - Implement AdvSIMD BFMMLA interface to accelerate w13 and w2 GEMMs - Extend generic micro kernel interface and MoE kernel to support packing input matrix - Abstract sleef.h includes and tanh symbol for x86 under the AVX vectorize...
[{"scope": "e2e", "hardware": null, "model": "gpt-oss", "shape": null, "batch_size": 256, "metric": "throughput", "unit": "tok/s", "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 2.1, "speedup": 2.1}, {"scope": "e2e", "hardware": null, "model": "gemma4", "shape": null, "batch_size": 256...
null
2.22
vllm
061043eacac0473769d86a1babb9adeb8402e833
2026-06-24T15:14:35+01:00
46,353
https://github.com/vllm-project/vllm/pull/46353
[CPU][Perf] Accelerate unquantized MoE for AArch64 (#46353)
[CPU][Perf] Accelerate unquantized MoE for AArch64 (#46353) Signed-off-by: Fadi Arafeh <fadi.arafeh@arm.com>
csrc/cpu/micro_gemm/cpu_micro_gemm_amx.hpp
cpp
Apache-2.0
#ifndef CPU_MICRO_GEMM_AMX_HPP #define CPU_MICRO_GEMM_AMX_HPP #include "cpu/micro_gemm/cpu_micro_gemm_impl.hpp" namespace cpu_micro_gemm { namespace { // AMX specific constexpr static int64_t AMX_TILE_ROW_BYTES = 64; constexpr static int64_t AMX_TILE_ROW_NUM = 16; constexpr static int64_t AMX_TILE_BYTES = AMX_TILE_ROW...
#ifndef CPU_MICRO_GEMM_AMX_HPP #define CPU_MICRO_GEMM_AMX_HPP #include "cpu/micro_gemm/cpu_micro_gemm_impl.hpp" namespace cpu_micro_gemm { namespace { // AMX specific constexpr static int64_t AMX_TILE_ROW_BYTES = 64; constexpr static int64_t AMX_TILE_ROW_NUM = 16; constexpr static int64_t AMX_TILE_BYTES = AMX_TILE_ROW...
--- csrc/cpu/micro_gemm/cpu_micro_gemm_amx.hpp +++ csrc/cpu/micro_gemm/cpu_micro_gemm_amx.hpp @@ -213,6 +213,8 @@ public: static constexpr int32_t MaxMSize = 32; static constexpr int32_t NSize = 32; + static constexpr int32_t WeightOCGroupSize = 16; + static constexpr bool PackA = false; public: MicroG...
2
0
10
[]
[ "CPU" ]
[]
Optimize this cpp kernel file from vllm (csrc/cpu/micro_gemm/cpu_micro_gemm_amx.hpp). Goal: [CPU][Perf] Accelerate unquantized MoE for AArch64 Target hardware: CPU Target models: unspecified Current file: ```cpp #ifndef CPU_MICRO_GEMM_AMX_HPP #define CPU_MICRO_GEMM_AMX_HPP #include "cpu/micro_gemm/cpu_micro_gemm_impl...
## Purpose Accelerate unquantized MoE for AArch64 - Enable FusedMoE kernel for AArch64 - Implement AdvSIMD BFMMLA interface to accelerate w13 and w2 GEMMs - Extend generic micro kernel interface and MoE kernel to support packing input matrix - Abstract sleef.h includes and tanh symbol for x86 under the AVX vectorize...
[{"scope": "e2e", "hardware": null, "model": "gpt-oss", "shape": null, "batch_size": 256, "metric": "throughput", "unit": "tok/s", "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 2.1, "speedup": 2.1}, {"scope": "e2e", "hardware": null, "model": "gemma4", "shape": null, "batch_size": 256...
null
2.22
vllm
061043eacac0473769d86a1babb9adeb8402e833
2026-06-24T15:14:35+01:00
46,353
https://github.com/vllm-project/vllm/pull/46353
[CPU][Perf] Accelerate unquantized MoE for AArch64 (#46353)
[CPU][Perf] Accelerate unquantized MoE for AArch64 (#46353) Signed-off-by: Fadi Arafeh <fadi.arafeh@arm.com>
csrc/cpu/micro_gemm/cpu_micro_gemm_impl.hpp
cpp
Apache-2.0
#ifndef CPU_MICRO_GEMM_IMPL_HPP #define CPU_MICRO_GEMM_IMPL_HPP #include "cpu/utils.hpp" #include "cpu/cpu_types.hpp" namespace cpu_micro_gemm { #define DEFINE_CPU_MICRO_GEMM_PARAMS \ scalar_t *__restrict__ a_ptr, scalar_t *__restrict__ b_ptr, \ float *__res...
#ifndef CPU_MICRO_GEMM_IMPL_HPP #define CPU_MICRO_GEMM_IMPL_HPP #include "cpu/utils.hpp" #include "cpu/cpu_types.hpp" namespace cpu_micro_gemm { #define DEFINE_CPU_MICRO_GEMM_PARAMS \ scalar_t *__restrict__ a_ptr, scalar_t *__restrict__ b_ptr, \ float *__res...
--- csrc/cpu/micro_gemm/cpu_micro_gemm_impl.hpp +++ csrc/cpu/micro_gemm/cpu_micro_gemm_impl.hpp @@ -21,6 +21,9 @@ public: static constexpr int32_t MaxMSize = 16; static constexpr int32_t NSize = 16; + static constexpr int32_t WeightOCGroupSize = 16; + // callers must pack A matrix before GEMM + static conste...
3
0
10
[]
[ "CPU" ]
[]
Optimize this cpp kernel file from vllm (csrc/cpu/micro_gemm/cpu_micro_gemm_impl.hpp). Goal: [CPU][Perf] Accelerate unquantized MoE for AArch64 Target hardware: CPU Target models: unspecified Current file: ```cpp #ifndef CPU_MICRO_GEMM_IMPL_HPP #define CPU_MICRO_GEMM_IMPL_HPP #include "cpu/utils.hpp" #include "cpu/cp...
## Purpose Accelerate unquantized MoE for AArch64 - Enable FusedMoE kernel for AArch64 - Implement AdvSIMD BFMMLA interface to accelerate w13 and w2 GEMMs - Extend generic micro kernel interface and MoE kernel to support packing input matrix - Abstract sleef.h includes and tanh symbol for x86 under the AVX vectorize...
[{"scope": "e2e", "hardware": null, "model": "gpt-oss", "shape": null, "batch_size": 256, "metric": "throughput", "unit": "tok/s", "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 2.1, "speedup": 2.1}, {"scope": "e2e", "hardware": null, "model": "gemma4", "shape": null, "batch_size": 256...
null
2.22
vllm
061043eacac0473769d86a1babb9adeb8402e833
2026-06-24T15:14:35+01:00
46,353
https://github.com/vllm-project/vllm/pull/46353
[CPU][Perf] Accelerate unquantized MoE for AArch64 (#46353)
[CPU][Perf] Accelerate unquantized MoE for AArch64 (#46353) Signed-off-by: Fadi Arafeh <fadi.arafeh@arm.com>
csrc/cpu/micro_gemm/cpu_micro_gemm_vec.hpp
cpp
Apache-2.0
#ifndef CPU_MICRO_GEMM_VEC_HPP #define CPU_MICRO_GEMM_VEC_HPP #include "cpu/micro_gemm/cpu_micro_gemm_impl.hpp" namespace cpu_micro_gemm { namespace { // 8-2-16 pattern, 8 regs for A, 2 regs for B, 16 regs for C, [8, K] @ [k, 32] template <typename scalar_t> class TileGemm82 { public: FORCE_INLINE static void gemm(...
#ifndef CPU_MICRO_GEMM_VEC_HPP #define CPU_MICRO_GEMM_VEC_HPP #include "cpu/micro_gemm/cpu_micro_gemm_impl.hpp" namespace cpu_micro_gemm { namespace { // 8-2-16 pattern, 8 regs for A, 2 regs for B, 16 regs for C, [8, K] @ [k, 32] template <typename scalar_t> class TileGemm82 { public: FORCE_INLINE static void gemm(...
--- csrc/cpu/micro_gemm/cpu_micro_gemm_vec.hpp +++ csrc/cpu/micro_gemm/cpu_micro_gemm_vec.hpp @@ -104,6 +104,8 @@ public: static constexpr int32_t MaxMSize = 8; static constexpr int32_t NSize = 32; + static constexpr int32_t WeightOCGroupSize = 16; + static constexpr bool PackA = false; public: void ge...
2
0
10
[]
[ "CPU" ]
[]
Optimize this cpp kernel file from vllm (csrc/cpu/micro_gemm/cpu_micro_gemm_vec.hpp). Goal: [CPU][Perf] Accelerate unquantized MoE for AArch64 Target hardware: CPU Target models: unspecified Current file: ```cpp #ifndef CPU_MICRO_GEMM_VEC_HPP #define CPU_MICRO_GEMM_VEC_HPP #include "cpu/micro_gemm/cpu_micro_gemm_impl...
## Purpose Accelerate unquantized MoE for AArch64 - Enable FusedMoE kernel for AArch64 - Implement AdvSIMD BFMMLA interface to accelerate w13 and w2 GEMMs - Extend generic micro kernel interface and MoE kernel to support packing input matrix - Abstract sleef.h includes and tanh symbol for x86 under the AVX vectorize...
[{"scope": "e2e", "hardware": null, "model": "gpt-oss", "shape": null, "batch_size": 256, "metric": "throughput", "unit": "tok/s", "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 2.1, "speedup": 2.1}, {"scope": "e2e", "hardware": null, "model": "gemma4", "shape": null, "batch_size": 256...
null
2.22
vllm
061043eacac0473769d86a1babb9adeb8402e833
2026-06-24T15:14:35+01:00
46,353
https://github.com/vllm-project/vllm/pull/46353
[CPU][Perf] Accelerate unquantized MoE for AArch64 (#46353)
[CPU][Perf] Accelerate unquantized MoE for AArch64 (#46353) Signed-off-by: Fadi Arafeh <fadi.arafeh@arm.com>
csrc/cpu/torch_bindings.cpp
cpp
Apache-2.0
#include "cache.h" #include "ops.h" #include "core/registration.h" #include <torch/library.h> // Note: overwrite the external definition for sharing same name between // libraries use different ISAs. #define TORCH_EXTENSION_NAME _C void release_dnnl_matmul_handler(int64_t handler); int64_t create_onednn_scaled_mm_h...
#include "cache.h" #include "ops.h" #include "core/registration.h" #include <torch/library.h> // Note: overwrite the external definition for sharing same name between // libraries use different ISAs. #define TORCH_EXTENSION_NAME _C void release_dnnl_matmul_handler(int64_t handler); int64_t create_onednn_scaled_mm_h...
--- csrc/cpu/torch_bindings.cpp +++ csrc/cpu/torch_bindings.cpp @@ -538,7 +538,7 @@ #endif // fused moe -#if defined(__AVX512F__) +#if defined(__AVX512F__) || (defined(ARM_BF16_SUPPORT)) ops.def( "prepack_moe_weight(Tensor weight, Tensor(a1!) packed_weight, str isa) " "-> ()"); @@ -549,7 +549,7 @...
2
2
10
[]
[ "CPU" ]
[]
Optimize this cpp kernel file from vllm (csrc/cpu/torch_bindings.cpp). Goal: [CPU][Perf] Accelerate unquantized MoE for AArch64 Target hardware: CPU Target models: unspecified Current file: ```cpp #include "cache.h" #include "ops.h" #include "core/registration.h" #include <torch/library.h> // Note: overwrite the ex...
## Purpose Accelerate unquantized MoE for AArch64 - Enable FusedMoE kernel for AArch64 - Implement AdvSIMD BFMMLA interface to accelerate w13 and w2 GEMMs - Extend generic micro kernel interface and MoE kernel to support packing input matrix - Abstract sleef.h includes and tanh symbol for x86 under the AVX vectorize...
[{"scope": "e2e", "hardware": null, "model": "gpt-oss", "shape": null, "batch_size": 256, "metric": "throughput", "unit": "tok/s", "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 2.1, "speedup": 2.1}, {"scope": "e2e", "hardware": null, "model": "gemma4", "shape": null, "batch_size": 256...
null
2.22
vllm
061043eacac0473769d86a1babb9adeb8402e833
2026-06-24T15:14:35+01:00
46,353
https://github.com/vllm-project/vllm/pull/46353
[CPU][Perf] Accelerate unquantized MoE for AArch64 (#46353)
[CPU][Perf] Accelerate unquantized MoE for AArch64 (#46353) Signed-off-by: Fadi Arafeh <fadi.arafeh@arm.com>
csrc/cpu/utils.hpp
cpp
Apache-2.0
#ifndef UTILS_HPP #define UTILS_HPP #include <atomic> #include <unistd.h> #include <ATen/cpu/Utils.h> #include "cpu/cpu_types.hpp" namespace cpu_utils { enum class ISA { AMX, VEC, RVV }; inline ISA get_isa(const std::string& isa) { if (isa == "amx") { return ISA::AMX; } else if (isa == "vec") { return I...
#ifndef UTILS_HPP #define UTILS_HPP #include <atomic> #include <string> #include <unistd.h> #include <ATen/cpu/Utils.h> #include "cpu/cpu_types.hpp" namespace cpu_utils { enum class ISA { AMX, VEC, RVV, NEON }; inline ISA get_isa(const std::string& isa) { if (isa == "amx") { return ISA::AMX; } else if (isa ...
--- csrc/cpu/utils.hpp +++ csrc/cpu/utils.hpp @@ -2,13 +2,14 @@ #define UTILS_HPP #include <atomic> +#include <string> #include <unistd.h> #include <ATen/cpu/Utils.h> #include "cpu/cpu_types.hpp" namespace cpu_utils { -enum class ISA { AMX, VEC, RVV }; +enum class ISA { AMX, VEC, RVV, NEON }; inline ISA ...
4
1
10
[]
[ "CPU" ]
[]
Optimize this cpp kernel file from vllm (csrc/cpu/utils.hpp). Goal: [CPU][Perf] Accelerate unquantized MoE for AArch64 Target hardware: CPU Target models: unspecified Current file: ```cpp #ifndef UTILS_HPP #define UTILS_HPP #include <atomic> #include <unistd.h> #include <ATen/cpu/Utils.h> #include "cpu/cpu_types.hp...
## Purpose Accelerate unquantized MoE for AArch64 - Enable FusedMoE kernel for AArch64 - Implement AdvSIMD BFMMLA interface to accelerate w13 and w2 GEMMs - Extend generic micro kernel interface and MoE kernel to support packing input matrix - Abstract sleef.h includes and tanh symbol for x86 under the AVX vectorize...
[{"scope": "e2e", "hardware": null, "model": "gpt-oss", "shape": null, "batch_size": 256, "metric": "throughput", "unit": "tok/s", "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 2.1, "speedup": 2.1}, {"scope": "e2e", "hardware": null, "model": "gemma4", "shape": null, "batch_size": 256...
null
2.22
vllm
855cd4d787608b9bdecdc491d51fefadd3fc67dd
2026-06-24T01:11:00+02:00
43,008
https://github.com/vllm-project/vllm/pull/43008
[Perf][DSv4/DSv3.2] Add cluster-cooperative topK kernel for low-latency scenarios (#43008)
[Perf][DSv4/DSv3.2] Add cluster-cooperative topK kernel for low-latency scenarios (#43008) Signed-off-by: LopezCastroRoberto <rocastro@redhat.com>
csrc/libtorch_stable/ops.h
cpp
Apache-2.0
#pragma once #include <torch/csrc/stable/library.h> #include <torch/csrc/stable/tensor.h> #include <torch/headeronly/util/Exception.h> #include <optional> #include <string> #include <vector> #include <torch/csrc/stable/ops.h> inline torch::stable::Tensor weak_ref_tensor(torch::stable::Tensor& tensor) { // Ensure ...
#pragma once #include <torch/csrc/stable/library.h> #include <torch/csrc/stable/tensor.h> #include <torch/headeronly/util/Exception.h> #include <optional> #include <string> #include <vector> #include <torch/csrc/stable/ops.h> inline torch::stable::Tensor weak_ref_tensor(torch::stable::Tensor& tensor) { // Ensure ...
--- csrc/libtorch_stable/ops.h +++ csrc/libtorch_stable/ops.h @@ -342,6 +342,14 @@ torch::stable::Tensor& output, torch::stable::Tensor& workspace, int64_t k, int64_t max_seq_len); + +#ifdef VLLM_ENABLE_COOPERATIVE_TOPK +void cooperative_topk(const torch...
8
0
4
[ "deepseek" ]
[]
[]
Optimize this cpp kernel file from vllm (csrc/libtorch_stable/ops.h). Goal: [Perf][DSv4/DSv3.2] Add cluster-cooperative topK kernel for low-latency scenarios Target hardware: unspecified Target models: deepseek Current file: ```cpp #pragma once #include <torch/csrc/stable/library.h> #include <torch/csrc/stable/tenso...
## Summary Adds a cluster-cooperative topK kernel for low-latency cases, which uses TMA and DSMEM, meaning that SM90+ arch is required. This new kernel has been extensively tuned to cover the whole low-latency regime (i.e. bs ≤32) with a cluster-level cooperation via cluster.sync() and distributed SMEM histogram reduct...
[{"scope": "e2e", "hardware": "B300", "model": "DeepSeek-V4-Flash", "shape": null, "batch_size": 1, "metric": "TTFT", "unit": "ms", "higher_is_better": false, "baseline": 18711.25, "optimized": 17825.19, "stated_speedup": null, "speedup": 1.0497}, {"scope": "e2e", "hardware": "B300", "model": "DeepSeek-V4-Flash", "shap...
null
1.0395
vllm
855cd4d787608b9bdecdc491d51fefadd3fc67dd
2026-06-24T01:11:00+02:00
43,008
https://github.com/vllm-project/vllm/pull/43008
[Perf][DSv4/DSv3.2] Add cluster-cooperative topK kernel for low-latency scenarios (#43008)
[Perf][DSv4/DSv3.2] Add cluster-cooperative topK kernel for low-latency scenarios (#43008) Signed-off-by: LopezCastroRoberto <rocastro@redhat.com>
csrc/libtorch_stable/persistent_topk.cuh
cuda
Apache-2.0
/* * Persistent TopK Scheduler for DSA Indexer */ #ifndef PERSISTENT_TOPK_CUH_ #define PERSISTENT_TOPK_CUH_ #include <cuda.h> #include <cuda_fp16.h> #include <cuda_runtime.h> #include <cub/cub.cuh> #include <cstdint> namespace vllm { namespace persistent { // ======================================================...
/* * Persistent TopK Scheduler for DSA Indexer */ #ifndef PERSISTENT_TOPK_CUH_ #define PERSISTENT_TOPK_CUH_ #include <cuda.h> #include <cuda_fp16.h> #include <cuda_runtime.h> #include <cub/cub.cuh> #include <cstdint> #include "topk_histogram_4096.cuh" namespace vllm { namespace persistent { // ==================...
--- csrc/libtorch_stable/persistent_topk.cuh +++ csrc/libtorch_stable/persistent_topk.cuh @@ -10,6 +10,8 @@ #include <cuda_runtime.h> #include <cub/cub.cuh> #include <cstdint> + +#include "topk_histogram_4096.cuh" namespace vllm { namespace persistent { @@ -935,8 +937,16 @@ } // namespace persistent // ====...
49
18
4
[ "deepseek" ]
[]
[]
Optimize this cuda kernel file from vllm (csrc/libtorch_stable/persistent_topk.cuh). Goal: [Perf][DSv4/DSv3.2] Add cluster-cooperative topK kernel for low-latency scenarios Target hardware: unspecified Target models: deepseek Current file: ```cuda /* * Persistent TopK Scheduler for DSA Indexer */ #ifndef PERSISTEN...
## Summary Adds a cluster-cooperative topK kernel for low-latency cases, which uses TMA and DSMEM, meaning that SM90+ arch is required. This new kernel has been extensively tuned to cover the whole low-latency regime (i.e. bs ≤32) with a cluster-level cooperation via cluster.sync() and distributed SMEM histogram reduct...
[{"scope": "e2e", "hardware": "B300", "model": "DeepSeek-V4-Flash", "shape": null, "batch_size": 1, "metric": "TTFT", "unit": "ms", "higher_is_better": false, "baseline": 18711.25, "optimized": 17825.19, "stated_speedup": null, "speedup": 1.0497}, {"scope": "e2e", "hardware": "B300", "model": "DeepSeek-V4-Flash", "shap...
null
1.0395
vllm
855cd4d787608b9bdecdc491d51fefadd3fc67dd
2026-06-24T01:11:00+02:00
43,008
https://github.com/vllm-project/vllm/pull/43008
[Perf][DSv4/DSv3.2] Add cluster-cooperative topK kernel for low-latency scenarios (#43008)
[Perf][DSv4/DSv3.2] Add cluster-cooperative topK kernel for low-latency scenarios (#43008) Signed-off-by: LopezCastroRoberto <rocastro@redhat.com>
csrc/libtorch_stable/torch_bindings.cpp
cpp
Apache-2.0
#include "ops.h" #include "cuda_utils.h" #include "core/registration.h" #include <torch/csrc/stable/library.h> // Register ops with STABLE_TORCH_LIBRARY for libtorch stable ABI compatibility. // Note: We register under namespace "_C" so ops are accessible as // torch.ops._C.<op_name> for compatibility with existing c...
#include "ops.h" #include "cuda_utils.h" #include "core/registration.h" #include <torch/csrc/stable/library.h> // Register ops with STABLE_TORCH_LIBRARY for libtorch stable ABI compatibility. // Note: We register under namespace "_C" so ops are accessible as // torch.ops._C.<op_name> for compatibility with existing c...
--- csrc/libtorch_stable/torch_bindings.cpp +++ csrc/libtorch_stable/torch_bindings.cpp @@ -492,6 +492,12 @@ ops.def( "persistent_topk(Tensor logits, Tensor lengths, Tensor! output, " "Tensor workspace, int k, int max_seq_len) -> ()"); + +#ifdef VLLM_ENABLE_COOPERATIVE_TOPK + ops.def( + "cooperat...
9
0
4
[ "deepseek" ]
[]
[]
Optimize this cpp kernel file from vllm (csrc/libtorch_stable/torch_bindings.cpp). Goal: [Perf][DSv4/DSv3.2] Add cluster-cooperative topK kernel for low-latency scenarios Target hardware: unspecified Target models: deepseek Current file: ```cpp #include "ops.h" #include "cuda_utils.h" #include "core/registration.h" ...
## Summary Adds a cluster-cooperative topK kernel for low-latency cases, which uses TMA and DSMEM, meaning that SM90+ arch is required. This new kernel has been extensively tuned to cover the whole low-latency regime (i.e. bs ≤32) with a cluster-level cooperation via cluster.sync() and distributed SMEM histogram reduct...
[{"scope": "e2e", "hardware": "B300", "model": "DeepSeek-V4-Flash", "shape": null, "batch_size": 1, "metric": "TTFT", "unit": "ms", "higher_is_better": false, "baseline": 18711.25, "optimized": 17825.19, "stated_speedup": null, "speedup": 1.0497}, {"scope": "e2e", "hardware": "B300", "model": "DeepSeek-V4-Flash", "shap...
null
1.0395
vllm
20b5af55c1c9ad0d1a00dc45771997dd490c8461
2026-06-23T12:12:04+02:00
43,673
https://github.com/vllm-project/vllm/pull/43673
[ROCm][Perf] DSv3.2: fuse MLA Q concat+fp8-quant in forward_mqa (#43673)
[ROCm][Perf] DSv3.2: fuse MLA Q concat+fp8-quant in forward_mqa (#43673) Signed-off-by: Frida Andersson <fanderss@amd.com>
vllm/v1/attention/backends/mla/rocm_aiter_mla_sparse.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project from dataclasses import dataclass from typing import TYPE_CHECKING, ClassVar import numpy as np import torch from vllm import _custom_ops as ops from vllm._aiter_ops import rocm_aiter_ops from vllm.config impor...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project from dataclasses import dataclass from typing import TYPE_CHECKING, ClassVar import numpy as np import torch from vllm import _custom_ops as ops from vllm._aiter_ops import rocm_aiter_ops from vllm.config impor...
--- vllm/v1/attention/backends/mla/rocm_aiter_mla_sparse.py +++ vllm/v1/attention/backends/mla/rocm_aiter_mla_sparse.py @@ -713,11 +713,16 @@ # NOTE(lucas): for the sparse FlashMLA kernels the kernels want to use # MQA 576/512 approach for both prefill and decode - # Concatenate q if it's a t...
12
7
1
[ "deepseek" ]
[ "ROCM" ]
[]
Optimize this triton kernel file from vllm (vllm/v1/attention/backends/mla/rocm_aiter_mla_sparse.py). Goal: [ROCm][Perf] DSv3.2: fuse MLA Q concat+fp8-quant in forward_mqa Target hardware: ROCM Target models: deepseek Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright co...
On the ROCm sparse-MLA fp8-KV decode path, the query tensor was being built by two back-to-back HBM-bound kernels: `ConcatMLAQKernel<bf16, 512>` (concatenate `q_nope` + `q_pe` into bf16, ~5.2 µs) followed by `scaled_fp8_quant` (~5 µs). Both are pure copy-with-scale, no compute. This PR routes `forward_mqa` through `la...
[{"scope": "e2e", "hardware": "MI355X", "model": "DSv3.2", "shape": "TP4", "batch_size": 1000, "metric": "latency", "unit": "ms", "higher_is_better": false, "baseline": 16.607, "optimized": 15.767, "stated_speedup": null, "speedup": 1.0533}, {"scope": "e2e", "hardware": "MI355X", "model": "DSv3.2", "shape": "TP4", "bat...
null
1.0385
vllm
745bba5ea8fa17dd6ae3751daf43c3d1bd8522df
2026-06-22T00:28:52+08:00
45,935
https://github.com/vllm-project/vllm/pull/45935
[Model]Fix MiniMaxM2ForCausalLM perf regression (#45935)
[Model]Fix MiniMaxM2ForCausalLM perf regression (#45935) Signed-off-by: Jee Jee Li <jeejeelee@inferact.ai>
vllm/model_executor/layers/minimax_rms_norm/rms_norm_tp.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project from functools import partial import torch from torch import nn from vllm.distributed.communication_op import tensor_model_parallel_all_reduce from vllm.distributed.parallel_state import ( get_tensor_model_...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project from functools import partial import torch from torch import nn from vllm.distributed.communication_op import tensor_model_parallel_all_reduce from vllm.distributed.parallel_state import ( get_tensor_model_...
--- vllm/model_executor/layers/minimax_rms_norm/rms_norm_tp.py +++ vllm/model_executor/layers/minimax_rms_norm/rms_norm_tp.py @@ -14,7 +14,7 @@ ) from vllm.logger import init_logger from vllm.model_executor.custom_op import CustomOp -from vllm.platforms import current_platform +from vllm.triton_utils import HAS_TRIT...
164
21
1
[ "minimax" ]
[]
[]
Optimize this triton kernel file from vllm (vllm/model_executor/layers/minimax_rms_norm/rms_norm_tp.py). Goal: [Model]Fix MiniMaxM2ForCausalLM perf regression Target hardware: unspecified Target models: minimax Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contribu...
## Purpose The root cause is that torch.compile can't fuse these torch glue ops, which leads to the M25 perf regression. This PR fuses these torch ops manually with Triton. ## Test Plan ## Test Result - PERF benchmark(nvidia/MiniMax-M2.5-NVFP4 TP4 on GB200*4) <img width="2940" height="1586" alt="image" src="htt...
[]
null
null
vllm
0a7bacdcacc5f5c7e511f596b1f6b372da6029b6
2026-06-17T10:55:48-04:00
45,863
https://github.com/vllm-project/vllm/pull/45863
[DSv4 Perf] DSv4 flashinfer sparse index cache for metadata, 2%~4% TTFT improvement (#45863)
[DSv4 Perf] DSv4 flashinfer sparse index cache for metadata, 2%~4% TTFT improvement (#45863) Signed-off-by: yewentao256 <zhyanwentao@126.com>
vllm/v1/attention/backends/mla/sparse_swa.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project from dataclasses import dataclass from typing import ClassVar, cast import torch from vllm.config import CacheConfig, VllmConfig, get_current_vllm_config from vllm.model_executor.layers.attention_layer_base impo...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project from dataclasses import dataclass, field from typing import ClassVar, cast import torch from vllm.config import CacheConfig, VllmConfig, get_current_vllm_config from vllm.model_executor.layers.attention_layer_ba...
--- vllm/v1/attention/backends/mla/sparse_swa.py +++ vllm/v1/attention/backends/mla/sparse_swa.py @@ -1,6 +1,6 @@ # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project -from dataclasses import dataclass +from dataclasses import dataclass, field from typing import ...
4
1
1
[ "deepseek" ]
[]
[]
Optimize this triton kernel file from vllm (vllm/v1/attention/backends/mla/sparse_swa.py). Goal: [DSv4 Perf] DSv4 flashinfer sparse index cache for metadata, 2%~4% TTFT improvement Target hardware: unspecified Target models: deepseek Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightTe...
## Purpose Part of https://github.com/vllm-project/vllm/issues/45861 We rebuild the same metadata for every layer, this can be easily optimized using a small cache ## Test `vllm serve deepseek-ai/DeepSeek-V4-Pro --trust-remote-code --kv-cache-dtype fp8 --block-size 256 --enable-expert-parallel -dp 8 --com...
[]
null
null
vllm
f2beaa80c8d672dc45c3313e0c8b2cec5a9b3ee3
2026-06-16T14:50:40-04:00
45,725
https://github.com/vllm-project/vllm/pull/45725
[ROCm][Quant] mxfp8 moe/linear gfx950 tuning for MiniMax-M3 (#45725)
[ROCm][Quant] mxfp8 moe/linear gfx950 tuning for MiniMax-M3 (#45725) Signed-off-by: Hongxia Yang <hongxia.yang@amd.com>
vllm/model_executor/layers/fused_moe/experts/mxfp8_native_moe.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Native MXFP8 (1x32 block, E8M0 scale) MoE for AMD CDNA4 (gfx950) via Triton ``tl.dot_scaled`` (hardware microscaling matmul). The expert GEMMs consume the FP8 E4M3 weights and their E8M0 block scales directly ...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project """Native MXFP8 (1x32 block, E8M0 scale) MoE for AMD CDNA4 (gfx950) via Triton ``tl.dot_scaled`` (hardware microscaling matmul). The expert GEMMs consume the FP8 E4M3 weights and their E8M0 block scales directly ...
--- vllm/model_executor/layers/fused_moe/experts/mxfp8_native_moe.py +++ vllm/model_executor/layers/fused_moe/experts/mxfp8_native_moe.py @@ -140,6 +140,9 @@ a_div: int, mul_weight_by: torch.Tensor | None = None, expert_map: torch.Tensor | None = None, + block_n: int = 128, + num_warps: int = 8, + ...
30
5
1
[ "minimax" ]
[ "GFX950", "ROCM" ]
[]
Optimize this triton kernel file from vllm (vllm/model_executor/layers/fused_moe/experts/mxfp8_native_moe.py). Goal: [ROCm][Quant] mxfp8 moe/linear gfx950 tuning for MiniMax-M3 Target hardware: GFX950, ROCM Target models: minimax Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: ...
## Purpose native mxfp8 moe/linea tuning to improve perf The native MXFP8 dot_scaled MoE/linear kernels used one hardcoded tile config (block_m=64, BLOCK_N=128, num_warps=8), which under-tiles long prefills. Gate the tiles on token count (threshold 1024): - prefill (>=1024): block_m=128, BLOCK_N=256, num_warps=8,...
[{"scope": "e2e", "hardware": null, "model": "MiniMax-M3", "shape": null, "batch_size": 1, "metric": "throughput", "unit": "tok/s", "higher_is_better": true, "baseline": 58.1, "optimized": 62.9, "stated_speedup": 1.083, "speedup": 1.0826}, {"scope": "e2e", "hardware": null, "model": "MiniMax-M3", "shape": null, "batch_...
null
1.0819
vllm
e18fe932ca61fbdcf9575989c75fefa8ff8d701b
2026-06-15T15:50:21-04:00
45,061
https://github.com/vllm-project/vllm/pull/45061
[Perf] Optimize DSv4 prefill chunk planning, 4.0% E2E Throughput Improvement (#45061)
[Perf] Optimize DSv4 prefill chunk planning, 4.0% E2E Throughput Improvement (#45061) Signed-off-by: yewentao256 <zhyanwentao@126.com>
vllm/v1/attention/backends/mla/sparse_swa.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project from dataclasses import dataclass from typing import ClassVar, cast import torch from vllm.config import CacheConfig, VllmConfig, get_current_vllm_config from vllm.model_executor.layers.attention_layer_base impo...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project from dataclasses import dataclass from typing import ClassVar, cast import torch from vllm.config import CacheConfig, VllmConfig, get_current_vllm_config from vllm.model_executor.layers.attention_layer_base impo...
--- vllm/v1/attention/backends/mla/sparse_swa.py +++ vllm/v1/attention/backends/mla/sparse_swa.py @@ -9,6 +9,7 @@ from vllm.model_executor.layers.attention_layer_base import AttentionLayerBase from vllm.platforms import current_platform from vllm.triton_utils import tl, triton +from vllm.utils.math_utils import cdiv...
100
3
1
[ "deepseek" ]
[]
[]
Optimize this triton kernel file from vllm (vllm/v1/attention/backends/mla/sparse_swa.py). Goal: [Perf] Optimize DSv4 prefill chunk planning, 4.0% E2E Throughput Improvement Target hardware: unspecified Target models: deepseek Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Cop...
## Purpose Optimize DSv4 prefill chunk planning, instead of fixed 4, we can pour in as much requests as possible for one chunk For example ```bash seq_lens = [256, 320, 448, 640, 1024, 1536, 3072, 4096, 6144, 8192] query_lens = [4, 8, 8, 8, 16, 16, 32, 32, 32, 32] compress_ratio = 4 window_size ...
[]
null
null
vllm
71b961dd356a399150d25738c175c71859aa1301
2026-06-13T15:05:45-04:00
44,572
https://github.com/vllm-project/vllm/pull/44572
[Perf] SM90 cutlass fp8 mm supports odd M by swap_ab, 180~290% kernel performance improvement (#44572)
[Perf] SM90 cutlass fp8 mm supports odd M by swap_ab, 180~290% kernel performance improvement (#44572) Signed-off-by: yewentao256 <zhyanwentao@126.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
csrc/libtorch_stable/quantization/w8a8/cutlass/c3x/scaled_mm_blockwise_sm90_fp8_dispatch.cuh
cuda
Apache-2.0
#pragma once #include <torch/headeronly/util/shim_utils.h> #include "cutlass/cutlass.h" #include "cutlass/numeric_types.h" #include "cute/tensor.hpp" #include "cutlass/tensor_ref.h" #include "cutlass/gemm/dispatch_policy.hpp" #include "cutlass/gemm/collective/collective_builder.hpp" #include "cutlass/gemm/device/gem...
#pragma once #include <torch/headeronly/util/shim_utils.h> #include "cutlass/cutlass.h" #include "cutlass/numeric_types.h" #include "cute/tensor.hpp" #include "cutlass/tensor_ref.h" #include "cutlass/gemm/dispatch_policy.hpp" #include "cutlass/gemm/collective/collective_builder.hpp" #include "cutlass/gemm/device/gem...
--- csrc/libtorch_stable/quantization/w8a8/cutlass/c3x/scaled_mm_blockwise_sm90_fp8_dispatch.cuh +++ csrc/libtorch_stable/quantization/w8a8/cutlass/c3x/scaled_mm_blockwise_sm90_fp8_dispatch.cuh @@ -25,33 +25,43 @@ template <class OutType, int ScaleGranularityM, int ScaleGranularityN, int ScaleGranularityK, ...
88
40
1
[]
[ "SM90" ]
[]
Optimize this cuda kernel file from vllm (csrc/libtorch_stable/quantization/w8a8/cutlass/c3x/scaled_mm_blockwise_sm90_fp8_dispatch.cuh). Goal: [Perf] SM90 cutlass fp8 mm supports odd M by swap_ab, 180~290% kernel performance improvement Target hardware: SM90 Target models: unspecified Current file: ```cuda #pragma on...
## Purpose A follow up for https://github.com/vllm-project/vllm/pull/43706, we now directly implement in kernel level. The swap_ab logic is from SM100/SM120 currently ## Test Acc covered in unit tests Perf: ```py import time import statistics import torch from vllm import _custom_ops as ops from vllm.model_execu...
[{"scope": "kernel", "hardware": null, "model": null, "shape": "M=1,N=4096,K=7168", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 49.86, "optimized": 17.31, "stated_speedup": 2.88, "speedup": 2.8804}, {"scope": "kernel", "hardware": null, "model": null, "shape": "M=2,N=4096,...
2.8504
null
vllm
badddd254f744d26b6523b464c596f19015370f1
2026-06-12T16:57:09-04:00
45,103
https://github.com/vllm-project/vllm/pull/45103
[ROCm][DSV4][Perf] Fuse inverse-RoPE and cache bf16 wo_a in o-projection (#45103)
[ROCm][DSV4][Perf] Fuse inverse-RoPE and cache bf16 wo_a in o-projection (#45103) Signed-off-by: Fangzhou Ai <fangzhouai@gmail.com> Co-authored-by: Claude Fable 5 <noreply@anthropic.com>
vllm/v1/attention/ops/rocm_aiter_mla_sparse.py
triton
Apache-2.0
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project import functools import importlib import math from importlib.util import find_spec import torch import torch.nn.functional as F import vllm.envs as envs from vllm.compilation.breakable_cudagraph import eager_bre...
# SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project import functools import importlib import math from importlib.util import find_spec import torch import torch.nn.functional as F import vllm.envs as envs from vllm.compilation.breakable_cudagraph import eager_bre...
--- vllm/v1/attention/ops/rocm_aiter_mla_sparse.py +++ vllm/v1/attention/ops/rocm_aiter_mla_sparse.py @@ -874,54 +874,131 @@ return scale -def _apply_gptj_inv_rope_ref( - x: torch.Tensor, +@triton.jit +def _inverse_rope_gptj_kernel( + o_ptr, # [T, H, D] input + out_ptr, # [T, H, D] bf16 output + ...
131
64
1
[ "deepseek" ]
[ "ROCM" ]
[]
Optimize this triton kernel file from vllm (vllm/v1/attention/ops/rocm_aiter_mla_sparse.py). Goal: [ROCm][DSV4][Perf] Fuse inverse-RoPE and cache bf16 wo_a in o-projection Target hardware: ROCM Target models: deepseek Current file: ```python # SPDX-License-Identifier: Apache-2.0 # SPDX-FileCopyrightText: Copyright co...
## Purpose The ROCm DeepSeek V4 o-projection (rocm_inv_rope_einsum, run once per decode layer) ran the inverse GPT-J RoPE as ~10 small PyTorch kernels (clone, index_select, 2x repeat_interleave, neg, stack, cat, casts) and re-dequantized the static fp8 wo_a weight every step (fp8->fp32->*scale ->bf16), which showed up...
[{"scope": "e2e", "hardware": null, "model": "DeepSeek-V4", "shape": null, "batch_size": 4, "metric": "throughput", "unit": "tok/s", "higher_is_better": true, "baseline": 78.03, "optimized": 90.19, "stated_speedup": 1.156, "speedup": 1.1558}, {"scope": "e2e", "hardware": null, "model": "DeepSeek-V4", "shape": null, "ba...
null
1.138