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miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/acl_batch_normalization.hpp

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+/*******************************************************************************
+* Copyright 2022 Arm Ltd. and affiliates
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef CPU_AARCH64_ACL_BATCH_NORMALIZATION_HPP
+#define CPU_AARCH64_ACL_BATCH_NORMALIZATION_HPP
+
+#include "cpu/cpu_batch_normalization_pd.hpp"
+
+#include "cpu/aarch64/acl_post_ops.hpp"
+#include "cpu/aarch64/acl_utils.hpp"
+
+namespace dnnl {
+namespace impl {
+namespace cpu {
+namespace aarch64 {
+
+struct acl_batch_normalization_obj_t {
+    arm_compute::NEBatchNormalizationLayer bnorm;
+    arm_compute::Tensor src_tensor;
+    arm_compute::Tensor dst_tensor;
+    arm_compute::Tensor mean_tensor;
+    arm_compute::Tensor var_tensor;
+    arm_compute::Tensor beta_tensor; // shift
+    arm_compute::Tensor gamma_tensor; // scale
+};
+
+struct acl_batch_normalization_conf_t {
+    // src and dst
+    arm_compute::TensorInfo data_info;
+    // TensorInfo for statistics (mean and/or variance), shift and scale
+    arm_compute::TensorInfo stats_info;
+    arm_compute::ActivationLayerInfo act_info;
+};
+
+struct acl_batch_normalization_resource_t : public resource_t {
+    acl_batch_normalization_resource_t()
+        : acl_obj_(utils::make_unique<acl_batch_normalization_obj_t>()) {}
+
+    status_t configure(const acl_batch_normalization_conf_t &abp,
+            const batch_normalization_pd_t *pd) {
+        if (!acl_obj_) return status::out_of_memory;
+
+        // Init Compute Library tensors based on info from descriptor
+        acl_obj_->src_tensor.allocator()->init(abp.data_info);
+        acl_obj_->dst_tensor.allocator()->init(abp.data_info);
+
+        acl_obj_->mean_tensor.allocator()->init(abp.stats_info);
+        acl_obj_->var_tensor.allocator()->init(abp.stats_info);
+        if (pd->use_shift())
+            acl_obj_->beta_tensor.allocator()->init(abp.stats_info);
+        if (pd->use_scale())
+            acl_obj_->gamma_tensor.allocator()->init(abp.stats_info);
+
+        // clang-format off
+        acl_obj_->bnorm.configure(
+            &acl_obj_->src_tensor,
+            &acl_obj_->dst_tensor,
+            &acl_obj_->mean_tensor,
+            &acl_obj_->var_tensor,
+            pd->use_shift() ? &acl_obj_->beta_tensor : nullptr,
+            pd->use_scale() ? &acl_obj_->gamma_tensor : nullptr,
+            pd->desc()->batch_norm_epsilon,
+            abp.act_info);
+        // clang-format on
+
+        return status::success;
+    }
+
+    acl_batch_normalization_obj_t &get_acl_obj() const { return *acl_obj_; }
+
+    DNNL_DISALLOW_COPY_AND_ASSIGN(acl_batch_normalization_resource_t);
+
+private:
+    std::unique_ptr<acl_batch_normalization_obj_t> acl_obj_;
+}; // acl_batch_normalization_resource_t
+
+struct acl_batch_normalization_fwd_t : public primitive_t {
+    struct pd_t : public cpu_batch_normalization_fwd_pd_t {
+        using cpu_batch_normalization_fwd_pd_t::
+                cpu_batch_normalization_fwd_pd_t;
+
+        pd_t(const batch_normalization_desc_t *adesc,
+                const primitive_attr_t *attr,
+                const typename pd_t::base_class *hint_fwd_pd)
+            : cpu_batch_normalization_fwd_pd_t(adesc, attr, hint_fwd_pd)
+            , abp() {}
+
+        DECLARE_COMMON_PD_T("acl", acl_batch_normalization_fwd_t);
+
+        status_t init(engine_t *engine) {
+            using namespace format_tag;
+
+            // Get memory desc to find sizes and dims
+            const memory_desc_wrapper src_d(src_md_);
+            const memory_desc_wrapper stat_d(stat_md_);
+
+            using smask_t = primitive_attr_t::skip_mask_t;
+            ACL_CHECK_SUPPORT(!attr()->has_default_values(smask_t::post_ops),
+                    "attr must have default values");
+
+            ACL_CHECK_SUPPORT(!set_default_formats_common(),
+                    "Failed to set default formats");
+            ACL_CHECK_SUPPORT(src_d != memory_desc_wrapper(dst_md()),
+                    "Source and destination must have the same layout");
+
+            // Stats must already have been calculated
+            ACL_CHECK_SUPPORT(!use_global_stats(),
+                    "stats must already have been computed (use global stats)");
+
+            ACL_CHECK_SUPPORT(!is_fwd(), "must be forward mode");
+
+            ACL_CHECK_SUPPORT(!utils::one_of(src_d.data_type(), data_type::f32,
+                                      data_type::f16),
+                    "data type must be f32/f16");
+
+            // Dimensions can be permuted but no blocking or padding
+            ACL_CHECK_SUPPORT((!src_d.is_plain() || !stat_d.is_plain()),
+                    "tensors must be plain");
+            ACL_CHECK_SUPPORT((!src_d.is_dense() || !stat_d.is_dense()),
+                    "tensors must be dense");
+
+            ACL_CHECK_SUPPORT(src_d.is_zero() || src_d.has_zero_dim(),
+                    "zero sized src tensor");
+            ACL_CHECK_SUPPORT(stat_d.is_zero() || stat_d.has_zero_dim(),
+                    "zero sized stats tensor");
+
+            // mean, var, scale and shift all have a single dimension with size
+            // equal to the number of channels
+            auto acl_stats_dt = acl_utils::get_acl_data_t(stat_d.data_type());
+            abp.stats_info
+                    = arm_compute::TensorInfo(arm_compute::TensorShape(C()), 1,
+                            acl_stats_dt, arm_compute::DataLayout::NHWC);
+
+            // We can simplify into two cases: channels are dense or not dense
+            auto channel_stride = src_d.blocking_desc().strides[1];
+            if (channel_stride == 1) {
+                // Channels are dense => NHWC
+                // Collapse all dims except channels into W
+                auto elems = src_d.nelems();
+                dim_t w = elems / C();
+
+                // For small problems, it is better to disable threads with ACL
+                bool use_acl_threads = elems > 20000;
+
+                // The number of threads each candidate implementation
+                // (acl,nspc) is able to use for these problem parameters
+                int max_threads = dnnl_get_max_threads();
+                int acl_threads
+                        = use_acl_threads ? std::min((int)w, max_threads) : 1;
+                int nspc_threads = std::min((int)MB(), max_threads);
+
+                // A simple empirical heuristic which is negative when ACL is
+                // faster, positive when slower. The first term represents a
+                // constant overhead when calling ACL as an external library,
+                // the second term represents the cost per tensor elem for the
+                // two candidate implementations (scaling for the number of
+                // threads used)
+                double acl_ref_time_diff = 33
+                        + elems * (0.11 / acl_threads - 0.48 / nspc_threads);
+
+                // Threads in ACL incur an additional cost
+                if (use_acl_threads) {
+                    acl_ref_time_diff += 1500.0 + 130.0 * (acl_threads - 1);
+                }
+
+                // If ACL is slower, don't use it, fall back to nspc_bnorm
+                if (acl_ref_time_diff > 0) return status::unimplemented;
+
+                // We disable threading in ACL by moving the width into height
+                auto data_shape = use_acl_threads
+                        ? arm_compute::TensorShape(C(), w, 1, 1)
+                        : arm_compute::TensorShape(C(), 1, w, 1);
+                auto acl_data_dt = acl_utils::get_acl_data_t(src_d.data_type());
+                abp.data_info = arm_compute::TensorInfo(data_shape, 1,
+                        acl_data_dt, arm_compute::DataLayout::NHWC);
+            } else {
+                // Implemented in ACL but not yet optimal
+                return status::unimplemented;
+            }
+
+            ACL_CHECK_SUPPORT(fuse_norm_relu()
+                            && desc()->prop_kind == prop_kind::forward_training,
+                    "forward training with fused ReLU is not supported");
+
+            // oneDNN only supports eltwise post ops with bnorm
+            for (int i = 0; i < attr()->post_ops_.len(); ++i)
+                if (!attr()->post_ops_.entry_[i].is_eltwise())
+                    return status::unimplemented;
+
+            if (fuse_norm_relu()) {
+                abp.act_info = arm_compute::ActivationLayerInfo(arm_compute::
+                                ActivationLayerInfo::ActivationFunction::RELU);
+                // ACL BNorm supports fusing ReLU. If this validate fails, it
+                // will be for a different, unrecoverable reason
+                CHECK(validate(abp.act_info));
+                // init any additional post ops
+                CHECK(post_ops.init(engine, attr_.post_ops_, src_md_));
+            } else {
+                // init post ops, removing first eltwise for fusion
+                arm_compute::ActivationLayerInfo act_info;
+                CHECK(post_ops.init(
+                        engine, attr_.post_ops_, src_md_, act_info));
+                // ACL BNorm doesn't support all the same eltwise ops as the
+                // standalone ACL operator, so fall back to unfused eltwise if
+                // validate fails
+                if (validate(act_info) == status::success) {
+                    // validate succeeded => we can fuse the eltwise
+                    abp.act_info = act_info;
+                } else {
+                    // validate unfused eltwise + remaining post ops
+                    CHECK(validate());
+                    CHECK(post_ops.init(engine, attr_.post_ops_, src_md_));
+                }
+            }
+
+            return status::success;
+        }
+
+        status_t validate() { return validate(abp.act_info); }
+
+        status_t validate(arm_compute::ActivationLayerInfo &act_info) {
+            ACL_CHECK_VALID(arm_compute::NEBatchNormalizationLayer::validate(
+                    &abp.data_info, &abp.data_info, &abp.stats_info,
+                    &abp.stats_info, use_shift() ? &abp.stats_info : nullptr,
+                    use_scale() ? &abp.stats_info : nullptr,
+                    desc()->batch_norm_epsilon, act_info));
+            return status::success;
+        }
+
+        acl_batch_normalization_conf_t abp;
+
+        acl_post_ops_t post_ops;
+    }; // pd_t
+
+    acl_batch_normalization_fwd_t(const pd_t *apd) : primitive_t(apd) {}
+
+    status_t create_resource(
+            engine_t *engine, resource_mapper_t &mapper) const override {
+        if (mapper.has_resource(this)) return status::success;
+
+        auto r = utils::make_unique<acl_batch_normalization_resource_t>();
+        if (!r) return status::out_of_memory;
+
+        // Configure the resource based on information from primitive descriptor
+        CHECK(r->configure(pd()->abp, pd()));
+        mapper.add(this, std::move(r));
+
+        CHECK(pd()->post_ops.create_resource(engine, mapper));
+
+        return status::success;
+    }
+
+    status_t execute(const exec_ctx_t &ctx) const override {
+        return execute_forward(ctx);
+    }
+
+private:
+    // To guard the const execute_forward, the mutex must be 'mutable'
+    mutable std::mutex mtx;
+    status_t execute_forward(const exec_ctx_t &ctx) const;
+    const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); }
+}; // acl_batch_normalization_fwd_t
+
+} // namespace aarch64
+} // namespace cpu
+} // namespace impl
+} // namespace dnnl
+
+#endif

miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/acl_benchmark_scheduler.hpp

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+/*******************************************************************************
+* Copyright 2023 Arm Ltd. and affiliates
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+#ifndef CPU_AARCH64_ACL_BENCHMARK_SCHEDULER_HPP
+#define CPU_AARCH64_ACL_BENCHMARK_SCHEDULER_HPP
+
+#include "arm_compute/core/CPP/ICPPKernel.h"
+#include "arm_compute/runtime/IScheduler.h"
+
+namespace dnnl {
+namespace impl {
+namespace cpu {
+namespace aarch64 {
+// BenchmarkScheduler implement's ACL IScheduler interface and acts as an interceptor scheduler
+// when DNNL_VERBOSE=profile,profile_externals. It intercepts calls made by the actual scheduler used by ACL and adds
+// timers to benchmark execution time of ACL kernels and store kernel information.
+class BenchmarkScheduler final : public arm_compute::IScheduler {
+public:
+    BenchmarkScheduler(IScheduler &real_scheduler);
+
+    ~BenchmarkScheduler();
+
+    void set_num_threads(unsigned int num_threads) override;
+    unsigned int num_threads() const override;
+    void set_num_threads_with_affinity(
+            unsigned int num_threads, BindFunc func) override;
+    void schedule(arm_compute::ICPPKernel *kernel,
+            const arm_compute::IScheduler::Hints &hints) override;
+    void schedule_op(arm_compute::ICPPKernel *kernel,
+            const arm_compute::IScheduler::Hints &hints,
+            const arm_compute::Window &window,
+            arm_compute::ITensorPack &tensors) override;
+
+protected:
+    void run_workloads(std::vector<Workload> &workloads) override;
+    void run_tagged_workloads(
+            std::vector<Workload> &workloads, const char *tag) override;
+
+private:
+    IScheduler &_real_scheduler;
+};
+
+#endif // CPU_AARCH64_ACL_BENCHMARK_SCHEDULER_HPP
+
+} // namespace aarch64
+} // namespace cpu
+} // namespace impl
+} // namespace dnnl

miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/acl_binary.hpp

@@ -0,0 +1,278 @@
+/*******************************************************************************
+* Copyright 2022 Arm Ltd. and affiliates
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed tos in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef CPU_AARCH64_ACL_BINARY_HPP
+#define CPU_AARCH64_ACL_BINARY_HPP
+
+#include "cpu/cpu_binary_pd.hpp"
+
+#include "cpu/aarch64/acl_utils.hpp"
+
+namespace dnnl {
+namespace impl {
+namespace cpu {
+namespace aarch64 {
+
+struct acl_binary_obj_t {
+    std::unique_ptr<arm_compute::IFunction> binary_op;
+    arm_compute::Tensor src0_tensor;
+    arm_compute::Tensor src1_tensor;
+    arm_compute::Tensor dst_tensor;
+};
+
+struct acl_binary_conf_t {
+    arm_compute::TensorInfo src0_info;
+    arm_compute::TensorInfo src1_info;
+    arm_compute::TensorInfo dst_info;
+    alg_kind_t alg;
+};
+
+struct acl_binary_resource_t : public resource_t {
+    acl_binary_resource_t()
+        : acl_obj_(utils::make_unique<acl_binary_obj_t>()) {}
+
+    status_t configure(const acl_binary_conf_t &asp) {
+        if (!acl_obj_) return status::out_of_memory;
+
+        // Init Compute Library tensors based on info from descriptor
+        acl_obj_->src0_tensor.allocator()->init(asp.src0_info);
+        acl_obj_->src1_tensor.allocator()->init(asp.src1_info);
+        acl_obj_->dst_tensor.allocator()->init(asp.dst_info);
+
+        switch (asp.alg) {
+            case alg_kind::binary_add: {
+                auto add_op
+                        = std::make_unique<arm_compute::NEArithmeticAddition>();
+                add_op->configure(&acl_obj_->src0_tensor,
+                        &acl_obj_->src1_tensor, &acl_obj_->dst_tensor,
+                        arm_compute::ConvertPolicy::SATURATE);
+                acl_obj_->binary_op = std::move(add_op);
+                break;
+            }
+            case alg_kind::binary_sub: {
+                auto sub_op = std::make_unique<
+                        arm_compute::NEArithmeticSubtraction>();
+                sub_op->configure(&acl_obj_->src0_tensor,
+                        &acl_obj_->src1_tensor, &acl_obj_->dst_tensor,
+                        arm_compute::ConvertPolicy::SATURATE);
+                acl_obj_->binary_op = std::move(sub_op);
+                break;
+            }
+            case alg_kind::binary_div: {
+                auto div_op = std::make_unique<
+                        arm_compute::NEElementwiseDivision>();
+                div_op->configure(&acl_obj_->src0_tensor,
+                        &acl_obj_->src1_tensor, &acl_obj_->dst_tensor);
+                acl_obj_->binary_op = std::move(div_op);
+                break;
+            }
+            case alg_kind::binary_mul: {
+                auto mul_op = std::make_unique<
+                        arm_compute::NEPixelWiseMultiplication>();
+                mul_op->configure(&acl_obj_->src0_tensor,
+                        &acl_obj_->src1_tensor, &acl_obj_->dst_tensor, 1.0f,
+                        arm_compute::ConvertPolicy::SATURATE,
+                        arm_compute::RoundingPolicy::TO_ZERO);
+                acl_obj_->binary_op = std::move(mul_op);
+                break;
+            }
+            case alg_kind::binary_min: {
+                auto min_op = std::make_unique<arm_compute::NEElementwiseMin>();
+                min_op->configure(&acl_obj_->src0_tensor,
+                        &acl_obj_->src1_tensor, &acl_obj_->dst_tensor);
+                acl_obj_->binary_op = std::move(min_op);
+                break;
+            }
+            case alg_kind::binary_max: {
+                auto max_op = std::make_unique<arm_compute::NEElementwiseMax>();
+                max_op->configure(&acl_obj_->src0_tensor,
+                        &acl_obj_->src1_tensor, &acl_obj_->dst_tensor);
+                acl_obj_->binary_op = std::move(max_op);
+                break;
+            }
+            default: return status::runtime_error;
+        }
+
+        return status::success;
+    }
+
+    acl_binary_obj_t &get_acl_obj() const { return *acl_obj_; }
+
+    DNNL_DISALLOW_COPY_AND_ASSIGN(acl_binary_resource_t);
+
+private:
+    std::unique_ptr<acl_binary_obj_t> acl_obj_;
+}; // acl_binary_resource_t
+
+struct acl_binary_t : public primitive_t {
+    struct pd_t : public cpu_binary_pd_t {
+        using cpu_binary_pd_t::cpu_binary_pd_t;
+
+        DECLARE_COMMON_PD_T("acl", acl_binary_t);
+
+        status_t init(engine_t *engine) {
+
+            using namespace acl_utils;
+
+            // Only support f16/f32/s32 for now
+            data_type_t ddt = dst_md(0)->data_type;
+            if (!utils::one_of(
+                        ddt, data_type::f16, data_type::f32, data_type::s32))
+                return status::unimplemented;
+
+            // Only support src and dst all matching for now
+            if (ddt != src_md(0)->data_type || src_md(1)->data_type != ddt)
+                return status::unimplemented;
+
+            // Sets the memory format of dst from any to src_md(0) blocking desc
+            CHECK(set_default_params());
+
+            if (!attr()->has_default_values()) return status::unimplemented;
+
+            asp_.alg = desc()->alg_kind;
+
+            // All the algorithms we support
+            if (!utils::one_of(asp_.alg, alg_kind::binary_add,
+                        alg_kind::binary_sub, alg_kind::binary_mul,
+                        alg_kind::binary_div, alg_kind::binary_max,
+                        alg_kind::binary_min))
+                return status::unimplemented;
+
+            // s32 div in ACL does not round as oneDNN expects
+            if (ddt == data_type::s32 && asp_.alg == alg_kind::binary_div)
+                return status::unimplemented;
+
+            // ACL pointwise arithmetic operators assume that the innermost
+            // dimensions are dense for src0, src1 and dst. Reordering the
+            // logical dimensions by stride does this (if reordered_dims >= 1 )
+            // and also makes memory accesses contiguous in ACL (without any
+            // data reordering).
+            memory_desc_t src_d0_permed, src_d1_permed, dst_d_permed;
+            int reordered_dims = reorder_dimensions_by_stride(
+                    {&src_d0_permed, &src_d1_permed, &dst_d_permed},
+                    {src_md(0), src_md(1), dst_md()});
+            if (reordered_dims < 1) return status::unimplemented;
+
+            // Create ACL tensor infos with permuted descs
+            CHECK(tensor_info(asp_.src0_info, src_d0_permed));
+            CHECK(tensor_info(asp_.src1_info, src_d1_permed));
+            CHECK(tensor_info(asp_.dst_info, dst_d_permed));
+
+            // In this case ACL tries to treat src0 and src1 as a 1D array, but
+            // fails because the strides aren't equal. TODO: remove when fixed
+            // in ACL
+            if (asp_.alg == alg_kind::binary_add
+                    && asp_.src0_info.tensor_shape()
+                            == asp_.src1_info.tensor_shape()
+                    && asp_.src0_info.strides_in_bytes()
+                            != asp_.src1_info.strides_in_bytes()) {
+                return status::unimplemented;
+            }
+
+            // This forces ACL not to parallelise with small workloads, this is
+            // a temporary fix and should be removed in future versions (TODO)
+            memory_desc_wrapper dst_d(dst_md());
+            if (dst_d.nelems() < 40000) {
+                size_t acl_y_axis_i = 1;
+                CHECK(insert_singleton_dimension(asp_.src0_info, acl_y_axis_i));
+                CHECK(insert_singleton_dimension(asp_.src1_info, acl_y_axis_i));
+                CHECK(insert_singleton_dimension(asp_.dst_info, acl_y_axis_i));
+            }
+
+            // Call operator specific validate function to check support
+            ACL_CHECK_VALID(validate(asp_));
+
+            return status::success;
+        }
+
+        acl_binary_conf_t asp_;
+
+    private:
+        arm_compute::Status validate(const acl_binary_conf_t &asp) {
+            switch (asp.alg) {
+                case alg_kind::binary_add:
+                    return arm_compute::NEArithmeticAddition::validate(
+                            &asp.src0_info, &asp.src1_info, &asp.dst_info,
+                            arm_compute::ConvertPolicy::SATURATE);
+                case alg_kind::binary_sub:
+                    return arm_compute::NEArithmeticSubtraction::validate(
+                            &asp.src0_info, &asp.src1_info, &asp.dst_info,
+                            arm_compute::ConvertPolicy::SATURATE);
+                case alg_kind::binary_div:
+                    return arm_compute::NEElementwiseDivision::validate(
+                            &asp.src0_info, &asp.src1_info, &asp.dst_info);
+                case alg_kind::binary_mul:
+                    return arm_compute::NEPixelWiseMultiplication::validate(
+                            &asp.src0_info, &asp.src1_info, &asp.dst_info, 1.0f,
+                            arm_compute::ConvertPolicy::SATURATE,
+                            arm_compute::RoundingPolicy::TO_ZERO);
+                case alg_kind::binary_min:
+                    return arm_compute::NEElementwiseMin::validate(
+                            &asp.src0_info, &asp.src1_info, &asp.dst_info);
+                case alg_kind::binary_max:
+                    return arm_compute::NEElementwiseMax::validate(
+                            &asp.src0_info, &asp.src1_info, &asp.dst_info);
+                default:
+                    return arm_compute::Status(
+                            arm_compute::ErrorCode::RUNTIME_ERROR,
+                            "unsupported alg_kind");
+            }
+        }
+
+        friend struct acl_post_ops_t;
+    }; // pd_t
+
+    acl_binary_t(const pd_t *apd) : primitive_t(apd) {}
+
+    status_t create_resource(
+            engine_t *engine, resource_mapper_t &mapper) const override {
+        if (mapper.has_resource(this)) return status::success;
+
+        auto r = utils::make_unique<acl_binary_resource_t>();
+        if (!r) return status::out_of_memory;
+
+        // Configure the resource based on information from primitive descriptor
+        auto st = r->configure(pd()->asp_);
+        if (st == status::success) { mapper.add(this, std::move(r)); }
+
+        return st;
+    }
+
+    status_t execute(const exec_ctx_t &ctx) const override {
+        return execute_forward(ctx);
+    }
+
+private:
+    // To guard the const execute_forward, the mutex must be 'mutable'
+    mutable std::mutex mtx;
+
+    status_t execute_forward(const exec_ctx_t &ctx) const;
+    // Execute forward with arbitrary src0, src1 and dst, used by acl_post_ops_t
+    status_t execute_forward(const exec_ctx_t &ctx, const void *src0,
+            const void *src1, void *dst) const;
+
+    const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); }
+
+    friend struct acl_post_ops_t;
+
+}; // acl_binary_t
+
+} // namespace aarch64
+} // namespace cpu
+} // namespace impl
+} // namespace dnnl
+
+#endif

miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/acl_convolution_utils.hpp

@@ -0,0 +1,128 @@
+/*******************************************************************************
+* Copyright 2020-2023 Arm Ltd. and affiliates
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef CPU_AARCH64_ACL_CONVOLUTION_UTILS_HPP
+#define CPU_AARCH64_ACL_CONVOLUTION_UTILS_HPP
+
+#include "cpu/cpu_convolution_pd.hpp"
+
+#include "cpu/aarch64/acl_post_ops.hpp"
+#include "cpu/aarch64/acl_utils.hpp"
+
+namespace dnnl {
+namespace impl {
+namespace cpu {
+namespace aarch64 {
+
+template <typename NEConv>
+struct acl_obj_t {
+    NEConv conv;
+    arm_compute::Tensor src_tensor;
+    arm_compute::Tensor wei_tensor;
+    arm_compute::Tensor bia_tensor;
+    arm_compute::Tensor dst_tensor;
+};
+
+struct acl_conv_conf_t {
+    bool with_bias;
+    bool fast_math;
+    // If this is true, the result of the convolution goes into a temporarily
+    // allocated ACL tensor to be accumulated into the oneDNN dst during postops
+    bool use_dst_acc;
+    arm_compute::TensorInfo src_tensor_info;
+    arm_compute::TensorInfo wei_tensor_info;
+    arm_compute::TensorInfo bia_tensor_info;
+    arm_compute::TensorInfo dst_tensor_info;
+    arm_compute::PadStrideInfo padstride_info;
+    arm_compute::Size2D dilation_info;
+    // Additional information about the weights not included in wei_tensor_info
+    arm_compute::WeightsInfo weights_info;
+    // Note: this will default to not enabled, and will do nothing
+    arm_compute::ActivationLayerInfo act_info;
+};
+
+namespace acl_convolution_utils {
+
+status_t init_conf_gemm(acl_conv_conf_t &acp, memory_desc_t &src_md,
+        memory_desc_t &weights_md, memory_desc_t &dst_md,
+        memory_desc_t &bias_md, const convolution_desc_t &cd,
+        const primitive_attr_t &attr);
+
+status_t init_conf_indirect_gemm(acl_conv_conf_t &acp, memory_desc_t &src_md,
+        memory_desc_t &weights_md, memory_desc_t &dst_md,
+        memory_desc_t &bias_md, const convolution_desc_t &cd,
+        const primitive_attr_t &attr);
+
+status_t init_conf_depthwise(acl_conv_conf_t &acp, memory_desc_t &src_md,
+        memory_desc_t &weights_md, memory_desc_t &dst_md,
+        memory_desc_t &bias_md, const convolution_desc_t &cd,
+        const primitive_attr_t &attr);
+
+} // namespace acl_convolution_utils
+
+template <typename conv_obj_t, typename conv_pd_t, typename src_data_t,
+        typename wei_data_t = src_data_t, typename dst_data_t = src_data_t,
+        typename bia_data_t = src_data_t>
+status_t execute_forward_conv_acl(
+        const exec_ctx_t &ctx, conv_obj_t &acl_conv_obj, const conv_pd_t *pd) {
+    bool with_bias = pd->acp_.with_bias;
+    bool use_dst_acc = pd->acp_.use_dst_acc;
+
+    auto src_base = CTX_IN_MEM(const src_data_t *, DNNL_ARG_SRC);
+    auto wei_base = CTX_IN_MEM(const wei_data_t *, DNNL_ARG_WEIGHTS);
+
+    // import_memory() and free() methods do not allocate/free any additional
+    // memory, only acquire/release pointers.
+    acl_conv_obj.src_tensor.allocator()->import_memory(
+            const_cast<src_data_t *>(src_base));
+    acl_conv_obj.wei_tensor.allocator()->import_memory(
+            const_cast<wei_data_t *>(wei_base));
+
+    if (use_dst_acc) {
+        // Put the result in a new tensor, it will be accumalated to the dst
+        // during the post ops
+        acl_conv_obj.dst_tensor.allocator()->allocate();
+    } else {
+        auto dst_base = CTX_OUT_MEM(dst_data_t *, DNNL_ARG_DST);
+        acl_conv_obj.dst_tensor.allocator()->import_memory(dst_base);
+    }
+
+    if (with_bias) {
+        auto bia_base = CTX_IN_MEM(const bia_data_t *, DNNL_ARG_BIAS);
+        acl_conv_obj.bia_tensor.allocator()->import_memory(
+                const_cast<bia_data_t *>(bia_base));
+    }
+
+    acl_conv_obj.conv.run();
+
+    acl_conv_obj.src_tensor.allocator()->free();
+    acl_conv_obj.wei_tensor.allocator()->free();
+    if (with_bias) { acl_conv_obj.bia_tensor.allocator()->free(); }
+
+    void *dst = acl_conv_obj.dst_tensor.buffer();
+    pd->post_ops.execute(ctx, dst);
+
+    acl_conv_obj.dst_tensor.allocator()->free();
+
+    return status::success;
+}
+
+} // namespace aarch64
+} // namespace cpu
+} // namespace impl
+} // namespace dnnl
+
+#endif // CPU_AARCH64_ACL_CONVOLUTION_UTILS_HPP

miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/acl_deconvolution.hpp

@@ -0,0 +1,335 @@
+/*******************************************************************************
+* Copyright 2022-2023 Arm Ltd. and affiliates
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef CPU_AARCH64_ACL_DECONVOLUTION_HPP
+#define CPU_AARCH64_ACL_DECONVOLUTION_HPP
+
+#include "cpu/aarch64/acl_post_ops.hpp"
+#include "cpu/cpu_deconvolution_pd.hpp"
+
+namespace dnnl {
+namespace impl {
+namespace cpu {
+namespace aarch64 {
+
+struct acl_deconv_obj_t {
+    arm_compute::NEDeconvolutionLayer deconv;
+    arm_compute::Tensor src_tensor;
+    arm_compute::Tensor wei_tensor;
+    arm_compute::Tensor bia_tensor;
+    arm_compute::Tensor dst_tensor;
+};
+
+struct acl_deconv_conf_t {
+    bool with_bias;
+    // If this is true, the result of the convolution goes into a temporarily
+    // allocated ACL tensor to be accumulated into the oneDNN dst during postops
+    bool use_dst_acc;
+    bool fast_math;
+    arm_compute::TensorInfo src_info;
+    arm_compute::TensorInfo wei_info;
+    arm_compute::TensorInfo bia_info;
+    arm_compute::TensorInfo dst_info;
+    arm_compute::PadStrideInfo deconv_info;
+};
+
+struct acl_deconv_resource_t : public resource_t {
+    acl_deconv_resource_t()
+        : acl_obj_(utils::make_unique<acl_deconv_obj_t>()) {}
+
+    status_t configure(const acl_deconv_conf_t &adp) {
+        if (!acl_obj_) return status::out_of_memory;
+
+        // Init Compute Library tensors based on info from descriptor
+        acl_obj_->src_tensor.allocator()->init(adp.src_info);
+        acl_obj_->wei_tensor.allocator()->init(adp.wei_info);
+        acl_obj_->bia_tensor.allocator()->init(adp.bia_info);
+        acl_obj_->dst_tensor.allocator()->init(adp.dst_info);
+
+        // clang-format off
+        acl_obj_->deconv.configure(
+            &acl_obj_->src_tensor,
+            &acl_obj_->wei_tensor,
+            adp.with_bias ? &acl_obj_->bia_tensor : nullptr,
+            &acl_obj_->dst_tensor,
+            adp.deconv_info, adp.fast_math);
+        // clang-format on
+
+        return status::success;
+    }
+
+    acl_deconv_obj_t &get_acl_obj() const { return *acl_obj_; }
+
+    DNNL_DISALLOW_COPY_AND_ASSIGN(acl_deconv_resource_t);
+
+private:
+    std::unique_ptr<acl_deconv_obj_t> acl_obj_;
+}; // acl_deconv_resource_t
+
+struct acl_deconvolution_fwd_t : public primitive_t {
+    struct pd_t : public cpu_deconvolution_fwd_pd_t {
+        using cpu_deconvolution_fwd_pd_t::cpu_deconvolution_fwd_pd_t;
+        pd_t(const deconvolution_desc_t *adesc, const primitive_attr_t *attr,
+                const deconvolution_fwd_pd_t *hint_fwd_pd)
+            : cpu_deconvolution_fwd_pd_t(adesc, attr, hint_fwd_pd)
+            , acl_pd_conf()
+            , post_ops() {}
+
+        DECLARE_COMMON_PD_T("acl", acl_deconvolution_fwd_t);
+
+        status_t init(engine_t *engine) {
+            using namespace data_type;
+            using namespace format_tag;
+
+            const memory_desc_wrapper src_d(&src_md_);
+            const memory_desc_wrapper wei_d(&weights_md_);
+            const memory_desc_wrapper dst_d(&dst_md_);
+            const memory_desc_wrapper bia_d(&bias_md_);
+
+            const auto src_data_t = src_d.data_type();
+            const auto wei_data_t = wei_d.data_type();
+            const auto dst_data_t = dst_d.data_type();
+            const auto bia_data_t = bia_d.data_type();
+
+            const bool ok = is_fwd() // Only forward deconvolutions
+                    && utils::one_of(
+                            desc()->alg_kind, alg_kind::deconvolution_direct)
+                    && attr()->has_default_values(
+                            primitive_attr_t::skip_mask_t::post_ops,
+                            dst_data_t);
+            if (!ok) return status::unimplemented;
+
+            // Strides
+            const auto sh = KSH();
+            const auto sw = KSW();
+
+            // Padding
+            const auto pt = padT();
+            const auto pb = padB();
+            const auto pl = padL();
+            const auto pr = padR();
+
+            acl_pd_conf.deconv_info = arm_compute::PadStrideInfo(sw, sh, pl, pr,
+                    pt, pb, arm_compute::DimensionRoundingType::FLOOR);
+
+            // Tensor info
+            const auto mb = MB();
+
+            const auto ih = IH();
+            const auto iw = IW();
+            const auto ic = IC();
+
+            const auto oh = OH();
+            const auto ow = OW();
+            const auto oc = OC();
+
+            const auto kw = KW();
+            const auto kh = KH();
+
+            const bool with_groups = G() != 1;
+            const int ndims = src_d.ndims();
+            const bool is_1d = ndims == 3;
+            const bool is_3d = ndims == 5;
+
+            // Compute Library unsupported shape scenarios
+            if (utils::one_of(true, is_3d, is_1d, with_groups)) {
+                return status::unimplemented;
+            }
+
+            acl_pd_conf.with_bias
+                    = desc_.bias_desc.format_kind != format_kind::undef;
+
+            // Data type
+
+            auto acl_src_data_t = acl_utils::get_acl_data_t(src_data_t);
+            auto acl_wei_data_t = acl_utils::get_acl_data_t(wei_data_t);
+            auto acl_dst_data_t = acl_utils::get_acl_data_t(dst_data_t);
+            auto acl_bia_data_t = acl_utils::get_acl_data_t(bia_data_t);
+
+            if (acl_bia_data_t == arm_compute::DataType::UNKNOWN) {
+                acl_bia_data_t = arm_compute::DataType::F32;
+            }
+
+            // Set memory formats
+            auto src_tag = src_d.format_kind() == format_kind::any
+                    ? nhwc
+                    : memory_desc_matches_one_of_tag(src_md_, nhwc, nchw);
+            auto dst_tag = dst_d.format_kind() == format_kind::any
+                    ? nhwc
+                    : memory_desc_matches_one_of_tag(dst_md_, nhwc, nchw);
+
+            bool is_nspc = src_tag == nhwc;
+
+            auto wei_tag = wei_d.format_kind() == format_kind::any
+                    ? (is_nspc ? ohwi : oihw)
+                    : memory_desc_matches_one_of_tag(weights_md_, ohwi, oihw);
+
+            // Compute Library does not support mismatching layouts
+            if ((src_tag != wei_tag) || (src_tag != dst_tag)) {
+                return status::unimplemented;
+            }
+
+            CHECK(memory_desc_init_by_tag(src_md_, src_tag));
+            CHECK(memory_desc_init_by_tag(dst_md_, dst_tag));
+            CHECK(memory_desc_init_by_tag(weights_md_, wei_tag));
+            if (acl_pd_conf.with_bias) {
+                CHECK(memory_desc_init_by_tag(bias_md_, format_tag::a));
+            }
+
+            // Data layout
+            const auto acl_layout = is_nspc ? arm_compute::DataLayout::NHWC
+                                            : arm_compute::DataLayout::NCHW;
+
+            acl_pd_conf.src_info = arm_compute::TensorInfo(is_nspc
+                            ? arm_compute::TensorShape(ic, iw, ih, mb)
+                            : arm_compute::TensorShape(iw, ih, ic, mb),
+                    1, acl_src_data_t, acl_layout);
+
+            acl_pd_conf.wei_info = arm_compute::TensorInfo(is_nspc
+                            ? arm_compute::TensorShape(ic, kw, kh, oc)
+                            : arm_compute::TensorShape(kw, kh, ic, oc),
+                    1, acl_wei_data_t, acl_layout);
+
+            acl_pd_conf.dst_info = arm_compute::TensorInfo(is_nspc
+                            ? arm_compute::TensorShape(oc, ow, oh, mb)
+                            : arm_compute::TensorShape(ow, oh, oc, mb),
+                    1, acl_dst_data_t, acl_layout);
+
+            acl_pd_conf.bia_info = arm_compute::TensorInfo(acl_pd_conf.with_bias
+                            ? arm_compute::TensorShape(oc)
+                            : arm_compute::TensorShape(),
+                    1, acl_bia_data_t, acl_layout);
+
+            acl_pd_conf.fast_math = utils::one_of(
+                    attr()->fpmath_mode_, fpmath_mode::bf16, fpmath_mode::any);
+
+            ACL_CHECK_VALID(arm_compute::NEDeconvolutionLayer::validate(
+                    &acl_pd_conf.src_info, &acl_pd_conf.wei_info,
+                    acl_pd_conf.with_bias ? &acl_pd_conf.bia_info : nullptr,
+                    &acl_pd_conf.dst_info, acl_pd_conf.deconv_info,
+                    acl_pd_conf.fast_math));
+
+            // Calculate scaled output tensor info for determining the convolution method
+            auto out_dims = arm_compute::deconvolution_output_dimensions(
+                    iw, ih, kw, kh, acl_pd_conf.deconv_info);
+            uint32_t deconv_pad_x = 0;
+            uint32_t deconv_pad_y = 0;
+            auto scale_out_shape = arm_compute::misc::shape_calculator::
+                    compute_deconvolution_upsampled_shape(acl_pd_conf.src_info,
+                            acl_pd_conf.wei_info, sw, sh, out_dims,
+                            deconv_pad_x, deconv_pad_y);
+
+            // If strides are unit in all dimensions, upsampling of input is skipped and a correct
+            // padding is set for convolution. Otherwise, describe deconvolution as convolution of
+            // upsampling input with stride = 1 and pad = 0.
+            arm_compute::ConvolutionMethod conv_method;
+            arm_compute::TensorInfo *conv_src_info;
+            unsigned int pad_left = 0;
+            unsigned int pad_right = 0;
+            unsigned int pad_top = 0;
+            unsigned int pad_bottom = 0;
+            if (sh != 1 || sw != 1) {
+                arm_compute::TensorInfo scale_out_info(
+                        acl_pd_conf.src_info.clone()
+                                ->set_is_resizable(true)
+                                .reset_padding()
+                                .set_tensor_shape(scale_out_shape));
+                conv_src_info = &scale_out_info;
+            } else {
+                // compute correct padding here
+                pad_left = pr > pl ? pr - pl : 0;
+                pad_right = pl > pr ? pl - pr : 0;
+                pad_top = pb > pt ? pb - pt : 0;
+                pad_bottom = pt > pb ? pt - pb : 0;
+
+                deconv_pad_x -= pad_left + pad_right;
+                deconv_pad_y -= pad_top + pad_bottom;
+
+                pad_left += deconv_pad_x / 2;
+                pad_right += deconv_pad_x / 2;
+                pad_top += deconv_pad_y / 2;
+                pad_bottom += deconv_pad_y / 2;
+
+                conv_src_info = &acl_pd_conf.src_info;
+            }
+            const arm_compute::PadStrideInfo conv_info(1, 1, pad_left,
+                    pad_right, pad_top, pad_bottom,
+                    arm_compute::DimensionRoundingType::CEIL);
+            conv_method
+                    = arm_compute::NEConvolutionLayer::get_convolution_method(
+                            conv_src_info, &acl_pd_conf.wei_info,
+                            &acl_pd_conf.dst_info, conv_info,
+                            arm_compute::WeightsInfo(),
+                            arm_compute::Size2D(1U, 1U),
+                            arm_compute::ActivationLayerInfo(),
+                            acl_pd_conf.fast_math);
+
+            // Disable use of winograd based convolution algorithm when performing
+            // direct deconvolution because it introduces accuracy loss.
+            if (conv_method == arm_compute::ConvolutionMethod::WINOGRAD) {
+                return status::unimplemented;
+            }
+
+            CHECK(post_ops.init(engine, attr_.post_ops_, dst_md_));
+            acl_pd_conf.use_dst_acc = post_ops.has_sum();
+
+            return status::success;
+        }
+
+        acl_deconv_conf_t acl_pd_conf;
+        acl_post_ops_t post_ops;
+
+    private:
+        bool post_ops_ok() const {
+            return attr()->post_ops_.find(primitive_kind::convolution) == -1;
+        }
+    }; // pd_t
+
+    acl_deconvolution_fwd_t(const pd_t *apd) : primitive_t(apd) {}
+
+    status_t execute(const exec_ctx_t &ctx) const override {
+        return execute_forward(ctx);
+    }
+
+    status_t create_resource(
+            engine_t *engine, resource_mapper_t &mapper) const override {
+        if (mapper.has_resource(this)) return status::success;
+
+        auto r = utils::make_unique<acl_deconv_resource_t>();
+        if (!r) return status::out_of_memory;
+
+        // Configure the resource based on information from primitive descriptor
+        auto st = r->configure(pd()->acl_pd_conf);
+        if (st == status::success) { mapper.add(this, std::move(r)); }
+
+        CHECK(pd()->post_ops.create_resource(engine, mapper));
+
+        return st;
+    }
+
+private:
+    // To guard the const execute_forward, the mutex must be 'mutable'
+    mutable std::mutex mtx;
+    status_t execute_forward(const exec_ctx_t &ctx) const;
+    const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); }
+}; // acl_deconvolution_fwd_t
+
+} // namespace aarch64
+} // namespace cpu
+} // namespace impl
+} // namespace dnnl
+
+#endif

miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/acl_depthwise_convolution.hpp

@@ -0,0 +1,141 @@
+/*******************************************************************************
+* Copyright 2023 Arm Ltd. and affiliates
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef CPU_AARCH64_ACL_DEPTHWISE_CONVOLUTION_HPP
+#define CPU_AARCH64_ACL_DEPTHWISE_CONVOLUTION_HPP
+
+#include "cpu/aarch64/acl_convolution_utils.hpp"
+#include "cpu/cpu_convolution_pd.hpp"
+
+namespace dnnl {
+namespace impl {
+namespace cpu {
+namespace aarch64 {
+
+struct acl_depthwise_convolution_resource_t : public resource_t {
+    acl_depthwise_convolution_resource_t()
+        : acl_obj_(utils::make_unique<
+                acl_obj_t<arm_compute::NEDepthwiseConvolutionLayer>>()) {}
+
+    status_t configure(const acl_conv_conf_t &acp) {
+        if (!acl_obj_) return status::out_of_memory;
+
+        acl_obj_->src_tensor.allocator()->init(acp.src_tensor_info);
+        acl_obj_->wei_tensor.allocator()->init(acp.wei_tensor_info);
+        acl_obj_->dst_tensor.allocator()->init(acp.dst_tensor_info);
+        acl_obj_->bia_tensor.allocator()->init(acp.bia_tensor_info);
+
+        // clang-format off
+        acl_obj_->conv.configure(
+            &acl_obj_->src_tensor,
+            &acl_obj_->wei_tensor,
+            acp.with_bias ? &acl_obj_->bia_tensor : nullptr,
+            &acl_obj_->dst_tensor,
+            acp.padstride_info,
+            1, // depth multiplier default value
+            acp.act_info);
+
+        // clang-format on
+        return status::success;
+    }
+
+    acl_obj_t<arm_compute::NEDepthwiseConvolutionLayer> &get_acl_obj() const {
+        return *acl_obj_;
+    }
+
+    DNNL_DISALLOW_COPY_AND_ASSIGN(acl_depthwise_convolution_resource_t);
+
+private:
+    std::unique_ptr<acl_obj_t<arm_compute::NEDepthwiseConvolutionLayer>>
+            acl_obj_;
+};
+
+struct acl_depthwise_convolution_fwd_t : public primitive_t {
+
+    struct pd_t : public cpu_convolution_fwd_pd_t {
+        pd_t(const convolution_desc_t *adesc, const primitive_attr_t *attr,
+                const typename pd_t::base_class *hint_fwd_pd)
+            : cpu_convolution_fwd_pd_t(adesc, attr, hint_fwd_pd), acp_() {}
+
+        DECLARE_COMMON_PD_T("depthwise_convolution:acl",
+                acl_depthwise_convolution_fwd_t, USE_GLOBAL_SCRATCHPAD);
+
+        status_t init(engine_t *engine) {
+            using namespace data_type;
+
+            const bool is_fp16_ok = expect_data_types(f16, f16, f16, f16, undef)
+                    && attr()->has_default_values(
+                            primitive_attr_t::skip_mask_t::post_ops, f16);
+            const bool is_fp32_ok = expect_data_types(f32, f32, f32, f32, undef)
+                    && attr()->has_default_values(
+                            primitive_attr_t::skip_mask_t::post_ops, f32);
+            bool ok = is_fwd()
+                    && set_default_alg_kind(alg_kind::convolution_direct)
+                    && utils::one_of(true, is_fp16_ok, is_fp32_ok)
+                    && !has_zero_dim_memory();
+            if (!ok) return status::unimplemented;
+
+            CHECK(acl_convolution_utils::init_conf_depthwise(acp_, src_md_,
+                    weights_md_, dst_md_, bias_md_, *desc(), *attr()));
+
+            CHECK(post_ops.init(
+                    engine, attr_.post_ops_, dst_md_, acp_.act_info));
+            acp_.use_dst_acc = post_ops.has_sum();
+
+            return status::success;
+        }
+
+        acl_conv_conf_t acp_;
+
+        acl_post_ops_t post_ops;
+    };
+
+    acl_depthwise_convolution_fwd_t(const pd_t *apd) : primitive_t(apd) {}
+
+    status_t create_resource(
+            engine_t *engine, resource_mapper_t &mapper) const override {
+        if (mapper.has_resource(this)) return status::success;
+
+        auto r = utils::make_unique<acl_depthwise_convolution_resource_t>();
+        if (!r) return status::out_of_memory;
+
+        CHECK(r->configure(pd()->acp_));
+        mapper.add(this, std::move(r));
+
+        CHECK(pd()->post_ops.create_resource(engine, mapper));
+
+        return status::success;
+    }
+
+    typedef typename prec_traits<data_type::f32>::type data_t;
+
+    status_t execute(const exec_ctx_t &ctx) const override {
+        return execute_forward(ctx);
+    }
+
+private:
+    mutable std::mutex mtx;
+    status_t execute_forward(const exec_ctx_t &ctx) const;
+
+    const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); }
+};
+
+} // namespace aarch64
+} // namespace cpu
+} // namespace impl
+} // namespace dnnl
+
+#endif // CPU_AARCH64_ACL_DEPTHWISE_CONVOLUTION_HPP

miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/acl_eltwise.hpp

@@ -0,0 +1,162 @@
+/*******************************************************************************
+* Copyright 2021-2022 Arm Ltd. and affiliates
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef CPU_AARCH64_ACL_ELTWISE_HPP
+#define CPU_AARCH64_ACL_ELTWISE_HPP
+
+#include "cpu/cpu_eltwise_pd.hpp"
+
+#include "cpu/aarch64/acl_utils.hpp"
+
+namespace dnnl {
+namespace impl {
+namespace cpu {
+namespace aarch64 {
+
+struct acl_eltwise_obj_t {
+    arm_compute::NEActivationLayer act;
+    arm_compute::Tensor src_tensor;
+    arm_compute::Tensor dst_tensor;
+};
+
+struct acl_eltwise_conf_t {
+    arm_compute::ActivationLayerInfo act_info;
+    // src and dst have the same info
+    arm_compute::TensorInfo data_info;
+};
+
+struct acl_eltwise_resource_t : public resource_t {
+    acl_eltwise_resource_t()
+        : acl_eltwise_obj_(utils::make_unique<acl_eltwise_obj_t>()) {}
+
+    status_t configure(const acl_eltwise_conf_t &aep) {
+        if (!acl_eltwise_obj_) return status::out_of_memory;
+
+        // Init Compute Library tensors based on info from descriptor
+        acl_eltwise_obj_->src_tensor.allocator()->init(aep.data_info);
+        acl_eltwise_obj_->dst_tensor.allocator()->init(aep.data_info);
+
+        acl_eltwise_obj_->act.configure(&acl_eltwise_obj_->src_tensor,
+                &acl_eltwise_obj_->dst_tensor, aep.act_info);
+
+        return status::success;
+    }
+
+    acl_eltwise_obj_t &get_acl_obj() const { return *acl_eltwise_obj_; }
+
+    DNNL_DISALLOW_COPY_AND_ASSIGN(acl_eltwise_resource_t);
+
+private:
+    std::unique_ptr<acl_eltwise_obj_t> acl_eltwise_obj_;
+}; // acl_eltwise_resource_t
+
+struct acl_eltwise_fwd_t : public primitive_t {
+    struct pd_t : public cpu_eltwise_fwd_pd_t {
+        using cpu_eltwise_fwd_pd_t::cpu_eltwise_fwd_pd_t;
+
+        DECLARE_COMMON_PD_T("acl", acl_eltwise_fwd_t);
+
+        status_t init(engine_t *engine) {
+            using namespace utils;
+            using namespace data_type;
+            const memory_desc_wrapper src_d(src_md());
+
+            bool ok = is_fwd() && one_of(src_d.data_type(), f32, f16, s32, s8)
+                    && !has_zero_dim_memory() && attr()->has_default_values()
+                    && set_default_formats_common() && src_d.is_dense()
+                    && src_d == memory_desc_wrapper(dst_md());
+            if (!ok) return status::unimplemented;
+
+            // Workaround for the nan-value caused by tanh of ACL for fp16
+            // ARM-software/ComputeLibrary#998. Workaround for the inaccuracies
+            // caused by logistic/soft_relu/elu of ACL for fp16.
+            // TODO: Relax the error bounds in eltwise checks, or rework these
+            // fp16 operations in ACL for better accuracy.
+            using namespace dnnl::impl::alg_kind;
+            if (src_d.data_type() == f16
+                    && utils::one_of(desc_.alg_kind, eltwise_tanh,
+                            eltwise_logistic, eltwise_soft_relu, eltwise_elu)) {
+                return status::unimplemented;
+            }
+
+            auto acl_data_t = acl_utils::get_acl_data_t(src_d.data_type());
+
+            // Operator acts elementwise, so we only require that the product of
+            // all the dimensions equals the total number of elements. We are
+            // free to swap/combine dimensions. ACL performs SIMD parallelism
+            // over the first dimension and thread parallelism over the second.
+            // We pick a single dimension to thread over (taking the max of 2 to
+            // reduce the chance of it being 1), with the remaining dimensions
+            // to SIMD over.
+            dim_t thread_dim = std::max(W(), ndims() >= 2 ? C() : 1);
+            auto shape = arm_compute::TensorShape(
+                    src_d.nelems() / thread_dim, thread_dim);
+            aep.data_info = arm_compute::TensorInfo(shape, 1, acl_data_t);
+
+            CHECK(acl_utils::convert_to_acl_act(desc_, aep.act_info));
+
+            ACL_CHECK_VALID(arm_compute::NEActivationLayer::validate(
+                    &aep.data_info, &aep.data_info, aep.act_info));
+
+            return status::success;
+        }
+
+        acl_eltwise_conf_t aep;
+
+        friend struct acl_post_ops_t;
+    };
+
+    acl_eltwise_fwd_t(const pd_t *apd) : primitive_t(apd) {}
+
+    status_t execute(const exec_ctx_t &ctx) const override {
+        return execute_forward(ctx);
+    }
+
+    status_t create_resource(
+            engine_t *engine, resource_mapper_t &mapper) const override {
+        if (mapper.has_resource(this)) return status::success;
+
+        auto r = utils::make_unique<acl_eltwise_resource_t>();
+        if (!r) return status::out_of_memory;
+
+        // Configure the resource based on information from primitive descriptor
+        CHECK(r->configure(pd()->aep));
+        mapper.add(this, std::move(r));
+
+        return status::success;
+    }
+
+private:
+    // execute_forward has to be const thus mutability of mtx
+    mutable std::mutex mtx;
+
+    status_t execute_forward(const exec_ctx_t &ctx) const;
+
+    // Execute forward with arbitrary src and dst, used by acl_post_ops_t
+    status_t execute_forward(
+            const exec_ctx_t &ctx, const void *src, void *dst) const;
+
+    const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); }
+
+    friend struct acl_post_ops_t;
+}; // acl_eltwise_fwd_t
+
+} // namespace aarch64
+} // namespace cpu
+} // namespace impl
+} // namespace dnnl
+
+#endif // CPU_AARCH64_ACL_ELTWISE_HPP

miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/acl_gemm_convolution.hpp

@@ -0,0 +1,156 @@
+/*******************************************************************************
+* Copyright 2020-2023 Arm Ltd. and affiliates
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef CPU_AARCH64_ACL_GEMM_CONVOLUTION_HPP
+#define CPU_AARCH64_ACL_GEMM_CONVOLUTION_HPP
+
+#include "cpu/cpu_convolution_pd.hpp"
+
+#include "cpu/aarch64/acl_convolution_utils.hpp"
+#include "cpu/aarch64/acl_post_ops.hpp"
+
+namespace dnnl {
+namespace impl {
+namespace cpu {
+namespace aarch64 {
+
+struct acl_resource_t : public resource_t {
+    acl_resource_t()
+        : acl_obj_(utils::make_unique<
+                acl_obj_t<arm_compute::NEGEMMConvolutionLayer>>()) {}
+
+    status_t configure(const acl_conv_conf_t &acp) {
+        if (!acl_obj_) return status::out_of_memory;
+
+        // Init Compute Library tensors based on info from descriptor
+        acl_obj_->src_tensor.allocator()->init(acp.src_tensor_info);
+        acl_obj_->wei_tensor.allocator()->init(acp.wei_tensor_info);
+        acl_obj_->dst_tensor.allocator()->init(acp.dst_tensor_info);
+        acl_obj_->bia_tensor.allocator()->init(acp.bia_tensor_info);
+
+        acl_obj_->conv.configure(&acl_obj_->src_tensor, &acl_obj_->wei_tensor,
+                acp.with_bias ? &acl_obj_->bia_tensor : nullptr,
+                &acl_obj_->dst_tensor, acp.padstride_info, acp.weights_info,
+                acp.dilation_info, acp.act_info, acp.fast_math);
+        return status::success;
+    }
+
+    acl_obj_t<arm_compute::NEGEMMConvolutionLayer> &get_acl_obj() const {
+        return *acl_obj_;
+    }
+
+    DNNL_DISALLOW_COPY_AND_ASSIGN(acl_resource_t);
+
+private:
+    std::unique_ptr<acl_obj_t<arm_compute::NEGEMMConvolutionLayer>> acl_obj_;
+
+}; // acl_resource_t
+
+template <data_type_t src_type, data_type_t wei_type = src_type,
+        data_type_t dst_type = src_type, data_type_t bia_type = dst_type>
+struct acl_gemm_convolution_fwd_t : public primitive_t {
+    struct pd_t : public cpu_convolution_fwd_pd_t {
+        pd_t(const convolution_desc_t *adesc, const primitive_attr_t *attr,
+                const typename pd_t::base_class *hint_fwd_pd)
+            : cpu_convolution_fwd_pd_t(adesc, attr, hint_fwd_pd), acp_() {}
+
+        DECLARE_COMMON_PD_T(
+                "gemm:acl", acl_gemm_convolution_fwd_t, USE_GLOBAL_SCRATCHPAD);
+
+        status_t init(engine_t *engine) {
+            using namespace data_type;
+            using smask_t = primitive_attr_t::skip_mask_t;
+
+            bool ok = is_fwd()
+                    && set_default_alg_kind(alg_kind::convolution_direct)
+                    && expect_data_types(
+                            src_type, wei_type, bia_type, dst_type, undef)
+                    && !has_zero_dim_memory()
+                    && attr()->has_default_values(smask_t::post_ops, dst_type)
+                    && output_scales_mask_ok() && zero_points_ok();
+            if (!ok) return status::unimplemented;
+
+            CHECK(acl_convolution_utils::init_conf_gemm(acp_, src_md_,
+                    weights_md_, dst_md_, bias_md_, *desc(), *attr()));
+
+            CHECK(post_ops.init(
+                    engine, attr_.post_ops_, dst_md_, acp_.act_info));
+            acp_.use_dst_acc = post_ops.has_sum();
+
+            return status::success;
+        }
+
+        acl_conv_conf_t acp_;
+
+        acl_post_ops_t post_ops;
+
+    protected:
+        bool output_scales_mask_ok() const {
+            using namespace data_type;
+            const auto &mask = attr()->output_scales_.mask_;
+            return IMPLICATION(!utils::one_of(src_type, s8, u8),
+                           attr()->output_scales_.has_default_values())
+                    // TODO: add support for per_channel quantization
+                    && mask == 0;
+        }
+
+        bool zero_points_ok() const {
+            using namespace data_type;
+            // TODO: add support for asymmetric quantization
+            return attr()->zero_points_.has_default_values();
+        }
+    };
+
+    acl_gemm_convolution_fwd_t(const pd_t *apd) : primitive_t(apd) {}
+
+    status_t create_resource(
+            engine_t *engine, resource_mapper_t &mapper) const override {
+        if (mapper.has_resource(this)) return status::success;
+
+        auto r = utils::make_unique<acl_resource_t>();
+        if (!r) return status::out_of_memory;
+
+        // Configure the resource based on information from primitive descriptor
+        CHECK(r->configure(pd()->acp_));
+        mapper.add(this, std::move(r));
+
+        CHECK(pd()->post_ops.create_resource(engine, mapper));
+
+        return status::success;
+    }
+
+    typedef typename prec_traits<src_type>::type src_data_t;
+    typedef typename prec_traits<wei_type>::type wei_data_t;
+    typedef typename prec_traits<dst_type>::type dst_data_t;
+    typedef typename prec_traits<bia_type>::type bia_data_t;
+
+    status_t execute(const exec_ctx_t &ctx) const override {
+        return execute_forward(ctx);
+    }
+
+private:
+    // To guard the const execute_forward(), the mutex must be 'mutable'
+    mutable std::mutex mtx;
+    status_t execute_forward(const exec_ctx_t &ctx) const;
+    const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); }
+}; // acl_gemm_convolution_fwd_t
+
+} // namespace aarch64
+} // namespace cpu
+} // namespace impl
+} // namespace dnnl
+
+#endif

miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/acl_indirect_gemm_convolution.hpp

@@ -0,0 +1,147 @@
+/*******************************************************************************
+* Copyright 2021-2023 Arm Ltd. and affiliates
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef CPU_AARCH64_ACL_INDIRECT_GEMM_CONVOLUTION_HPP
+#define CPU_AARCH64_ACL_INDIRECT_GEMM_CONVOLUTION_HPP
+
+#include "cpu/cpu_convolution_pd.hpp"
+
+#include "cpu/aarch64/acl_convolution_utils.hpp"
+
+namespace dnnl {
+namespace impl {
+namespace cpu {
+namespace aarch64 {
+
+struct acl_indirect_gemm_resource_t : public resource_t {
+    acl_indirect_gemm_resource_t()
+        : acl_obj_(utils::make_unique<acl_obj_t<arm_compute::NEGEMMConv2d>>()) {
+    }
+
+    status_t configure(const acl_conv_conf_t &acp) {
+        if (!acl_obj_) return status::out_of_memory;
+
+        // Init Compute Library tensors based on info from descriptor
+        acl_obj_->src_tensor.allocator()->init(acp.src_tensor_info);
+        acl_obj_->wei_tensor.allocator()->init(acp.wei_tensor_info);
+        acl_obj_->dst_tensor.allocator()->init(acp.dst_tensor_info);
+        acl_obj_->bia_tensor.allocator()->init(acp.bia_tensor_info);
+
+        // clang-format off
+        acl_obj_->conv.configure(
+            &acl_obj_->src_tensor,
+            &acl_obj_->wei_tensor,
+            acp.with_bias ? &acl_obj_->bia_tensor : nullptr,
+            &acl_obj_->dst_tensor,
+            arm_compute::Conv2dInfo(acp.padstride_info,
+                                    acp.dilation_info,
+                                    acp.act_info,
+                                    acp.fast_math,
+                                    1,
+                                    {},
+                                    acp.weights_info));
+        // clang-format on
+
+        return status::success;
+    }
+
+    acl_obj_t<arm_compute::NEGEMMConv2d> &get_acl_obj() const {
+        return *acl_obj_;
+    }
+
+    DNNL_DISALLOW_COPY_AND_ASSIGN(acl_indirect_gemm_resource_t);
+
+private:
+    std::unique_ptr<acl_obj_t<arm_compute::NEGEMMConv2d>> acl_obj_;
+
+}; // acl_indirect_gemm_resource_t
+
+struct acl_indirect_gemm_convolution_fwd_t : public primitive_t {
+
+    struct pd_t : public cpu_convolution_fwd_pd_t {
+        pd_t(const convolution_desc_t *adesc, const primitive_attr_t *attr,
+                const typename pd_t::base_class *hint_fwd_pd)
+            : cpu_convolution_fwd_pd_t(adesc, attr, hint_fwd_pd), acp_() {}
+
+        DECLARE_COMMON_PD_T("indirect_gemm:acl",
+                acl_indirect_gemm_convolution_fwd_t, USE_GLOBAL_SCRATCHPAD);
+
+        status_t init(engine_t *engine) {
+            using namespace data_type;
+            const bool is_fp16_ok = expect_data_types(f16, f16, f16, f16, undef)
+                    && attr()->has_default_values(
+                            primitive_attr_t::skip_mask_t::post_ops, f16);
+            const bool is_fp32_ok = expect_data_types(f32, f32, f32, f32, undef)
+                    && attr()->has_default_values(
+                            primitive_attr_t::skip_mask_t::post_ops, f32);
+            bool ok = is_fwd()
+                    && set_default_alg_kind(alg_kind::convolution_direct)
+                    && utils::one_of(true, is_fp16_ok, is_fp32_ok)
+                    && !has_zero_dim_memory();
+            if (!ok) return status::unimplemented;
+
+            CHECK(acl_convolution_utils::init_conf_indirect_gemm(acp_, src_md_,
+                    weights_md_, dst_md_, bias_md_, *desc(), *attr()));
+
+            CHECK(post_ops.init(
+                    engine, attr_.post_ops_, dst_md_, acp_.act_info));
+            acp_.use_dst_acc = post_ops.has_sum();
+
+            return status::success;
+        }
+
+        acl_conv_conf_t acp_;
+
+        acl_post_ops_t post_ops;
+    };
+
+    acl_indirect_gemm_convolution_fwd_t(const pd_t *apd) : primitive_t(apd) {}
+
+    status_t create_resource(
+            engine_t *engine, resource_mapper_t &mapper) const override {
+        if (mapper.has_resource(this)) return status::success;
+
+        auto r = utils::make_unique<acl_indirect_gemm_resource_t>();
+        if (!r) return status::out_of_memory;
+
+        // Configure the resource based on information from primitive descriptor
+        CHECK(r->configure(pd()->acp_));
+        mapper.add(this, std::move(r));
+
+        CHECK(pd()->post_ops.create_resource(engine, mapper));
+
+        return status::success;
+    }
+
+    typedef typename prec_traits<data_type::f32>::type data_t;
+
+    status_t execute(const exec_ctx_t &ctx) const override {
+        return execute_forward(ctx);
+    }
+
+private:
+    // To guard the const execute_forward(), the mutex must be 'mutable'
+    mutable std::mutex mtx;
+    status_t execute_forward(const exec_ctx_t &ctx) const;
+    const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); }
+};
+
+} // namespace aarch64
+} // namespace cpu
+} // namespace impl
+} // namespace dnnl
+
+#endif // CPU_AARCH64_ACL_INDIRECT_GEMM_CONVOLUTION_HPP

miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/acl_inner_product.hpp

@@ -0,0 +1,314 @@
+/*******************************************************************************
+* Copyright 2021-2023 Arm Ltd. and affiliates
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef CPU_AARCH64_ACL_INNER_PRODUCT_HPP
+#define CPU_AARCH64_ACL_INNER_PRODUCT_HPP
+
+#include "cpu/aarch64/acl_utils.hpp"
+#include "cpu/cpu_inner_product_pd.hpp"
+
+#include "cpu/aarch64/acl_post_ops.hpp"
+
+namespace dnnl {
+namespace impl {
+namespace cpu {
+namespace aarch64 {
+
+struct acl_ip_obj_t {
+    arm_compute::NEFullyConnectedLayer fc;
+    arm_compute::Tensor src_tensor;
+    arm_compute::Tensor wei_tensor;
+    arm_compute::Tensor bia_tensor;
+    arm_compute::Tensor dst_tensor;
+};
+
+struct acl_ip_conf_t {
+    bool with_bias;
+    // If this is true, the result of the inner product goes into a temporarily
+    // allocated ACL tensor to be accumulated into the oneDNN dst during postops
+    bool use_dst_acc;
+    arm_compute::TensorInfo src_tensor_info;
+    arm_compute::TensorInfo wei_tensor_info;
+    arm_compute::TensorInfo bia_tensor_info;
+    arm_compute::TensorInfo dst_tensor_info;
+    arm_compute::FullyConnectedLayerInfo fc_info;
+    // Additional information about the weights not included in wei_tensor_info
+    arm_compute::WeightsInfo weights_info;
+};
+struct acl_ip_resource_t : public resource_t {
+    acl_ip_resource_t() : acl_ip_obj_(utils::make_unique<acl_ip_obj_t>()) {}
+
+    status_t configure(const acl_ip_conf_t &aip) {
+        if (!acl_ip_obj_) return status::out_of_memory;
+
+        // Init Compute Library tensors based on info from descriptor
+        acl_ip_obj_->src_tensor.allocator()->init(aip.src_tensor_info);
+        acl_ip_obj_->wei_tensor.allocator()->init(aip.wei_tensor_info);
+        acl_ip_obj_->dst_tensor.allocator()->init(aip.dst_tensor_info);
+        acl_ip_obj_->bia_tensor.allocator()->init(aip.bia_tensor_info);
+
+        // clang-format off
+        acl_ip_obj_->fc.configure(
+            &acl_ip_obj_->src_tensor,
+            &acl_ip_obj_->wei_tensor,
+            aip.with_bias ? &acl_ip_obj_->bia_tensor : nullptr,
+            &acl_ip_obj_->dst_tensor,
+            aip.fc_info,
+            aip.weights_info);
+        // clang-format on
+
+        return status::success;
+    }
+
+    acl_ip_obj_t &get_acl_obj() const { return *acl_ip_obj_; }
+
+    DNNL_DISALLOW_COPY_AND_ASSIGN(acl_ip_resource_t);
+
+private:
+    std::unique_ptr<acl_ip_obj_t> acl_ip_obj_;
+}; // acl_ip_resource_t
+
+struct acl_inner_product_fwd_t : public primitive_t {
+    struct pd_t : public cpu_inner_product_fwd_pd_t {
+        using cpu_inner_product_fwd_pd_t::cpu_inner_product_fwd_pd_t;
+
+        pd_t(const inner_product_desc_t *adesc, const primitive_attr_t *attr,
+                const typename pd_t::base_class *hint_fwd_pd)
+            : cpu_inner_product_fwd_pd_t(adesc, attr, hint_fwd_pd), aip() {}
+
+        DECLARE_COMMON_PD_T("acl", acl_inner_product_fwd_t);
+
+        status_t init(engine_t *engine) {
+            using namespace data_type;
+            const bool is_fp16_ok = expect_data_types(f16, f16, f16, f16, undef)
+                    && attr()->has_default_values(
+                            primitive_attr_t::skip_mask_t::post_ops, f16);
+            const bool is_fp32_ok = expect_data_types(f32, f32, f32, f32, undef)
+                    && attr()->has_default_values(
+                            primitive_attr_t::skip_mask_t::post_ops, f32);
+            const bool ok = is_fwd() && !has_zero_dim_memory()
+                    && utils::one_of(true, is_fp16_ok, is_fp32_ok)
+                    && weights_md_.format_kind == format_kind::any
+                    && set_default_params() == status::success;
+
+            if (!ok) return status::unimplemented;
+
+            CHECK(init_conf_ip(engine));
+
+            return status::success;
+        }
+
+        acl_ip_conf_t aip;
+
+        acl_post_ops_t post_ops;
+
+        status_t init_conf_ip(engine_t *engine) {
+
+            ACL_CHECK_SUPPORT(src_md()->ndims != weights_md()->ndims,
+                    "source and weights dimensions must match");
+
+            const int ndims = src_md()->ndims;
+
+            const bool is_2d = (ndims == 2);
+            const bool is_4d = (ndims == 4);
+
+            ACL_CHECK_SUPPORT(
+                    !(is_2d || is_4d), "ACL supports only 2d or 4d cases");
+
+            using namespace format_tag;
+            auto src_tag
+                    = memory_desc_matches_one_of_tag(src_md_, nhwc, nchw, nc);
+            auto dst_tag = memory_desc_matches_one_of_tag(dst_md_, nc);
+
+            ACL_CHECK_SUPPORT(
+                    utils::one_of(format_tag::undef, src_tag, dst_tag),
+                    "unsupported memory layout");
+
+            ACL_CHECK_SUPPORT(is_2d && src_tag != dst_tag,
+                    "for src and dst layouts must match");
+
+            const dim_t ic_total = IC_total();
+            const dim_t n = MB();
+            const dim_t oc = OC();
+
+            aip.src_tensor_info = arm_compute::TensorInfo(
+                    arm_compute::TensorShape(ic_total, n), 1,
+                    acl_utils::get_acl_data_t(src_md()->data_type));
+
+            // ACL requires the weights to be in 2D flattened shape
+            aip.wei_tensor_info = arm_compute::TensorInfo(
+                    arm_compute::TensorShape(oc, ic_total), 1,
+                    acl_utils::get_acl_data_t(weights_md(0)->data_type));
+
+            auto acl_dst_data_t
+                    = acl_utils::get_acl_data_t(dst_md()->data_type);
+            aip.dst_tensor_info = arm_compute::TensorInfo(
+                    arm_compute::TensorShape(oc, n), 1, acl_dst_data_t);
+
+            aip.with_bias = desc()->bias_desc.format_kind != format_kind::undef;
+            auto acl_bia_data_t = aip.with_bias
+                    ? acl_utils::get_acl_data_t(weights_md(1)->data_type)
+                    : acl_dst_data_t;
+            aip.bia_tensor_info = arm_compute::TensorInfo(aip.with_bias
+                            ? arm_compute::TensorShape(oc)
+                            : arm_compute::TensorShape(),
+                    1, acl_bia_data_t);
+
+            aip.fc_info.transpose_weights = false;
+
+            aip.fc_info.enable_fast_math = utils::one_of(
+                    attr()->fpmath_mode_, fpmath_mode::bf16, fpmath_mode::any);
+
+            CHECK(post_ops.init(engine, attr_.post_ops_, dst_md_,
+                    aip.fc_info.activation_info));
+            aip.use_dst_acc = post_ops.has_sum();
+
+            // WeightFormat::ANY tells ACL we can handle any format
+            aip.weights_info = arm_compute::WeightsInfo(false, 1, 1, ic_total,
+                    false, arm_compute::WeightFormat::ANY);
+
+            // Get the format that the ACL kernel will expect the weights to be
+            // in (if a kernel exists) Note that these are referred to as fixed
+            // format kernels, because they require one specific weights format
+            arm_compute::WeightFormat expected_weight_format;
+            ACL_CHECK_VALID(arm_compute::NEFullyConnectedLayer::has_opt_impl(
+                    expected_weight_format, &aip.src_tensor_info,
+                    &aip.wei_tensor_info,
+                    aip.with_bias ? &aip.bia_tensor_info : nullptr,
+                    &aip.dst_tensor_info, aip.fc_info, aip.weights_info));
+
+            // Set weights info to the one returned by has_opt_impl
+            aip.weights_info.set_weight_format(expected_weight_format);
+
+            // has_opt_impl may return a non fast math kernel, even if requested
+            aip.fc_info.enable_fast_math
+                    = arm_compute::is_fixed_format_fast_math(
+                            expected_weight_format);
+
+            // Inner product is the same as the matmul n x (chw) * (ihw) x o
+            // (note that the src c and weights i both correspond to the input
+            // channel). ACL FullyConnectedLayer assumes the chw dimensions of
+            // src and ihw dimensions of weights are collapsed, so we need to
+            // make sure that they have the same layout. Given that weights are
+            // more often fixed, (so reorders can be hoisted) it makes sense to
+            // reorder the weights to fit the src.
+
+            // For 4D tensors we need to:
+            // - reorder the ihw of the weights to match the src chw
+            // - collapse ihw
+            // - pad the collapsed ihw
+            // But there is not yet a way to express this collapse+pad as a
+            // reorder. So we try to reorder the weights to match the src,
+            // implicitly collapse ihw in our definition of the weights
+            // TensorInfo and hope that the inner_dim has zero padding
+            // (weights_md_.dims[inner_dim] % block_by == 0). If it does, we
+            // fall back to a kernel without blocking (currently this is
+            // equivalent to non-fastmath).
+
+            // 2D just works because we just pad the only dimension.
+
+            // o_dim is always the first logical dimension (oihw, ohwi, oi)
+            dim_t o_dim = 0;
+            dim_t inner_dim;
+            // Rest of logical dimensions in order of innermost to outermost
+            std::vector<dim_t> remaining_dims = {};
+
+            if (src_tag == nchw) {
+                inner_dim = 3; // w
+                remaining_dims = {2, 1}; // h, i
+            } else if (src_tag == nhwc) {
+                inner_dim = 1; // i
+                remaining_dims = {3, 2}; // w, h
+            } else { // Only remaining case is 2D (nc)
+                inner_dim = 1; // i
+                remaining_dims = {}; // No other dimensions for 2D
+            }
+
+            // Fallback
+            int block_by = arm_compute::block_by(expected_weight_format);
+            if (is_4d && weights_md_.dims[inner_dim] % block_by != 0
+                    && aip.fc_info.enable_fast_math) {
+                aip.fc_info.enable_fast_math = false;
+                aip.weights_info.set_weight_format(
+                        arm_compute::WeightFormat::ANY);
+                ACL_CHECK_VALID(
+                        arm_compute::NEFullyConnectedLayer::has_opt_impl(
+                                expected_weight_format, &aip.src_tensor_info,
+                                &aip.wei_tensor_info,
+                                aip.with_bias ? &aip.bia_tensor_info : nullptr,
+                                &aip.dst_tensor_info, aip.fc_info,
+                                aip.weights_info));
+                aip.weights_info.set_weight_format(expected_weight_format);
+                block_by = arm_compute::block_by(expected_weight_format);
+                if (weights_md_.dims[inner_dim] % block_by != 0)
+                    return status::unimplemented;
+            }
+
+            acl_utils::reorder_to_weight_format(aip.wei_tensor_info,
+                    weights_md_, expected_weight_format, inner_dim, o_dim,
+                    remaining_dims, {});
+
+            // clang-format off
+
+            // Validate fully connected layer manually to check for return status
+            ACL_CHECK_VALID(arm_compute::NEFullyConnectedLayer::validate(
+                &aip.src_tensor_info,
+                &aip.wei_tensor_info,
+                aip.with_bias ? &aip.bia_tensor_info : nullptr,
+                &aip.dst_tensor_info,
+                aip.fc_info,
+                aip.weights_info));
+            // clang-format on
+
+            return status::success;
+        }
+    }; // pd_t
+
+    acl_inner_product_fwd_t(const pd_t *apd) : primitive_t(apd) {}
+
+    status_t create_resource(
+            engine_t *engine, resource_mapper_t &mapper) const override {
+        if (mapper.has_resource(this)) return status::success;
+
+        auto r = utils::make_unique<acl_ip_resource_t>();
+        if (!r) return status::out_of_memory;
+
+        // Configure the resource based on information from primitive descriptor
+        CHECK(r->configure(pd()->aip));
+        mapper.add(this, std::move(r));
+
+        CHECK(pd()->post_ops.create_resource(engine, mapper));
+
+        return status::success;
+    }
+
+    status_t execute(const exec_ctx_t &ctx) const override {
+        return execute_forward(ctx);
+    }
+
+private:
+    //To guard the const execute_forward, the mutex must be 'mutable'
+    mutable std::mutex mtx;
+    status_t execute_forward(const exec_ctx_t &ctx) const;
+    const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); }
+}; // acl_inner_product_fwd_t
+
+} // namespace aarch64
+} // namespace cpu
+} // namespace impl
+} // namespace dnnl
+
+#endif // CPU_AARCH64_ACL_INNER_PRODUCT_HPP

miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/acl_layer_normalization.hpp

@@ -0,0 +1,258 @@
+/*******************************************************************************
+* Copyright 2023 Arm Ltd. and affiliates
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef CPU_AARCH64_ACL_LAYER_NORMALIZATION_HPP
+#define CPU_AARCH64_ACL_LAYER_NORMALIZATION_HPP
+
+#include "cpu/aarch64/acl_utils.hpp"
+#include "cpu/cpu_layer_normalization_pd.hpp"
+
+namespace dnnl {
+namespace impl {
+namespace cpu {
+namespace aarch64 {
+
+struct acl_msdnorm_obj_t {
+    arm_compute::NEMeanStdDevNormalizationLayer msdNorm;
+    arm_compute::Tensor src_tensor;
+    arm_compute::Tensor dst_tensor;
+};
+
+struct acl_msdnorm_conf_t {
+    arm_compute::TensorInfo data_info; // src and dst tensors
+};
+
+struct acl_layer_normalization_resource_t : public resource_t {
+    acl_layer_normalization_resource_t()
+        : acl_obj(utils::make_unique<acl_msdnorm_obj_t>()) {}
+
+    status_t configure(
+            const acl_msdnorm_conf_t &anp, const layer_normalization_pd_t *pd) {
+        if (!acl_obj) return status::out_of_memory;
+
+        acl_obj->src_tensor.allocator()->init(anp.data_info);
+        acl_obj->dst_tensor.allocator()->init(anp.data_info);
+
+        // clang-format off
+        acl_obj->msdNorm.configure(
+            &acl_obj->src_tensor,
+            &acl_obj->dst_tensor,
+            pd->desc()->layer_norm_epsilon);
+        // clang-format on
+
+        return status::success;
+    }
+
+    acl_msdnorm_obj_t &get_acl_obj() const { return *acl_obj; }
+
+    DNNL_DISALLOW_COPY_AND_ASSIGN(acl_layer_normalization_resource_t);
+
+private:
+    std::unique_ptr<acl_msdnorm_obj_t> acl_obj;
+}; // acl_layer_normalization_resource_t
+
+struct acl_layer_normalization_fwd_t : public primitive_t {
+    struct pd_t : public cpu_layer_normalization_fwd_pd_t {
+        using cpu_layer_normalization_fwd_pd_t::
+                cpu_layer_normalization_fwd_pd_t;
+        pd_t(const layer_normalization_desc_t *adesc,
+                const primitive_attr_t *attr,
+                const typename pd_t::base_class *hint_fwd_pd)
+            : cpu_layer_normalization_fwd_pd_t(adesc, attr, hint_fwd_pd)
+            , anp() {}
+
+        DECLARE_COMMON_PD_T("acl", acl_layer_normalization_fwd_t);
+
+        status_t init(engine_t *engine) {
+
+            // dir and flags
+            ACL_CHECK_SUPPORT(
+                    !is_fwd(), "ACL lnorm supports forward propagation only");
+            ACL_CHECK_SUPPORT(is_training() && !use_global_stats(),
+                    "ACL only supports forward training with lnorm if stats "
+                    "are provided (use global stats)");
+            ACL_CHECK_SUPPORT(use_scale() || use_shift(),
+                    "ACL does not support lnorm scale and shift");
+
+            // attr-scales
+            ACL_CHECK_SUPPORT(!attr()->has_default_values(),
+                    "ACL does not support scales attribute");
+
+            // tag and stat_tag
+            ACL_CHECK_SUPPORT(src_md()->ndims < 2 || src_md()->ndims > 5,
+                    "src tensor must have between 2 and 5 (inclusive) "
+                    "dimensions");
+
+            // msdNorm only supports lnorm for src in a channels last format.
+            // So if channels aren't last (ie. if they aren't dense),
+            // then reorder into a channels last format
+            std::string ref_implementation_guess = "simple:any";
+            if (src_md()->format_desc.blocking.strides[ndims() - 1] != 1) {
+                CHECK(memory_desc_init_by_tag(
+                        src_md_, get_channels_last_format(src_md_.ndims)));
+                ref_implementation_guess = "ref:any";
+            }
+            if (dst_md_ != src_md_)
+                // Make sure dst and src share a format
+                CHECK(memory_desc_init_by_md_and_dt(
+                        dst_md_, src_md_, src_md()->data_type));
+            if (!set_default_stat_md_format(src_md_))
+                return status::unimplemented;
+
+            const memory_desc_wrapper src_d(src_md_);
+            const memory_desc_wrapper dst_d(dst_md_);
+
+            ACL_CHECK_SUPPORT(src_d.has_zero_dim() || dst_d.has_zero_dim(),
+                    "data tensor(s) must not have a zero dimension");
+
+            // data type
+            ACL_CHECK_SUPPORT(src_d.data_type() != data_type::f32,
+                    "ACL Lnorm only supports F32");
+            ACL_CHECK_SUPPORT(dst_d.data_type() != src_d.data_type(),
+                    "src and dst must share data types");
+
+            // Problem shape
+            int C = norm_axis(); // Channel dim size
+            int X = src_d.nelems() / C; // Non-channel dims size
+
+            ACL_CHECK_SUPPORT(!use_acl_heuristic(X, C, dnnl_get_max_threads(),
+                                      is_training(), ref_implementation_guess),
+                    "ACL is unoptimal in this case");
+
+            anp.data_info
+                    = arm_compute::TensorInfo(arm_compute::TensorShape(C, X), 1,
+                            arm_compute::DataType::F32);
+
+            ACL_CHECK_VALID(
+                    arm_compute::NEMeanStdDevNormalizationLayer::validate(
+                            &anp.data_info, &anp.data_info,
+                            desc()->layer_norm_epsilon));
+
+            return status::success;
+        }
+
+        format_tag_t get_channels_last_format(size_t ndim) {
+            assert(ndim > 1 && ndim < 6);
+            switch (ndim) {
+                case 2: return format_tag::nc;
+                case 3: return format_tag::tnc;
+                case 4: return format_tag::ldnc;
+                case 5: return format_tag::abcde;
+                default: return format_tag::undef;
+            }
+        }
+
+        bool use_acl_heuristic(int X, int C, int threads, bool ref_has_stats,
+                std::string ref_implementation_guess) {
+            // Above a certain C, acl is always better, and below a certain C,
+            // acl is always worse. for C in between these two, whether acl is
+            // better can be approximated with the workload (X*C) per thread.
+            // The values here were derived empirically and all depend on
+            // threads, whether ref can use provided stats, and which reference
+            // implementation acl is competing with.
+
+            int acl_competitive_C = C;
+            int acl_better_C = C;
+            int acl_better_XC_per_thread = X * C;
+
+            if (ref_implementation_guess == "simple:any") {
+                acl_competitive_C = 64;
+                if (ref_has_stats) {
+                    acl_better_C = 4096;
+                    acl_better_XC_per_thread = threads == 1 ? 4096 : 8192;
+                } else {
+                    acl_better_C = threads <= 2 ? 1024 : 4096;
+                    acl_better_XC_per_thread = threads == 1 ? 1024 : 4096;
+                }
+            } else if (ref_implementation_guess == "ref:any") {
+                acl_competitive_C = 0;
+                if (ref_has_stats) {
+                    if (threads == 1) {
+                        acl_better_C = 64;
+                    } else if (threads == 2) {
+                        acl_better_C = 256;
+                    } else {
+                        acl_better_C = 1024;
+                    }
+
+                    if (threads == 1) {
+                        acl_better_XC_per_thread = 256;
+                    } else if (threads <= 16) {
+                        acl_better_XC_per_thread = 512;
+                    } else {
+                        acl_better_XC_per_thread = 1024;
+                    }
+                } else {
+                    if (threads == 1) {
+                        acl_better_C = 64;
+                    } else if (threads <= 32) {
+                        acl_better_C = 256;
+                    } else {
+                        acl_better_C = 1024;
+                    }
+
+                    if (threads == 1) {
+                        acl_better_XC_per_thread = 128;
+                    } else if (threads <= 32) {
+                        acl_better_XC_per_thread = 256;
+                    } else {
+                        acl_better_XC_per_thread = 512;
+                    }
+                }
+            }
+
+            return C > acl_competitive_C
+                    && (C > acl_better_C
+                            || X * C > acl_better_XC_per_thread * threads);
+        }
+
+        acl_msdnorm_conf_t anp;
+
+    }; // pd_t
+
+    acl_layer_normalization_fwd_t(const pd_t *apd) : primitive_t(apd) {}
+
+    status_t create_resource(
+            engine_t *engine, resource_mapper_t &mapper) const override {
+        if (mapper.has_resource(this)) return status::success;
+
+        auto r = utils::make_unique<acl_layer_normalization_resource_t>();
+        if (!r) return status::out_of_memory;
+
+        // Configure the resource based on information from primitive descriptor
+        CHECK(r->configure(pd()->anp, pd()));
+        mapper.add(this, std::move(r));
+
+        return status::success;
+    }
+
+    status_t execute(const exec_ctx_t &ctx) const override {
+        return execute_forward(ctx);
+    }
+
+private:
+    // To guard the const execute_forward, the mutex must be 'mutable'
+    mutable std::mutex mtx;
+    status_t execute_forward(const exec_ctx_t &ctx) const;
+    const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); }
+}; // acl_layer_normalization_fwd_t
+
+} // namespace aarch64
+} // namespace cpu
+} // namespace impl
+} // namespace dnnl
+
+#endif // CPU_AARCH64_ACL_LAYER_NORMALIZATION_HPP

miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/acl_pooling.hpp

@@ -0,0 +1,225 @@
+/*******************************************************************************
+* Copyright 2022 Arm Ltd. and affiliates
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef CPU_AARCH64_ACL_POOLING_HPP
+#define CPU_AARCH64_ACL_POOLING_HPP
+
+#include "cpu/aarch64/acl_utils.hpp"
+#include "cpu/cpu_pooling_pd.hpp"
+
+namespace dnnl {
+namespace impl {
+namespace cpu {
+namespace aarch64 {
+
+struct acl_pooling_obj_t {
+    arm_compute::NEPoolingLayer pool;
+    arm_compute::Tensor src_tensor;
+    arm_compute::Tensor dst_tensor;
+};
+
+struct acl_pooling_conf_t {
+    arm_compute::PoolingLayerInfo pool_info;
+    arm_compute::TensorInfo src_info;
+    arm_compute::TensorInfo dst_info;
+};
+
+struct acl_pooling_resource_t : public resource_t {
+    acl_pooling_resource_t()
+        : acl_pooling_obj_(utils::make_unique<acl_pooling_obj_t>()) {}
+
+    status_t configure(const acl_pooling_conf_t &app) {
+        if (!acl_pooling_obj_) return status::out_of_memory;
+
+        // Init Compute Library tensors based on info from descriptor
+        acl_pooling_obj_->src_tensor.allocator()->init(app.src_info);
+        acl_pooling_obj_->dst_tensor.allocator()->init(app.dst_info);
+
+        acl_pooling_obj_->pool.configure(&acl_pooling_obj_->src_tensor,
+                &acl_pooling_obj_->dst_tensor, app.pool_info);
+
+        return status::success;
+    }
+
+    acl_pooling_obj_t &get_acl_obj() const { return *acl_pooling_obj_; }
+
+    DNNL_DISALLOW_COPY_AND_ASSIGN(acl_pooling_resource_t);
+
+private:
+    std::unique_ptr<acl_pooling_obj_t> acl_pooling_obj_;
+}; // acl_pooling_resource_t
+
+struct acl_pooling_fwd_t : public primitive_t {
+    struct pd_t : public cpu_pooling_fwd_pd_t {
+        using cpu_pooling_fwd_pd_t::cpu_pooling_fwd_pd_t;
+        pd_t(const pooling_desc_t *adesc, const primitive_attr_t *attr,
+                const pooling_fwd_pd_t *hint_fwd_pd)
+            : cpu_pooling_fwd_pd_t(adesc, attr, hint_fwd_pd), app() {}
+
+        DECLARE_COMMON_PD_T("acl", acl_pooling_fwd_t);
+
+        status_t init(engine_t *engine) {
+            bool ok = set_default_params() == status::success
+                    && is_fwd() // ACL supports forward propagation only
+                    && utils::everyone_is(
+                            src_md()->data_type, dst_md()->data_type)
+                    && utils::one_of(
+                            src_md()->data_type, data_type::f32, data_type::f16)
+                    && attr()->has_default_values()
+                    && attr_.set_default_formats(dst_md(0)) == status::success
+                    && !is_dilated() && !has_zero_dim_memory();
+            if (!ok) return status::unimplemented;
+
+            const pooling_desc_t *pod = desc();
+
+            // Choose the pooling type
+            const alg_kind_t alg = pod->alg_kind;
+            const bool is_max_pool = (alg == alg_kind::pooling_max);
+            app.pool_info.pool_type = is_max_pool
+                    ? arm_compute::PoolingType::MAX
+                    : arm_compute::PoolingType::AVG;
+
+            // Max forward training requires a worksace tensor.
+            // For this workspace tensor, oneDNN uses pool window coordinates,
+            // Whereas ACL uses absolute image coordinates.
+            // Due to this mismatch, reject max forward training cases
+            ACL_CHECK_SUPPORT(
+                    (is_max_pool
+                            && pod->prop_kind == prop_kind::forward_training),
+                    "ACL does not support training for max pooling in oneDNN");
+
+            // When padding is larger than the kernel, infinite values are
+            // produced.
+            // ACL and oneDNN use different values to represent infinity
+            // which is difficult to account for, so return unimplemented.
+            // See https://github.com/oneapi-src/oneDNN/issues/1205
+            ACL_CHECK_SUPPORT(KH() <= padT() || KH() <= padB() || KW() <= padL()
+                            || KW() <= padR(),
+                    "ACL does not support pooling cases where padding >= kernel"
+                    " in oneDNN");
+
+            auto src_tag = memory_desc_matches_one_of_tag(
+                    *src_md(), format_tag::nhwc, format_tag::nchw);
+            auto dst_tag = memory_desc_matches_one_of_tag(
+                    *dst_md(), format_tag::nhwc, format_tag::nchw);
+
+            ACL_CHECK_SUPPORT(
+                    utils::one_of(format_tag::undef, src_tag, dst_tag),
+                    "src or dst is not format nhwc or nchw");
+            ACL_CHECK_SUPPORT(src_tag != dst_tag,
+                    "src and dst have different memory formats");
+
+            const memory_desc_wrapper src_d(src_md());
+            const memory_desc_wrapper dst_d(dst_md());
+            const int ndims = src_d.ndims();
+            ACL_CHECK_SUPPORT(ndims != 4, "Tensor is not 4d");
+
+            // Pooling window
+            app.pool_info.pool_size = arm_compute::Size2D(KW(), KH());
+            // Choose the data layout
+            bool is_nspc = utils::one_of(src_tag, format_tag::nhwc);
+            const auto acl_layout = is_nspc ? arm_compute::DataLayout::NHWC
+                                            : arm_compute::DataLayout::NCHW;
+            app.pool_info.data_layout = acl_layout;
+            const auto acl_data_t
+                    = acl_utils::get_acl_data_t(src_d.data_type());
+
+            ACL_CHECK_SUPPORT(
+                    !use_acl_heuristic(MB() * IC() * OH() * OW() * KH() * KW(),
+                            dnnl_get_max_threads(), is_max_pool, is_nspc),
+                    "ACL is unoptimal in this case");
+
+            app.pool_info.exclude_padding
+                    = (alg == alg_kind::pooling_avg_exclude_padding);
+
+            app.pool_info.pad_stride_info = arm_compute::PadStrideInfo(KSW(),
+                    KSH(), padL(), padR(), padT(), padB(),
+                    arm_compute::DimensionRoundingType::FLOOR);
+
+            app.src_info = arm_compute::TensorInfo(is_nspc
+                            ? arm_compute::TensorShape(IC(), IW(), IH(), MB())
+                            : arm_compute::TensorShape(IW(), IH(), IC(), MB()),
+                    1, acl_data_t, acl_layout);
+            app.dst_info = arm_compute::TensorInfo(is_nspc
+                            ? arm_compute::TensorShape(OC(), OW(), OH(), MB())
+                            : arm_compute::TensorShape(OW(), OH(), OC(), MB()),
+                    1, acl_data_t, acl_layout);
+
+            ACL_CHECK_VALID(arm_compute::NEPoolingLayer::validate(
+                    &app.src_info, &app.dst_info, app.pool_info));
+
+            return status::success;
+        }
+
+        bool use_acl_heuristic(
+                int problem_size, int thread_count, bool is_max, bool is_nhwc) {
+            // For nhwc, ACL is faster above a certain problem size 'cutoff'
+            // This cutoff scales linearly with thread count (except 1 thread)
+            // So return true iff problem size is larger than this cutoff.
+            // Note: This rule is approximate, Not all problems follow this rule
+            if (is_nhwc) {
+                if (is_max) {
+                    if (thread_count == 1)
+                        return problem_size > 512;
+                    else
+                        return problem_size > 4096 * thread_count;
+                } else { // pooling_alg == avg_p || pooling_alg == avg_np
+                    if (thread_count == 1)
+                        return problem_size > 1024;
+                    else
+                        return problem_size > 8192 * thread_count;
+                }
+            } else { // memory_format == nchw
+                return false;
+            }
+        }
+
+        acl_pooling_conf_t app;
+    };
+
+    acl_pooling_fwd_t(const pd_t *apd) : primitive_t(apd) {}
+
+    status_t execute(const exec_ctx_t &ctx) const override {
+        return execute_forward(ctx);
+    }
+
+    status_t create_resource(
+            engine_t *engine, resource_mapper_t &mapper) const override {
+        if (mapper.has_resource(this)) return status::success;
+
+        auto r = utils::make_unique<acl_pooling_resource_t>();
+        if (!r) return status::out_of_memory;
+
+        // Configure the resource based on information from primitive descriptor
+        auto st = r->configure(pd()->app);
+        if (st == status::success) { mapper.add(this, std::move(r)); }
+
+        return st;
+    }
+
+private:
+    // execute_forward has to be const thus mutability of mtx
+    mutable std::mutex mtx;
+    status_t execute_forward(const exec_ctx_t &ctx) const;
+    const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); }
+}; // acl_pooling_fwd_t
+
+} // namespace aarch64
+} // namespace cpu
+} // namespace impl
+} // namespace dnnl
+
+#endif // CPU_AARCH64_ACL_POOLING_HPP

miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/acl_post_ops.hpp

@@ -0,0 +1,194 @@
+/*******************************************************************************
+* Copyright 2022-2023 Arm Ltd. and affiliates
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef CPU_AARCH64_ACL_POST_OPS_HPP
+#define CPU_AARCH64_ACL_POST_OPS_HPP
+
+#include "cpu/aarch64/acl_binary.hpp"
+#include "cpu/aarch64/acl_eltwise.hpp"
+
+namespace dnnl {
+namespace impl {
+namespace cpu {
+namespace aarch64 {
+
+struct acl_post_ops_t {
+
+    acl_post_ops_t() = default;
+
+    // init the acl_post_ops_t. Note that this function modifies the passed in
+    // post ops by setting the preferred memory formats
+    status_t init(engine_t *engine, post_ops_t &post_ops,
+            const memory_desc_t &dst_md) {
+
+        CHECK(post_ops.set_default_formats(&dst_md));
+        dst_data_type = dst_md.data_type;
+
+        // Reset properties derived from post_ops
+        sum_index = -1;
+        post_op_primitives = {};
+
+        for (int i = 0; i < post_ops.len(); i++) {
+            auto &po = post_ops.entry_[i];
+
+            if (po.is_sum()) {
+                ACL_CHECK_SUPPORT(po.sum.scale != 1.0f,
+                        "sum post op scale must be 1 (no scale)");
+
+                ACL_CHECK_SUPPORT(po.sum.zero_point != 0,
+                        "sum post op zero point must be 0 (no shift)");
+
+                // >= 0 means we had one already
+                ACL_CHECK_SUPPORT(sum_index >= 0,
+                        "there must not be more than 1 sum post op");
+
+                sum_index = i;
+
+                // Sum is an add primitive where dst = temp_dst + dst
+                binary_desc_t po_desc;
+                po_desc.primitive_kind = primitive_kind::binary;
+                po_desc.alg_kind = alg_kind::binary_add;
+                po_desc.src_desc[0] = dst_md;
+                po_desc.src_desc[1] = dst_md;
+                po_desc.dst_desc = dst_md;
+                auto empty_attr = dnnl_primitive_attr();
+                typename acl_binary_t::pd_t acl_binary_pd(
+                        &po_desc, &empty_attr, nullptr);
+                CHECK(acl_binary_pd.init(engine));
+
+                auto acl_binary
+                        = std::make_shared<acl_binary_t>(&acl_binary_pd);
+                CHECK(acl_binary->init(engine));
+                post_op_primitives.push_back(acl_binary);
+
+            } else if (po.is_binary()) {
+                binary_desc_t po_desc;
+                po_desc.primitive_kind = primitive_kind::binary;
+                po_desc.alg_kind = po.binary.alg;
+                po_desc.src_desc[0] = dst_md;
+                po_desc.src_desc[1] = po.binary.src1_desc;
+                po_desc.dst_desc = dst_md;
+                auto empty_attr = dnnl_primitive_attr();
+                typename acl_binary_t::pd_t acl_binary_pd(
+                        &po_desc, &empty_attr, nullptr);
+                CHECK(acl_binary_pd.init(engine));
+
+                auto acl_binary
+                        = std::make_shared<acl_binary_t>(&acl_binary_pd);
+                CHECK(acl_binary->init(engine));
+                post_op_primitives.push_back(acl_binary);
+
+            } else if (po.is_eltwise()) {
+                ACL_CHECK_SUPPORT(po.eltwise.scale != 1.0f,
+                        "eltwise post op scale must be 1 (no scale)");
+
+                eltwise_desc_t eltwise_desc;
+                eltwise_desc.primitive_kind = primitive_kind::eltwise;
+                eltwise_desc.alg_kind = po.eltwise.alg;
+                eltwise_desc.alpha = po.eltwise.alpha;
+                eltwise_desc.beta = po.eltwise.beta;
+                memory_desc_t temp_dst = dst_md;
+                // pass eltwise a desc with f32 datatype to perform the operation in fp32 rather than fp16
+                // since oneDNN requires all post-ops to run in fp32.
+                // we don't need to do that to the other post-ops as executing them in fp16 yields the same result.
+                if (dst_data_type == data_type::f16) {
+                    temp_dst.data_type = data_type::f32;
+                }
+                eltwise_desc.src_desc = temp_dst;
+                eltwise_desc.dst_desc = temp_dst;
+                eltwise_desc.prop_kind = prop_kind_t::dnnl_forward;
+                auto empty_attr = dnnl_primitive_attr();
+                typename acl_eltwise_fwd_t::pd_t acl_eltwise_pd(
+                        &eltwise_desc, &empty_attr, nullptr);
+                CHECK(acl_eltwise_pd.init(engine));
+
+                auto acl_eltwise
+                        = std::make_shared<acl_eltwise_fwd_t>(&acl_eltwise_pd);
+                CHECK(acl_eltwise->init(engine));
+                post_op_primitives.push_back(acl_eltwise);
+
+            } else {
+                // Unsupported catchall
+                return status::unimplemented;
+            }
+        }
+
+        return status::success;
+    }
+
+    // init acl_post_ops_t, ignoring the first post op if it is an eltwise so
+    // that it can be fused, placing it in act_info_to_fuse. Note that this
+    // function modifies the passed in post ops by setting the preferred memory
+    // formats
+    status_t init(engine_t *engine, post_ops_t &base_post_ops,
+            const memory_desc_t &dst_md,
+            arm_compute::ActivationLayerInfo &act_info_to_fuse) {
+
+        CHECK(base_post_ops.set_default_formats(&dst_md));
+        dst_data_type = dst_md.data_type;
+        // If the first entry is eltwise, we fuse it, except when the datatype
+        // is fp16 because in this case we want to execute the eltwise in fp32.
+        if (base_post_ops.len() >= 1 && base_post_ops.entry_[0].is_eltwise()
+                && dst_data_type != data_type::f16) {
+
+            const auto &first_po = base_post_ops.entry_[0].eltwise;
+            ACL_CHECK_SUPPORT(first_po.scale != 1.0f,
+                    "eltwise post op scale must be 1 (no scale)");
+            CHECK(acl_utils::convert_to_acl_act(first_po, act_info_to_fuse));
+
+            // Copy all but the first, because it has been fused
+            post_ops_t post_ops;
+            for (int idx = 1; idx < base_post_ops.len(); ++idx) {
+                // Construct empty entry then copy, so that we can check for failure
+                post_ops.entry_.emplace_back();
+                post_ops.entry_.back().copy_from(base_post_ops.entry_[idx]);
+            }
+            return init(engine, post_ops, dst_md);
+
+        } else {
+            // Nothing to fuse, just copy all post ops
+            return init(engine, base_post_ops, dst_md);
+        }
+    }
+
+    bool has_sum() const { return sum_index >= 0; }
+
+    status_t create_resource(
+            engine_t *engine, resource_mapper_t &mapper) const {
+        for (const auto &post_op : post_op_primitives) {
+            CHECK(post_op->create_resource(engine, mapper));
+        }
+        return status::success;
+    }
+
+    status_t execute(const exec_ctx_t &ctx, void *src) const;
+
+private:
+    // Index of the sum post op if there is one, < 0 means no sum
+    int sum_index = -1;
+    data_type_t dst_data_type;
+    // Vector of primitives used to execute the post ops. They are constructed
+    // in init to be either acl_binary_t (for sum, add, sub, div, mul, min and
+    // max) or acl_eltwise_fwd_t (for relu, elu, tanh, square, abs etc)
+    std::vector<std::shared_ptr<primitive_t>> post_op_primitives;
+};
+
+} // namespace aarch64
+} // namespace cpu
+} // namespace impl
+} // namespace dnnl
+
+#endif

miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/acl_prelu.hpp

@@ -0,0 +1,159 @@
+/*******************************************************************************
+* Copyright 2022 Arm Ltd. and affiliates
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+#ifndef CPU_AARCH64_ACL_PRELU_HPP
+#define CPU_AARCH64_ACL_PRELU_HPP
+
+#include "cpu/aarch64/acl_utils.hpp"
+#include "cpu/cpu_prelu_pd.hpp"
+
+namespace dnnl {
+namespace impl {
+namespace cpu {
+namespace aarch64 {
+
+struct acl_prelu_obj_t {
+    arm_compute::NEPReluLayer prelu;
+    arm_compute::Tensor src_tensor;
+    arm_compute::Tensor weights_tensor;
+    arm_compute::Tensor dst_tensor;
+};
+
+struct acl_prelu_conf_t {
+    arm_compute::TensorInfo src_info;
+    arm_compute::TensorInfo weights_info;
+    arm_compute::TensorInfo dst_info;
+};
+
+struct acl_prelu_resource_t : public resource_t {
+    acl_prelu_resource_t() : acl_obj_(utils::make_unique<acl_prelu_obj_t>()) {}
+
+    status_t configure(const acl_prelu_conf_t &app) {
+        if (!acl_obj_) return status::out_of_memory;
+
+        // Init Compute Library tensors based on info from descriptor
+        acl_obj_->src_tensor.allocator()->init(app.src_info);
+        acl_obj_->weights_tensor.allocator()->init(app.weights_info);
+        acl_obj_->dst_tensor.allocator()->init(app.dst_info);
+
+        // clang-format off
+        acl_obj_->prelu.configure(
+            &acl_obj_->src_tensor,
+            &acl_obj_->weights_tensor,
+            &acl_obj_->dst_tensor);
+        // clang-format on
+
+        return status::success;
+    }
+
+    acl_prelu_obj_t &get_acl_obj() const { return *acl_obj_; }
+
+    DNNL_DISALLOW_COPY_AND_ASSIGN(acl_prelu_resource_t);
+
+private:
+    std::unique_ptr<acl_prelu_obj_t> acl_obj_;
+}; // acl_prelu_resource_t
+
+struct acl_prelu_fwd_t : public primitive_t {
+    struct pd_t : public cpu_prelu_fwd_pd_t {
+        using cpu_prelu_fwd_pd_t::cpu_prelu_fwd_pd_t;
+
+        DECLARE_COMMON_PD_T("acl", acl_prelu_fwd_t);
+
+        status_t init(engine_t *engine) {
+            using namespace format_tag;
+            using namespace acl_utils;
+
+            // Forward only
+            if (!prelu_pd_t::is_fwd()) return status::unimplemented;
+
+            // Only support f32 and f16 for now
+            data_type_t ddt = dst_md(0)->data_type;
+            if (!utils::one_of(ddt, data_type::f32, data_type::f16))
+                return status::unimplemented;
+
+            if (!set_default_formats()) return status::unimplemented;
+
+            if (!attr()->has_default_values()) return status::unimplemented;
+
+            // ACL pointwise arithmetic operators assume that the innermost
+            // dimensions are dense for src, weights and dst. Reordering the
+            // logical dimensions by stride does this (if reordered_dims >= 1 )
+            // and also makes memory accesses contiguous in ACL (without any
+            // data reordering).
+            memory_desc_t src_d_permed, weights_d_permed, dst_d_permed;
+            int reordered_dims = reorder_dimensions_by_stride(
+                    {&src_d_permed, &weights_d_permed, &dst_d_permed},
+                    {src_md(0), weights_md(0), dst_md(0)});
+            if (reordered_dims < 1) return status::unimplemented;
+
+            // Create ACL tensor infos with permuted descs
+            CHECK(tensor_info(app_.src_info, src_d_permed));
+            CHECK(tensor_info(app_.weights_info, weights_d_permed));
+            CHECK(tensor_info(app_.dst_info, dst_d_permed));
+
+            // This forces ACL not to parallelise with small workloads, this is
+            // a temporary fix and should be removed in future versions (TODO)
+            memory_desc_wrapper dst_d(dst_md(0));
+            if (dst_d.nelems() < 40000) {
+                size_t acl_y_axis_i = 1;
+                CHECK(insert_singleton_dimension(app_.src_info, acl_y_axis_i));
+                CHECK(insert_singleton_dimension(
+                        app_.weights_info, acl_y_axis_i));
+                CHECK(insert_singleton_dimension(app_.dst_info, acl_y_axis_i));
+            }
+
+            ACL_CHECK_VALID(arm_compute::NEPReluLayer::validate(
+                    &app_.src_info, &app_.weights_info, &app_.dst_info));
+
+            return status::success;
+        }
+
+        acl_prelu_conf_t app_;
+    }; // pd_t
+
+    acl_prelu_fwd_t(const pd_t *apd) : primitive_t(apd) {}
+
+    status_t create_resource(
+            engine_t *engine, resource_mapper_t &mapper) const override {
+        if (mapper.has_resource(this)) return status::success;
+
+        auto r = utils::make_unique<acl_prelu_resource_t>();
+        if (!r) return status::out_of_memory;
+
+        // Configure the resource based on information from primitive descriptor
+        CHECK(r->configure(pd()->app_));
+
+        mapper.add(this, std::move(r));
+        return status::success;
+    }
+
+    status_t execute(const exec_ctx_t &ctx) const override {
+        return execute_forward(ctx);
+    }
+
+private:
+    // To guard the const execute_forward, the mutex must be 'mutable'
+    mutable std::mutex mtx;
+    status_t execute_forward(const exec_ctx_t &ctx) const;
+    const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); }
+}; // acl_prelu_fwd_t
+
+} // namespace aarch64
+} // namespace cpu
+} // namespace impl
+} // namespace dnnl
+
+#endif // CPU_AARCH64_ACL_PRELU_HPP

miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/acl_softmax.hpp

@@ -0,0 +1,239 @@
+/*******************************************************************************
+* Copyright 2021-2022 Arm Ltd. and affiliates
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef CPU_AARCH64_ACL_SOFTMAX_HPP
+#define CPU_AARCH64_ACL_SOFTMAX_HPP
+
+#include "cpu/cpu_softmax_pd.hpp"
+
+#include "cpu/aarch64/acl_utils.hpp"
+
+namespace dnnl {
+namespace impl {
+namespace cpu {
+namespace aarch64 {
+
+struct acl_softmax_obj_t {
+    std::unique_ptr<arm_compute::IFunction> softmax;
+    arm_compute::Tensor src_tensor;
+    arm_compute::Tensor dst_tensor;
+};
+
+struct acl_softmax_conf_t {
+    arm_compute::TensorInfo src_info;
+    arm_compute::TensorInfo dst_info;
+    float beta;
+    int32_t axis;
+    bool is_logsoftmax;
+};
+
+struct acl_softmax_resource_t : public resource_t {
+    acl_softmax_resource_t()
+        : acl_obj_(utils::make_unique<acl_softmax_obj_t>()) {}
+
+    status_t configure(const acl_softmax_conf_t &asp) {
+        if (!acl_obj_) return status::out_of_memory;
+
+        // Init Compute Library tensors based on info from descriptor
+        acl_obj_->src_tensor.allocator()->init(asp.src_info);
+        acl_obj_->dst_tensor.allocator()->init(asp.dst_info);
+
+        if (asp.is_logsoftmax) {
+            auto logsoftmax
+                    = std::make_unique<arm_compute::NELogSoftmaxLayer>();
+            // clang-format off
+            logsoftmax->configure(
+                &acl_obj_->src_tensor,
+                &acl_obj_->dst_tensor,
+                asp.beta,
+                asp.axis);
+            // clang-format on
+            acl_obj_->softmax = std::move(logsoftmax);
+        } else {
+            auto softmax = std::make_unique<arm_compute::NESoftmaxLayer>();
+            // clang-format off
+            softmax->configure(
+                &acl_obj_->src_tensor,
+                &acl_obj_->dst_tensor,
+                asp.beta,
+                asp.axis);
+            // clang-format on
+            acl_obj_->softmax = std::move(softmax);
+        }
+
+        return status::success;
+    }
+
+    acl_softmax_obj_t &get_acl_obj() const { return *acl_obj_; }
+
+    DNNL_DISALLOW_COPY_AND_ASSIGN(acl_softmax_resource_t);
+
+private:
+    std::unique_ptr<acl_softmax_obj_t> acl_obj_;
+}; // acl_softmax_resource_t
+
+struct acl_softmax_fwd_t : public primitive_t {
+    struct pd_t : public cpu_softmax_fwd_pd_t {
+        using cpu_softmax_fwd_pd_t::cpu_softmax_fwd_pd_t;
+
+        DECLARE_COMMON_PD_T("acl", acl_softmax_fwd_t);
+
+        status_t init(engine_t *engine) {
+
+            bool ok = is_fwd()
+                    // ACL only supports matching src/dst data types
+                    && src_md()->data_type == dst_md()->data_type
+                    && utils::one_of(
+                            src_md()->data_type, data_type::f32, data_type::f16)
+                    && attr()->has_default_values()
+                    && set_default_formats() == status::success;
+            if (!ok) return status::unimplemented;
+
+            // Get memory desc to find sizes and dims
+            const memory_desc_wrapper src_d(src_md());
+            const data_type_t data_type = src_d.data_type();
+
+            // ACL only supports plain tensors, can be permuted but not blocked
+            if (!src_d.is_plain()) return status::unimplemented;
+
+            // Guards against a 0-sized dimension
+            if (src_d.has_zero_dim()) return status::unimplemented;
+
+            // No scaling
+            asp_.beta = 1;
+
+            asp_.is_logsoftmax = is_logsoftmax();
+
+            // The strides give us the in memory inner size
+            dim_t inner_size_ = src_d.blocking_desc().strides[axis()];
+
+            dim_t axis_size_ = axis_size();
+
+            // The outer size is any left-over dimensions not inner or on the axis
+            dim_t outer_size_ = src_d.nelems() / (inner_size_ * axis_size_);
+
+            // In this context, NHWC tells ACL that the logical and physical
+            // dimensions are the same
+            arm_compute::DataLayout acl_layout = arm_compute::DataLayout::NHWC;
+
+            const arm_compute::DataType acl_data_t
+                    = acl_utils::get_acl_data_t(data_type);
+
+            const int threads = dnnl_get_max_threads();
+            if (inner_size_ == 1) {
+                // A rough empirical heuristic created by fitting a polynomial
+                // of the tensor sizes and thread count to the run time of the
+                // ref and ACL softmax. This variable is greater than zero when
+                // ref is faster, and less than zero when ACL is faster. We can
+                // interpret the constant term as the constant overhead
+                // associated with calling the external library and the negative
+                // coefficient on total_size as ACL being faster at processing
+                // each element
+                double acl_ref_performance_diff = 1 + 0.005 * outer_size_
+                        - 0.0027 * axis_size_
+                                * std::ceil(double(outer_size_) / threads);
+                if (threads > 1 || outer_size_ > 1) {
+                    // Using threads within ACL adds another constant overhead
+                    acl_ref_performance_diff += 17;
+                }
+                if (acl_ref_performance_diff > 0) return status::unimplemented;
+
+                // If the inner size is 1, we can get rid of the dimension.
+                // This stops ACL doing a unnecessary permute
+                arm_compute::TensorShape acl_tensor_shape
+                        = arm_compute::TensorShape(axis_size_, outer_size_);
+                asp_.axis = 0;
+
+                asp_.src_info = arm_compute::TensorInfo(
+                        acl_tensor_shape, 1, acl_data_t, acl_layout);
+                asp_.dst_info = arm_compute::TensorInfo(
+                        acl_tensor_shape, 1, acl_data_t, acl_layout);
+            } else {
+                // A rough empirical heuristic, see comment above
+                // The only difference here is that ACL does a reorder, and so
+                // is considerably better
+                double acl_ref_performance_diff = 1 + 0.005 * outer_size_
+                        - 0.01 * inner_size_ * axis_size_
+                                * std::ceil(double(outer_size_) / threads);
+                if (threads > 1 || outer_size_ > 1) {
+                    // Using threads within ACL adds another constant overhead
+                    acl_ref_performance_diff += 17;
+                }
+
+                if (acl_ref_performance_diff > 0) return status::unimplemented;
+
+                // Irrespective of the input dimensions, we construct a tensor
+                // with dimensions such that softmax can be applied over the
+                // middle axis (1), with the correct stride and vector length.
+                arm_compute::TensorShape acl_tensor_shape
+                        = arm_compute::TensorShape(
+                                inner_size_, axis_size_, outer_size_);
+                asp_.axis = 1;
+
+                asp_.src_info = arm_compute::TensorInfo(
+                        acl_tensor_shape, 1, acl_data_t, acl_layout);
+                asp_.dst_info = arm_compute::TensorInfo(
+                        acl_tensor_shape, 1, acl_data_t, acl_layout);
+            }
+
+            // Validate manually to check for return status
+            if (asp_.is_logsoftmax) {
+                ACL_CHECK_VALID(arm_compute::NELogSoftmaxLayer::validate(
+                        &asp_.src_info, &asp_.dst_info, asp_.beta, asp_.axis));
+            } else {
+                ACL_CHECK_VALID(arm_compute::NESoftmaxLayer::validate(
+                        &asp_.src_info, &asp_.dst_info, asp_.beta, asp_.axis));
+            }
+
+            return status::success;
+        }
+
+        acl_softmax_conf_t asp_;
+    }; // pd_t
+
+    acl_softmax_fwd_t(const pd_t *apd) : primitive_t(apd) {}
+
+    status_t create_resource(
+            engine_t *engine, resource_mapper_t &mapper) const override {
+        if (mapper.has_resource(this)) return status::success;
+
+        auto r = utils::make_unique<acl_softmax_resource_t>();
+        if (!r) return status::out_of_memory;
+
+        // Configure the resource based on information from primitive descriptor
+        auto st = r->configure(pd()->asp_);
+        if (st == status::success) { mapper.add(this, std::move(r)); }
+
+        return st;
+    }
+
+    status_t execute(const exec_ctx_t &ctx) const override {
+        return execute_forward(ctx);
+    }
+
+private:
+    // To guard the const execute_forward, the mutex must be 'mutable'
+    mutable std::mutex mtx;
+    status_t execute_forward(const exec_ctx_t &ctx) const;
+    const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); }
+}; // acl_softmax_fwd_t
+
+} // namespace aarch64
+} // namespace cpu
+} // namespace impl
+} // namespace dnnl
+
+#endif

miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/acl_thread.hpp

@@ -0,0 +1,57 @@
+/*******************************************************************************
+* Copyright 2022-2023 Arm Ltd. and affiliates
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef CPU_AARCH64_ACL_THREAD_HPP
+#define CPU_AARCH64_ACL_THREAD_HPP
+
+#include "common/dnnl_thread.hpp"
+#include "common/verbose.hpp"
+
+#include "arm_compute/runtime/Scheduler.h"
+
+namespace dnnl {
+namespace impl {
+namespace cpu {
+namespace aarch64 {
+
+namespace acl_thread_utils {
+
+#if DNNL_CPU_THREADING_RUNTIME == DNNL_RUNTIME_OMP
+// Number of threads in Compute Library is set by OMP_NUM_THREADS
+// dnnl_get_max_threads() == OMP_NUM_THREADS
+void acl_thread_bind();
+// Swap BenchmarkScheduler for default ACL scheduler builds (i.e. CPPScheduler, OMPScheduler)
+// for DNNL_VERBOSE=profile,profile_externals
+void acl_set_benchmark_scheduler_default();
+#endif
+
+#if DNNL_CPU_THREADING_RUNTIME == DNNL_RUNTIME_THREADPOOL
+// Retrieve threadpool size during primitive execution and set ThreadpoolScheduler num_threads
+void acl_set_tp_scheduler();
+void acl_set_threadpool_num_threads();
+// Swap BenchmarkScheduler for custom scheduler builds (i.e. ThreadPoolScheduler) for DNNL_VERBOSE=profile,profile_externals
+void acl_set_tp_benchmark_scheduler();
+#endif
+// Set threading for ACL
+void set_acl_threading();
+} // namespace acl_thread_utils
+
+} // namespace aarch64
+} // namespace cpu
+} // namespace impl
+} // namespace dnnl
+
+#endif // CPU_AARCH64_ACL_THREAD_HPP

miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/acl_threadpool_scheduler.hpp

@@ -0,0 +1,68 @@
+/*******************************************************************************
+* Copyright 2022 Arm Ltd. and affiliates
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef CPU_AARCH64_ACL_THREADPOOL_SCHEDULER_HPP
+#define CPU_AARCH64_ACL_THREADPOOL_SCHEDULER_HPP
+
+#include "oneapi/dnnl/dnnl_config.h"
+
+#if DNNL_CPU_THREADING_RUNTIME == DNNL_RUNTIME_THREADPOOL
+
+#include "arm_compute/runtime/IScheduler.h"
+#include "support/Mutex.h"
+
+namespace dnnl {
+namespace impl {
+namespace cpu {
+namespace aarch64 {
+
+class ThreadpoolScheduler final : public arm_compute::IScheduler {
+public:
+    ThreadpoolScheduler();
+    ~ThreadpoolScheduler();
+
+    /// Sets the number of threads the scheduler will use to run the kernels.
+    void set_num_threads(unsigned int num_threads) override;
+    /// Returns the number of threads that the ThreadpoolScheduler has in its pool.
+    unsigned int num_threads() const override;
+
+    /// Multithread the execution of the passed kernel if possible.
+    void schedule(arm_compute::ICPPKernel *kernel,
+            const arm_compute::IScheduler::Hints &hints) override;
+
+    /// Multithread the execution of the passed kernel if possible.
+    void schedule_op(arm_compute::ICPPKernel *kernel,
+            const arm_compute::IScheduler::Hints &hints,
+            const arm_compute::Window &window,
+            arm_compute::ITensorPack &tensors) override;
+
+protected:
+    /// Execute workloads in parallel using num_threads
+    void run_workloads(std::vector<Workload> &workloads) override;
+
+private:
+    uint _num_threads {};
+    arm_compute::Mutex _run_workloads_mutex {};
+};
+
+} // namespace aarch64
+} // namespace cpu
+} // namespace impl
+} // namespace dnnl
+
+#endif // CPU_AARCH64_ACL_THREADPOOL_SCHEDULER_HPP
+
+#endif // DNNL_CPU_THREADING_RUNTIME == DNNL_RUNTIME_THREADPOOL

miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/acl_utils.hpp

@@ -0,0 +1,132 @@
+/*******************************************************************************
+* Copyright 2021-2023 Arm Ltd. and affiliates
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef CPU_AARCH64_ACL_UTILS_HPP
+#define CPU_AARCH64_ACL_UTILS_HPP
+
+#include <mutex>
+
+#include "oneapi/dnnl/dnnl_types.h"
+
+#include "common/dnnl_thread.hpp"
+#include "common/memory_tracking.hpp"
+#include "common/primitive.hpp"
+#include "common/resource.hpp"
+#include "common/utils.hpp"
+
+#include "arm_compute/runtime/NEON/NEFunctions.h"
+#include "arm_compute/runtime/Scheduler.h"
+
+namespace dnnl {
+namespace impl {
+namespace cpu {
+namespace aarch64 {
+
+namespace acl_utils {
+
+arm_compute::DataType get_acl_data_t(
+        const dnnl_data_type_t dt, const bool is_quantized = false);
+
+// Convert alg_kind_t, alpha and beta into an ACL ActivationLayerInfo. Will
+// return unimplemented and a disabled ActivationLayerInfo if the conversion
+// fails
+status_t convert_to_acl_act(alg_kind_t eltwise_alg, float alpha, float beta,
+        arm_compute::ActivationLayerInfo &act_info);
+
+// Convert an eltwise_desc_t into an ACL ActivationLayerInfo. Will return
+// unimplemented and a disabled ActivationLayerInfo if the conversion fails
+status_t convert_to_acl_act(
+        const eltwise_desc_t &ed, arm_compute::ActivationLayerInfo &act_info);
+
+// Convert an eltwise post op into an ACL ActivationLayerInfo. Will return
+// unimplemented and a disabled ActivationLayerInfo if the conversion fails
+status_t convert_to_acl_act(const post_ops_t::entry_t::eltwise_t &elt,
+        arm_compute::ActivationLayerInfo &act_info);
+
+// Convert a memory desc to an arm_compute::TensorInfo. Note that memory desc
+// must be blocking format, plain, dense and have no zero dimensions.
+status_t tensor_info(arm_compute::TensorInfo &info, const memory_desc_t &md);
+status_t tensor_info(
+        arm_compute::TensorInfo &info, const memory_desc_wrapper &md);
+
+// Insert a dimension of size 1 at the index dim_i of TensorInfo
+status_t insert_singleton_dimension(arm_compute::TensorInfo &ti, size_t dim_i);
+
+// Reorder the logical dimensions of the memory descriptors (mds) by stride so
+// that accessing the tensor elements in the natural order is dense. Note, this
+// does not reorder the data, it just reorders the logical indices. The
+// permutation is common to all mds, so the function returns when it cannot find
+// a dimension with a common smallest stride. Returns the number of dimensions
+// that we managed to reorder to be dense.
+int reorder_dimensions_by_stride(std::vector<memory_desc_t *> permuted_mds,
+        std::vector<const memory_desc_t *> mds);
+
+// Reorder a memory_desc_t and set the strides on a arm_compute::TensorInfo to
+// match an arm_compute::WeightFormat. You are required to specify how various
+// logical dimensions in oneDNN correspond to logical dimensions in arm_compute.
+// info  TensorInfo where the strides will be changed to match the reordering
+// md    memory descriptor where the stride and padded dimensions will be
+//       changed or reordering
+// wf    Describes the memory format/layout of the weights
+// I_dim The logical dimension of md corresponding to the input channel of
+//       a convolution or the K dimension in a matmul
+// O_dim The logical dimension of md corresponding to the output channel of a
+//       convolution or the N dimension in a matmul
+// spatial_dims The logical dimensions of md corresponding to the spatial
+//              dimensions of the weights (H, W, D for example). These will be
+//              the next densest after the inner blocks and the input channel.
+// batch_dims The logical dimensions of md related to the batch in a batched
+//            matmul, ordered from innermost to outermost. ACL calls these
+//            the multi_stride_b. These will become the outermost (least dense)
+//            dimensions and will be collapsed.
+void reorder_to_weight_format(arm_compute::TensorInfo &info, memory_desc_t &md,
+        arm_compute::WeightFormat wf, dim_t I_dim, dim_t O_dim,
+        std::vector<dim_t> spatial_dims, std::vector<dim_t> batch_dims = {});
+
+// Logs a custom 'info' line describing an unsupported case
+#define LOG_ACL_UNSUPPORTED(msg) \
+    do { \
+        if (verbose_has_create_dispatch()) \
+            printf("onednn_verbose,cpu,acl,unsupported: %s\n", (msg)); \
+    } while (0)
+
+// Returns unimplemented if error code x is NOT OK
+#define ACL_CHECK_VALID(x) \
+    do { \
+        arm_compute::Status s = x; \
+        if (s.error_code() != arm_compute::ErrorCode::OK) { \
+            LOG_ACL_UNSUPPORTED(s.error_description().c_str()); \
+            return dnnl::impl::status::unimplemented; \
+        } \
+    } while (0)
+
+// Returns unimplemented on condition x == true
+#define ACL_CHECK_SUPPORT(x, msg) \
+    do { \
+        if (x) { \
+            LOG_ACL_UNSUPPORTED(msg); \
+            return dnnl::impl::status::unimplemented; \
+        } \
+    } while (0)
+
+} // namespace acl_utils
+
+} // namespace aarch64
+} // namespace cpu
+} // namespace impl
+} // namespace dnnl
+
+#endif // CPU_AARCH64_ACL_UTILS_HPP

miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/cpu_barrier.hpp

@@ -0,0 +1,84 @@
+/*******************************************************************************
+* Copyright 2020-2021 Intel Corporation
+* Copyright 2020-2021 FUJITSU LIMITED
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef CPU_AARCH64_CPU_BARRIER_HPP
+#define CPU_AARCH64_CPU_BARRIER_HPP
+
+#include <assert.h>
+
+#include "common/utils.hpp"
+#include "cpu/aarch64/jit_generator.hpp"
+
+namespace dnnl {
+namespace impl {
+namespace cpu {
+namespace aarch64 {
+
+namespace simple_barrier {
+
+#define CTX_ALIGNMENT 4096
+
+STRUCT_ALIGN(
+        CTX_ALIGNMENT, struct ctx_t {
+            enum { CACHE_LINE_SIZE = 256 };
+            volatile size_t ctr;
+            char pad1[CACHE_LINE_SIZE - 1 * sizeof(size_t)];
+            volatile size_t sense;
+            char pad2[CACHE_LINE_SIZE - 1 * sizeof(size_t)];
+        });
+
+/* TODO: remove ctx_64_t once batch normalization switches to barrier-less
+ * implementation.
+ * Different alignments of context structure affect performance differently for
+ * convolution and batch normalization. Convolution performance becomes more
+ * stable with page alignment compared to cache line size alignment.
+ * Batch normalization (that creates C / simd_w barriers) degrades with page
+ * alignment due to significant overhead of ctx_init in case of mb=1. */
+STRUCT_ALIGN(
+        256, struct ctx_64_t {
+            enum { CACHE_LINE_SIZE = 256 };
+            volatile size_t ctr;
+            char pad1[CACHE_LINE_SIZE - 1 * sizeof(size_t)];
+            volatile size_t sense;
+            char pad2[CACHE_LINE_SIZE - 1 * sizeof(size_t)];
+        });
+
+template <typename ctx_t>
+inline void ctx_init(ctx_t *ctx) {
+    *ctx = utils::zero<ctx_t>();
+}
+void barrier(ctx_t *ctx, int nthr);
+
+/** injects actual barrier implementation into another jitted code
+ * @params:
+ *   code      -- jit_generator object where the barrier is to be injected
+ *   reg_ctx   -- read-only register with pointer to the barrier context
+ *   reg_nnthr -- read-only register with the # of synchronizing threads
+ */
+void generate(jit_generator &code, Xbyak_aarch64::XReg reg_ctx,
+        Xbyak_aarch64::XReg reg_nthr, bool usedAsFunc = false);
+
+} // namespace simple_barrier
+
+} // namespace aarch64
+} // namespace cpu
+} // namespace impl
+} // namespace dnnl
+
+#endif
+
+// vim: et ts=4 sw=4 cindent cino+=l0,\:4,N-s

miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/cpu_isa_traits.hpp

@@ -0,0 +1,237 @@
+/*******************************************************************************
+* Copyright 2018-2023 Intel Corporation
+* Copyright 2020-2023 FUJITSU LIMITED
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef CPU_AARCH64_CPU_ISA_TRAITS_HPP
+#define CPU_AARCH64_CPU_ISA_TRAITS_HPP
+
+#include <type_traits>
+
+#include "dnnl_types.h"
+
+#include "common/dnnl_thread.hpp"
+#include "common/utils.hpp"
+
+/* in order to make selinux happy memory that would be marked with X-bit should
+ * be obtained with mmap */
+#if !defined(_WIN32)
+#define XBYAK_USE_MMAP_ALLOCATOR
+#endif
+
+#include "cpu/aarch64/xbyak_aarch64/xbyak_aarch64/xbyak_aarch64.h"
+#include "cpu/aarch64/xbyak_aarch64/xbyak_aarch64/xbyak_aarch64_util.h"
+
+namespace dnnl {
+namespace impl {
+namespace cpu {
+namespace aarch64 {
+
+/* The following enum is temporal implementation.
+   It should be made in dnnl_types.h,
+   but an RFC is requird to modify dnnl_types.h.
+   The following values are used with
+   static_cast<dnnl_cpu_isa_t>, the same values
+   defined in dnnl_cpu_isa_t are temporaly used. */
+/// CPU instruction set flags
+enum {
+    /// AARCH64 Advanced SIMD & floating-point
+    dnnl_cpu_isa_asimd = 0x1,
+    /// AARCH64 SVE 128 bits
+    dnnl_cpu_isa_sve_128 = 0x3,
+    /// AARCH64 SVE 256 bits
+    dnnl_cpu_isa_sve_256 = 0x7,
+    /// AARCH64 SVE 384 bits
+    dnnl_cpu_isa_sve_384 = 0xf,
+    /// AARCH64 SVE 512 bits
+    dnnl_cpu_isa_sve_512 = 0x27,
+};
+
+enum cpu_isa_bit_t : unsigned {
+    asimd_bit = 1u << 0,
+    sve_128_bit = 1u << 1,
+    sve_256_bit = 1u << 2,
+    sve_384_bit = 1u << 3,
+    sve_512_bit = 1u << 4,
+};
+
+enum cpu_isa_t : unsigned {
+    isa_undef = 0u,
+    asimd = asimd_bit,
+    sve_128 = sve_128_bit | asimd,
+    sve_256 = sve_256_bit | sve_128,
+    sve_384 = sve_384_bit | sve_256,
+    sve_512 = sve_512_bit | sve_384,
+    isa_all = ~0u,
+};
+
+enum class cpu_isa_cmp_t {
+    // List of infix comparison relations between two cpu_isa_t
+    // where we take isa_1 and isa_2 to be two cpu_isa_t instances.
+
+    // isa_1 SUBSET isa_2 if all feature flags supported by isa_1
+    // are supported by isa_2 as well (equality allowed)
+    SUBSET,
+
+    // isa_1 SUPERSET isa_2 if all feature flags supported by isa_2
+    // are supported by isa_1 as well (equality allowed)
+    SUPERSET,
+
+    // Few more options that (depending upon need) can be enabled in future
+
+    // 1. PROPER_SUBSET: isa_1 SUBSET isa_2 and isa_1 != isa_2
+    // 2. PROPER_SUPERSET: isa_1 SUPERSET isa_2 and isa_1 != isa_2
+};
+
+const char *get_isa_info();
+
+cpu_isa_t get_max_cpu_isa();
+cpu_isa_t DNNL_API get_max_cpu_isa_mask(bool soft = false);
+status_t set_max_cpu_isa(dnnl_cpu_isa_t isa);
+dnnl_cpu_isa_t get_effective_cpu_isa();
+
+static inline bool compare_isa(
+        cpu_isa_t isa_1, cpu_isa_cmp_t cmp, cpu_isa_t isa_2) {
+    // By default, comparison between ISA ignores ISA specific hints
+    unsigned mask_1 = static_cast<unsigned>(isa_1);
+    unsigned mask_2 = static_cast<unsigned>(isa_2);
+    unsigned mask_common = mask_1 & mask_2;
+
+    switch (cmp) {
+        case cpu_isa_cmp_t::SUBSET: return mask_1 == mask_common;
+        case cpu_isa_cmp_t::SUPERSET: return mask_2 == mask_common;
+        default: assert(!"unsupported comparison of isa"); return false;
+    }
+}
+
+static inline bool is_subset(cpu_isa_t isa_1, cpu_isa_t isa_2) {
+    return compare_isa(isa_1, cpu_isa_cmp_t::SUBSET, isa_2);
+}
+
+static inline bool is_superset(cpu_isa_t isa_1, cpu_isa_t isa_2) {
+    return compare_isa(isa_1, cpu_isa_cmp_t::SUPERSET, isa_2);
+}
+
+template <cpu_isa_t>
+struct cpu_isa_traits {}; /* ::vlen -> 32 (for avx2) */
+
+template <>
+struct cpu_isa_traits<isa_all> {
+    static constexpr dnnl_cpu_isa_t user_option_val = dnnl_cpu_isa_default;
+    static constexpr const char *user_option_env = "default";
+};
+
+template <>
+struct cpu_isa_traits<asimd> {
+    typedef Xbyak_aarch64::VReg TReg;
+    typedef Xbyak_aarch64::VReg16B TRegB;
+    typedef Xbyak_aarch64::VReg8H TRegH;
+    typedef Xbyak_aarch64::VReg4S TRegS;
+    typedef Xbyak_aarch64::VReg2D TRegD;
+    static constexpr int vlen_shift = 4;
+    static constexpr int vlen = 16;
+    static constexpr int n_vregs = 32;
+    static constexpr dnnl_cpu_isa_t user_option_val
+            = static_cast<dnnl_cpu_isa_t>(dnnl_cpu_isa_asimd);
+    static constexpr const char *user_option_env = "advanced_simd";
+};
+
+#define CPU_ISA_SVE(bits, shift) \
+    template <> \
+    struct cpu_isa_traits<sve_##bits> { \
+        typedef Xbyak_aarch64::ZReg TReg; \
+        typedef Xbyak_aarch64::ZRegB TRegB; \
+        typedef Xbyak_aarch64::ZRegH TRegH; \
+        typedef Xbyak_aarch64::ZRegS TRegS; \
+        typedef Xbyak_aarch64::ZRegD TRegD; \
+        static constexpr int vlen_shift = shift; \
+        static constexpr int vlen = bits / 8; \
+        static constexpr int n_vregs = 32; \
+        static constexpr dnnl_cpu_isa_t user_option_val \
+                = static_cast<dnnl_cpu_isa_t>(dnnl_cpu_isa_sve_##bits); \
+        static constexpr const char *user_option_env = "sve_ ## bits"; \
+    };
+
+CPU_ISA_SVE(128, 4)
+CPU_ISA_SVE(256, 5)
+CPU_ISA_SVE(512, 6)
+#undef CPU_ISA_SVE
+
+inline const Xbyak_aarch64::util::Cpu &cpu() {
+    const static Xbyak_aarch64::util::Cpu cpu_;
+    return cpu_;
+}
+
+namespace {
+
+static inline bool mayiuse(const cpu_isa_t cpu_isa, bool soft = false) {
+    using namespace Xbyak_aarch64::util;
+
+    unsigned cpu_isa_mask = aarch64::get_max_cpu_isa_mask(soft);
+    if ((cpu_isa_mask & cpu_isa) != cpu_isa) return false;
+
+    switch (cpu_isa) {
+        case asimd: return cpu().has(XBYAK_AARCH64_HWCAP_ADVSIMD);
+        case sve_128:
+            return cpu().has(XBYAK_AARCH64_HWCAP_SVE)
+                    && cpu().getSveLen() >= SVE_128;
+        case sve_256:
+            return cpu().has(XBYAK_AARCH64_HWCAP_SVE)
+                    && cpu().getSveLen() >= SVE_256;
+        case sve_384:
+            return cpu().has(XBYAK_AARCH64_HWCAP_SVE)
+                    && cpu().getSveLen() >= SVE_384;
+        case sve_512:
+            return cpu().has(XBYAK_AARCH64_HWCAP_SVE)
+                    && cpu().getSveLen() >= SVE_512;
+        case isa_undef: return true;
+        case isa_all: return false;
+    }
+    return false;
+}
+
+static inline uint64_t get_sve_length() {
+    return cpu().getSveLen();
+}
+
+static inline bool mayiuse_atomic() {
+    using namespace Xbyak_aarch64::util;
+    return cpu().isAtomicSupported();
+}
+
+inline bool isa_has_bf16(cpu_isa_t isa) {
+    return false;
+}
+
+} // namespace
+
+/* whatever is required to generate string literals... */
+#include "common/z_magic.hpp"
+/* clang-format off */
+#define JIT_IMPL_NAME_HELPER(prefix, isa, suffix_if_any) \
+    ((isa) == isa_undef ? prefix STRINGIFY(any) : \
+    ((isa) == asimd ? prefix STRINGIFY(asimd) : \
+    ((isa) == sve_128 ? prefix STRINGIFY(sve_128) : \
+    ((isa) == sve_256 ? prefix STRINGIFY(sve_256) : \
+    ((isa) == sve_512 ? prefix STRINGIFY(sve_512) : \
+    prefix suffix_if_any)))))
+/* clang-format on */
+
+} // namespace aarch64
+} // namespace cpu
+} // namespace impl
+} // namespace dnnl
+
+#endif

miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/cpu_reducer.hpp

@@ -0,0 +1,357 @@
+/*******************************************************************************
+* Copyright 2020-2021 Intel Corporation
+* Copyright 2020-2021 FUJITSU LIMITED
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef CPU_AARCH64_CPU_REDUCER_HPP
+#define CPU_AARCH64_CPU_REDUCER_HPP
+
+#include <assert.h>
+
+#include "common/c_types_map.hpp"
+#include "common/dnnl_thread.hpp"
+#include "common/memory_tracking.hpp"
+#include "common/nstl.hpp"
+#include "common/type_helpers.hpp"
+#include "common/utils.hpp"
+#include "dnnl_types.h"
+
+#include "cpu/aarch64/cpu_barrier.hpp"
+
+namespace dnnl {
+namespace impl {
+namespace cpu {
+namespace aarch64 {
+
+/** class to perform balancing over 3D array
+ *
+ * Conceptually the reduction happens according to the picture below:
+ *
+ *  <--job_size->
+ *  +-----------+   +-----------+           +-----------+  ^
+ *  |           |   |           |           |           |  |
+ *  |           |   |           |           |           |  |
+ *  |     1     |   |     2     |   . . .   |   njobs   |  | reduction_size
+ *  |           |   |           |           |           |  |
+ *  |           |   |           |           |           |  |
+ *  +-----------+   +-----------+           +-----------+  v
+ *
+ *    |   |   |       |   |   |               |   |   |
+ *    v   v   v       v   v   v               v   v   v
+ *  ===================================================== vertical reduction
+ *
+ *  +-----------+   +-----------+   . . .   +-----------+ result
+ *
+ * In a simple case the result must be contiguous in memory.
+ * @class cpu_reducer_t is an implementation.
+ *
+ * Threads are divided into groups. The groups are independent of each other.
+ * Each group may work on several jobs (the distribution is not uniform, since
+ * njobs might be not a multiple of groups). Threads within a group work on
+ * different parts of the reduction dimension. Thread 0 in each group is called
+ * master (@sa reduce_balancer_t::master()).
+ *
+ * If threading driver does not allow sync between sub-group of threads (e.g.
+ * TBB) the # of thread per group is enforced to be 1.
+ */
+struct reduce_balancer_t {
+    reduce_balancer_t() { init(1, 1, 1, 1, 0); } /* trivial balance */
+    reduce_balancer_t(int nthr, int job_size, int njobs, int reduction_size,
+            size_t max_buffer_size, bool lock_free = false) {
+        init(nthr, job_size, njobs, reduction_size, max_buffer_size, lock_free);
+    }
+
+    reduce_balancer_t &init(int nthr, int job_size, int njobs,
+            int reduction_size, size_t max_buffer_size,
+            bool lock_free = false) {
+        allow_nthr_in_group_ = lock_free ? true : dnnl_thr_syncable();
+        nthr_ = nthr;
+        job_size_ = job_size;
+        njobs_ = njobs;
+        reduction_size_ = reduction_size;
+        max_buffer_size_ = max_buffer_size;
+        balance();
+        return *this;
+    }
+
+    bool allow_nthr_in_group_;
+    int nthr_;
+    int job_size_, njobs_, reduction_size_;
+
+    int ngroups_; /** number of independent work (thread) groups */
+    int nthr_per_group_; /** number of threads within a single work group */
+    int njobs_per_group_ub_; /** the max # of jobs within a work group */
+
+    bool master(int ithr) const { return id_in_group(ithr) == 0; }
+    bool idle(int ithr) const { return ithr >= nthr_per_group_ * ngroups_; }
+
+    int group_id(int ithr) const { return ithr / nthr_per_group_; }
+    int id_in_group(int ithr) const { return ithr % nthr_per_group_; }
+
+    int grp_njobs(int grp) const {
+        if (grp >= ngroups_) return 0;
+        return njobs_ / ngroups_ + (grp < njobs_ % ngroups_);
+    }
+    int grp_job_off(int grp) const {
+        if (grp >= ngroups_) return njobs_;
+        return njobs_ / ngroups_ * grp + nstl::min(grp, njobs_ % ngroups_);
+    }
+
+    int ithr_njobs(int ithr) const { return grp_njobs(group_id(ithr)); }
+    int ithr_job_off(int ithr) const { return grp_job_off(group_id(ithr)); }
+
+private:
+    size_t max_buffer_size_;
+    void balance();
+};
+
+/** forward declaration of reduce driver */
+template <impl::data_type_t data_type>
+struct reducer_2d_driver_t;
+
+/** class to perform a reduction over 3D array
+ *
+ * Balancing is based on @class reduce_balancer_t.
+ * Restrictions: the result of the reduction must be contiguous in memory. *
+ * The reduction happens according to the picture below (once more):
+ *
+ *  <--job_size->
+ *  +-----------+   +-----------+           +-----------+  ^
+ *  |           |   |           |           |           |  |
+ *  |           |   |           |           |           |  |
+ *  |     1     |   |     2     |   . . .   |   njobs   |  | reduction_size
+ *  |           |   |           |           |           |  |
+ *  |           |   |           |           |           |  |
+ *  +-----------+   +-----------+           +-----------+  v
+ *
+ *    |   |   |       |   |   |               |   |   |
+ *    v   v   v       v   v   v               v   v   v
+ *  ===================================================== vertical reduction
+ *
+ *  +-----------+   +-----------+   . . .   +-----------+ (contiguous) result
+ *
+ * An example how work might be shared is shown below.
+ *
+ * In this example group 0 owns 2 (independent) jobs -- 2 big squares.
+ * The number of threads per group is also 2 (thread 0 of group 0 and thread 1
+ * of group 0). Master threads (i.e. threads with id 0 in corresponding group)
+ * from each group put the partial result directly into destination memory,
+ * while all the other threads with-in the group use workspace (on the picture
+ * the only thread 1). Once intermediate results obtained each group reduces
+ * corresponding part (own jobs) to the destination memory.
+ *
+ *  <-------   group 0   ------->
+ *
+ *  +-----------+   +-----------+  ^
+ *  |           |   |           |  | thread 0 of  reduces to the dest-memory
+ *  |           |   |           |  | group 0      +-----------+   +-----------+
+ *  |- - - - - -|   |- - - - - -|  X
+ *  |           |   |           |  | thread 1 of  reduces to workspace[tid=1]:
+ *  |           |   |           |  | group 0      +-----------+   +-----------+
+ *  +-----------+   +-----------+  v
+ *                                                  |   |   |       |   |   |
+ *                                                  v   v   v       v   v   v
+ *                                   ((barrier))  =============================
+ *
+ *                                  dest-memory:  +-----------+   +-----------+
+ */
+template <impl::data_type_t data_type>
+struct cpu_reducer_t {
+    typedef typename prec_traits<data_type>::type data_t;
+
+    struct conf_t {
+        conf_t() = default;
+        conf_t &init(const reduce_balancer_t &balancer) {
+            balancer_ = balancer;
+            return *this;
+        }
+
+        void init_scratchpad(memory_tracking::registrar_t &scratchpad) const;
+
+        reduce_balancer_t balancer_;
+    };
+
+    status_t create_kernel();
+
+    cpu_reducer_t(const conf_t &conf);
+    ~cpu_reducer_t();
+
+    /** initializes reducer.
+     * Must be called from a single thread prior to actual usage */
+    void init(const memory_tracking::grantor_t &scratchpad) const {
+        if (balancer().nthr_per_group_ == 1 || !dnnl_thr_syncable()) return;
+
+        auto bctx = scratchpad.template get<simple_barrier::ctx_t>(
+                memory_tracking::names::key_reducer_space_bctx);
+        for (int i = 0; i < balancer().ngroups_; ++i)
+            simple_barrier::ctx_init(&bctx[i]);
+    }
+
+    /** for given thread returns the pointer where to put partial results.
+     * Reduction destination @p dst must be provided as well (master threads
+     * from each group will use it for partial result to reduce memory
+     * pressure).
+     *
+     * @note: job offset is already applied by get_local_ptr(), which means all
+     *        threads should start writing from the very beginning of returned
+     *        address.
+     */
+    data_t *get_local_ptr(int ithr, data_t *dst,
+            const memory_tracking::grantor_t &scratchpad) const;
+
+    /** performs the reduction with built-in synchronization. */
+    void reduce(int ithr, data_t *dst,
+            const memory_tracking::grantor_t &scratchpad) const {
+        bool redundant_reduction
+                = balancer().nthr_per_group_ == 1 || balancer().idle(ithr);
+        if (redundant_reduction) return;
+
+        auto bctx = scratchpad.template get<simple_barrier::ctx_t>(
+                memory_tracking::names::key_reducer_space_bctx);
+        simple_barrier::barrier(
+                &bctx[balancer().group_id(ithr)], balancer().nthr_per_group_);
+
+        reduce_nolock(ithr, dst, scratchpad);
+    }
+
+    void reduce_nolock(int ithr, data_t *dst,
+            const memory_tracking::grantor_t &scratchpad) const;
+
+    const reduce_balancer_t &balancer() const { return conf_.balancer_; }
+
+private:
+    static size_t space_per_thread(const reduce_balancer_t &balancer) {
+        return balancer.njobs_per_group_ub_ * balancer.job_size_;
+    }
+
+    /* The scratchpad is organized as follows:
+     *
+     * data_t space[nthr_][njobs_per_group_ub_][jobs_size_];
+     * simple_barrier::ctx_t barriers[groups_]; */
+
+    const conf_t conf_;
+    reducer_2d_driver_t<data_type> *drv_;
+
+    DNNL_DISALLOW_COPY_AND_ASSIGN(cpu_reducer_t);
+};
+
+template <impl::data_type_t data_type>
+struct cpu_reducer_2d_t {
+    typedef typename prec_traits<data_type>::type data_t;
+
+    struct conf_t {
+        conf_t() = default;
+        conf_t &init(const reduce_balancer_t &balancer, int job_size_x,
+                int job_size_y, int x_block, int dst_x, int dst_y) {
+            balancer_ = balancer;
+            job_size_x_ = job_size_x;
+            job_size_y_ = job_size_y;
+            x_block_ = x_block;
+            dst_x_ = dst_x;
+            dst_y_ = dst_y;
+            return *this;
+        }
+
+        void init_scratchpad(memory_tracking::registrar_t &scratchpad) const;
+
+        reduce_balancer_t balancer_;
+        int job_size_x_, job_size_y_, x_block_, dst_x_, dst_y_;
+    };
+
+    status_t create_kernel();
+
+    cpu_reducer_2d_t(const conf_t &conf);
+    ~cpu_reducer_2d_t();
+
+    /** initializes reducer.
+     * Must be called from a single thread prior to actual usage */
+    void init(const memory_tracking::grantor_t &scratchpad) const {
+        if (balancer().nthr_per_group_ == 1 || !dnnl_thr_syncable()) return;
+
+        auto bctx = scratchpad.template get<simple_barrier::ctx_t>(
+                memory_tracking::names::key_reducer_space_bctx);
+        for (int i = 0; i < balancer().ngroups_; ++i)
+            simple_barrier::ctx_init(&bctx[i]);
+    }
+
+    /** for given thread returns the pointer where to put partial results */
+    data_t *get_local_ptr(
+            int ithr, const memory_tracking::grantor_t &scratchpad) const;
+
+    /** performs the reduction with built-in synchronization. */
+    void reduce(int ithr, data_t *dst,
+            const memory_tracking::grantor_t &scratchpad) const {
+        bool redundant_reduction
+                = balancer().nthr_per_group_ == 1 || balancer().idle(ithr);
+        if (redundant_reduction) return;
+
+        auto bctx = scratchpad.template get<simple_barrier::ctx_t>(
+                memory_tracking::names::key_reducer_space_bctx);
+        simple_barrier::barrier(
+                &bctx[balancer().group_id(ithr)], balancer().nthr_per_group_);
+
+        reduce_nolock(ithr, dst, scratchpad);
+    }
+
+    void reduce_nolock(int ithr, data_t *dst,
+            const memory_tracking::grantor_t &scratchpad) const;
+
+    const reduce_balancer_t &balancer() const { return conf_.balancer_; }
+
+private:
+    static size_t space_per_thread(const reduce_balancer_t &balancer) {
+        return balancer.njobs_per_group_ub_ * balancer.job_size_;
+    }
+
+    /* The scratchpad is organized as follows:
+     *
+     * data_t space[nthr_][njobs_per_group_ub_][jobs_size_];
+     * simple_barrier::ctx_t barriers[groups_]; */
+
+    const conf_t conf_;
+    reducer_2d_driver_t<data_type> *drv_;
+
+    int choose_x_blocking(int nx, int ny, int nthr_per_grp) const;
+    void reduce_block(const data_t *space_base, data_t *dst, int job,
+            int start_y, int start_x, int ny_start, int nx_start, int ny_step,
+            int nx_step) const;
+
+    DNNL_DISALLOW_COPY_AND_ASSIGN(cpu_reducer_2d_t);
+};
+
+/** simple 1d accumulator: y[:] += x[:] */
+template <impl::data_type_t data_type>
+struct cpu_accumulator_1d_t {
+    typedef typename prec_traits<data_type>::type data_t;
+
+    cpu_accumulator_1d_t();
+    ~cpu_accumulator_1d_t();
+    void accumulate(data_t *dst, const data_t *src, size_t size);
+
+    status_t create_kernel();
+
+    reducer_2d_driver_t<data_type> *drv_;
+
+    DNNL_DISALLOW_COPY_AND_ASSIGN(cpu_accumulator_1d_t);
+};
+
+} // namespace aarch64
+} // namespace cpu
+} // namespace impl
+} // namespace dnnl
+
+#endif
+
+// vim: et ts=4 sw=4 cindent cino+=l0,\:4,N-s

miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/injectors/injector_utils.hpp

@@ -0,0 +1,113 @@
+/*******************************************************************************
+* Copyright 2020-2022 Intel Corporation
+* Copyright 2021-2022 FUJITSU LIMITED
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+#ifndef CPU_AARCH64_JIT_INJECTOR_UTILS_HPP
+#define CPU_AARCH64_JIT_INJECTOR_UTILS_HPP
+
+#include <array>
+#include <cstddef>
+#include <set>
+#include <stack>
+
+#include "cpu/aarch64/jit_generator.hpp"
+
+namespace dnnl {
+namespace impl {
+namespace cpu {
+namespace aarch64 {
+namespace injector_utils {
+
+using vmm_index_set_t = typename std::set<size_t>;
+using vmm_index_set_iterator_t = typename std::set<size_t>::iterator;
+template <cpu_isa_t isa>
+struct vmm_size_t;
+
+template <>
+struct vmm_size_t<sve_512> {
+    static constexpr std::size_t bytes = 64u;
+};
+
+/*
+template <>
+struct vmm_size_t<sve_256> {
+    static constexpr std::size_t bytes = 32u;
+};
+
+template <>
+struct vmm_size_t<sve_128> {
+    static constexpr std::size_t bytes = 16u;
+    };*/
+
+enum class layout_t { ncsp, c_blocked, nspc, cspn, unsupported };
+
+inline layout_t get_layout_type(const memory_desc_wrapper &dst_d) {
+    const auto strides = dst_d.blocking_desc().strides;
+    if (!dst_d.is_plain()) return layout_t::c_blocked;
+    if (strides[0] >= strides[1]
+            && IMPLICATION(dst_d.ndims() >= 3, strides[1] >= strides[2]))
+        return layout_t::ncsp;
+    if (strides[1] == 1) return layout_t::nspc;
+    if (strides[0] == 1) return layout_t::cspn;
+    return layout_t::unsupported;
+}
+
+/*
+ * Scope guard for general purpose register and vector registers preservation.
+ * Pushes registers to stack during construction and pops during destruction.
+ */
+template <cpu_isa_t isa>
+class register_preserve_guard_t {
+
+public:
+    register_preserve_guard_t(jit_generator *host,
+            std::initializer_list<Xbyak_aarch64::XReg> reg64_to_preserve,
+            std::initializer_list<Xbyak_aarch64::VReg> vmm_to_preserve = {});
+    register_preserve_guard_t(register_preserve_guard_t &&other) = default;
+    register_preserve_guard_t &operator=(register_preserve_guard_t &&other)
+            = default;
+    DNNL_DISALLOW_COPY_AND_ASSIGN(register_preserve_guard_t);
+    ~register_preserve_guard_t();
+    size_t calc_vmm_to_preserve_size_bytes(
+            const std::initializer_list<Xbyak_aarch64::VReg> &vmm_to_preserve)
+            const;
+    size_t stack_space_occupied() const;
+
+private:
+    jit_generator *host_;
+    std::stack<Xbyak_aarch64::XReg> reg64_stack_;
+    std::stack<Xbyak_aarch64::VReg> vmm_stack_;
+    const uint64_t cpu_sveLen_ = get_sve_length();
+    size_t vmm_to_preserve_size_bytes_;
+};
+
+template <cpu_isa_t isa>
+class conditional_register_preserve_guard_t
+    : public register_preserve_guard_t<isa> {
+public:
+    conditional_register_preserve_guard_t(bool condition_to_be_met,
+            jit_generator *host,
+            std::initializer_list<Xbyak_aarch64::XReg> reg64_to_preserve,
+            std::initializer_list<Xbyak_aarch64::VReg> vmm_to_preserve = {});
+    DNNL_DISALLOW_COPY_AND_ASSIGN(conditional_register_preserve_guard_t);
+};
+
+} // namespace injector_utils
+} // namespace aarch64
+} // namespace cpu
+} // namespace impl
+} // namespace dnnl
+
+#endif

miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/injectors/jit_uni_binary_injector.hpp

@@ -0,0 +1,631 @@
+/*******************************************************************************
+* Copyright 2020-2023 Intel Corporation
+* Copyright 2022-2023 FUJITSU LIMITED
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef CPU_AARCH64_JIT_UNI_BINARY_INJECTOR_HPP
+#define CPU_AARCH64_JIT_UNI_BINARY_INJECTOR_HPP
+
+#include <array>
+#include <cassert>
+#include <functional>
+#include <map>
+#include <utility>
+#include <vector>
+#include <unordered_set>
+
+#include "common/broadcast_strategy.hpp"
+#include "common/c_types_map.hpp"
+#include "common/primitive_attr.hpp"
+#include "common/primitive_exec_types.hpp"
+#include "cpu/aarch64/cpu_isa_traits.hpp"
+#include "cpu/aarch64/injectors/injector_utils.hpp"
+#include "cpu/aarch64/jit_generator.hpp"
+#include "cpu/binary_injector_utils.hpp"
+
+namespace dnnl {
+namespace impl {
+namespace cpu {
+namespace aarch64 {
+namespace binary_injector {
+using dnnl::impl::cpu::binary_injector_utils::prepare_binary_args;
+
+bool binary_args_matches_tag(format_tag_t tag, const post_ops_t &post_ops);
+
+bool binary_args_broadcast_supported(const post_ops_t &post_ops,
+        const memory_desc_wrapper &dst_d,
+        const bcast_set_t &supported_strategy_set);
+
+bool binary_args_tail_supported(const post_ops_t &post_ops,
+        const memory_desc_wrapper &dst_d, int vlen,
+        const bcast_set_t &supported_strategy_set);
+
+bool any_binary_postop_rhs_per_oc_broadcast(
+        const post_ops_t &post_ops, const memory_desc_wrapper &dst_d);
+bool any_binary_postop_rhs_per_oc_broadcast(const post_ops_t &post_ops,
+        const memory_desc_wrapper &dst_d,
+        const bcast_set_t &supported_strategy_set);
+
+bool all_binary_postop_rhs_per_oc_broadcast(const post_ops_t &post_ops,
+        const memory_desc_wrapper &dst_d,
+        const std::function<bool(const memory_desc_wrapper &)> &predicate);
+bool all_binary_postop_rhs_per_oc_broadcast(const post_ops_t &post_ops,
+        const memory_desc_wrapper &dst_d,
+        const bcast_set_t &supported_strategy_set,
+        const std::function<bool(const memory_desc_wrapper &)> &predicate);
+
+/*
+ * Represents params related to all binary post-ops right-hand side arguments
+ * (arg1) that don't change during jit_uni_binary_injector_t object lifetime
+ * and between compute_vector_range calls.
+ *
+ * @param rhs_dt_helper_vmm_idx - index of vmm helper used when loading data for
+ * calculations. Treated as hint from user. If inside compute_vector_range hint
+ * turns out to be invalid, it will be overwriten by register preserving logic inside
+ * binary injector.
+ * @param rhs_addr_reg - gpr register, used as the currently processed address of
+ * rhs tensor slice. Data of rhs(arg1) for the binary operation is loaded from address
+ * stored inside rhs_addr_reg.
+ * @param rhs_helper_reg - gpr register used as helper for calculations during data
+ * loading phase.
+ * @param rhs_addr_cache_reg - gpr register used for caching part of calculated
+ * offset, this register is always preserved.
+ * @param preserve_gpr_helpers - determines whether gpr registers specified above
+ * should be preserved (pushed to stack and poped back afterwords) between
+ * compute_vector_range calls.
+ * @param preserve_vmm_helper - determines whether vmm helper register specified
+ * above should be preserved between compute_vector_range calls.
+ * @param abi_param_offset - offset to rhs tensor from first binary post-op operation
+ * specified by user from runtime structure passed to kernel as abi param 1.
+ * @param dst_orig_offset - offset 0 to destination tensor
+ * @param dst_d - descriptor of destination tensor (result after applying all post-ops
+ * operations).
+ * @param tail_opmask - register with loaded by user mask, used in avx512 for load with
+ * tail handling.
+ * @param tail_size - size of processed tail in elements.
+ * @param use_exact_tail_scalar_bcast - in case of scalar broadcast user can disable
+ * loading data with tail, usually bcast through entire vector is faster (usually 1 instruction)
+ * vs. broadcasting limited by tail size (potentially several instructions). In case
+ * when user during storing ignores values from vmm above tail size, setting this option to
+ * false can result in better performance.
+ * @param reg_tail_size - register with loaded size of tail, used in sse41/avx/avx2
+ * for load with tail in runtime.
+ */
+struct rhs_arg_static_params_t {
+    rhs_arg_static_params_t(std::size_t rhs_dt_helper_vmm_idx,
+            const Xbyak_aarch64::XReg &rhs_addr_reg,
+            const Xbyak_aarch64::XReg &rhs_helper_reg,
+            const Xbyak_aarch64::XReg &rhs_addr_cache_reg,
+            bool preserve_gpr_helpers, bool preserve_vmm_helper,
+            std::size_t abi_param_offset, const memory_desc_wrapper &dst_d,
+            std::size_t tail_size = 0u,
+            bool use_exact_tail_scalar_bcast = false);
+    rhs_arg_static_params_t(std::size_t rhs_dt_helper_vmm_idx,
+            const Xbyak_aarch64::XReg &rhs_addr_reg,
+            const Xbyak_aarch64::XReg &rhs_helper_reg,
+            const Xbyak_aarch64::XReg &rhs_addr_cache_reg,
+            bool preserve_gpr_helpers, bool preserve_vmm_helper,
+            std::size_t abi_param_offset, std::size_t dst_orig_offset,
+            const memory_desc_wrapper &dst_d, std::size_t tail_size = 0u,
+            bool use_exact_tail_scalar_bcast = false);
+    rhs_arg_static_params_t(std::size_t rhs_dt_helper_vmm_idx,
+            const Xbyak_aarch64::XReg &rhs_addr_reg,
+            const Xbyak_aarch64::XReg &rhs_helper_reg,
+            const Xbyak_aarch64::XReg &rhs_addr_cache_reg,
+            bool preserve_gpr_helpers, bool preserve_vmm_helper,
+            std::size_t abi_param_offset, const memory_desc_wrapper &dst_d,
+            std::size_t tail_size, const Xbyak_aarch64::PReg &tail_opmask,
+            bool use_exact_tail_scalar_bcast);
+    rhs_arg_static_params_t(std::size_t rhs_dt_helper_vmm_idx,
+            const Xbyak_aarch64::XReg &rhs_addr_reg,
+            const Xbyak_aarch64::XReg &rhs_helper_reg,
+            const Xbyak_aarch64::XReg &rhs_addr_cache_reg,
+            bool preserve_gpr_helpers, bool preserve_vmm_helper,
+            std::size_t abi_param_offset, std::size_t dst_orig_offset,
+            const memory_desc_wrapper &dst_d, std::size_t tail_size,
+            const Xbyak_aarch64::PReg &tail_opmask,
+            bool use_exact_tail_scalar_bcast);
+    rhs_arg_static_params_t(std::size_t rhs_dt_helper_vmm_idx,
+            const Xbyak_aarch64::XReg &rhs_addr_reg,
+            const Xbyak_aarch64::XReg &rhs_helper_reg,
+            const Xbyak_aarch64::XReg &rhs_addr_cache_reg,
+            bool preserve_gpr_helpers, bool preserve_vmm_helper,
+            std::size_t abi_param_offset, const memory_desc_wrapper &dst_d,
+            std::size_t tail_size, const Xbyak_aarch64::PReg &tail_opmask,
+            const Xbyak_aarch64::XReg &reg_tail_size,
+            bool use_exact_tail_scalar_bcast);
+    rhs_arg_static_params_t(std::size_t rhs_dt_helper_vmm_idx,
+            const Xbyak_aarch64::XReg &rhs_addr_reg,
+            const Xbyak_aarch64::XReg &rhs_helper_reg,
+            const Xbyak_aarch64::XReg &rhs_addr_cache_reg,
+            bool preserve_gpr_helpers, bool preserve_vmm_helper,
+            std::size_t abi_param_offset, std::size_t dst_orig_offset,
+            const memory_desc_wrapper &dst_d, std::size_t tail_size,
+            const Xbyak_aarch64::PReg &tail_opmask,
+            const Xbyak_aarch64::XReg &reg_tail_size,
+            bool use_exact_tail_scalar_bcast);
+
+    bool is_opmask_set() const noexcept { return is_opmask_set_; }
+    bool is_dst_orig_set() const noexcept { return is_dst_orig_set_; }
+
+    mutable std::size_t rhs_dt_helper_vmm_idx;
+    Xbyak_aarch64::XReg rhs_addr_reg;
+    Xbyak_aarch64::XReg rhs_helper_reg;
+    Xbyak_aarch64::XReg rhs_addr_cache_reg;
+    bool preserve_gpr_helpers;
+    bool preserve_vmm_helper;
+    std::size_t abi_param_offset;
+    std::size_t dst_orig_offset;
+    memory_desc_wrapper dst_d;
+    std::size_t tail_size;
+    Xbyak_aarch64::PReg tail_opmask;
+    bool use_exact_tail_scalar_bcast;
+    Xbyak_aarch64::XReg reg_tail_size;
+    bool is_tail;
+
+private:
+    rhs_arg_static_params_t(std::size_t rhs_dt_helper_vmm_idx,
+            const Xbyak_aarch64::XReg &rhs_addr_reg,
+            const Xbyak_aarch64::XReg &rhs_helper_reg,
+            const Xbyak_aarch64::XReg &rhs_addr_cache_reg,
+            bool preserve_gpr_helpers, bool preserve_vmm_helper,
+            std::size_t abi_param_offset, std::size_t dst_orig_offset,
+            const memory_desc_wrapper &dst_d, std::size_t tail_size,
+            const Xbyak_aarch64::PReg &tail_opmask,
+            bool use_exact_tail_scalar_bcast,
+            const Xbyak_aarch64::XReg &reg_tail_size, bool is_opmask_set,
+            bool is_dst_orig_set);
+
+    bool is_opmask_set_;
+    bool is_dst_orig_set_;
+};
+
+/*
+ * Represents params required by jit_uni_binary_injector_t that don't change
+ * during it's entire lifetime.
+ *
+ * @param param1 - register storing abi param1. At the moment of calling
+ * compute_vector_range method can be different than the default one defined
+ * inside jit_generator.
+ * @param bcast_set_t supported_strategy_set - set allowing disabling particular
+ * bcast strategies
+ * @param rhs_arg_static_params - params related to all binary post-ops right-hand side
+ * arguments that don't change during entire lifetime of jit_uni_binary_injector_t
+ * object.
+ */
+struct static_params_t {
+    static_params_t(const Xbyak_aarch64::XReg &param1,
+            const bcast_set_t &supported_strategy_set,
+            const rhs_arg_static_params_t &rhs_arg_static_params);
+    static_params_t(const Xbyak_aarch64::XReg &param1,
+            const rhs_arg_static_params_t &rhs_arg_static_params);
+
+    Xbyak_aarch64::XReg param1;
+    const bcast_set_t supported_strategy_set;
+    rhs_arg_static_params_t rhs_arg_static_params;
+};
+
+/*
+ * Mode of data load with tail for rhs:
+ * STATIC - load based on given integer.
+ * DYNAMIC - load based on opmask or 64-bit register.
+ * DEFAULT - DYNAMIC for avx512, STATIC for others.
+ */
+
+enum class tail_lode_mode_t { STATIC, DYNAMIC, DEFAULT };
+
+struct rhs_address_t {
+    Xbyak_aarch64::XReg base_;
+    int64_t offt_ = 0;
+    bool isBroadcast_ = false;
+    uint32_t bits_ = 0;
+
+    rhs_address_t(const Xbyak_aarch64::XReg &base, const int64_t offt = 0,
+            bool isBroadcast = false, const uint32_t bits = 0)
+        : base_(base), offt_(offt), isBroadcast_(isBroadcast), bits_(bits) {}
+
+    bool operator==(const rhs_address_t &rhs) const {
+        return getBit() == rhs.getBit()
+                && getBase().getIdx() == rhs.getBase().getIdx()
+                && isBroadcast_ == rhs.isBroadcast();
+    }
+    bool operator!=(const rhs_address_t &rhs) const { return !operator==(rhs); }
+
+    Xbyak_aarch64::XReg getBase() const { return base_; }
+    uint32_t getBit() const { return bits_; }
+    bool isBroadcast() const { return isBroadcast_; }
+};
+
+struct rhs_operand_t {
+
+    bool isAddress_ = false;
+    uint32_t idx_;
+    rhs_address_t address_;
+
+    bool operator==(const rhs_operand_t &rhs) const {
+        if (isAddress_) {
+            if (isAddress_ == rhs.isAddress_ && address_ == rhs.address_)
+                return true;
+            else
+                return false;
+        } else {
+            if (isAddress_ == rhs.isAddress_ && idx_ == rhs.idx_)
+                return true;
+            else
+                return false;
+        }
+    }
+
+    bool operator!=(const rhs_operand_t &rhs) const { return !operator==(rhs); }
+
+    bool isBroadcast() const { return isAddress_ && address_.isBroadcast(); }
+};
+
+/*
+ * Represents params passed to compute_vector_range method of
+ * jit_uni_binary_injector_t that can be different for each call.
+ * Contains configurable std::maps where key is vmm index and value is
+ * offset in elements. The offset value identifies tensor slice in particular
+ * vmm. This is utilized by broadcasting mechanism. Offset, depending on the
+ * implementation particular kernels, can be passed as value (usually during
+ * unrolling), inside operand, under memory address.
+ *
+ * @param vmm_idx_to_out_addr - vmm mapped to address of destination tensor with offset,
+ * used to calculate offset in no_broadcast strategy, but also in other strategies whose
+ * calculations are based on no_broadcast strategy.
+ * @param vmm_idx_to_out_reg - vmm mapped to register containing address of destination
+ * with offset, used to calculate offset in no_broadcast strategy, but also in other
+ * strategies whose calculations are based on no_broadcast strategy.
+ * @param vmm_idx_to_out_elem_off_addr - vmm mapped to offset in elements stored under
+ * memory address intended to use in no_broadcast strategy.
+ * @param vmm_idx_to_out_elem_off_addr - vmm mapped to offset in elements stored under
+ * memory address intended to use in no_broadcast strategy.
+ * @param vmm_idx_to_out_elem_off_val - vmm mapped to offset in elements passed as raw
+ * value intended to use in no_broadcast strategy
+ * @param vmm_idx_to_out_off_oprnd - vmm mapped to offset in elements inside operand
+ * intended to use in no_broadcast strategy
+ * @param vmm_idx_to_oc_elem_off_addr - vmm mapped to output channel offset in elements
+ * stored under memory address intended to use in per_oc broadcast strategies.
+ * @param vmm_idx_to_oc_elem_off_val - vmm mapped to  output channel offset in elements
+ * passed as raw value intended to use in per_oc broadcast strategies.
+ * @param vmm_idx_to_oc_off_oprnd - vmm mapped to output channel offset in elements inside
+ * operand intended to use in per_oc broadcast strategies.
+ * @param vmm_idx_to_sp_elem_off_addr - vmm mapped to proper output spatial offset in
+ * elements stored under memory address intended to use in per_mb_spatial strategies.
+ * @param vmm_idx_to_sp_elem_off_val - vmm mapped to proper output spatial offset in
+ * elements passed as raw value intended to use in per_mb_spatial strategies.
+ * @param vmm_idx_to_sp_off_oprnd - vmm mapped to proper output spatial offset in 
+ * elements inside operand intended to use in per_mb_spatial strategies.
+ * @param vmm_idx_to_mb_w_elem_off_addr - vmm mapped to proper output last dim
+ * per first dim offset in elements stored under memory address intended to use
+ * in per_mb_w strategies.
+ * @param vmm_idx_to_mb_w_elem_off_val - vmm mapped to proper output last dim
+ * per first dim offset in elements passed as raw value intended to use in
+ * per_mb_w strategies.
+ * @param vmm_idx_to_mb_w_off_oprnd - vmm mapped to proper output last dim
+ * per first dim offset in elements inside operand intended to use in per_mb_w
+ * strategies.
+ * @param vmm_idx_to_w_elem_off_addr - vmm mapped to proper output last dim
+ * offset in elements stored under memory address intended to use in per_w strategy.
+ * @param vmm_idx_to_w_elem_off_val - vmm mapped to proper output last dim
+ * offset in elements passed as raw value intended to use in per_w strategy.
+ * @param vmm_idx_to_w_off_oprnd - vmm mapped to proper output last dim offset
+ * in elements inside operand intended to use in per_w strategy.
+ * @param vmm_tail_idx - vmm indices that contains data don't fill the whole vector (tail).
+ * @param is_dynamic_tail_load - determines whether to load with tail in
+ * runtime (based on the value from reg_tail_size or opmask) or based on given
+ * integer.
+ */
+
+struct rhs_arg_dynamic_params_t {
+    std::map<int, rhs_address_t> vmm_idx_to_out_addr;
+    std::map<int, Xbyak_aarch64::XReg> vmm_idx_to_out_reg;
+
+    std::map<int, rhs_address_t> vmm_idx_to_out_elem_off_addr;
+    std::map<int, size_t> vmm_idx_to_out_elem_off_val;
+    std::map<int, rhs_operand_t> vmm_idx_to_out_off_oprnd;
+
+    std::map<int, rhs_address_t> vmm_idx_to_oc_elem_off_addr;
+    std::map<int, size_t> vmm_idx_to_oc_elem_off_val;
+    std::map<int, rhs_operand_t> vmm_idx_to_oc_off_oprnd;
+
+    std::map<int, rhs_address_t> vmm_idx_to_sp_elem_off_addr;
+    std::map<int, size_t> vmm_idx_to_sp_elem_off_val;
+    std::map<int, rhs_operand_t> vmm_idx_to_sp_off_oprnd;
+
+    std::map<int, rhs_address_t> vmm_idx_to_mb_w_elem_off_addr;
+    std::map<int, size_t> vmm_idx_to_mb_w_elem_off_val;
+    std::map<int, rhs_operand_t> vmm_idx_to_mb_w_off_oprnd;
+
+    std::map<int, rhs_address_t> vmm_idx_to_w_elem_off_addr;
+    std::map<int, size_t> vmm_idx_to_w_elem_off_val;
+    std::map<int, rhs_operand_t> vmm_idx_to_w_off_oprnd;
+
+    std::unordered_set<int> vmm_tail_idx_;
+    tail_lode_mode_t tail_load_mode = tail_lode_mode_t::DEFAULT;
+};
+
+/*
+ * Checks if src1 data type is supported by binary injector.
+ */
+bool is_data_supported(cpu_isa_t isa, data_type_t data_type);
+
+/*
+ * Checks if broadcast of src1 is supported by binary injector.
+ */
+bool is_bcast_supported(const dnnl::impl::memory_desc_t &src1_desc,
+        const memory_desc_wrapper &dst_d,
+        const bcast_set_t &supported_strategy_set);
+
+/*
+ * Checks if binary injection for given args is supported.
+ */
+bool is_supported(cpu_isa_t isa, const dnnl::impl::memory_desc_t &src1_desc,
+        const memory_desc_wrapper &dst_d,
+        const bcast_set_t &supported_strategy_set);
+
+/*
+ * Main mechanism responsible for injecting binary postops supporting various
+ * isa: sve_512
+ * types: f32, s32, u8, s8.
+ */
+template <cpu_isa_t isa>
+class jit_uni_binary_injector_t {
+    using TReg = typename cpu_isa_traits<isa>::TReg;
+    using TRegS = typename cpu_isa_traits<isa>::TRegS;
+    using Vmm = typename cpu_isa_traits<isa>::TReg;
+
+public:
+    jit_uni_binary_injector_t(
+            jit_generator *host, const static_params_t &static_params);
+
+    /*
+     * Generates code of binary post_op injected to host primitive. Applied to
+     * ordered set of vector registers' indexes. Function loads appropriate
+     * slice of rhs tensor for computations based on internally determined
+     * broadcast strategy and information about stored data in particular vmm
+     * described inside rhs_arg_params.
+     */
+    void compute_vector_range(const injector_utils::vmm_index_set_t &vmm_idxs,
+            std::size_t rhs_arg_idx, const dnnl_post_ops::entry_t &post_op,
+            const rhs_arg_dynamic_params_t &rhs_arg_params) const;
+
+    /*
+     * Generates code of binary post_op injected to host primitive. Applied to
+     * range <start_idx, end_idx) of vector registers' indexes. Function loads
+     * appropriate slice of rhs tensor for computations based on internally
+     * determined broadcast strategy and information about stored data in particular
+     * vmm described inside rhs_arg_params.
+     */
+    void compute_vector_range(size_t start_idx, size_t end_idx,
+            std::size_t rhs_arg_idx, const dnnl_post_ops::entry_t &post_op,
+            const rhs_arg_dynamic_params_t &rhs_arg_params) const;
+
+    /*
+     * Generates code of binary post_op injected to host primitive. Applied to
+     * a single vector register index. Function loads appropriate slice of rhs tensor
+     * for computations based on internally determined broadcast strategy and information
+     * about stored data in particular vmm described inside rhs_arg_params.
+     */
+    void compute_vector(size_t idx, std::size_t rhs_arg_idx,
+            const dnnl_post_ops::entry_t &post_op,
+            const rhs_arg_dynamic_params_t &rhs_arg_params) const;
+
+private:
+    /*
+     * Determines if hint passed by user is valid (is inside range
+     * <start_idx, end_idx>). If not it returns new vmm idx value that will be
+     * used as temporary vmm in future computations.
+     */
+    int adjust_temp_vmm_hint(
+            int user_hint, int start_idx, int end_idx, int max_vmm_idx) const;
+    /*
+     * Taking into account rhs_broadcasting_strategy and information from user
+     * about tensor slice (rhs_arg_params) stored in Vmm(vmm_idx) calculates
+     * address of rhs tensor slice needed for binary operation and returns
+     * ptr to it.
+     */
+    rhs_address_t prepare_rhs_arg_addr(std::size_t vmm_idx,
+            std::size_t rhs_arg_idx, const dnnl_post_ops::entry_t &post_op,
+            const rhs_arg_dynamic_params_t &rhs_arg_params,
+            const broadcasting_strategy_t rhs_broadcasting_strategy) const;
+    /*
+     * Loads data and applies particular binary operation.
+     */
+    void inject_binary(const dnnl_post_ops::entry_t &post_op, Vmm dst,
+            const rhs_address_t &rhs_addr, bool with_tail,
+            const tail_lode_mode_t tail_load_mode) const;
+
+    /*
+     * Helper functions responsible for preparing rhs tensor slice address.
+     */
+    void append_offset_from_operand(
+            const std::map<int, rhs_operand_t> &vmm_idx_to_elem_addr_off,
+            int vmm_idx, const Xbyak_aarch64::XReg &addr_reg,
+            const Xbyak_aarch64::XReg &tmp_reg,
+            std::size_t elem_size_bytes) const;
+    void append_offset_under_mem_addr(
+            const std::map<int, rhs_address_t> &vmm_idx_to_elem_addr_off,
+            int vmm_idx, const Xbyak_aarch64::XReg &addr_reg,
+            const Xbyak_aarch64::XReg &tmp_reg,
+            std::size_t elem_size_bytes) const;
+    void append_value_offset(
+            const std::map<int, size_t> &vmm_idx_to_elem_val_off, int vmm_idx,
+            const Xbyak_aarch64::XReg &addr_reg,
+            std::size_t elem_size_bytes) const;
+
+    void append_no_broadcast_offset(
+            const std::map<int, rhs_address_t> &vmm_idx_to_out_addr,
+            const std::map<int, Xbyak_aarch64::XReg> &vmm_idx_to_out_reg,
+            const std::map<int, size_t> &vmm_idx_to_out_elem_off_val,
+            int vmm_idx, const Xbyak_aarch64::XReg &addr_reg,
+            const Xbyak_aarch64::XReg &tmp_reg,
+            std::size_t elem_size_bytes) const;
+    void calculate_no_broadcast(rhs_address_t addr, std::size_t offset,
+            const Xbyak_aarch64::XReg &out_reg) const;
+
+    void append_oc_offset(
+            const std::map<int, rhs_address_t> &vmm_idx_to_out_addr,
+            const std::map<int, Xbyak_aarch64::XReg> &vmm_idx_to_out_reg,
+            const std::map<int, size_t> &vmm_idx_to_out_elem_off_val,
+            int vmm_idx, const Xbyak_aarch64::XReg &addr_reg,
+            const Xbyak_aarch64::XReg &tmp_reg,
+            std::size_t elem_size_bytes) const;
+    void calculate_oc_ncsp(const dim_t *strides,
+            const Xbyak_aarch64::XReg &tmp_reg,
+            const bool residue = false) const;
+    void calculate_oc_blocked(
+            const dim_t *strides, const Xbyak_aarch64::XReg &tmp_reg) const;
+    void calculate_oc_nspc(
+            const dim_t *strides, const Xbyak_aarch64::XReg &tmp_reg) const;
+    void calculate_oc_cspn(
+            const dim_t *strides, const Xbyak_aarch64::XReg &tmp_reg) const;
+
+    void append_mb_sp_offset(
+            const std::map<int, rhs_address_t> &vmm_idx_to_out_addr,
+            const std::map<int, Xbyak_aarch64::XReg> &vmm_idx_to_out_reg,
+            const std::map<int, size_t> &vmm_idx_to_out_elem_off_val,
+            int vmm_idx, const Xbyak_aarch64::XReg &addr_reg,
+            const Xbyak_aarch64::XReg &tmp_reg,
+            std::size_t elem_size_bytes) const;
+    void calculate_mb_sp_ncsp(
+            const dim_t *strides, const Xbyak_aarch64::XReg &tmp_reg) const;
+    void calculate_mb_sp_blocked(
+            const dim_t *strides, const Xbyak_aarch64::XReg &tmp_reg) const;
+    void calculate_mb_sp_nspc(
+            const dim_t *strides, const Xbyak_aarch64::XReg &tmp_reg) const;
+    void calculate_mb_sp_cspn(
+            const dim_t *strides, const Xbyak_aarch64::XReg &tmp_reg) const;
+
+    void append_mb_w_offset(
+            const std::map<int, rhs_address_t> &vmm_idx_to_out_addr,
+            const std::map<int, Xbyak_aarch64::XReg> &vmm_idx_to_out_reg,
+            const std::map<int, size_t> &vmm_idx_to_out_elem_off_val,
+            int vmm_idx, const Xbyak_aarch64::XReg &addr_reg,
+            const Xbyak_aarch64::XReg &tmp_reg,
+            std::size_t elem_size_bytes) const;
+    void calculate_mb_w_ncsp(
+            const dim_t *strides, const Xbyak_aarch64::XReg &tmp_reg) const;
+    void calculate_mb_w_blocked(
+            const dim_t *strides, const Xbyak_aarch64::XReg &tmp_reg) const;
+    void calculate_mb_w_nspc(
+            const dim_t *strides, const Xbyak_aarch64::XReg &tmp_reg) const;
+    void calculate_mb_w_cspn(
+            const dim_t *strides, const Xbyak_aarch64::XReg &tmp_reg) const;
+
+    void append_w_offset(
+            const std::map<int, rhs_address_t> &vmm_idx_to_out_addr,
+            const std::map<int, Xbyak_aarch64::XReg> &vmm_idx_to_out_reg,
+            const std::map<int, size_t> &vmm_idx_to_out_elem_off_val,
+            int vmm_idx, const Xbyak_aarch64::XReg &addr_reg,
+            const Xbyak_aarch64::XReg &tmp_reg,
+            std::size_t elem_size_bytes) const;
+    void calculate_w_ncsp(
+            const dim_t *strides, const Xbyak_aarch64::XReg &tmp_reg) const;
+    void calculate_w_blocked(
+            const dim_t *strides, const Xbyak_aarch64::XReg &tmp_reg) const;
+    void calculate_w_nspc(
+            const dim_t *strides, const Xbyak_aarch64::XReg &tmp_reg) const;
+    void calculate_w_cspn(
+            const dim_t *strides, const Xbyak_aarch64::XReg &tmp_reg) const;
+
+    void compute_cmp_mask(const Xbyak_aarch64::PReg &cmp_dst,
+            const Xbyak_aarch64::PReg &mask, const Xbyak_aarch64::ZReg &cmp_src,
+            const Xbyak_aarch64::ZReg &cmp_src2, const unsigned int uimm) const;
+
+    template <typename T>
+    void fdiv(const Vmm &dst, const Xbyak_aarch64::PReg &mask, const Vmm &lhs,
+            const T &rhs) const;
+    template <typename T>
+    void fdiv(const Vmm &dst, const Vmm &lhs, const T &rhs) const;
+
+    void execute_cmp_binary(const Vmm &dst, const Xbyak_aarch64::PReg &mask,
+            const Vmm &lhs, const Vmm &rhs,
+            const unsigned int cmp_predicate) const;
+    template <typename T>
+    void execute_binary(alg_kind_t binary_alg, const Vmm &dst,
+            const Xbyak_aarch64::PReg &mask, const Vmm &lhs,
+            const T &rhs) const;
+    /*
+     * Used in scalar broadcast strategy, broadcasting single value of given
+     * data type over entire vector Vmm register.
+     */
+    void execute_broadcast(const data_type_t &data_type, const Vmm &tmp_reg,
+            const rhs_address_t &rhs_addr,
+            const tail_lode_mode_t tail_load_mode,
+            bool with_tail = false) const;
+    void load_rhs(const data_type_t &data_type, const Vmm &tmp_reg,
+            const rhs_address_t &rhs_addr,
+            const tail_lode_mode_t tail_load_mode,
+            bool with_tail = false) const;
+    void execute_broadcast_tail_with_opmask(const data_type_t &data_type,
+            const Vmm &tmp_reg, const rhs_address_t &rhs_addr) const;
+    void execute_broadcast_tail_statically(const data_type_t &data_type,
+            const Vmm &tmp_reg, const rhs_address_t &rhs_addr,
+            const std::size_t tail_size) const;
+    void execute_broadcast_tail_with_gpr(const data_type_t &data_type,
+            const Vmm &tmp_reg, const rhs_address_t &rhs_addr) const;
+    void load_rhs_tail_dynamically_with_opmask(const data_type_t &data_type,
+            const Vmm &tmp_vmm, const rhs_address_t &rhs_addr) const;
+    void load_rhs_tail_dynamically_with_gpr(
+            const data_type_t &data_type, const Vmm &tmp_vmm) const;
+    void load_rhs_tail_statically(const data_type_t &data_type,
+            const Vmm &tmp_vmm, const rhs_address_t &rhs_addr) const;
+    void execute_broadcast_no_tail(const data_type_t &data_type,
+            const Vmm &tmp_vmm, const rhs_address_t &rhs_addr) const;
+    void execute_broadcast_s8u8_no_tail(const data_type_t &data_type,
+            const Vmm &tmp_vmm, const rhs_address_t &rhs_addr) const;
+    void load_rhs_no_tail(const data_type_t &data_type, const Vmm &tmp_reg,
+            const rhs_address_t &rhs_addr) const;
+    void load_rhs_i8_no_tail(const data_type_t &data_type, const Vmm &tmp_reg,
+            const rhs_address_t &rhs_addr) const;
+    void cvt_to_f32(const Vmm &tmp_reg) const;
+    /*
+     * Returns pair consisting of flag indication preservation is needed for vmm
+     * index in second member that should be used as temporary vmm inside inject
+     * binary.
+     */
+    std::pair<bool, int> should_preserve_vmm(int curr_idx, int vmm_hint,
+            int max_vmm_idx, bool dt_helper_vmm_needed) const;
+    /*
+     * Used in isa != avx512 where m32bcst is not supported, replaces ptr_b
+     * with ptr.
+     */
+    rhs_address_t remove_bcast_bit(const rhs_address_t &rhs_addr) const;
+
+    jit_generator *host_;
+    const rhs_arg_static_params_t rhs_arg_static_params_;
+    const Xbyak_aarch64::XReg param1_;
+    const bcast_set_t supported_strategy_set_;
+
+    static constexpr int sizeof_reg64 = 8;
+    /*
+     * Instructions from SSE/AVX used to compute binary result like vaddps where
+     * second operand is memory, require mem operand to be 16/32 byte explicitly
+     * aligned. (Intel Manual chapter 2.4).
+     * Rule is relaxed from AVX2 (Intel Manual chapter 14.9).
+     * When using benchdnn zmalloc_protect doesn't guarantee that tensor memory
+     * address is 64 byte aligned, which can cause segmentation fault.
+     */
+    static constexpr bool binary_op_with_unaligned_mem_operand_allowed_ = true;
+};
+
+} // namespace binary_injector
+} // namespace aarch64
+} // namespace cpu
+} // namespace impl
+} // namespace dnnl
+
+#endif

miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/injectors/jit_uni_eltwise_injector.hpp

@@ -0,0 +1,359 @@
+/*******************************************************************************
+* Copyright 2019-2023 Intel Corporation
+* Copyright 2021-2023 FUJITSU LIMITED
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef CPU_AARCH64_JIT_UNI_ELTWISE_INJECTOR_HPP
+#define CPU_AARCH64_JIT_UNI_ELTWISE_INJECTOR_HPP
+
+#include <assert.h>
+#include <type_traits>
+
+#include "common/c_types_map.hpp"
+#include "common/primitive_attr.hpp"
+#include "common/type_helpers.hpp"
+#include "common/utils.hpp"
+
+#include "cpu/aarch64/injectors/injector_utils.hpp"
+#include "cpu/aarch64/jit_generator.hpp"
+
+namespace dnnl {
+namespace impl {
+namespace cpu {
+namespace aarch64 {
+
+namespace eltwise_injector {
+struct static_params_t {
+
+    static_params_t(bool save_state = true,
+            Xbyak_aarch64::XReg x_table = Xbyak_aarch64::XReg(0),
+            Xbyak_aarch64::PReg p_mask = Xbyak_aarch64::PReg(1),
+            Xbyak_aarch64::PReg p_tmp0 = Xbyak_aarch64::PReg(4),
+            bool is_fwd = true, bool use_dst = false, bool preserve_vmm = true,
+            bool preserve_p_table = true)
+        : save_state(save_state)
+        , x_table(x_table)
+        , p_mask(p_mask)
+        , p_tmp0(p_tmp0)
+        , is_fwd(is_fwd)
+        , use_dst(use_dst)
+        , preserve_vmm(preserve_vmm)
+        , preserve_p_table(preserve_p_table) {}
+
+    bool save_state;
+    Xbyak_aarch64::XReg x_table;
+    Xbyak_aarch64::PReg p_mask;
+    Xbyak_aarch64::PReg p_tmp0;
+    bool is_fwd;
+    bool use_dst;
+    bool preserve_vmm;
+    bool preserve_p_table;
+};
+
+/*
+ * Checks if isa is supported by eltwise injector.
+ */
+bool is_isa_supported(cpu_isa_t isa);
+
+/*
+ * Checks if eltwise algorithm is supported by eltwise injector.
+ */
+bool is_alg_supported(alg_kind_t alg);
+
+/*
+ * Checks if eltwise injection for given args is supported.
+ */
+bool is_supported(cpu_isa_t isa, alg_kind_t alg);
+
+} // namespace eltwise_injector
+
+template <cpu_isa_t isa>
+struct jit_uni_eltwise_injector_f32 {
+    using TReg = typename cpu_isa_traits<isa>::TReg;
+    using TRegS = typename cpu_isa_traits<isa>::TRegS;
+
+    // Arguments description:
+    // host - jit generator which is filled with instructions
+    // alg, alpha, beta, scale - user eltwise arguments
+    // save_state - when true, preserves on stack vmm_aux registers preventing
+    //   results spoiling. Restores them when done in injector_postamble().
+    // p_table - GPR where table label is stored to get access for pre-defined
+    //   constants used in alg codes.
+    // k_mask - k_register to operate with masks in alg codes.
+    // is_fwd - when true, computes d = alg(s), otherwise, computes ds = alg'(s)
+    //   - algorithm derivative.
+    // use_dst - defines whether source or destination point is passed to alg
+    //   code. Depends on algorithm. See `_use_dst_for_bwd` algs definition.
+    jit_uni_eltwise_injector_f32(jit_generator *host, alg_kind_t alg,
+            float alpha, float beta, float scale, bool save_state = true,
+            Xbyak_aarch64::XReg x_table = Xbyak_aarch64::XReg(0),
+            Xbyak_aarch64::PReg p_mask = Xbyak_aarch64::PReg(1),
+            Xbyak_aarch64::PReg p_tmp0 = Xbyak_aarch64::PReg(4),
+            bool is_fwd = true, bool use_dst = false, bool preserve_vmm = true,
+            bool preserve_p_table = true)
+        : alg_(alg)
+        , alpha_(alpha)
+        , beta_(beta)
+        , scale_(scale)
+        , h(host)
+        , save_state_(save_state)
+        , x_table(x_table)
+        , p_mask(p_mask)
+        , p_tmp0(p_tmp0)
+        , is_fwd_(is_fwd)
+        , use_dst_(use_dst)
+        , preserve_vmm_(preserve_vmm)
+        , preserve_p_table_(preserve_p_table) {
+        assert(eltwise_injector::is_supported(isa, alg_));
+
+        register_table_entries();
+    }
+
+    jit_uni_eltwise_injector_f32(jit_generator *host,
+            const post_ops_t::entry_t::eltwise_t &eltwise,
+            bool save_state = true,
+            Xbyak_aarch64::XReg x_table = Xbyak_aarch64::XReg(0),
+            Xbyak_aarch64::PReg p_mask = Xbyak_aarch64::PReg(1),
+            Xbyak_aarch64::PReg p_tmp0 = Xbyak_aarch64::PReg(4),
+            bool is_fwd = true, bool use_dst = false, bool preserve_vmm = true,
+            bool preserve_p_table = true)
+        : jit_uni_eltwise_injector_f32(host, eltwise.alg, eltwise.alpha,
+                eltwise.beta, eltwise.scale, save_state, x_table, p_mask,
+                p_tmp0, is_fwd, use_dst, preserve_vmm, preserve_p_table) {}
+
+    void compute_vector_range(size_t start_idx, size_t end_idx);
+    void compute_vector_range(const injector_utils::vmm_index_set_t &vmm_idxs);
+    void compute_vector(size_t idx) { compute_vector_range(idx, idx + 1); }
+    void prepare_table(bool gen_table = true);
+    void load_table_addr() { h->adr(x_table, l_table); }
+
+private:
+    const alg_kind_t alg_;
+    const float alpha_;
+    const float beta_;
+    const float scale_;
+
+    jit_generator *const h;
+
+    const bool save_state_;
+    const Xbyak_aarch64::XReg x_table;
+    // 99 is dummy and must be replaced meaningfull value at runtime.
+    Xbyak_aarch64::PReg p_all = Xbyak_aarch64::PReg(99);
+    const Xbyak_aarch64::PReg p_mask;
+    const Xbyak_aarch64::PReg p_tmp0;
+    const bool is_fwd_;
+    const bool use_dst_;
+    const bool preserve_vmm_;
+    const bool preserve_p_table_;
+
+    Xbyak_aarch64::Label l_table;
+
+    // if only the injector was inherited from jit_generator...
+    enum {
+        _cmp_eq_oq = jit_generator::_cmp_eq_oq,
+        _cmp_lt_os = jit_generator::_cmp_lt_os,
+        _cmp_le_os = jit_generator::_cmp_le_os,
+        _cmp_ge_os = jit_generator::_cmp_nlt_us,
+        _cmp_gt_os = jit_generator::_cmp_nle_us,
+        _op_floor = jit_generator::_op_floor,
+        _op_mxcsr = jit_generator::_op_mxcsr
+    };
+
+    const size_t vlen = get_sve_length();
+    static constexpr size_t preserved_vecs_max = 9;
+    static constexpr size_t preserved_gprs_max = 4;
+    static constexpr size_t vecs_count = cpu_isa_traits<isa>::n_vregs;
+    static constexpr int n_mantissa_bits = 23;
+    static constexpr int k_mask_size = 8;
+
+    size_t vecs_to_preserve = 0;
+    size_t preserved_vecs_count = 0;
+    size_t preserved_vec_idxs[preserved_vecs_max] = {0};
+    size_t preserved_gpr_idxs[preserved_gprs_max] = {0};
+    injector_utils::vmm_index_set_iterator_t start_idx_tail;
+
+    /* These vector register must be assigned proper index. */
+    TRegS vmm_mask {0}, vmm_aux0 {0}, vmm_aux1 {0}, vmm_aux2 {0}, vmm_aux3 {0},
+            vmm_aux4 {0}, vmm_aux5 {0}, vmm_aux6 {0}, vmm_aux7 {0}, vmm_tmp {0};
+    /* Default tempooral index. Chose a SVE register
+     not to be same as jit_uni_eltwise.(cpp|hpp).
+     This index is changed by assign_regs() in case of eltwise injection.
+  */
+    TRegS z_tmp {31};
+
+    size_t aux_vecs_count();
+    size_t aux_gprs_count();
+
+    void compute_body(
+            const injector_utils::vmm_index_set_iterator_t &start_idx_it,
+            const injector_utils::vmm_index_set_iterator_t &end_idx_it);
+    void injector_preamble(const injector_utils::vmm_index_set_t &vmm_idxs);
+    void injector_preamble_tail(
+            const injector_utils::vmm_index_set_iterator_t start_idx_it);
+    void injector_postamble();
+    void assign_regs();
+    void set_coef_to_regs();
+    void compute_cmp_mask(
+            const TRegS &vmm_src, const TRegS &vmm_cmpare, int cmp_predicate);
+    void blend_with_mask(const TRegS &vmm_dst, const TRegS &src);
+    void test_mask();
+
+    void exp_compute_vector_fwd(const TRegS &vmm_src);
+    void relu_compute_vector_fwd(const TRegS &vmm_src);
+    void relu_zero_ns_compute_vector_fwd(const TRegS &vmm_src);
+    void elu_compute_vector_fwd(const TRegS &vmm_src);
+    void tanh_compute_vector_fwd(const TRegS &vmm_src);
+    void square_compute_vector_fwd(const TRegS &vmm_src);
+    void abs_compute_vector_fwd(const TRegS &vmm_src);
+    void sqrt_compute_vector_fwd(const TRegS &vmm_src);
+    void linear_compute_vector_fwd(const TRegS &vmm_src);
+    void soft_relu_compute_vector_fwd(const TRegS &vmm_src);
+    void mish_compute_vector_fwd(const TRegS &vmm_src);
+    void logistic_compute_vector_fwd(const TRegS &vmm_src);
+    void gelu_tanh_compute_vector_fwd(const TRegS &vmm_src);
+    void swish_compute_vector_fwd(const TRegS &vmm_src);
+    void log_compute_vector_fwd(const TRegS &vmm_src);
+    void clip_compute_vector_fwd(const TRegS &vmm_src);
+    void gelu_erf_compute_vector_fwd(const TRegS &vmm_src);
+    void gelu_erf_minimax_approx_compute_vector_fwd(const TRegS &vmm_src);
+    void round_compute_vector_fwd(const TRegS &vmm_src);
+    void hardswish_compute_vector_fwd(const TRegS &vmm_src);
+    void hardsigmoid_compute_vector_fwd(const TRegS &vmm_src);
+
+    void exp_compute_vector_bwd(const TRegS &vmm_src);
+    void relu_compute_vector_bwd(const TRegS &vmm_src);
+    void elu_compute_vector_bwd(const TRegS &vmm_src);
+    void tanh_compute_vector_bwd(const TRegS &vmm_src);
+    void square_compute_vector_bwd(const TRegS &vmm_src);
+    void abs_compute_vector_bwd(const TRegS &vmm_src);
+    void sqrt_compute_vector_bwd(const TRegS &vmm_src);
+    void linear_compute_vector_bwd(const TRegS &vmm_src);
+    void soft_relu_compute_vector_bwd(const TRegS &vmm_src);
+    void logistic_compute_vector_bwd(const TRegS &vmm_src);
+    void mish_compute_vector_bwd(const TRegS &vmm_src);
+    void gelu_tanh_compute_vector_bwd(const TRegS &vmm_src);
+    void swish_compute_vector_bwd(const TRegS &vmm_src);
+    void log_compute_vector_bwd(const TRegS &vmm_src);
+    void clip_compute_vector_bwd(const TRegS &vmm_src);
+    void gelu_erf_compute_vector_bwd(const TRegS &vmm_src);
+    void hardswish_compute_vector_bwd(const TRegS &vmm_src);
+    void hardsigmoid_compute_vector_bwd(const TRegS &vmm_src);
+
+    enum key_t {
+        scale = 0, // scale argument
+        alpha, // alpha argument
+        beta, // beta argument
+        zero, // 0.f
+        half, // 0.5f
+        one, // 1.f  or  mask for exponent bits
+        two, // 2.f
+        minus_one, // -1.f  or  changes sign to opposite
+        minus_two, // -2.f
+        ln2f, // 0.69314718f
+        positive_mask, // changes sign to positive
+        sign_mask, // gets sign value
+        exponent_bias, // (127 = 2^7 - 1), gets exponent bits
+        exp_log2ef, // 1.44269502f - formula-based for approx
+        exp_ln_flt_max_f, // logf(FLT_MAX) - max normal value
+        exp_ln_flt_min_f, // logf(FLT_MIN) - min normal value
+        exp_pol, // see correspondent table for float values
+        exp_coeff1, // 0.6931473921 (0x3f31721c)
+        exp_coeff2, // 0.2413862043 (0x3e772df2)
+        exp_not_mask17, // ~((1u << 17) - 1)
+        fwd_mish_max_x_for_equation_f,
+        // e^x(e^3x+4e^2x+e^x*(6+4*x)+4*(1+x)) = FLT_MAX; x =~ 22.18070976278534
+        bwd_mish_max_x_for_equation_f,
+        tanh_range, // tanh(x) = x - x^3/3 for |x| < tanh_range
+        tanh_m1d3, // -1/3
+        soft_relu_one_twenty_six, // 126.f
+        soft_relu_mantissa_sign_mask, // mask for mantissa bits and sign
+        soft_relu_pol, // see correspondent table for float values
+        gelu_tanh_fitting_const, // 0.044715f
+        gelu_tanh_fitting_const_times_three, // 0.134145f
+        gelu_tanh_sqrt_two_over_pi, // sqrtf(2.f/pi) = 0.797884f
+        gelu_erf_approx_const, // 0.3275911f - implementation based for approx
+        gelu_erf_one_over_sqrt_two, // 1.f / sqrtf(2.f)
+        gelu_erf_one_over_sqrt_pi, // 1.f / sqrtf(pi) = 0.564190f
+        gelu_erf_pol, // see correspondent table for float values
+        log_minus_inf, // -inf
+        log_qnan, // qnan
+        log_mantissa_mask, // gets mantissa bits
+        log_full_k_reg_mask, // sets k_register with all bits of 1
+        log_full_vector_reg_mask, // sets vector register will all bits of 1
+        log_five_bit_offset, // 5 bits off (31 = 2^5 - 1)
+        log_pol, // see correspondent table for float values
+        log_predefined_vals, // see correspondent table for float values
+        log_i127shl23,
+        log_x7fffff,
+        log_log2,
+        log_log1p5,
+        log_f2div3,
+        log_coeffTbl,
+        undef_key,
+    };
+
+    size_t table_off(key_t key, size_t key_off_val_shift = 0) {
+        // assumption: all table entries sharing the same key also
+        // share their broadcast property
+        // TODO: enforce through data structure
+        const auto it = entry_map_.find(key); // search an entry for a key
+        assert(it != entry_map_.end());
+        const auto &te = (*it).second;
+        const auto scale = te.bcast ? vlen : sizeof(table_entry_val_t);
+        return te.off + key_off_val_shift * scale;
+    }
+
+    TRegS table_val(key_t key, TRegS zreg, size_t key_off_val_shift = 0) {
+        Xbyak_aarch64::XReg x_addr(h->X_DEFAULT_ADDR);
+        auto off = table_off(key, key_off_val_shift);
+
+        if (off) {
+            h->add_imm(x_addr, x_table, off, h->X_TMP_0);
+        } else {
+            x_addr = x_table;
+        }
+
+        h->ldr(TReg(zreg.getIdx()), ptr(x_addr));
+        return zreg;
+    }
+
+    // we accept only 32bit hexadecimal table values to avoid any rounding
+    using table_entry_val_t = uint32_t;
+    using table_entry_offset_t = size_t; // offsets are in bytes wrt p_table
+    using table_entry_bcast_t = bool; // true => bcast value
+
+    struct table_entry_t {
+        table_entry_val_t val;
+        table_entry_bcast_t bcast;
+    };
+    struct mapped_table_entry_t {
+        table_entry_offset_t off;
+        table_entry_val_t val;
+        table_entry_bcast_t bcast;
+    };
+
+    using table_t = std::multimap<key_t, table_entry_t>;
+    using mapped_table_t = std::multimap<key_t, mapped_table_entry_t>;
+
+    void register_table_entries();
+    mapped_table_t entry_map_;
+};
+
+} // namespace aarch64
+} // namespace cpu
+} // namespace impl
+} // namespace dnnl
+
+#endif

miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/injectors/jit_uni_postops_injector.hpp

@@ -0,0 +1,167 @@
+/*******************************************************************************
+* Copyright 2020-2023 Intel Corporation
+* Copyright 2022-2023 FUJITSU LIMITED
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+#ifndef CPU_AARCH64_JIT_UNI_POSTOPS_INJECTOR_HPP
+#define CPU_AARCH64_JIT_UNI_POSTOPS_INJECTOR_HPP
+
+#include <functional>
+#include <map>
+#include <memory>
+
+#include "common/c_types_map.hpp"
+#include "common/primitive_attr.hpp"
+#include "common/type_helpers.hpp"
+#include "common/utils.hpp"
+#include "cpu/aarch64/injectors/injector_utils.hpp"
+#include "cpu/aarch64/injectors/jit_uni_binary_injector.hpp"
+#include "cpu/aarch64/injectors/jit_uni_eltwise_injector.hpp"
+#include "cpu/aarch64/jit_generator.hpp"
+#include <initializer_list>
+
+namespace dnnl {
+namespace impl {
+namespace cpu {
+namespace aarch64 {
+namespace injector {
+
+/*
+ * Allows specifying custom injector function for given post-op type - one
+ * function per primitive. There are post-ops type (example: sum) that don't
+ * have specialized injector. They heavily rely on kernel specific intrnals,
+ * which makes the generalization unreasonable. As so user can prepare internal
+ * kernel lambda and pass it explicitly to injector.
+ */
+using lambda_jit_injectors_t
+        = std::map<dnnl_primitive_kind_t, std::function<void()>>;
+
+struct post_ops_ok_args_t;
+/*
+ * Checks if postops injection for given args is supported.
+ */
+bool is_supported(const post_ops_ok_args_t &post_ops_ok_args);
+
+/*
+ * Main mechanism of handling various post-ops types. It utilizes internally
+ * specialized injectors to generate post-ops code to host primitive. Random
+ * order of post-ops is supported.
+ */
+template <cpu_isa_t isa>
+class jit_uni_postops_injector_t {
+public:
+    /*
+     * @param host <required> - user primitive where post-ops generated code is
+     * injected
+     * @param post_ops <required> - struct representing requested post-ops chain
+     * @binary_static_params <reguired> - static params needed for binary_injector.
+     * see: jit_uni_binary_injector.hpp for more info.
+     * @param eltwise_static_params <optional> - allows user specify non default
+     * params for eltwise_injector
+     * @param lambda_jit_injectors <optional> - allows user specify custom injector
+     * function for given post-op type
+     */
+    jit_uni_postops_injector_t(jit_generator *host, const post_ops_t &post_ops,
+            const binary_injector::static_params_t &binary_static_params);
+    jit_uni_postops_injector_t(jit_generator *host, const post_ops_t &post_ops,
+            const binary_injector::static_params_t &binary_static_params,
+            const lambda_jit_injectors_t &lambda_jit_injectors);
+    jit_uni_postops_injector_t(jit_generator *host, const post_ops_t &post_ops,
+            const binary_injector::static_params_t &binary_static_params,
+            const eltwise_injector::static_params_t &eltwise_static_params);
+    jit_uni_postops_injector_t(jit_generator *host, const post_ops_t &post_ops,
+            const binary_injector::static_params_t &binary_static_params,
+            const eltwise_injector::static_params_t &eltwise_static_params,
+            const lambda_jit_injectors_t &lambda_jit_injectors);
+
+    /*
+     * Generates code of post_ops chain injected to host primitive. Applied to
+     * ordered set of vector registers' indexes.
+     *
+     * @rhs_arg_params: see jit_uni_binary_injector description
+     */
+    void compute_vector_range(const injector_utils::vmm_index_set_t &vmm_idxs,
+            const binary_injector::rhs_arg_dynamic_params_t &rhs_arg_params);
+
+    void compute_vector_range(const injector_utils::vmm_index_set_t &vmm_idxs);
+
+    /*
+     * Generates code of post_ops chain injected to host primitive. Applied to
+     * range <start_idx, end_idx) of vector registers' indexes.
+     *
+     * @rhs_arg_params: see jit_uni_binary_injector description
+     */
+    void compute_vector_range(size_t start_idx, size_t end_idx,
+            const binary_injector::rhs_arg_dynamic_params_t &rhs_arg_params);
+
+    void compute_vector_range(size_t start_idx, size_t end_idx);
+
+    /*
+     * Generates code of post_ops chain injected to host primitive. Applied to
+     * a single vector register index.
+     *
+     * @rhs_arg_params: see jit_uni_binary_injector description
+     */
+    void compute_vector(size_t idx,
+            const binary_injector::rhs_arg_dynamic_params_t &rhs_arg_params);
+    void compute_vector(size_t idx);
+
+    /*
+     * Thin wrapper for eltwise injector specific function
+     */
+    void prepare_table(bool gen_table = true);
+    void set_lambda_injector(lambda_jit_injectors_t::key_type,
+            const lambda_jit_injectors_t::mapped_type &jit_injector);
+
+private:
+    post_ops_t post_ops_;
+    jit_generator *host_;
+    // Key is a numerical order of a post-op in attributes.
+    std::map<int, jit_uni_eltwise_injector_f32<isa>> alg_to_eltwise_injector_;
+    std::unique_ptr<binary_injector::jit_uni_binary_injector_t<isa>>
+            binary_injector_;
+    lambda_jit_injectors_t lambda_jit_injectors_;
+};
+
+enum post_op_type { sum = 0, eltwise, binary };
+
+struct post_ops_ok_args_t {
+    post_ops_ok_args_t(const cpu_isa_t isa,
+            const std::vector<post_op_type> &accepted_post_op_types,
+            const post_ops_t &post_ops, const memory_desc_wrapper *dst_d,
+            const bool sum_at_pos_0_only, const bool sum_requires_scale_one,
+            const bool sum_requires_zp_zero = true,
+            const bool sum_requires_same_params = true,
+            const bcast_set_t &enabled_bcast_strategy = default_strategies());
+
+    const cpu_isa_t isa;
+    const std::vector<post_op_type> &accepted_post_op_types;
+    const post_ops_t &post_ops;
+    const memory_desc_wrapper *dst_d;
+    const bool sum_at_pos_0_only;
+    const bool sum_requires_scale_one;
+    const bool sum_requires_zp_zero;
+    const bool sum_requires_same_params;
+    const bcast_set_t enabled_bcast_strategy;
+};
+
+bool post_ops_ok(const post_ops_ok_args_t &args);
+
+} // namespace injector
+} // namespace aarch64
+} // namespace cpu
+} // namespace impl
+} // namespace dnnl
+
+#endif

miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_generator.hpp

@@ -0,0 +1,728 @@
+/*******************************************************************************
+* Copyright 2016-2023 Intel Corporation
+* Copyright 2020-2023 FUJITSU LIMITED
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef CPU_AARCH64_JIT_GENERATOR_HPP
+#define CPU_AARCH64_JIT_GENERATOR_HPP
+
+#include <limits.h>
+
+#include "common/bit_cast.hpp"
+#include "common/type_helpers.hpp"
+#include "common/utils.hpp"
+
+#include "cpu/aarch64/cpu_isa_traits.hpp"
+
+#include "cpu/jit_utils/jit_utils.hpp"
+
+#if defined(_WIN32) && !defined(__GNUC__)
+#define STRUCT_ALIGN(al, ...) __declspec(align(al)) __VA_ARGS__
+#else
+#define STRUCT_ALIGN(al, ...) __VA_ARGS__ __attribute__((__aligned__(al)))
+#endif
+
+#define DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_name) \
+    const char *name() const override { return STRINGIFY(jit_name); } \
+    const char *source_file() const override { return __FILE__; }
+
+static const size_t CSIZE = sizeof(uint32_t);
+
+namespace dnnl {
+namespace impl {
+namespace cpu {
+namespace aarch64 {
+
+// TODO: move this to jit_generator class?
+namespace {
+
+typedef enum {
+    MAX_CODE_SIZE = 256 * 1024,
+} max_code_size_t;
+
+// Callee-saved registers
+constexpr Xbyak_aarch64::Operand::Code abi_save_gpr_regs[]
+        = {Xbyak_aarch64::Operand::X16, Xbyak_aarch64::Operand::X17,
+                Xbyak_aarch64::Operand::X19, Xbyak_aarch64::Operand::X20,
+                Xbyak_aarch64::Operand::X21, Xbyak_aarch64::Operand::X22,
+                Xbyak_aarch64::Operand::X23, Xbyak_aarch64::Operand::X24,
+                Xbyak_aarch64::Operand::X25, Xbyak_aarch64::Operand::X26,
+                Xbyak_aarch64::Operand::X27, Xbyak_aarch64::Operand::X28};
+
+// See "Procedure Call Standsard for the ARM 64-bit Architecture (AArch64)"
+static const Xbyak_aarch64::XReg abi_param1(Xbyak_aarch64::Operand::X0),
+        abi_param2(Xbyak_aarch64::Operand::X1),
+        abi_param3(Xbyak_aarch64::Operand::X2),
+        abi_param4(Xbyak_aarch64::Operand::X3),
+        abi_param5(Xbyak_aarch64::Operand::X4),
+        abi_param6(Xbyak_aarch64::Operand::X5),
+        abi_param7(Xbyak_aarch64::Operand::X6),
+        abi_param8(Xbyak_aarch64::Operand::X7),
+        abi_not_param1(Xbyak_aarch64::Operand::X15);
+} // namespace
+
+class jit_generator : public Xbyak_aarch64::CodeGenerator, public c_compatible {
+public:
+    using c_compatible::operator new;
+    using c_compatible::operator new[];
+    using c_compatible::operator delete;
+    using c_compatible::operator delete[];
+
+private:
+    const size_t xreg_len = 8;
+    const size_t vreg_len_preserve = 8; // Only bottom 8byte must be preserved.
+    const size_t vreg_to_preserve = 8; // VREG8 - VREG15
+
+    const size_t num_abi_save_gpr_regs
+            = sizeof(abi_save_gpr_regs) / sizeof(abi_save_gpr_regs[0]);
+
+    const size_t preserved_stack_size = xreg_len * (2 + num_abi_save_gpr_regs)
+            + vreg_len_preserve * vreg_to_preserve;
+
+    const size_t size_of_abi_save_regs = num_abi_save_gpr_regs * x0.getBit() / 8
+            + vreg_to_preserve * vreg_len_preserve;
+
+public:
+    enum {
+        _cmp_eq_oq = 0u,
+        _cmp_lt_os = 1u,
+        _cmp_le_os = 2u,
+        _cmp_neq_uq = 4u,
+        _cmp_nlt_us = 5u,
+        _cmp_nle_us = 6u,
+
+        _op_floor = 1u,
+        _op_mxcsr = 4u,
+    };
+
+    const uint64_t cpu_sveLen = get_sve_length();
+
+    const Xbyak_aarch64::WReg W_TMP_0 = w23;
+    const Xbyak_aarch64::WReg W_TMP_1 = w24;
+    const Xbyak_aarch64::WReg W_TMP_2 = w25;
+    const Xbyak_aarch64::WReg W_TMP_3 = w26;
+    const Xbyak_aarch64::WReg W_TMP_4 = w27;
+    const Xbyak_aarch64::XReg X_TMP_0 = x23;
+    const Xbyak_aarch64::XReg X_TMP_1 = x24;
+    const Xbyak_aarch64::XReg X_TMP_2 = x25;
+    const Xbyak_aarch64::XReg X_TMP_3 = x26;
+    const Xbyak_aarch64::XReg X_TMP_4 = x27;
+    const Xbyak_aarch64::XReg X_DEFAULT_ADDR = x28;
+    const Xbyak_aarch64::XReg X_SP = x21;
+    const Xbyak_aarch64::XReg X_TRANSLATOR_STACK = x22;
+    const Xbyak_aarch64::PReg P_TMP = p7;
+    const Xbyak_aarch64::PReg P_TMP_0 = p11;
+    const Xbyak_aarch64::PReg P_TMP_1 = p12;
+    const Xbyak_aarch64::PReg P_ALL_ZERO = p10;
+    const Xbyak_aarch64::PReg P_NOT_256 = p13;
+    const Xbyak_aarch64::PReg P_NOT_128 = p14;
+    const Xbyak_aarch64::PReg P_ALL_ONE = p0;
+
+    const std::vector<Xbyak_aarch64::XReg> x_tmp_vec
+            = {X_TMP_0, X_TMP_1, X_TMP_2, X_TMP_3, X_TMP_4};
+    const int x_tmp_vec_size = x_tmp_vec.size();
+
+    const Xbyak_aarch64::XReg param1 = abi_param1;
+    constexpr static size_t translator_stack_offset = 1024 * 128;
+    constexpr static uint32_t DUMMY_IDX = 99;
+
+    inline size_t get_size_of_abi_save_regs() { return size_of_abi_save_regs; }
+
+    void preamble() {
+        using namespace Xbyak_aarch64::util;
+        uint64_t sveLen = get_sve_length();
+
+        stp(x29, x30, pre_ptr(sp, -16));
+        /* x29 is a frame pointer. */
+        mov(x29, sp);
+        sub(sp, sp, static_cast<int64_t>(preserved_stack_size) - 16);
+
+        /* x9 can be used as a temporal register. */
+        mov(x9, sp);
+
+        if (vreg_to_preserve) {
+            st4((v8.d - v11.d)[0], post_ptr(x9, vreg_len_preserve * 4));
+            st4((v12.d - v15.d)[0], post_ptr(x9, vreg_len_preserve * 4));
+        }
+        for (size_t i = 0; i < num_abi_save_gpr_regs; i += 2) {
+            stp(Xbyak_aarch64::XReg(abi_save_gpr_regs[i]),
+                    Xbyak_aarch64::XReg(abi_save_gpr_regs[i + 1]),
+                    post_ptr(x9, xreg_len * 2));
+        }
+
+        if (sveLen) { /* SVE is available. */
+            ptrue(P_ALL_ONE.b);
+            pfalse(P_ALL_ZERO.b);
+        }
+        if (sveLen >= SVE_256) {
+            ptrue(P_NOT_128.b, Xbyak_aarch64::VL16);
+            not_(P_NOT_128.b, P_ALL_ONE / Xbyak_aarch64::T_z, P_NOT_128.b);
+        }
+        if (sveLen >= SVE_512) {
+            ptrue(P_NOT_256.b, Xbyak_aarch64::VL32);
+            not_(P_NOT_256.b, P_ALL_ONE / Xbyak_aarch64::T_z, P_NOT_256.b);
+        }
+
+        mov(X_SP, sp);
+        sub_imm(X_TRANSLATOR_STACK, X_SP, translator_stack_offset, X_TMP_0);
+    }
+
+    void postamble() {
+        using namespace Xbyak_aarch64::util;
+
+        mov(x9, sp);
+
+        if (vreg_to_preserve) {
+            ld4((v8.d - v11.d)[0], post_ptr(x9, vreg_len_preserve * 4));
+            ld4((v12.d - v15.d)[0], post_ptr(x9, vreg_len_preserve * 4));
+        }
+
+        for (size_t i = 0; i < num_abi_save_gpr_regs; i += 2) {
+            ldp(Xbyak_aarch64::XReg(abi_save_gpr_regs[i]),
+                    Xbyak_aarch64::XReg(abi_save_gpr_regs[i + 1]),
+                    post_ptr(x9, xreg_len * 2));
+        }
+
+        add(sp, sp, static_cast<int64_t>(preserved_stack_size) - 16);
+        ldp(x29, x30, post_ptr(sp, 16));
+        ret();
+    }
+
+    // Disallow char-based labels completely
+    void L(const char *label) = delete;
+    void L(Xbyak_aarch64::Label &label) {
+        Xbyak_aarch64::CodeGenerator::L(label);
+    }
+
+    void L_aligned(Xbyak_aarch64::Label &label, int alignment = 16) {
+        align(alignment);
+        L(label);
+    }
+
+    template <typename T>
+    Xbyak_aarch64::XReg addr_off(const Xbyak_aarch64::XReg &base, const T off,
+            const Xbyak_aarch64::XReg &addr, const Xbyak_aarch64::XReg &x_tmp) {
+        if (off == 0) return base;
+
+        add_imm(addr, base, off, x_tmp);
+        return addr;
+    }
+
+    template <typename PRegBHSD, typename T>
+    void set_preg(const PRegBHSD &p, T tail_size,
+            const Xbyak_aarch64::XReg x_tmp0 = Xbyak_aarch64::XReg(DUMMY_IDX),
+            const Xbyak_aarch64::XReg x_tmp1 = Xbyak_aarch64::XReg(DUMMY_IDX)) {
+        using namespace Xbyak_aarch64;
+
+        assert(tail_size <= 64); // Implemented only for "SVE size <=  512"
+
+        switch (tail_size) {
+            case 0: pfalse(PRegB(p.getIdx())); return;
+            case 1: ptrue(p, VL1); return;
+            case 2: ptrue(p, VL2); return;
+            case 3: ptrue(p, VL3); return;
+            case 4: ptrue(p, VL4); return;
+            case 5: ptrue(p, VL5); return;
+            case 6: ptrue(p, VL6); return;
+            case 7: ptrue(p, VL7); return;
+            case 8: ptrue(p, VL8); return;
+            case 16: ptrue(p, VL16); return;
+            case 32: ptrue(p, VL32); return;
+            case 64: ptrue(p, VL64); return;
+        }
+
+        assert(x_tmp0.getIdx() != DUMMY_IDX && x_tmp1.getIdx() != DUMMY_IDX);
+        mov_imm(x_tmp0, 0);
+        mov_imm(x_tmp1, tail_size);
+        whilelt(p, x_tmp0, x_tmp1);
+    }
+
+    template <typename T>
+    void uni_add(const T &x1, const T &x2, const T &op) {
+        add(x1, x2, op);
+    }
+
+    void uni_add(const Xbyak_aarch64::VReg4S &x1,
+            const Xbyak_aarch64::VReg4S &x2, const Xbyak_aarch64::VReg4S &op) {
+        add(x1, x2, op);
+    }
+
+    void uni_add(const Xbyak_aarch64::ZReg &x1, const Xbyak_aarch64::ZReg &x2,
+            const Xbyak_aarch64::ZReg &op) {
+        add(Xbyak_aarch64::ZRegS(x1.getIdx()),
+                Xbyak_aarch64::ZRegS(x2.getIdx()),
+                Xbyak_aarch64::ZRegS(op.getIdx()));
+    }
+
+    template <typename T>
+    void udiv_mod(const T &q, const T &r, const T &divend, const T &divisor) {
+        assert(q.getIdx() != divisor.getIdx());
+        assert(q.getIdx() != divend.getIdx());
+        assert(r.getIdx() != divend.getIdx());
+
+        udiv(q, divend, divisor);
+        mul(r, q, divisor);
+        sub(r, divend, r);
+    }
+
+    template <typename T>
+    void umod(const T &r, const T &divend, const T &divisor) {
+        assert(r.getIdx() != divend.getIdx());
+        assert(r.getIdx() != divisor.getIdx());
+
+        udiv(r, divend, divisor);
+        mul(r, r, divisor);
+        sub(r, divend, r);
+    }
+
+    void uni_clear(const Xbyak_aarch64::VReg &dst) { eor(dst.b, dst.b, dst.b); }
+
+    void uni_clear(const Xbyak_aarch64::ZReg &dst) { eor(dst.d, dst.d, dst.d); }
+
+    template <typename T>
+    void uni_fadd(const T &dst, const T &src, const T &src2) {
+        fadd(dst, src, src2);
+    }
+
+    void uni_fcvtzs(
+            const Xbyak_aarch64::VReg4S &d, const Xbyak_aarch64::VReg4S &s) {
+        fcvtzs(d, s);
+    }
+
+    void uni_fcvtzs(
+            const Xbyak_aarch64::ZRegS &d, const Xbyak_aarch64::ZRegS &s) {
+        fcvtzs(d, P_ALL_ONE / Xbyak_aarch64::T_z, s);
+    }
+
+    template <typename TReg>
+    void uni_fdiv(const TReg &dst, const TReg &src, const TReg &src2,
+            const TReg &tmp, const Xbyak_aarch64::PReg &pred) {
+        uint32_t dstIdx = dst.getIdx();
+        uint32_t srcIdx = src.getIdx();
+        uint32_t src2Idx = src2.getIdx();
+        uint32_t tmpIdx = tmp.getIdx();
+
+        if (dstIdx == src2Idx) {
+            assert(tmpIdx != srcIdx && tmpIdx != src2Idx);
+
+            mov(Xbyak_aarch64::ZRegD(tmpIdx), Xbyak_aarch64::ZRegD(src2Idx));
+            mov(dst, pred / Xbyak_aarch64::T_m, src);
+            fdiv(dst, pred / Xbyak_aarch64::T_m, tmp);
+        } else if (dstIdx == srcIdx) {
+            fdiv(dst, pred / Xbyak_aarch64::T_m, src2);
+        } else {
+            mov(dst, P_ALL_ONE / Xbyak_aarch64::T_m, src);
+            fdiv(dst, pred / Xbyak_aarch64::T_m, src2);
+        }
+    }
+
+    template <typename TReg>
+    void uni_fdiv(const TReg &dst, const TReg &src, const TReg &src2) {
+        fdiv(dst, src, src2);
+    }
+
+    void uni_fdiv(const Xbyak_aarch64::VReg4S &dst,
+            const Xbyak_aarch64::VReg4S &src, const Xbyak_aarch64::VReg4S &src2,
+            const Xbyak_aarch64::VReg4S &tmp, const Xbyak_aarch64::PReg &pred) {
+        UNUSED(tmp);
+        UNUSED(pred);
+        fdiv(dst, src, src2);
+    }
+
+    template <typename T>
+    void uni_fmad(const T &dst, const T &src, const T &src2) {
+        fmad(dst, P_ALL_ONE / Xbyak_aarch64::T_m, src, src2);
+    }
+
+    void uni_fmad(const Xbyak_aarch64::VReg4S &dst,
+            const Xbyak_aarch64::VReg4S &src,
+            const Xbyak_aarch64::VReg4S &src2) {
+        fmul(dst, dst, src);
+        fadd(dst, dst, src2);
+    }
+
+    template <typename T>
+    void uni_fmax(const T &dst, const T &src, const T &src2) {
+        uint32_t dstIdx = dst.getIdx();
+        uint32_t srcIdx = src.getIdx();
+        if (dstIdx != srcIdx)
+            mov(Xbyak_aarch64::ZRegD(dstIdx), Xbyak_aarch64::ZRegD(srcIdx));
+        fmax(dst, P_ALL_ONE / Xbyak_aarch64::T_m, src2);
+    }
+
+    template <typename T>
+    void uni_fmaxnm(const T &dst, const T &src, const T &src2) {
+        uint32_t dstIdx = dst.getIdx();
+        uint32_t srcIdx = src.getIdx();
+        if (dstIdx != srcIdx)
+            mov(Xbyak_aarch64::ZRegD(dstIdx), Xbyak_aarch64::ZRegD(srcIdx));
+        fmaxnm(dst, P_ALL_ONE / Xbyak_aarch64::T_m, src2);
+    }
+
+    void uni_fmaxnm(const Xbyak_aarch64::VReg4S &dst,
+            const Xbyak_aarch64::VReg4S &src,
+            const Xbyak_aarch64::VReg4S &src2) {
+        fmaxnm(dst, src, src2);
+    }
+
+    template <typename T>
+    void uni_fmin(const T &dst, const T &src, const T &src2) {
+        uint32_t dstIdx = dst.getIdx();
+        uint32_t srcIdx = src.getIdx();
+        if (dstIdx != srcIdx)
+            mov(Xbyak_aarch64::ZRegD(dstIdx), Xbyak_aarch64::ZRegD(srcIdx));
+        fmin(dst, P_ALL_ONE / Xbyak_aarch64::T_m, src2);
+    }
+
+    template <typename T>
+    void uni_fmul(const T &dst, const T &src, const T &src2) {
+        fmul(dst, src, src2);
+    }
+
+    void uni_frinti(
+            const Xbyak_aarch64::VReg4S &d, const Xbyak_aarch64::VReg4S &s) {
+        frinti(d, s);
+    }
+
+    void uni_frinti(
+            const Xbyak_aarch64::ZRegS &d, const Xbyak_aarch64::ZRegS &s) {
+        frinti(d, P_ALL_ONE / Xbyak_aarch64::T_m, s);
+    }
+
+    template <typename T>
+    void uni_fsqrt(const T &dst, const T &src) {
+        fsqrt(dst, P_ALL_ONE / Xbyak_aarch64::T_m, src);
+    }
+
+    void uni_fsqrt(const Xbyak_aarch64::VReg4S &dst,
+            const Xbyak_aarch64::VReg4S &src) {
+        fsqrt(dst, src);
+    }
+
+    void uni_fsub(const Xbyak_aarch64::VReg4S &v1,
+            const Xbyak_aarch64::VReg4S &v2, const Xbyak_aarch64::VReg4S &v3) {
+        fsub(v1, v2, v3);
+    }
+
+    template <typename T>
+    void uni_fsub(const T &dst, const T &src, const T &src2) {
+        fsub(dst, src, src2);
+    }
+
+    void uni_fsub(const Xbyak_aarch64::ZRegS &z1,
+            const Xbyak_aarch64::ZRegS &z2, const Xbyak_aarch64::ZRegS &z3) {
+        fsub(z1, z2, z3);
+    }
+
+    void uni_eor(const Xbyak_aarch64::VReg &v1, const Xbyak_aarch64::VReg &v2,
+            const Xbyak_aarch64::VReg &v3) {
+        eor(Xbyak_aarch64::VReg16B(v1.getIdx()),
+                Xbyak_aarch64::VReg16B(v2.getIdx()),
+                Xbyak_aarch64::VReg16B(v3.getIdx()));
+    }
+
+    void uni_eor(const Xbyak_aarch64::ZReg &z1, const Xbyak_aarch64::ZReg &z2,
+            const Xbyak_aarch64::ZReg &z3) {
+        eor(Xbyak_aarch64::ZRegD(z1.getIdx()),
+                Xbyak_aarch64::ZRegD(z2.getIdx()),
+                Xbyak_aarch64::ZRegD(z3.getIdx()));
+    }
+
+    void uni_ld1rw(const Xbyak_aarch64::VReg4S &dst,
+            const Xbyak_aarch64::XReg &base, const int64_t off) {
+        if (off == 0) {
+            ld1r(dst, ptr(base));
+        } else {
+            add_imm(X_DEFAULT_ADDR, base, off, X_TMP_0);
+            ld1r(dst, ptr(X_DEFAULT_ADDR));
+        }
+    }
+
+    void uni_ld1rw(const Xbyak_aarch64::ZRegS &dst,
+            const Xbyak_aarch64::XReg &base, const int64_t off) {
+        if (-32 <= off && off < 32) {
+            ld1rw(dst, P_ALL_ONE / Xbyak_aarch64::T_z, ptr(base, (int)off));
+        } else {
+            add_imm(X_DEFAULT_ADDR, base, off, X_TMP_0);
+            ld1rw(dst, P_ALL_ONE / Xbyak_aarch64::T_z, ptr(X_DEFAULT_ADDR));
+        }
+    }
+
+    void uni_ldr(
+            const Xbyak_aarch64::VReg &dst, const Xbyak_aarch64::XReg &addr) {
+        ldr(Xbyak_aarch64::QReg(dst.getIdx()), ptr(addr));
+    }
+
+    void uni_ldr(
+            const Xbyak_aarch64::ZReg &dst, const Xbyak_aarch64::XReg &addr) {
+        ldr(dst, ptr(addr));
+    }
+
+    template <typename T>
+    void uni_ldr(const Xbyak_aarch64::ZReg &r, const Xbyak_aarch64::XReg &base,
+            const T off) {
+        const int off_mod = off % cpu_sveLen;
+        const int off_mul_vl = off / cpu_sveLen;
+
+        if (off_mod == 0 && -256 <= off_mul_vl && off_mul_vl <= 255) {
+            ldr(r, Xbyak_aarch64::ptr(base, off_mul_vl, Xbyak_aarch64::MUL_VL));
+        } else {
+            const int offset = off_mod * 0x10 * (cpu_sveLen / 16);
+            add_imm(X_DEFAULT_ADDR, base, offset, X_TMP_0);
+            ldr(r, Xbyak_aarch64::ptr(X_DEFAULT_ADDR));
+        }
+    }
+
+    template <typename T>
+    void uni_ldr(const Xbyak_aarch64::VReg &r, const Xbyak_aarch64::XReg &base,
+            const T off) {
+        const int off_mod = off % 16;
+        const int off_mul_vl = off / 16;
+
+        if (off_mod == 0 && 0 <= off_mul_vl && off_mul_vl <= 65520) {
+            ldr(Xbyak_aarch64::QReg(r.getIdx()), Xbyak_aarch64::ptr(base, off));
+        } else {
+            add_imm(X_DEFAULT_ADDR, base, off_mod * 4, X_TMP_0);
+            ldr(Xbyak_aarch64::QReg(r.getIdx()),
+                    Xbyak_aarch64::ptr(X_DEFAULT_ADDR));
+        }
+    }
+
+    void uni_orr(const Xbyak_aarch64::VReg &d, const Xbyak_aarch64::VReg &s0,
+            const Xbyak_aarch64::VReg &s1) {
+        orr(d.b16, s0.b16, s1.b16);
+    }
+
+    void uni_orr(const Xbyak_aarch64::ZReg &d, const Xbyak_aarch64::ZReg &s0,
+            const Xbyak_aarch64::ZReg &s1) {
+        orr(d.d, s0.d, s1.d);
+    }
+
+    void uni_scvtf(
+            const Xbyak_aarch64::VReg4S &t0, const Xbyak_aarch64::VReg4S &t1) {
+        scvtf(t0, t1);
+    }
+
+    void uni_scvtf(
+            const Xbyak_aarch64::ZRegS &t0, const Xbyak_aarch64::ZRegS &t1) {
+        scvtf(t0, P_ALL_ONE / Xbyak_aarch64::T_m, t1);
+    }
+
+    void uni_str(
+            const Xbyak_aarch64::VReg &src, const Xbyak_aarch64::XReg &addr) {
+        str(Xbyak_aarch64::QReg(src.getIdx()), ptr(addr));
+    }
+
+    void uni_str(
+            const Xbyak_aarch64::ZReg &src, const Xbyak_aarch64::XReg &addr) {
+        str(src, ptr(addr));
+    }
+
+    template <typename T>
+    void uni_sub(const T &x1, const T &x2, const T &op) {
+        sub(x1, x2, op);
+    }
+
+    /*
+      Saturation facility functions. enable to prepare the register
+      holding the saturation upperbound and apply the saturation on
+      the floating point register
+     */
+    template <typename Vmm>
+    void init_vmm(Vmm vmm, Xbyak_aarch64::XReg reg_tmp, float value) {
+        using namespace data_type;
+        bool isSVE = get_sve_length() ? true : false;
+        Xbyak_aarch64::ZRegS z_tmp(vmm.getIdx());
+        Xbyak_aarch64::VReg4S v_tmp(vmm.getIdx());
+        Xbyak_aarch64::WReg w_tmp(reg_tmp.getIdx());
+        mov_imm(w_tmp, float2int(value));
+        if (isSVE) /* SVE is available. */
+            dup(z_tmp, w_tmp);
+        else
+            dup(v_tmp, w_tmp);
+    }
+
+    template <typename Vmm>
+    void init_saturate_f32(Vmm vmm_lbound, Vmm vmm_ubound,
+            Xbyak_aarch64::XReg reg_tmp, data_type_t idt, data_type_t odt,
+            bool force_lbound = false) {
+        using namespace data_type;
+        bool isSVE = get_sve_length() ? true : false;
+
+        if (!((idt == f32) && utils::one_of(odt, u8, data_type::s8, s32)))
+            return;
+
+        assert(IMPLICATION(
+                idt == u8, vmm_lbound.getIdx() != vmm_ubound.getIdx()));
+        // No need to saturate on lower bound for signed integer types, as
+        // the conversion to int would return INT_MIN, and then proper
+        // saturation will happen in store_data. The param force_lbound, will
+        // force saturate values unconditionally to lbound.
+        if (odt == u8) {
+            if (isSVE) /* SVE is available. */
+                dup(Xbyak_aarch64::ZRegS(vmm_lbound.getIdx()), 0);
+            else if (mayiuse(asimd))
+                movi(Xbyak_aarch64::VReg4S(vmm_lbound.getIdx()), 0);
+            else
+                assert(!"unreachable");
+        } else if (force_lbound) {
+            const float saturation_lbound
+                    = odt == data_type::s8 ? INT8_MIN : INT32_MIN;
+            init_vmm(vmm_lbound, reg_tmp, saturation_lbound);
+        }
+
+        float saturation_ubound = types::max_value<float>(odt);
+        init_vmm(vmm_ubound, reg_tmp, saturation_ubound);
+    }
+
+    template <typename Vmm>
+    void saturate_f32(const Vmm &vmm, const Vmm &vmm_lbound,
+            const Vmm &vmm_ubound, data_type_t odt,
+            const Xbyak_aarch64::PReg &p_true, bool force_lbound = false) {
+        // This function is used to saturate to odt in f32 before converting
+        // to s32 in order to avoid bad saturation due to cvtps2dq
+        // behavior (it returns INT_MIN if the f32 is out of the
+        // s32 range)
+        using namespace data_type;
+        bool isSVE = get_sve_length() ? true : false;
+
+        if (!utils::one_of(odt, u8, data_type::s8, s32)) return;
+
+        Xbyak_aarch64::VReg4S v_tmp(vmm.getIdx());
+        Xbyak_aarch64::VReg4S v_lbound(vmm_lbound.getIdx());
+        Xbyak_aarch64::VReg4S v_ubound(vmm_ubound.getIdx());
+        Xbyak_aarch64::ZRegS z_tmp(vmm.getIdx());
+        Xbyak_aarch64::ZRegS z_lbound(vmm_lbound.getIdx());
+        Xbyak_aarch64::ZRegS z_ubound(vmm_ubound.getIdx());
+
+        // no need to apply lower saturation bound when odt is
+        // signed, as cvtps2dq will return MIN_INT if the value
+        // does not fit. The param force_lbound, will force saturate values
+        // unconditionally to lbound.
+        if (odt == u8 || force_lbound) {
+            if (isSVE) /* SVE is available. */
+                fmax(z_tmp, p_true / Xbyak_aarch64::T_m, z_lbound);
+            else if (mayiuse(asimd))
+                fmax(v_tmp, v_tmp, v_lbound);
+            else
+                assert(!"unreachable");
+        }
+        if (isSVE) /* SVE is available. */
+            fmin(z_tmp, p_true / Xbyak_aarch64::T_m, z_ubound);
+        else if (mayiuse(asimd))
+            fmin(v_tmp, v_tmp, v_ubound);
+        else
+            assert(!"unreachable");
+    }
+
+    /* A utility function to process f32 tail (load, store or other) depending
+     * on tail size, stored in Reg64. Tail size must be value from 0 to 3/7
+     * (Xmm/Ymm). Tail process functions require integer as argument to specify
+     * behavior for each tail size.
+     *
+     * Only supported for Xmm and Ymm.
+     */
+    template <cpu_isa_t isa>
+    void runtime_tail_process(const Xbyak_aarch64::XReg &reg_tail,
+            const Xbyak_aarch64::XReg &reg_tmp,
+            const std::function<void(int)> &tail_process) {
+        constexpr int simd_w_ymm = 8;
+        constexpr int f32_bits = sizeof(float) * 8;
+        const auto simd_w = cpu_isa_traits<isa>::vlen * 8 / f32_bits;
+        assert(simd_w != cpu_isa_traits<isa>::vlen * 8 / f32_bits);
+
+        Xbyak_aarch64::Label label_tbl, label_tbl_end;
+        Xbyak_aarch64::Label l_case[simd_w_ymm];
+
+        adr(reg_tmp, label_tbl);
+        mov_imm(X_TMP_0, sizeof(void *));
+        madd(X_DEFAULT_ADDR, reg_tail, X_TMP_0, reg_tmp);
+        br(X_DEFAULT_ADDR);
+
+        // create jump table
+        L(label_tbl);
+        for (size_t i = 0; i < simd_w; i++)
+            putL(l_case[i]);
+
+        // cases for each tail size - from 0 to 3/7
+        L(l_case[0]);
+        b(label_tbl_end);
+        for (size_t i = 1; i < simd_w; i++) {
+            L(l_case[i]);
+            tail_process(i);
+            b(label_tbl_end);
+        }
+        L(label_tbl_end);
+    }
+
+    DNNL_DISALLOW_COPY_AND_ASSIGN(jit_generator);
+
+public:
+    jit_generator(void *code_ptr = nullptr, size_t code_size = MAX_CODE_SIZE,
+            bool use_autogrow = true)
+        : Xbyak_aarch64::CodeGenerator(code_size,
+                (code_ptr == nullptr && use_autogrow) ? Xbyak_aarch64::AutoGrow
+                                                      : code_ptr) {}
+    virtual ~jit_generator() {}
+
+    virtual const char *name() const = 0;
+    virtual const char *source_file() const = 0;
+
+    void register_jit_code(const uint8_t *code, size_t code_size) const {
+        jit_utils::register_jit_code(code, code_size, name(), source_file());
+    }
+
+    const uint8_t *jit_ker() const { return jit_ker_; }
+
+    template <typename... kernel_args_t>
+    void operator()(kernel_args_t... args) const {
+        using jit_kernel_func_t = void (*)(const kernel_args_t... args);
+        auto *fptr = (jit_kernel_func_t)jit_ker_;
+        (*fptr)(std::forward<kernel_args_t>(args)...);
+    }
+
+    virtual status_t create_kernel() {
+        generate();
+        jit_ker_ = getCode();
+        return (jit_ker_) ? status::success : status::runtime_error;
+    }
+
+private:
+    const uint8_t *getCode() {
+        this->ready();
+        if (!is_initialized()) return nullptr;
+        const uint8_t *code
+                = reinterpret_cast<const uint8_t *>(CodeGenerator::getCode());
+        register_jit_code(code, getSize() * CSIZE);
+        return code;
+    }
+
+    static inline bool is_initialized() {
+        /* At the moment, Xbyak_aarch64 does not have GetError()\
+         so that return dummy result. */
+        return true;
+    }
+
+protected:
+    virtual void generate() = 0;
+    const uint8_t *jit_ker_ = nullptr;
+};
+
+} // namespace aarch64
+} // namespace cpu
+} // namespace impl
+} // namespace dnnl
+
+#endif

miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_op_imm_check.hpp

@@ -0,0 +1,97 @@
+/*******************************************************************************
+* Copyright 2020-2021 FUJITSU LIMITED
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef JIT_OP_IMM_CHECK_HPP
+#define JIT_OP_IMM_CHECK_HPP
+
+#define LDRMAX 255
+#define LDRMIN (-256)
+#define STRMAX 255
+#define STRMIN (-256)
+#define LD1RWMAX 252
+#define PRFMMAX 32760
+#define PRFMMIN 0
+#define PRFWMAX 31
+#define PRFWMIN (-32)
+
+namespace dnnl {
+namespace impl {
+namespace cpu {
+namespace aarch64 {
+
+// Check the immediate value for LDR(vector) instruction
+//
+//   The imm9 in the LDR instruction is the optional signed immediate vector
+//   offset, in the range -256 to 255, defaulting to 0.
+template <typename T>
+bool ldr_imm_check(T ofs) {
+    int vlen = cpu_isa_traits<sve_512>::vlen;
+    int vlen_shift = cpu_isa_traits<sve_512>::vlen_shift;
+    int shifted_ofs = ofs >> vlen_shift;
+    return ((shifted_ofs) <= LDRMAX) && (shifted_ofs >= LDRMIN)
+            && ((ofs % vlen) == 0);
+}
+
+// Check the immediate value for SDR(vector) instruction
+//
+//   The imm9 in the STR instruction is the optional signed immediate vector
+//   offset, in the range -256 to 255, defaulting to 0.
+template <typename T>
+bool str_imm_check(T ofs) {
+    int vlen = cpu_isa_traits<sve_512>::vlen;
+    int vlen_shift = cpu_isa_traits<sve_512>::vlen_shift;
+    int shifted_ofs = ofs >> vlen_shift;
+    return ((shifted_ofs) <= STRMAX) && (shifted_ofs >= STRMIN)
+            && ((ofs % vlen) == 0);
+}
+
+// Check the immediate value for LD1RW instruction
+//
+//   The imm6 in the LD1RW instruction is the optional unsigned immediate byte
+//   offset, a multiple of 4 in the range 0 to 252, defaulting to 0.
+template <typename T>
+bool ld1rw_imm_check(T ofs) {
+    return ((ofs & 0x3) == 0) && (ofs <= LD1RWMAX) && (ofs >= 0);
+}
+
+// Check the immediate value for PRFM(immediate) instruction
+//
+//   The pimm in the PRFM instruction is the optional positive immediate byte
+//   offset, a multiple of 8 in the range 0 to 32760, defaulting to 0.
+template <typename T>
+bool prfm_imm_check(T ofs) {
+    return (ofs <= PRFMMAX) && (ofs >= PRFMMIN) && ((ofs & 0x7) == 0);
+}
+
+// Check the immediate value for PRFW(scalar plus immediate) instruction
+//
+//   The imm6 in the PRFW instruction is the optional signed immediate vector
+//   offset, in the range -32 to 31, defaulting to 0.
+template <typename T>
+bool prfw_imm_check(T ofs) {
+    int vlen = cpu_isa_traits<sve_512>::vlen;
+    int vlen_shift = cpu_isa_traits<sve_512>::vlen_shift;
+    int shifted_ofs = ofs >> vlen_shift;
+
+    return (shifted_ofs <= PRFWMAX) && (shifted_ofs >= PRFWMIN)
+            && ((ofs % vlen) == 0);
+}
+
+} // namespace aarch64
+} // namespace cpu
+} // namespace impl
+} // namespace dnnl
+#endif

miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_primitive_conf.hpp

@@ -0,0 +1,581 @@
+/*******************************************************************************
+* Copyright 2016-2022 Intel Corporation
+* Copyright 2020-2022 FUJITSU LIMITED
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef CPU_AARCH64_JIT_PRIMITIVE_CONF_HPP
+#define CPU_AARCH64_JIT_PRIMITIVE_CONF_HPP
+
+#include <stdint.h>
+
+#include "common/primitive_attr.hpp"
+#include "cpu/aarch64/cpu_isa_traits.hpp"
+
+namespace dnnl {
+namespace impl {
+namespace cpu {
+namespace aarch64 {
+
+enum class jit_memory_tag_kind_t { ncsp, nspc, blocked, undef };
+
+/* convolution */
+enum conv_version_t {
+    ver_unused,
+    ver_fma,
+    ver_sve_512,
+};
+
+enum conv_loop_order_t {
+    loop_cgn,
+    loop_gnc,
+    loop_ngc,
+    loop_gncw,
+    loop_cwgn,
+    loop_ngcw,
+    loop_nhwcg,
+    loop_nwcg
+};
+
+enum conv_kernel_kind_t { embd_bcast, expl_bcast };
+
+enum conv_1x1_loop_order_t {
+    loop_rbl,
+    loop_rlb,
+    loop_lbr,
+    loop_lrb,
+    loop_blr,
+    loop_brl
+};
+
+enum conv_harness_t {
+    harness_2d_reduction,
+    harness_3d_reduction,
+    harness_mb_reduction,
+    harness_compute_full_spatial,
+    harness_nxc
+};
+
+enum {
+    FLAG_MB_FIRST = 1 << 0,
+    FLAG_MB_LAST = 1 << 1,
+    FLAG_OC_FIRST = 1 << 2,
+    FLAG_OC_LAST = 1 << 3,
+    FLAG_IC_FIRST = 1 << 4,
+    FLAG_IC_LAST = 1 << 5,
+    FLAG_SP_FIRST = 1 << 6,
+    FLAG_SP_LAST = 1 << 7,
+    FLAG_REDUCE_FIRST = 1 << 8,
+    FLAG_REDUCE_LAST = 1 << 9,
+    FLAG_ZERO_FILTER = 1 << 0, /* Controls whether the inner kernel skips
+                                   loading weights-data from memory; this
+                                   needs to happen on the first Group/16
+                                   iteration. */
+    FLAG_ZERO_BIAS = 1 << 1, /* Controls whether the inner kernel skip
+                               loading bias data from memory */
+    FLAG_COMPUTE_BIAS = 1 << 2, /* Controls bias computation during execution
+                                    pass */
+};
+
+struct jit_conv_conf_t {
+    prop_kind_t prop_kind;
+    conv_version_t ver;
+    conv_loop_order_t loop_order;
+    conv_harness_t harness;
+
+    int simd_w;
+    int ndims;
+    int mb;
+    int ngroups, ic, oc, oc_without_padding, ic_without_padding;
+    int id, ih, iw, od, oh, ow;
+    int f_pad, l_pad, t_pad;
+    int back_pad, r_pad, b_pad;
+    int kd, kh, kw;
+    int stride_d, stride_h, stride_w;
+    int dilate_d, dilate_h, dilate_w;
+    format_tag_t src_tag, wei_tag, dst_tag; // temporary workaround
+    bool with_bias;
+    bool with_sum;
+    bool with_eltwise;
+    bool with_binary;
+
+    bool is_fused_conv;
+    int dw_conv_buffer_oc;
+
+    post_ops_t::entry_t::eltwise_t eltwise;
+    post_ops_t post_ops;
+
+    int nthr, nthr_mb, nthr_g, nthr_oc_b, nthr_ic_b;
+
+    int idp, ihp, iwp, ohp, owp;
+    int nb_ic, ic_block;
+    int nb_oc, oc_block;
+    int nb_iw, iw_block;
+    int nb_ow, ow_block;
+    int nb_oc_blocking; /* used in jit kernels for nb_oc work blocking taking
+                           into account vector registers distribution */
+    int nb_oc_blocking_thr_chunk; /* used for distribution of nb_oc work
+                                      within threads */
+    int nb_ic_blocking, nb_ic_blocking_max; // blocking of nb_ic work
+    int nb_ic_L2;
+    int h_blocking;
+    int nb_oc_L2;
+    int ic_tail, oc_tail;
+    int ur_h, ur_w;
+    int ur_w_tail;
+    int ur_ic, ur_kw;
+    bool is_1stconv;
+    int nonblk_group_off;
+    /* fma sve512_core */
+    conv_kernel_kind_t kernel_kind;
+
+    int tr_iw, tr_ih;
+    int tr_kw, tr_kh;
+    int tr_src_num_guard_elems;
+
+    // Transpose buffer management
+    size_t tr_src_buf_size, tr_src_buf_count;
+    size_t tr_diff_dst_buf_size, tr_diff_dst_buf_count;
+    int nthr_mb_work;
+
+    /* 1st conv */
+    int tr_ld;
+    int kh_step;
+    /* sve_512_u8s8u8 */
+    int typesize_in;
+    int typesize_out;
+    int typesize_bia;
+    int typesize_acc;
+    int ic_nb1, ic_nb2;
+    int oc_nb1;
+    int ur_ow_max, ur_ow, ur_ow_tail;
+    int ur_ow_nsteps;
+    data_type_t bia_dt;
+    /* bf16 data-type for output */
+    data_type_t dst_dt;
+    data_type_t src_dt;
+    /* bf16 weights update */
+    data_type_t wei_dt;
+    data_type_t dsrc_dt;
+    data_type_t dwei_dt;
+    bool expl_bcast;
+    bool large_spatial, large_w_filter;
+    int is_oc_scale;
+    int max_regs_ur; // maximum accumulation registers
+    // dw conv
+    int nb_ch, ch_block, nb_ch_blocking;
+    bool is_depthwise, is_fast_depthwise, is_resrc_depthwise;
+    int aligned_threads;
+    // large spatial
+    int h_blk_size, oh_blk_size;
+    // s8s8 convolution
+    bool signed_input;
+    bool need_saturation;
+    float wei_adj_scale;
+    // zero-point compensation
+    bool src_zero_point;
+    bool dst_zero_point;
+    bool zp_src_is_common; // common, otherwise (TODO) per-channel
+
+    bool uses_permw_transposition;
+    bool transpose_src;
+    bool transpose_dst;
+    int ic_block_step;
+
+    cpu_isa_t isa;
+
+    bool is_hw_transp; // spatial dim height-width transposed
+};
+
+// calculates filter size taking into account dilation
+inline int calculate_extended_filter_size(int filter_size, int dilation) {
+    return (filter_size - 1) * (dilation + 1) + 1;
+}
+
+inline int calculate_end_padding(int start_padding, int dst_size, int src_size,
+        int spatial_stride, int dilated_filter_size) {
+    return (dst_size - 1) * spatial_stride + dilated_filter_size
+            - (src_size + start_padding);
+}
+
+inline status_t init_tag(format_tag_t &tag, const memory_desc_wrapper &mdw,
+        const format_tag_t &tag_value) {
+    if (mdw.format_kind() == format_kind::any) return status::unimplemented;
+
+    tag = mdw.matches_one_of_tag(tag_value);
+    return tag == tag_value ? status::success : status::unimplemented;
+}
+
+struct jit_conv_call_s {
+    const void *src; /* hack, non-const for backward_data */
+    const void *dst; /* hack, non-const for forward */
+    const void *filt; /* hack, non-const for backward_weights */
+    const void *bias; /* hack, non-const for backward_bias */
+    const void *src_prf;
+    const void *dst_prf;
+    const void *filt_prf;
+    const void *bias_prf;
+    const void *scales;
+    const void *acc_s32;
+    const void *compensation;
+    const int32_t *zp_compensation;
+    const int32_t *src_zero_point;
+    const int32_t *dst_zero_point;
+    const void *tile_cfg;
+    const void *tile_cfg_tail;
+
+    // ptr to table of void * elements that are pointers to
+    // post_op binary src1 tensors
+    const void *post_ops_binary_rhs_arg_vec;
+    // logical (# of elems) offset to the processed output channel
+    // (for broadcasting [1,OC,1,1])
+    size_t oc_l_off;
+    const void *dst_orig; // pointer to dst memory (no offset)
+
+    size_t oc_l_off_prf;
+    const void *dst_orig_prf;
+
+    size_t kd_offset;
+    size_t kd_offset_prf;
+    size_t kh_offset;
+    size_t kh_offset_prf;
+    size_t os_index_begin;
+    size_t os_index_begin_prf;
+    size_t os_index_end;
+    size_t os_index_end_prf;
+    size_t kd_padding;
+    size_t kd_padding_prf;
+    size_t kh_padding;
+    size_t kh_padding_prf;
+    size_t iwb;
+    size_t iwb_prf;
+    size_t owb;
+    size_t owb_prf;
+    size_t kw_padding;
+    size_t channel;
+    size_t channel_prf;
+    size_t oc_blocks;
+    size_t ur_w;
+    size_t ur_str_w;
+    size_t ch_blocks;
+    size_t ch_blocks_prf;
+    size_t reduce_work;
+    size_t reduce_work_prf;
+    size_t load_work;
+    size_t load_work_prf;
+    size_t t_overflow;
+    size_t b_overflow;
+    size_t f_overflow;
+    size_t back_overflow;
+    size_t last_h;
+    size_t tail;
+    size_t current_iw;
+    size_t is_osb;
+    int flags;
+    int flags_prf;
+    int oc_flag;
+};
+
+struct jit_deconv_call_s {
+    const void *src; /* hack, non-const for backward_data */
+    const void *dst; /* hack, non-const for forward */
+    const void *filt; /* hack, non-const for backward_weights */
+    const void *bias; /* hack, non-const for backward_bias */
+    const void *scales;
+    const void *compensation;
+    const int32_t *zp_src_pad_str_compensation;
+    const int32_t *zp_compensation;
+    const int32_t *src_zero_point;
+    const int32_t *dst_zero_point;
+
+    /*
+     * ptr to table of void * elements that are pointers to post_op binary
+     * src1 tensors
+     */
+    const void *post_ops_binary_rhs_arg_vec;
+    const void *dst_orig; /* pointer to dst memory (no offset) */
+    /*
+     * logical (# of elems) offset to the processed output channel
+     * (for broadcasting [1,OC,1,1])
+     */
+    size_t oc_l_off;
+    size_t t_overflow;
+    size_t b_overflow;
+    size_t f_overflow;
+    size_t back_overflow;
+    size_t kh_padding;
+    size_t kd_padding;
+    size_t oc_blocks;
+};
+
+struct jit_dw_conv_call_s {
+    const void *input;
+    const void *output;
+    const void *filter;
+    const void *bias;
+    size_t kh_count;
+    size_t oh_count;
+    size_t oh_index;
+    size_t filter_pad_off;
+    unsigned char
+            exec_flags; /* Flags passed by driver execution to inner kernel */
+};
+
+struct jit_1x1_conv_conf_t {
+    prop_kind_t prop_kind;
+    conv_version_t ver;
+
+    int ndims;
+    int mb;
+    int ngroups, ic, oc, oc_without_padding, ic_without_padding;
+    int id, ih, iw, od, oh, ow;
+    int f_pad, t_pad, l_pad;
+    int kd, kh, kw;
+    int stride_d, stride_h, stride_w;
+    format_tag_t src_tag, wei_tag, dst_tag; // temporary workaround
+    bool with_bias;
+    bool with_sum;
+    bool with_eltwise;
+    bool with_binary;
+    bool with_dw_conv;
+
+    post_ops_t post_ops;
+    post_ops_t::entry_t::eltwise_t eltwise;
+
+    int is, os;
+    int ic_block, oc_block;
+
+    int ur, ur_tail;
+
+    int reduce_dim, reduce_block, nb_reduce, nb_reduce_blocking,
+            nb_reduce_blocking_max;
+    int load_dim, load_block, nb_load, nb_load_blocking, nb_load_blocking_max,
+            nb_load_chunk;
+    int bcast_dim, bcast_block, nb_bcast, nb_bcast_blocking,
+            nb_bcast_blocking_max;
+
+    int reduce_loop_unroll, reduce_loop_bcast_step, reduce_loop_load_step;
+    int load_loop_load_step, load_loop_iter_step;
+    int bcast_loop_output_step, bcast_loop_output_substep;
+    int bcast_loop_bcast_step, bcast_loop_bcast_substep;
+    int fma_step;
+    int load_grp_count;
+    conv_1x1_loop_order_t loop_order;
+    bool use_vmovntps;
+    /* sve512 core */
+    bool expl_bcast;
+    int typesize_in;
+    int typesize_out;
+    int typesize_bia;
+    int typesize_acc;
+    /* 4fma */
+    bool transpose_src;
+    int tr_is;
+    int nthr, nthr_mb, nthr_g, nthr_oc_b, nthr_ic_b;
+    int is_oc_scale;
+    data_type_t bia_dt;
+    data_type_t dst_dt;
+    bool signed_input;
+    float wei_adj_scale;
+    // zero-point compensation
+    bool src_zero_point;
+    bool dst_zero_point;
+    bool zp_src_is_common; // common, otherwise (TODO) per-channel
+
+    cpu_isa_t isa;
+    bool uses_permw_transposition;
+};
+
+struct jit_1x1_conv_call_s {
+    const void *bcast_data;
+    const void *load_data;
+    const void *output_data;
+    const void *bias_data; // used in forward and backward_weights only
+    const void *acc_s32;
+    const void *scales;
+    const void *compensation;
+    const void *store_buffer;
+    const int32_t *zp_compensation;
+    const int32_t *src_zero_point;
+    const int32_t *dst_zero_point;
+
+    // ptr to table of void * elements that are pointers to
+    // post_op binary src1 tensors
+    const void *post_ops_binary_rhs_arg_vec;
+    // logical (# of elems) offset to the processed output channel
+    // (for broadcasting [1,OC,1,1])
+    size_t oc_l_off;
+    const void *dst_orig; // pointer to dst memory (not offseted)
+
+    size_t load_dim;
+    size_t bcast_dim;
+    size_t reduce_dim;
+
+    size_t output_stride; // used in backward_weights only
+
+    size_t first_last_flag;
+};
+
+struct jit_pool_conf_t {
+    int ndims;
+    int mb, c, c_without_padding;
+    int id, ih, iw, od, oh, ow;
+    int stride_d, stride_h, stride_w;
+    int kd, kh, kw;
+    int f_pad, t_pad, l_pad;
+    alg_kind_t alg;
+    bool is_training;
+    bool pad_w_is_null;
+    bool is_backward;
+    bool simple_alg;
+    bool is_c_padded;
+    data_type_t ind_dt;
+
+    int c_block, c_tail, nb_c;
+    int ur_bc, ur_bc_tail;
+    int ur_c, ur_c_tail;
+    int ur;
+    size_t tail[4];
+    bool safe_c_tail;
+    data_type_t src_dt;
+    data_type_t dst_dt;
+
+    int dt_size;
+    bool is_bf16;
+    bool is_f16;
+    jit_memory_tag_kind_t tag_kind;
+    bool is_plain() const {
+        return (tag_kind == jit_memory_tag_kind_t::ncsp
+                || tag_kind == jit_memory_tag_kind_t::nspc);
+    }
+
+    cpu_isa_t isa;
+    post_ops_t post_ops;
+    bool with_postops;
+    bool with_eltwise;
+    bool with_binary;
+    int nthr;
+    memory_desc_t tmp_md;
+};
+
+struct jit_pool_call_s {
+    const void *src;
+    const void *dst;
+    const void *indices;
+    const void *src_prf;
+    const void *dst_prf;
+    const void *indices_prf;
+    const void *post_ops_binary_rhs_arg_vec;
+    const void *dst_orig;
+    const void *dst_po_helper;
+    size_t zero_ih;
+    size_t zero_id;
+    const void *zero_ptr;
+    size_t kd_padding;
+    size_t kh_padding;
+    size_t kh_padding_shift;
+    size_t kd_padding_shift;
+    size_t kw_padding;
+    const void *init_value;
+    float ker_area_h;
+    size_t ur_bc; // contains number of channel blocks to processing
+    size_t b_c; // contains number of channel blocks already processed
+};
+
+struct jit_shuffle_conf_t {
+    unsigned ndims = 0;
+
+    unsigned mb = 0, c = 0, d = 0, h = 0, w = 0, sp = 0;
+
+    unsigned stride_mb = 0;
+    unsigned blk_size = 0;
+    unsigned group_size = 0;
+    unsigned axis = 0;
+    unsigned axis_size = 0;
+    unsigned simd_tail = 0;
+    unsigned simd_w = 0;
+
+    jit_memory_tag_kind_t tag_kind = jit_memory_tag_kind_t::undef;
+    data_type_t data_type = data_type::undef;
+    size_t dt_size = 0;
+    unsigned el_size_of_indices = 0;
+    dim_t c_split_size = 0;
+    dim_t sp_split_size = 0;
+
+    cpu_isa_t isa = isa_undef;
+};
+
+struct jit_shuffle_call_s {
+    const void *src = nullptr;
+    void *dst = nullptr;
+    const void *input_off_ptr = nullptr;
+
+    dim_t cb_loop_size
+            = 0; // number of loop iterations over corresponding C batches
+    bool is_padded_block = false;
+};
+
+enum class binary_op_t : unsigned { none, c_blocked, n_spatial_c, n_c_spatial };
+
+enum class binary_bcast_t : unsigned {
+    none, // tensor operation
+    scalar,
+    per_batch,
+    per_c,
+    per_w
+};
+
+struct jit_binary_conf_t {
+    binary_op_t op_type = binary_op_t::none;
+    binary_bcast_t bcast_type = binary_bcast_t::none;
+    bool do_scale_src0 = false;
+    bool do_scale_src1 = false;
+    bool do_sum = false;
+    bool with_eltwise = false;
+    bool with_binary = false;
+    bool with_postops = false;
+    float sum_scale = 0.f;
+    bool use_stride_src1 = false;
+    bool broadcast_src1_value = false;
+    bool use_stride_rhs_postops = false;
+    bool postops_per_oc_broadcast_exists = false;
+    bool is_i8 = false;
+    bool is_bf16 = false;
+    bool is_src_different_layouts = false;
+    dim_t outer_dims = 1;
+    int src1_stride = 1;
+    int not_bcasted_sp_dims = 0;
+    cpu_isa_t isa = isa_undef;
+
+    data_type_t src0_type = data_type::undef;
+    data_type_t src1_type = data_type::undef;
+    data_type_t dst_type = data_type::undef;
+};
+
+struct jit_binary_call_s {
+    // keep all sizes at 8 bytes -- jit code expects this
+    const void *src0, *src1, *dst, *indices;
+    const float *scales_src0, *scales_src1;
+    size_t spat_offt_count;
+    const void *post_ops_binary_rhs_arg_vec;
+    size_t src1_stride_range;
+    const void *dst_orig;
+};
+
+} // namespace aarch64
+} // namespace cpu
+} // namespace impl
+} // namespace dnnl
+
+#endif

miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_sve_512_1x1_conv_kernel.hpp

@@ -0,0 +1,204 @@
+/*******************************************************************************
+* Copyright 2021-2023 Intel Corporation
+* Copyright 2021-2023 FUJITSU LIMITED
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef CPU_AARCH64_JIT_SVE_1x1_CONV_KERNEL_HPP
+#define CPU_AARCH64_JIT_SVE_1x1_CONV_KERNEL_HPP
+
+#include "common/c_types_map.hpp"
+#include "common/memory_tracking.hpp"
+
+#include "cpu/aarch64/injectors/jit_uni_postops_injector.hpp"
+#include "cpu/aarch64/jit_generator.hpp"
+#include "cpu/aarch64/jit_op_imm_check.hpp"
+#include "cpu/aarch64/jit_primitive_conf.hpp"
+
+using namespace Xbyak_aarch64;
+
+namespace dnnl {
+namespace impl {
+namespace cpu {
+namespace aarch64 {
+
+/* Get vector offsets, ofs / VL(VL: 512bits = 64Bytes) */
+#define VL64_OFS(ofs) ((ofs) >> 6)
+
+struct jit_sve_512_1x1_conv_kernel : public jit_generator {
+    jit_sve_512_1x1_conv_kernel(const jit_1x1_conv_conf_t &ajcp,
+            const primitive_attr_t &attr, const memory_desc_t &dst_md);
+
+    DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_sve_512_1x1_conv_kernel)
+
+    static status_t init_conf(jit_1x1_conv_conf_t &jcp,
+            const convolution_desc_t &cd, const memory_desc_wrapper &src_d,
+            const memory_desc_wrapper &weights_d,
+            const memory_desc_wrapper &dst_d, const primitive_attr_t &attr,
+            int nthreads, bool reduce_src);
+
+    static void init_scratchpad(memory_tracking::registrar_t &scratchpad,
+            const jit_1x1_conv_conf_t &jcp);
+
+    jit_1x1_conv_conf_t jcp;
+    const primitive_attr_t &attr_;
+
+private:
+    using reg64_t = const XReg;
+
+    /* Flags and loop variables */
+    reg64_t reg_reduce_pos_flag = x1;
+    reg64_t reduce_loop_iter = x2;
+    reg64_t reg_bcast_loop_iter = x3;
+    reg64_t reg_relu_ns = x20; // For forward
+    reg64_t reg_output_stride = x20; // For backward
+
+    /* Pointer */
+    reg64_t reg_bcast_data = x5; // Input
+    reg64_t reg_load_data = x6; // Weight
+    reg64_t reg_output_data = x7; // Output
+    reg64_t reg_bias_data = x8; // bias
+    reg64_t aux1_reg_bcast_data = x9;
+    reg64_t aux_reg_output_data = x10;
+    reg64_t aux_reg_bcast_data = x11;
+    reg64_t aux_reg_load_data = x12;
+    reg64_t reg_prev_bcast_addr
+            = x13; // Input: The reg keeps addr accessed by previous ldr inst
+    reg64_t reg_prev_out_addr
+            = x14; // Output: The reg keeps addr accessed by previous ldr or str inst
+
+    /* Workload */
+    reg64_t reg_load_loop_work = x15;
+    reg64_t reg_reduce_loop_work = x16;
+    reg64_t reg_bcast_loop_work = x17;
+
+    /* Temporay registers */
+    reg64_t reg_tmp_imm = x27; // tmp for add_imm
+    reg64_t reg_tmp_ofs = x19; // tmp reg to calc bwd wei offset in out_load
+
+    reg64_t reg_load_dim_tail_mask = aux_reg_load_data;
+
+    std::unique_ptr<injector::jit_uni_postops_injector_t<sve_512>>
+            postops_injector_;
+
+    constexpr static int isa_simd_width_
+            = cpu_isa_traits<sve_512>::vlen / sizeof(float);
+
+    ZReg vreg_bcast = ZReg(31);
+    PReg k_load_dim_mask = p2;
+    PReg k_load_dim_tail_mask = p3;
+    ZReg zreg_tmp = ZReg(31);
+    ZReg zreg_tmp1 = ZReg(30);
+
+    constexpr static int reg64_size_ = sizeof(int64_t);
+    constexpr static int reg_bcast_loop_work_offt = 0;
+    constexpr static int reg_binary_post_op_acc_off = 1 * reg64_size_;
+    constexpr static int reg_abi_param1_backup = 2 * reg64_size_;
+    constexpr static int stack_space_needed = 3 * reg64_size_;
+
+    template <typename T>
+    Xbyak_aarch64::XReg EVEX_compress_addr(const Xbyak_aarch64::XReg &addr,
+            const Xbyak_aarch64::XReg &x_tmp, Xbyak_aarch64::XReg base,
+            T raw_offt, bool bcast = false) {
+
+        assert(raw_offt <= INT_MAX);
+        auto offt = static_cast<int>(raw_offt);
+
+        add_imm(addr, base, offt, x_tmp);
+        if (bcast) {
+            // addr is the same as addr when bcast is false.
+        }
+        return addr;
+    }
+
+    void prefetch(
+            const std::string prfop, int level, reg64_t in, long long int ofs) {
+        bool for_load = false;
+        if (prfop == "LD") {
+            for_load = true;
+        } else if (prfop == "ST") {
+            for_load = false;
+        } else {
+            assert(!"invalid prfop");
+        }
+
+        bool cacheline_aligned = ((ofs & 0xFF) == 0) ? true : false;
+        if (cacheline_aligned == true) {
+            Prfop op;
+            switch (level) {
+                case 1: op = (for_load == true) ? PLDL1KEEP : PSTL1KEEP; break;
+                case 2: op = (for_load == true) ? PLDL2KEEP : PSTL2KEEP; break;
+                case 3: op = (for_load == true) ? PLDL3KEEP : PSTL3KEEP; break;
+                default: assert(!"invalid prfop"); break;
+            }
+
+            if (prfm_imm_check(ofs)) {
+                prfm(op, ptr(in, static_cast<int32_t>(ofs)));
+            } else {
+                add_imm(reg_tmp_ofs, in, ofs, reg_tmp_imm);
+                prfm(op, ptr(reg_tmp_ofs));
+            }
+        } else {
+            PrfopSve op_sve;
+            switch (level) {
+                case 1:
+                    op_sve = (for_load == true) ? PLDL1KEEP_SVE : PSTL1KEEP_SVE;
+                    break;
+                case 2:
+                    op_sve = (for_load == true) ? PLDL2KEEP_SVE : PSTL2KEEP_SVE;
+                    break;
+                case 3:
+                    op_sve = (for_load == true) ? PLDL3KEEP_SVE : PSTL3KEEP_SVE;
+                    break;
+                default: assert(!"invalid prfop"); break;
+            }
+
+            if (prfw_imm_check(ofs)) {
+                prfw(op_sve, P_ALL_ONE,
+                        ptr(in, static_cast<int32_t>(VL64_OFS(ofs))));
+            } else {
+                add_imm(reg_tmp_ofs, in, ofs, reg_tmp_imm);
+                prfw(op_sve, P_ALL_ONE, ptr(reg_tmp_ofs));
+            }
+        }
+    }
+
+    void bcast_loop(int load_loop_blk);
+    void reduce_loop(int load_loop_blk, int ur, int substep, bool wraparound);
+
+    void generate() override;
+    static void balance(jit_1x1_conv_conf_t &jcp);
+
+    inline size_t get_output_offset(
+            const bool is_out_layout_nxc, const int i_load, const int i_ur) {
+        const size_t i_load_shift = is_out_layout_nxc
+                ? jcp.load_block
+                : (jcp.with_dw_conv ? jcp.ow : jcp.bcast_dim) * jcp.load_block;
+        const size_t i_ur_shift
+                = is_out_layout_nxc ? jcp.load_dim : jcp.load_block;
+        return jcp.typesize_out * (i_load * i_load_shift + i_ur * i_ur_shift);
+    }
+
+    Xbyak_aarch64::XReg output_ptr(const bool out_layout_nxc, const int i_load,
+            const int i_ur, Xbyak_aarch64::XReg addr);
+    void apply_postops(const bool is_out_layout_nxc, const int load_loop_blk,
+            const int ur);
+};
+
+} // namespace aarch64
+} // namespace cpu
+} // namespace impl
+} // namespace dnnl
+
+#endif

miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_sve_512_1x1_convolution.hpp

@@ -0,0 +1,534 @@
+/*******************************************************************************
+* Copyright 2021-2023 Intel Corporation
+* Copyright 2021-2023 FUJITSU LIMITED
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef CPU_AARCH64_JIT_SVE_1X1_CONVOLUTION_HPP
+#define CPU_AARCH64_JIT_SVE_1X1_CONVOLUTION_HPP
+
+#include "common/c_types_map.hpp"
+#include "common/dnnl_thread.hpp"
+#include "common/memory_tracking.hpp"
+#include "common/primitive.hpp"
+#include "common/primitive_hashing.hpp"
+#include "common/utils.hpp"
+
+#include "cpu/cpu_convolution_pd.hpp"
+#include "cpu/dw_convolution_utils.hpp"
+#include "cpu/platform.hpp"
+
+#include "cpu/aarch64/cpu_reducer.hpp"
+#include "cpu/aarch64/jit_sve_512_1x1_conv_kernel.hpp"
+#include "cpu/aarch64/jit_uni_1x1_conv_utils.hpp"
+#include "cpu/aarch64/jit_uni_dw_convolution.hpp"
+
+namespace dnnl {
+namespace impl {
+namespace cpu {
+namespace aarch64 {
+
+template <impl::data_type_t src_type, impl::data_type_t wei_type = src_type,
+        impl::data_type_t dst_type = src_type>
+struct jit_sve_512_1x1_convolution_fwd_t : public primitive_t {
+    struct pd_t : public cpu_convolution_fwd_pd_t {
+        pd_t(const convolution_desc_t *adesc, const primitive_attr_t *attr,
+                const typename pd_t::base_class *hint_fwd_pd)
+            : cpu_convolution_fwd_pd_t(adesc, attr, hint_fwd_pd)
+            , jcp_()
+            , rtus_() {}
+        pd_t(const pd_t &other) : cpu_convolution_fwd_pd_t(other) {
+            if (copy(other) != status::success) is_initialized_ = false;
+        }
+
+        DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("jit_1x1:", sve_512, ""),
+                jit_sve_512_1x1_convolution_fwd_t);
+
+        status_t init(engine_t *engine) {
+            using namespace utils;
+
+            bool ok = true && is_fwd()
+                    && set_default_alg_kind(alg_kind::convolution_direct)
+                    && expect_data_types(src_type, wei_type, dst_type, dst_type,
+                            data_type::undef)
+                    && attr()->has_default_values(
+                            primitive_attr_t::skip_mask_t::post_ops, dst_type)
+                    && !has_zero_dim_memory() && set_default_formats()
+                    && attr_.set_default_formats(dst_md(0)) == status::success;
+            if (!ok) return status::unimplemented;
+
+            const convolution_desc_t *conv_d = desc();
+            const memory_desc_t *src_d = src_md();
+            rtus_prepare(this, conv_d, src_d, dst_md());
+
+            CHECK(jit_sve_512_1x1_conv_kernel::init_conf(jcp_, *conv_d, *src_d,
+                    *weights_md(), *dst_md(), *attr(), dnnl_get_max_threads(),
+                    rtus_.reduce_src_));
+            if (jcp_.with_dw_conv) CHECK(depthwise_po_init(engine));
+
+            auto scratchpad = scratchpad_registry().registrar();
+            jit_sve_512_1x1_conv_kernel::init_scratchpad(scratchpad, jcp_);
+
+            rtus_prepare_space_info(this, scratchpad, jcp_.nthr);
+
+            return status::success;
+        }
+
+        const memory_desc_t *dst_md(
+                int index = 0, bool user_input = false) const override {
+            return jcp_.with_dw_conv
+                    ? dw_conv_pd_->dst_md(index, user_input)
+                    : cpu_convolution_fwd_pd_t::dst_md(index, user_input);
+        }
+
+        const memory_desc_t *arg_md(
+                int arg, bool user_input = false) const override {
+            if (jcp_.with_dw_conv) {
+                switch (arg) {
+                    case DNNL_ARG_ATTR_POST_OP_DW | DNNL_ARG_SRC:
+                        return cpu_convolution_fwd_pd_t::dst_md(0, user_input);
+                    case DNNL_ARG_ATTR_POST_OP_DW | DNNL_ARG_WEIGHTS:
+                        return dw_conv_pd_->weights_md(0);
+                    case DNNL_ARG_ATTR_POST_OP_DW | DNNL_ARG_BIAS:
+                        return dw_conv_pd_->weights_md(1);
+                    default: break;
+                }
+            }
+            return convolution_fwd_pd_t::arg_md(arg, user_input);
+        }
+
+        arg_usage_t arg_usage(int arg) const override {
+            if (arg == (DNNL_ARG_ATTR_POST_OP_DW | DNNL_ARG_WEIGHTS))
+                return arg_usage_t::input;
+
+            if (arg == (DNNL_ARG_ATTR_POST_OP_DW | DNNL_ARG_BIAS)
+                    && attr_post_op_dw_inputs() > 1)
+                return arg_usage_t::input;
+
+            return convolution_fwd_pd_t::arg_usage(arg);
+        }
+
+        jit_1x1_conv_conf_t jcp_;
+        reduce_to_unit_stride_t rtus_;
+        using dw_pd_t = jit_sve_512_dw_convolution_fwd_t::pd_t;
+        std::unique_ptr<dw_pd_t> dw_conv_pd_;
+
+    protected:
+        bool set_default_formats() {
+            using namespace format_tag;
+
+            const memory_desc_wrapper src_d(&src_md_);
+            const memory_desc_wrapper dst_d(&dst_md_);
+
+            const auto dat_tag_nxc = utils::pick(ndims() - 3, nwc, nhwc, ndhwc);
+            const auto dat_tag_nCx16c
+                    = utils::pick(ndims() - 3, nCw16c, nChw16c, nCdhw16c);
+            const auto curr_src_tag
+                    = src_d.matches_one_of_tag(dat_tag_nxc, dat_tag_nCx16c);
+            const auto curr_dst_tag
+                    = dst_d.matches_one_of_tag(dat_tag_nxc, dat_tag_nCx16c);
+            const auto is_data_layout_nxc
+                    = IMPLICATION(curr_src_tag != dat_tag_nxc,
+                              src_d.format_kind() == format_kind::any)
+                    && IMPLICATION(curr_dst_tag != dat_tag_nxc,
+                            dst_d.format_kind() == format_kind::any)
+                    && utils::one_of(dat_tag_nxc, curr_src_tag, curr_dst_tag);
+            auto dat_tag = is_data_layout_nxc ? dat_tag_nxc : dat_tag_nCx16c;
+            auto wei_tag = utils::pick(2 * ndims() - 6 + with_groups(),
+                    OIw16i16o, gOIw16i16o, OIhw16i16o, gOIhw16i16o, OIdhw16i16o,
+                    gOIdhw16i16o);
+
+            return set_default_formats_common(dat_tag, wei_tag, dat_tag);
+        }
+        status_t copy(const pd_t &other) {
+            jcp_ = other.jcp_;
+            rtus_ = other.rtus_;
+            if (other.dw_conv_pd_) {
+                dw_conv_pd_.reset(other.dw_conv_pd_->clone());
+                if (!dw_conv_pd_) return status::out_of_memory;
+            }
+            return status::success;
+        }
+
+        status_t depthwise_po_init(engine_t *engine) {
+
+            using namespace memory_tracking;
+            auto &jcp_1x1 = jcp_;
+            primitive_attr_t attr_1x1(*attr());
+            if (!attr_1x1.is_initialized()) return status::out_of_memory;
+            const auto &src_md = dst_md_;
+            const memory_desc_wrapper src_d(src_md);
+            const auto nthr = dnnl_get_max_threads();
+            auto l2_cache = platform::get_per_core_cache_size(2) * nthr;
+
+            // Note: A robust fusion implementation would be to check if both
+            // 1x1 conv and dw conv that are considered here for fusion are
+            // optimal independently. This would require creating a new
+            // primitive_desc through primitive_iterator & check if they match.
+            // Due to concern that these creations and/or checks could be heavy,
+            // for 1x1: Check that no better ISA is available.
+            // for dw: Always fuse with same ISA.
+            // Caveat: May be a better dw conv exists.
+
+            // TODO: Add a check if better ISA exists following above note.
+            bool ok = true
+                    && (attr_1x1.post_ops_.find(primitive_kind::sum) == -1)
+                    // TODO: Below may be further tuned.
+                    && (l2_cache * 2 < src_d.size())
+                    // load_grp_count check can be redundant due to l2 check
+                    // above. Adding it explicitly as the current driver doesn't
+                    // work if this condition fails.
+                    && (jcp_1x1.load_grp_count < 2);
+            if (!ok) return status::unimplemented;
+
+            int dw_po_index
+                    = attr_1x1.post_ops_.find(primitive_kind::convolution);
+            convolution_desc_t cd_dw;
+            primitive_attr_t attr_dw;
+            CHECK(get_depthwise_conv_desc(
+                    cd_dw, src_md, attr_1x1, attr_dw, dw_po_index));
+
+            CHECK(safe_ptr_assign(
+                    dw_conv_pd_, new dw_pd_t(&cd_dw, &attr_dw, nullptr)));
+            CHECK(dw_conv_pd_->init(engine));
+            auto &jcp_dw = dw_conv_pd_->jcp_;
+
+            ok = true
+                    && (dnnl_memory_desc_equal(&src_md, dw_conv_pd_->src_md(0)))
+                    && (jcp_1x1.oc_without_padding % jcp_1x1.oc_block == 0)
+                    && IMPLICATION(
+                            jcp_dw.ow_block, jcp_dw.ow_block == jcp_dw.ow);
+            if (!ok) return status::unimplemented;
+
+            assert(dw_conv_pd_->dst_md(0)->format_kind != format_kind::any);
+            assert(dw_conv_pd_->weights_md(0)->format_kind != format_kind::any);
+            assert(IMPLICATION(
+                    dw_conv_pd_->weights_md(1)->data_type != data_type::undef,
+                    dw_conv_pd_->weights_md(1)->format_kind
+                            != format_kind::any));
+
+            jcp_dw.is_fused_conv = true;
+            // TODO: Support/experiment arbitary oc_work in dw conv.
+            // Until then we keep oc_work perfectly divisible.
+            while (jcp_1x1.nb_load % jcp_1x1.nb_load_blocking != 0)
+                --jcp_1x1.nb_load_blocking;
+            jcp_1x1.nb_load_blocking_max = jcp_1x1.nb_load_blocking;
+
+            while (jcp_1x1.nb_load_blocking % jcp_dw.nb_ch_blocking != 0)
+                --jcp_dw.nb_ch_blocking;
+
+            jcp_dw.dw_conv_buffer_oc
+                    = jcp_1x1.nb_load_blocking * jcp_1x1.oc_block;
+
+            const auto dat_tag_nxc = utils::pick(ndims() - 3, format_tag::nwc,
+                    format_tag::nhwc, format_tag::ndhwc);
+            const bool is_data_nxc = utils::everyone_is(
+                    dat_tag_nxc, jcp_1x1.src_tag, jcp_1x1.dst_tag);
+            if (!is_data_nxc)
+                jcp_1x1.bcast_loop_output_step = jcp_1x1.ur * jcp_1x1.load_block
+                        * jcp_1x1.typesize_out;
+
+            registrar_t scratchpad(scratchpad_registry_);
+            registrar_t dw_scratchpad(scratchpad, names::prefix_fusion);
+
+            size_t dw_conv_buffer_size_ = (size_t)nthr * jcp_dw.kh * jcp_dw.iw
+                    * jcp_dw.dw_conv_buffer_oc;
+            assert(dw_conv_buffer_size_);
+            dw_scratchpad.book(memory_tracking::names::key_fusion_inout_buffer,
+                    dw_conv_buffer_size_,
+                    types::data_type_size(dw_conv_pd_->src_md()->data_type));
+
+            jit_uni_dw_conv_fwd_kernel<sve_512,
+                    data_type::f32>::init_scratchpad(dw_scratchpad, jcp_dw);
+
+            return status::success;
+        }
+    };
+
+    template <cpu_isa_t isa, typename conv_t>
+    friend status_t init_rtus_driver(conv_t *self);
+
+    jit_sve_512_1x1_convolution_fwd_t(const pd_t *apd) : primitive_t(apd) {}
+
+    typedef typename prec_traits<src_type>::type src_data_t;
+    typedef typename prec_traits<wei_type>::type wei_data_t;
+    typedef typename prec_traits<dst_type>::type dst_data_t;
+
+    status_t init(engine_t *engine) override {
+        CHECK(safe_ptr_assign(kernel_,
+                new jit_sve_512_1x1_conv_kernel(
+                        pd()->jcp_, *pd()->attr(), *pd()->dst_md(0))));
+        CHECK(kernel_->create_kernel());
+
+        if (pd()->jcp_.with_dw_conv) {
+            CHECK(safe_ptr_assign(
+                    kernel_dw_, new dw_conv_kernel_t(pd()->dw_conv_pd_->jcp_)));
+            CHECK(kernel_dw_->create_kernel());
+        }
+
+        CHECK(init_rtus_driver<sve_512>(this));
+        return status::success;
+    }
+
+    status_t execute(const exec_ctx_t &ctx) const override {
+        execute_forward(ctx);
+        return status::success;
+    }
+
+private:
+    void execute_forward(const exec_ctx_t &ctx) const;
+    void execute_forward_thr(const int ithr, const int nthr,
+            const src_data_t *src, const wei_data_t *weights,
+            const dst_data_t *bias, const wei_data_t *weights_dw,
+            const dst_data_t *bias_dw, dst_data_t *dst,
+            const memory_tracking::grantor_t &scratchpad,
+            const void *post_ops_binary_rhs_arg_vec,
+            const void *post_ops_binary_rhs_arg_vec_dw) const;
+    const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); }
+
+    std::unique_ptr<jit_sve_512_1x1_conv_kernel> kernel_;
+    std::unique_ptr<rtus_driver_t<sve_512>> rtus_driver_;
+    using dw_conv_kernel_t = jit_uni_dw_conv_fwd_kernel_f32<sve_512>;
+    std::unique_ptr<dw_conv_kernel_t> kernel_dw_;
+};
+
+using jit_sve_512_1x1_convolution_fwd_f32_t
+        = jit_sve_512_1x1_convolution_fwd_t<data_type::f32>;
+
+template <impl::data_type_t diff_dst_type,
+        impl::data_type_t wei_type = diff_dst_type,
+        impl::data_type_t diff_src_type = diff_dst_type>
+struct jit_sve_512_1x1_convolution_bwd_data_t : public primitive_t {
+    struct pd_t : public cpu_convolution_bwd_data_pd_t {
+        pd_t(const convolution_desc_t *adesc, const primitive_attr_t *attr,
+                const convolution_fwd_pd_t *hint_fwd_pd)
+            : cpu_convolution_bwd_data_pd_t(adesc, attr, hint_fwd_pd)
+            , jcp_()
+            , rtus_() {}
+        DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("jit_1x1:", sve_512, ""),
+                jit_sve_512_1x1_convolution_bwd_data_t);
+
+        status_t init(engine_t *engine) {
+            bool ok = true && desc()->prop_kind == prop_kind::backward_data
+                    && set_default_alg_kind(alg_kind::convolution_direct)
+                    && expect_data_types(diff_src_type, wei_type,
+                            data_type::undef, diff_dst_type, data_type::undef)
+                    && attr()->has_default_values() && !has_zero_dim_memory()
+                    && set_default_formats();
+            if (!ok) return status::unimplemented;
+
+            const convolution_desc_t *conv_d = desc();
+            const memory_desc_t *diff_src_d = diff_src_md();
+            rtus_prepare(this, conv_d, diff_src_d, diff_dst_md());
+
+            status_t status = jit_sve_512_1x1_conv_kernel::init_conf(jcp_,
+                    *conv_d, *diff_src_d, *weights_md(), *diff_dst_md(),
+                    *attr(), dnnl_get_max_threads(), rtus_.reduce_src_);
+            if (status != status::success) return status;
+
+            auto scratchpad = scratchpad_registry().registrar();
+            jit_sve_512_1x1_conv_kernel::init_scratchpad(scratchpad, jcp_);
+
+            rtus_prepare_space_info(this, scratchpad, jcp_.nthr);
+
+            return status::success;
+        }
+
+        // TODO (Roma): structs conf header cleanup
+        jit_1x1_conv_conf_t jcp_;
+        reduce_to_unit_stride_t rtus_;
+
+    protected:
+        bool set_default_formats() {
+            using namespace format_tag;
+
+            const memory_desc_wrapper diff_src_d(&diff_src_md_);
+            const memory_desc_wrapper diff_dst_d(&diff_dst_md_);
+
+            const auto dat_tag_nxc = utils::pick(ndims() - 3, nwc, nhwc, ndhwc);
+            const auto dat_tag_nCx16c
+                    = utils::pick(ndims() - 3, nCw16c, nChw16c, nCdhw16c);
+            const auto curr_src_tag = diff_src_d.matches_one_of_tag(
+                    dat_tag_nxc, dat_tag_nCx16c);
+            const auto curr_dst_tag = diff_dst_d.matches_one_of_tag(
+                    dat_tag_nxc, dat_tag_nCx16c);
+            const auto is_data_layout_nxc
+                    = IMPLICATION(curr_src_tag != dat_tag_nxc,
+                              diff_src_d.format_kind() == format_kind::any)
+                    && IMPLICATION(curr_dst_tag != dat_tag_nxc,
+                            diff_dst_d.format_kind() == format_kind::any)
+                    && utils::one_of(dat_tag_nxc, curr_src_tag, curr_dst_tag);
+            auto dat_tag = is_data_layout_nxc ? dat_tag_nxc : dat_tag_nCx16c;
+            auto wei_tag = utils::pick(2 * ndims() - 6 + with_groups(),
+                    IOw16o16i, gIOw16o16i, IOhw16o16i, gIOhw16o16i, IOdhw16o16i,
+                    gIOdhw16o16i);
+
+            return set_default_formats_common(dat_tag, wei_tag, dat_tag);
+        }
+    };
+
+    template <cpu_isa_t isa, typename conv_t>
+    friend status_t init_rtus_driver(conv_t *self);
+
+    jit_sve_512_1x1_convolution_bwd_data_t(const pd_t *apd)
+        : primitive_t(apd) {}
+
+    typedef typename prec_traits<diff_dst_type>::type diff_dst_data_t;
+    typedef typename prec_traits<wei_type>::type wei_data_t;
+    typedef typename prec_traits<diff_src_type>::type diff_src_data_t;
+
+    status_t init(engine_t *engine) override {
+        CHECK(safe_ptr_assign(kernel_,
+                new jit_sve_512_1x1_conv_kernel(
+                        pd()->jcp_, *pd()->attr(), *pd()->dst_md(0))));
+        CHECK(kernel_->create_kernel());
+        CHECK(init_rtus_driver<sve_512>(this));
+        return status::success;
+    }
+
+    status_t execute(const exec_ctx_t &ctx) const override {
+        execute_backward_data(ctx);
+        return status::success;
+    }
+
+private:
+    void execute_backward_data(const exec_ctx_t &ctx) const;
+    const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); }
+    std::unique_ptr<jit_sve_512_1x1_conv_kernel> kernel_;
+    std::unique_ptr<rtus_driver_t<sve_512>> rtus_driver_;
+};
+
+using jit_sve_512_1x1_convolution_bwd_data_f32_t
+        = jit_sve_512_1x1_convolution_bwd_data_t<data_type::f32>;
+
+/* Backward weight */
+struct jit_sve_512_1x1_convolution_bwd_weights_t : public primitive_t {
+    struct pd_t : public cpu_convolution_bwd_weights_pd_t {
+        pd_t(const convolution_desc_t *adesc, const primitive_attr_t *attr,
+                const convolution_fwd_pd_t *hint_fwd_pd)
+            : cpu_convolution_bwd_weights_pd_t(adesc, attr, hint_fwd_pd)
+            , jcp_()
+            , rtus_() {}
+
+        DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("jit_1x1:", sve_512, ""),
+                jit_sve_512_1x1_convolution_bwd_weights_t);
+
+        status_t init(engine_t *engine) {
+            bool ok = true && desc()->prop_kind == prop_kind::backward_weights
+                    && set_default_alg_kind(alg_kind::convolution_direct)
+                    && expect_data_types(data_type::f32, data_type::f32,
+                            data_type::f32, data_type::f32, data_type::f32)
+                    && attr()->has_default_values() && !has_zero_dim_memory()
+                    && set_default_formats();
+            if (!ok) return status::unimplemented;
+
+            const convolution_desc_t *conv_d = desc();
+            const memory_desc_t *src_d = src_md();
+            rtus_prepare(this, conv_d, src_d, diff_dst_md());
+
+            status_t status = jit_sve_512_1x1_conv_kernel::init_conf(jcp_,
+                    *conv_d, *src_d, *diff_weights_md(), *diff_dst_md(),
+                    *attr(), dnnl_get_max_threads(), rtus_.reduce_src_);
+            if (status != status::success) return status;
+
+            init_balancers();
+
+            auto scratchpad = scratchpad_registry().registrar();
+            jit_sve_512_1x1_conv_kernel::init_scratchpad(scratchpad, jcp_);
+
+            auto reducer_bia_scratchpad = memory_tracking::registrar_t(
+                    scratchpad, memory_tracking::names::prefix_reducer_bia);
+            reducer_bia_conf_.init_scratchpad(reducer_bia_scratchpad);
+            rtus_prepare_space_info(this, scratchpad, jcp_.nthr);
+
+            return status::success;
+        }
+
+        // TODO (Roma): structs conf header cleanup
+        jit_1x1_conv_conf_t jcp_;
+        cpu_reducer_t<data_type::f32>::conf_t reducer_bia_conf_;
+        reduce_to_unit_stride_t rtus_;
+
+    protected:
+        bool set_default_formats() {
+            using namespace format_tag;
+
+            const memory_desc_wrapper src_d(&src_md_);
+            const memory_desc_wrapper diff_dst_d(&diff_dst_md_);
+
+            const auto dat_tag_nxc = utils::pick(ndims() - 3, nwc, nhwc, ndhwc);
+            const auto dat_tag_nCx16c
+                    = utils::pick(ndims() - 3, nCw16c, nChw16c, nCdhw16c);
+            const auto curr_src_tag
+                    = src_d.matches_one_of_tag(dat_tag_nxc, dat_tag_nCx16c);
+            const auto curr_dst_tag = diff_dst_d.matches_one_of_tag(
+                    dat_tag_nxc, dat_tag_nCx16c);
+            const auto is_data_layout_nxc
+                    = IMPLICATION(curr_src_tag != dat_tag_nxc,
+                              src_d.format_kind() == format_kind::any)
+                    && IMPLICATION(curr_dst_tag != dat_tag_nxc,
+                            diff_dst_d.format_kind() == format_kind::any)
+                    && utils::one_of(dat_tag_nxc, curr_src_tag, curr_dst_tag);
+
+            auto dat_tag = is_data_layout_nxc ? dat_tag_nxc : dat_tag_nCx16c;
+            auto wei_tag = utils::pick(2 * ndims() - 6 + with_groups(),
+                    OIw16i16o, gOIw16i16o, OIhw16i16o, gOIhw16i16o, OIdhw16i16o,
+                    gOIdhw16i16o);
+
+            return set_default_formats_common(dat_tag, wei_tag, dat_tag);
+        }
+
+    private:
+        void init_balancers() {
+            const size_t max_buffer_size = jcp_.nthr * 3 * 5 * 5 * 16 * 16;
+            if (with_bias()) {
+                reducer_bia_conf_.init(reduce_balancer_t(jcp_.nthr,
+                        jcp_.oc_block, jcp_.ngroups * jcp_.nb_load, jcp_.mb,
+                        max_buffer_size, true));
+            }
+        }
+    };
+
+    template <cpu_isa_t isa, typename conv_t>
+    friend status_t init_rtus_driver(conv_t *self);
+
+    jit_sve_512_1x1_convolution_bwd_weights_t(const pd_t *apd)
+        : primitive_t(apd) {}
+
+    typedef typename prec_traits<data_type::f32>::type data_t;
+
+    status_t init(engine_t *engine) override;
+
+    status_t execute(const exec_ctx_t &ctx) const override {
+        execute_backward_weights(ctx);
+        return status::success;
+    }
+
+private:
+    void execute_backward_weights(const exec_ctx_t &ctx) const;
+    const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); }
+
+    std::unique_ptr<jit_sve_512_1x1_conv_kernel> kernel_;
+    std::unique_ptr<cpu_accumulator_1d_t<data_type::f32>> acc_ker_;
+    std::unique_ptr<cpu_reducer_t<data_type::f32>> reducer_bias_;
+    // std::unique_ptr<jit_transpose4x16_src> trans_kernel_;
+    std::unique_ptr<rtus_driver_t<sve_512>> rtus_driver_;
+};
+
+} // namespace aarch64
+} // namespace cpu
+} // namespace impl
+} // namespace dnnl
+
+#endif

miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_sve_512_conv_kernel.hpp

@@ -0,0 +1,602 @@
+/*******************************************************************************
+* Copyright 2020-2022 Intel Corporation
+* Copyright 2020-2022 FUJITSU LIMITED
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef CPU_AARCH64_JIT_SVE_CONV_KERNEL_HPP
+#define CPU_AARCH64_JIT_SVE_CONV_KERNEL_HPP
+
+#include "common/c_types_map.hpp"
+#include "common/memory_tracking.hpp"
+
+#include "cpu/aarch64/jit_generator.hpp"
+#include "cpu/aarch64/jit_primitive_conf.hpp"
+
+#include "cpu/aarch64/injectors/jit_uni_eltwise_injector.hpp"
+
+#include "cpu/aarch64/jit_op_imm_check.hpp"
+
+#define LDRWMAX 252
+#define ADDMAX 4095
+/* Get vector offsets, ofs / VL(VL: 512bits = 64Bytes) */
+#define VL_OFS(ofs) ((ofs) >> 6)
+
+using namespace Xbyak_aarch64;
+
+namespace dnnl {
+namespace impl {
+namespace cpu {
+namespace aarch64 {
+
+struct jit_sve_512_conv_fwd_kernel : public jit_generator {
+
+    jit_sve_512_conv_fwd_kernel(
+            const jit_conv_conf_t &ajcp, const primitive_attr_t &attr)
+        : jcp(ajcp), attr_(attr), eltwise_injector_(nullptr) {
+
+        if (jcp.with_eltwise)
+            eltwise_injector_ = new jit_uni_eltwise_injector_f32<sve_512>(
+                    this, jcp.eltwise);
+    }
+
+    ~jit_sve_512_conv_fwd_kernel() { delete eltwise_injector_; }
+
+    DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_sve_512_conv_fwd_kernel)
+
+    jit_conv_conf_t jcp;
+    const primitive_attr_t &attr_;
+
+    static bool post_ops_ok(jit_conv_conf_t &jcp, const primitive_attr_t &attr);
+    static status_t init_conf(jit_conv_conf_t &jcp,
+            const convolution_desc_t &cd, memory_desc_t &src_pd,
+            memory_desc_t &weights_pd, memory_desc_t &dst_pd,
+            memory_desc_t &bias_pd, const primitive_attr_t &attr, int nthreads);
+    static void init_scratchpad(memory_tracking::registrar_t &scratchpad,
+            const jit_conv_conf_t &jcp);
+
+private:
+    using reg64_t = const XReg;
+    enum {
+        typesize = sizeof(float),
+        ker_reg_base_idx = 28,
+    };
+
+    reg64_t param = abi_param1;
+    reg64_t reg_inp = x1; // src base addr (2d)
+    reg64_t reg_ker = x2; // ker base addr (2d)
+    reg64_t aux_reg_ker_d = x2; // ker addr (3d)
+    reg64_t reg_out = x3; // dst base addr (2d)
+    reg64_t reg_ki = x3; // d-dim loop var? (3d)
+    reg64_t reg_owb = x5; // num of ow-block
+    reg64_t reg_out_prf = x6; // addr for prefetch
+
+    reg64_t aux_reg_inp = x7; // src addr (main loop)
+    reg64_t aux_reg_inp2 = x24; // src addr (main loop)
+    reg64_t aux_reg_inp3 = x25; // src addr (main loop)
+    reg64_t reg_out_ofs = x7; // dst addr (store_output)
+    reg64_t aux_reg_ker = x8; // ker addr (main loop)
+    reg64_t reg_channel = x9; // reduce workload
+    reg64_t reg_bias = x10; // bias addr (prepare_out)
+
+    reg64_t aux_reg_inp_d = x11; // src addr (3d)
+    reg64_t reg_oi = x11;
+
+    reg64_t reg_kh = x12; // ker h size
+    reg64_t reg_kj = x13; // ker h workload
+
+    /* Temporary registers for ARM insts */
+    reg64_t reg_tmp_addr = x14;
+    reg64_t reg_prev_bcast_addr = x15;
+    reg64_t reg_prev_wei_addr = x16;
+    reg64_t reg_tmp_imm = x17;
+
+    reg64_t reg_out_org = x27; // dst base addr (3d)
+    reg64_t reg_oi_org = x19; // base oi (3d)
+    reg64_t aux_reg_ker_d_org = x20;
+    reg64_t reg_ker_org = x21; // ker base addr (3d)
+    reg64_t reg_inp_org = x29; // src base addr (3d)
+
+    void prefetch(
+            const std::string prfop, int level, reg64_t in, long long int ofs) {
+        bool for_load = false;
+        if (prfop == "LD") {
+            for_load = true;
+        } else if (prfop == "ST") {
+            for_load = false;
+        } else {
+            assert(!"invalid prfop");
+        }
+
+        bool cacheline_aligned = ((ofs & 0xFF) == 0) ? true : false;
+        if (cacheline_aligned == true) {
+            Prfop op = PLDL1KEEP;
+            switch (level) {
+                case 1: op = (for_load == true) ? PLDL1KEEP : PSTL1KEEP; break;
+                case 2: op = (for_load == true) ? PLDL2KEEP : PSTL2KEEP; break;
+                case 3: op = (for_load == true) ? PLDL3KEEP : PSTL3KEEP; break;
+                default: assert(!"invalid prfop"); break;
+            }
+
+            if ((ofs <= PRFMMAX) && (ofs >= 0)) {
+                prfm(op, ptr(in, static_cast<int32_t>(ofs)));
+            } else {
+                add_imm(reg_tmp_addr, in, ofs, reg_tmp_imm);
+                prfm(op, ptr(reg_tmp_addr));
+            }
+        } else {
+            PrfopSve op_sve = PLDL1KEEP_SVE;
+            switch (level) {
+                case 1:
+                    op_sve = (for_load == true) ? PLDL1KEEP_SVE : PSTL1KEEP_SVE;
+                    break;
+                case 2:
+                    op_sve = (for_load == true) ? PLDL2KEEP_SVE : PSTL2KEEP_SVE;
+                    break;
+                case 3:
+                    op_sve = (for_load == true) ? PLDL3KEEP_SVE : PSTL3KEEP_SVE;
+                    break;
+                default: assert(!"invalid level"); break;
+            }
+
+            if ((VL_OFS(ofs) <= PRFWMAX)
+                    && (VL_OFS(ofs) >= (-1 * PRFWMAX - 1))) {
+                prfw(op_sve, P_ALL_ONE,
+                        ptr(in, static_cast<int32_t>(VL_OFS(ofs))));
+            } else {
+                add_imm(reg_tmp_addr, in, ofs, reg_tmp_imm);
+                prfw(op_sve, P_ALL_ONE, ptr(reg_tmp_addr));
+            }
+        }
+    }
+
+    jit_uni_eltwise_injector_f32<sve_512> *eltwise_injector_;
+
+    inline void prepare_output(int ur_w);
+    inline void store_output(int ur_w);
+    inline void compute_loop_fma_core(int ur_w, int pad_l, int pad_r);
+    inline void compute_loop(int ur_w, int pad_l, int pad_r);
+
+    void generate() override;
+
+    inline size_t get_output_offset(int oi, int n_oc_block) {
+        const bool is_nxc_layout = is_dst_layout_nxc();
+        size_t ow_str = is_nxc_layout ? jcp.ngroups * jcp.oc : jcp.oc_block;
+        size_t ocb_str = is_nxc_layout
+                ? jcp.oc_block
+                : (size_t)jcp.od * jcp.oh * jcp.ow * jcp.oc_block;
+
+        return jcp.typesize_out * (n_oc_block * ocb_str + oi * ow_str);
+    }
+
+    inline size_t get_input_offset(int ki, int ic, int oi, int pad_l) {
+        const bool is_nxc_layout = is_src_layout_nxc();
+        size_t iw_str = is_nxc_layout ? jcp.ngroups * jcp.ic
+                                      : (!jcp.is_1stconv ? jcp.ic_block : 1);
+        size_t ic_str = !jcp.is_1stconv || is_nxc_layout
+                ? 1
+                : (size_t)jcp.iw * jcp.ih * jcp.id;
+        size_t iw_idx = ki * (jcp.dilate_w + 1) + oi * jcp.stride_w - pad_l;
+
+        return jcp.typesize_in * (iw_idx * iw_str + ic * ic_str);
+    }
+
+    inline int get_kernel_offset(
+            int ki, int ic, int n_oc_block, int ker_number) {
+        return jcp.typesize_in * jcp.oc_block
+                * (n_oc_block * jcp.nb_ic * jcp.ic_block * jcp.kh * jcp.kw
+                                * jcp.kd
+                        + (ic + ker_number) + ki * jcp.ic_block);
+    }
+
+    inline int get_ow_start(int ki, int pad_l) {
+        return nstl::max(0,
+                utils::div_up(pad_l - ki * (jcp.dilate_w + 1), jcp.stride_w));
+    }
+
+    inline int get_ow_end(int ur_w, int ki, int pad_r) {
+        return ur_w
+                - nstl::max(0,
+                        utils::div_up(
+                                pad_r - (jcp.kw - 1 - ki) * (jcp.dilate_w + 1),
+                                jcp.stride_w));
+    }
+    inline bool is_src_layout_nxc() {
+        return utils::one_of(jcp.src_tag, format_tag::ndhwc, format_tag::nhwc,
+                format_tag::nwc);
+    }
+    inline bool is_dst_layout_nxc() {
+        return utils::one_of(jcp.dst_tag, format_tag::ndhwc, format_tag::nhwc,
+                format_tag::nwc);
+    }
+};
+
+struct jit_sve_512_conv_bwd_data_kernel_f32 : public jit_generator {
+
+    jit_sve_512_conv_bwd_data_kernel_f32(const jit_conv_conf_t &ajcp)
+        : jcp(ajcp) {}
+
+    DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_sve_512_conv_bwd_data_kernel_f32)
+    jit_conv_conf_t jcp;
+    void (*jit_ker_)(jit_conv_call_s *);
+
+    static status_t init_conf(jit_conv_conf_t &jcp,
+            const convolution_desc_t &cd, memory_desc_t &diff_src_d,
+            memory_desc_t &weights_d, memory_desc_t &diff_dst_d, int nthreads);
+    static void init_scratchpad(memory_tracking::registrar_t &scratchpad,
+            const jit_conv_conf_t &jcp);
+
+private:
+    using reg64_t = const XReg;
+    enum {
+        typesize = sizeof(float),
+    };
+    int ker_reg_base_idx = (jcp.nb_ic_blocking == 1) ? 16 : 24;
+
+    reg64_t param = abi_param1;
+    reg64_t reg_dst = x1;
+    reg64_t reg_ker = x2;
+    reg64_t reg_src = x3;
+
+    reg64_t reg_dst_prf = x23;
+    reg64_t reg_ker_prf = x5;
+    reg64_t reg_src_prf = x6;
+    reg64_t reg_iwb = x24;
+
+    reg64_t aux_reg_dst = x7;
+    reg64_t aux_reg_ker = x8;
+
+    reg64_t aux_reg_dst_prf = x9;
+    reg64_t aux_reg_ker_prf = x10;
+
+    reg64_t aux_reg_dst_d_prf = x6;
+    reg64_t aux_reg_dst_d = x11;
+    reg64_t aux_reg_ker_d_prf = x12;
+    reg64_t aux_reg_ker_d = x2;
+    reg64_t reg_ki = x3;
+
+    reg64_t reg_kj = x13;
+    reg64_t reg_oi = x11;
+    reg64_t reg_kh = x12;
+
+    reg64_t reg_channel = x9;
+
+    reg64_t reg_tmp = x14;
+    reg64_t reg_long_offt = x7;
+
+    /* Temporary registers for ARM insts */
+    reg64_t reg_prev_bcast_addr = x15;
+    reg64_t reg_prev_bcast_addr2 = x17;
+    reg64_t reg_prev_bcast_addr3 = x21;
+    reg64_t reg_tmp_imm = x16;
+    reg64_t reg_tmp_addr = x27;
+
+    reg64_t reg_src_prf_org = x19;
+    reg64_t reg_src_org = x20;
+    reg64_t reg_oi_org = x25;
+    reg64_t reg_dst_org = x22;
+    reg64_t reg_ker_org = x26;
+    reg64_t reg_input_org = x22;
+    reg64_t reg_kernel_org = x26;
+
+    long long int prefetch(const std::string prfop, int level, reg64_t in,
+            long long int ofs, long long int prev_ofs) {
+        bool for_load = false;
+        if (prfop == "LD") {
+            for_load = true;
+        } else if (prfop == "ST") {
+            for_load = false;
+        } else {
+            assert(!"invalid prfop");
+        }
+
+        bool cacheline_aligned = ((ofs & 0xFF) == 0) ? true : false;
+        if (cacheline_aligned == true) {
+            Prfop op = PLDL1KEEP;
+            switch (level) {
+                case 1: op = (for_load == true) ? PLDL1KEEP : PSTL1KEEP; break;
+                case 2: op = (for_load == true) ? PLDL2KEEP : PSTL2KEEP; break;
+                case 3: op = (for_load == true) ? PLDL3KEEP : PSTL3KEEP; break;
+                default: assert(!"invalid prfop"); break;
+            }
+
+            long long int tmp_ofs = ofs - prev_ofs;
+            if ((ofs <= PRFMMAX) && (ofs >= 0)) {
+                prfm(op, ptr(in, static_cast<int32_t>(ofs)));
+            } else if ((tmp_ofs <= PRFMMAX) && (tmp_ofs >= 0)) {
+                prfm(op, ptr(reg_tmp_addr, static_cast<int32_t>(tmp_ofs)));
+            } else {
+                add_imm(reg_tmp_addr, in, ofs, reg_tmp_imm);
+                prfm(op, ptr(reg_tmp_addr));
+                prev_ofs = ofs;
+            }
+        } else {
+            PrfopSve op_sve = PLDL1KEEP_SVE;
+            switch (level) {
+                case 1:
+                    op_sve = (for_load == true) ? PLDL1KEEP_SVE : PSTL1KEEP_SVE;
+                    break;
+                case 2:
+                    op_sve = (for_load == true) ? PLDL2KEEP_SVE : PSTL2KEEP_SVE;
+                    break;
+                case 3:
+                    op_sve = (for_load == true) ? PLDL3KEEP_SVE : PSTL3KEEP_SVE;
+                    break;
+                default: assert(!"invalid prfop"); break;
+            }
+
+            long long int tmp_ofs = ofs - prev_ofs;
+            if ((VL_OFS(ofs) <= PRFWMAX)
+                    && (VL_OFS(ofs) >= (-1 * PRFWMAX - 1))) {
+                prfw(op_sve, P_ALL_ONE,
+                        ptr(in, static_cast<int32_t>(VL_OFS(ofs))));
+            } else if ((VL_OFS(tmp_ofs) <= PRFWMAX)
+                    && (VL_OFS(tmp_ofs) >= (-1 * PRFWMAX - 1))) {
+                prfw(op_sve, P_ALL_ONE,
+                        ptr(reg_tmp_addr,
+                                static_cast<int32_t>(VL_OFS(tmp_ofs))));
+            } else {
+                add_imm(reg_tmp_addr, in, ofs, reg_tmp_imm);
+                prfw(op_sve, P_ALL_ONE, ptr(reg_tmp_addr));
+                prev_ofs = ofs;
+            }
+        }
+        return prev_ofs;
+    }
+
+    ZReg reg_wei = ZReg(31);
+
+    inline void prepare_output(int ur_w);
+    inline void store_output(int ur_w);
+    inline void compute_loop_fma(int ur_w, int l_overflow, int r_overflow);
+    inline void compute_loop_fma_core(
+            int ur_w, int l_overflow, int r_overflow, int k_offset);
+    inline void compute_loop(
+            int ur_w, int l_overflow, int r_overflow, int k_offset = 0);
+    void generate() override;
+
+    inline int get_iw_start(int ki, int l_overflow) {
+        int res = (jcp.iw - 1 + jcp.r_pad) % jcp.stride_w
+                + l_overflow * jcp.stride_w
+                - (jcp.kw - 1 - ki) * (jcp.dilate_w + 1);
+        while (res < 0)
+            res += jcp.stride_w;
+
+        return res;
+    }
+
+    inline int get_iw_end(int ur_w, int ki, int r_overflow) {
+        if (utils::one_of(ur_w, jcp.iw, jcp.ur_w_tail))
+            ur_w += nstl::min(0, jcp.r_pad); // remove negative padding
+        int res = (ur_w - 1 + jcp.l_pad) % jcp.stride_w
+                + r_overflow * jcp.stride_w - ki * (jcp.dilate_w + 1);
+        while (res < 0)
+            res += jcp.stride_w;
+
+        return ur_w - res;
+    }
+
+    inline size_t get_diff_src_offset(int iw, int icb) {
+        const bool is_nxc_layout = is_dsrc_layout_nxc();
+        size_t iw_str = is_nxc_layout ? jcp.ngroups * jcp.ic : jcp.ic_block;
+        size_t icb_str = is_nxc_layout
+                ? jcp.ic_block
+                : (size_t)jcp.id * jcp.ih * jcp.iw * jcp.ic_block;
+
+        return typesize * (icb * icb_str + iw * iw_str);
+    }
+
+    inline ptrdiff_t get_dst_offset(int iw, int oc, int kw) {
+        ptrdiff_t ow
+                = (iw + jcp.l_pad - kw * (jcp.dilate_w + 1)) / jcp.stride_w;
+        ptrdiff_t ow_str
+                = is_ddst_layout_nxc() ? jcp.ngroups * jcp.oc : jcp.oc_block;
+
+        return typesize * (ow * ow_str + oc);
+    };
+
+    inline bool is_dsrc_layout_nxc() {
+        return utils::one_of(jcp.src_tag, format_tag::ndhwc, format_tag::nhwc,
+                format_tag::nwc);
+    }
+    inline bool is_ddst_layout_nxc() {
+        return utils::one_of(jcp.dst_tag, format_tag::ndhwc, format_tag::nhwc,
+                format_tag::nwc);
+    }
+};
+
+struct jit_sve_512_conv_bwd_weights_kernel_f32 : public jit_generator {
+
+    jit_sve_512_conv_bwd_weights_kernel_f32(const jit_conv_conf_t &ajcp)
+        : jcp(ajcp) {}
+
+    void generate() override {
+        if (jcp.harness != harness_nxc) {
+            generate_kernel();
+        } else {
+            assert(!"none microkernel");
+        }
+    }
+
+    DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_sve_512_conv_bwd_weights_kernel_f32)
+
+    static status_t init_conf(jit_conv_conf_t &jcp,
+            const convolution_desc_t &cd, memory_desc_t &src_md,
+            memory_desc_t &diff_weights_md, memory_desc_t &diff_bias_md,
+            memory_desc_t &diff_dst_md, int nthreads);
+    static void init_scratchpad(memory_tracking::registrar_t &scratchpad,
+            const jit_conv_conf_t &jcp);
+
+    jit_conv_conf_t jcp;
+
+private:
+    using reg64_t = const XReg;
+    enum { typesize = sizeof(float) };
+    static const int max_ur_w;
+    static const int min_oh_reduce;
+
+    reg64_t param = abi_param1;
+    reg64_t reg_input = x1;
+    reg64_t reg_kernel = x2;
+    reg64_t reg_output = x3;
+    reg64_t b_ic = x20;
+    reg64_t kj = x5;
+    reg64_t reg_kh = x6;
+    reg64_t reg_ur_w_trips = x7;
+    reg64_t reg_oj = x8;
+    reg64_t reg_tmp = x10;
+    reg64_t reg_icb = x9;
+
+    reg64_t ki = x11;
+    reg64_t reg_kd_count = x12;
+    reg64_t reg_oi = x12;
+    reg64_t reg_d_index = x13;
+    reg64_t reg_input_d = x8;
+    reg64_t reg_output_d = x9;
+    reg64_t aux_reg_input = x12;
+    reg64_t aux_reg_kernel = x13;
+    reg64_t reg_bias = x9;
+    reg64_t reg_oc_tail = x10;
+
+    /* Temporary registers */
+    reg64_t reg_add_tmp = x14;
+    reg64_t reg_tmp_imm = x15;
+
+    reg64_t reg_kd_count_org = x16;
+    reg64_t reg_input_d_org = x17;
+    reg64_t reg_output_d_org = x19;
+
+    reg64_t reg_input_org = x24;
+    reg64_t reg_kernel_org = x22;
+    reg64_t reg_output_org = x23;
+
+    reg64_t reg_pre_addr_input = x25;
+    reg64_t reg_pre_addr_out = x26;
+    reg64_t reg_pre_addr_ker = x26;
+    reg64_t reg_ker_start_addr = x27;
+    reg64_t reg_addr_diff_input = x28;
+
+    void prefetch(
+            const std::string prfop, int level, reg64_t in, long long int ofs) {
+        bool for_load = false;
+        if (prfop == "LD") {
+            for_load = true;
+        } else if (prfop == "ST") {
+            for_load = false;
+        } else {
+            assert(!"invalid prfop");
+        }
+
+        bool cacheline_aligned = ((ofs & 0xFF) == 0) ? true : false;
+        if (cacheline_aligned == true) {
+            Prfop op = PLDL1KEEP;
+            switch (level) {
+                case 1: op = (for_load == true) ? PLDL1KEEP : PSTL1KEEP; break;
+                case 2: op = (for_load == true) ? PLDL2KEEP : PSTL2KEEP; break;
+                case 3: op = (for_load == true) ? PLDL3KEEP : PSTL3KEEP; break;
+                default: assert(!"invalid prfop"); break;
+            }
+
+            if ((ofs <= PRFMMAX) && (ofs >= 0)) {
+                prfm(op, ptr(in, static_cast<int32_t>(ofs)));
+            } else {
+                add_imm(reg_add_tmp, in, ofs, reg_tmp_imm);
+                prfm(op, ptr(reg_add_tmp));
+            }
+        } else {
+            PrfopSve op_sve;
+            switch (level) {
+                case 1:
+                    op_sve = (for_load == true) ? PLDL1KEEP_SVE : PSTL1KEEP_SVE;
+                    break;
+                case 2:
+                    op_sve = (for_load == true) ? PLDL2KEEP_SVE : PSTL2KEEP_SVE;
+                    break;
+                case 3:
+                    op_sve = (for_load == true) ? PLDL3KEEP_SVE : PSTL3KEEP_SVE;
+                    break;
+                default: assert(!"invalid prfop"); break;
+            }
+
+            if ((VL_OFS(ofs) <= PRFWMAX)
+                    && (VL_OFS(ofs) >= (-1 * PRFWMAX - 1))) {
+                prfw(op_sve, P_ALL_ONE,
+                        ptr(in, static_cast<int32_t>(VL_OFS(ofs))));
+            } else {
+                add_imm(reg_add_tmp, in, ofs, reg_tmp_imm);
+                prfw(op_sve, P_ALL_ONE, ptr(reg_add_tmp));
+            }
+        }
+    }
+
+    inline void bias_kernel_2d();
+    inline void bias_kernel_3d();
+    inline void maybe_zero_kernel();
+    inline void compute_oh_step_unroll_ow_icblock(
+            int ic_block_step, int max_ur_w);
+    inline void od_step_comeback_pointers();
+    inline void oh_step_comeback_pointers();
+    inline void compute_oh_step_unroll_ow(int ic_block_step, int max_ur_w);
+    inline void compute_ic_block_step(int ur_w, int pad_l, int pad_r,
+            int ic_block_step, int input_offset, int kernel_offset,
+            int output_offset, bool input_wraparound = false);
+    inline void compute_oh_step_common(int ic_block_step, int max_ur_w);
+    inline void compute_oh_step_disp();
+    inline void compute_oh_loop_common();
+    inline void compute_oh_loop_partial();
+    inline void compute_od_loop_partial();
+
+    inline bool compute_full_spat_loop();
+    inline bool flat_4ops_compute();
+
+    inline void compute_loop();
+    inline bool is_src_layout_nxc() {
+        return utils::one_of(jcp.src_tag, format_tag::ndhwc, format_tag::nhwc,
+                format_tag::nwc);
+    }
+    inline bool is_ddst_layout_nxc() {
+        return utils::one_of(jcp.dst_tag, format_tag::ndhwc, format_tag::nhwc,
+                format_tag::nwc);
+    }
+
+    inline ptrdiff_t get_full_src_offset(
+            int i_iw, int i_ic, ptrdiff_t input_offset) {
+        const bool is_nxc_layout = is_src_layout_nxc();
+        const size_t w_shift_st = (jcp.is_hw_transp ? jcp.iw : 1)
+                * (jcp.is_1stconv ? 1 : jcp.ic_block);
+        ptrdiff_t w_shift = is_nxc_layout ? jcp.ngroups * jcp.ic : w_shift_st;
+        ptrdiff_t ic_shift = (jcp.is_1stconv && !is_nxc_layout
+                        ? (ptrdiff_t)jcp.ih * jcp.iw * jcp.id
+                        : 1);
+
+        ptrdiff_t local_input_offset = i_iw * w_shift + i_ic * ic_shift;
+        return input_offset + typesize * local_input_offset;
+    };
+
+    inline int get_iw_idx(int ow, int kw, int l_pad) {
+        return ow * jcp.stride_w + kw * (jcp.dilate_w + 1) - l_pad;
+    }
+
+    void generate_kernel();
+
+    static void balance(const jit_conv_conf_t &j, int &nthr, int &nthr_mb,
+            int &nthr_g, int &nthr_oc_b, int &nthr_ic_b, int nthreads);
+};
+
+} // namespace aarch64
+} // namespace cpu
+} // namespace impl
+} // namespace dnnl
+
+#endif

miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_sve_512_convolution.hpp

@@ -0,0 +1,274 @@
+/*******************************************************************************
+* Copyright 2020-2021 Intel Corporation
+* Copyright 2020-2021 FUJITSU LIMITED
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef CPU_AARCH64_JIT_SVE_CONVOLUTION_HPP
+#define CPU_AARCH64_JIT_SVE_CONVOLUTION_HPP
+
+#include "common/c_types_map.hpp"
+#include "common/dnnl_thread.hpp"
+#include "common/memory_tracking.hpp"
+#include "common/primitive.hpp"
+#include "common/utils.hpp"
+
+#include "cpu/aarch64/cpu_barrier.hpp"
+#include "cpu/aarch64/cpu_reducer.hpp"
+#include "cpu/cpu_convolution_pd.hpp"
+
+#include "cpu/aarch64/jit_sve_512_conv_kernel.hpp"
+
+namespace dnnl {
+namespace impl {
+namespace cpu {
+namespace aarch64 {
+
+template <impl::data_type_t src_type, impl::data_type_t wei_type = src_type,
+        impl::data_type_t dst_type = src_type>
+struct jit_sve_512_convolution_fwd_t : public primitive_t {
+    struct pd_t : public cpu_convolution_fwd_pd_t {
+        pd_t(const convolution_desc_t *adesc, const primitive_attr_t *attr,
+                const typename pd_t::base_class *hint_fwd_pd)
+            : cpu_convolution_fwd_pd_t(adesc, attr, hint_fwd_pd), jcp_() {}
+
+        DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("jit:", sve_512, ""),
+                jit_sve_512_convolution_fwd_t);
+
+        status_t init(engine_t *engine) {
+            bool ok = true && is_fwd()
+                    && set_default_alg_kind(alg_kind::convolution_direct)
+                    && expect_data_types(src_type, wei_type, dst_type, dst_type,
+                            data_type::undef)
+                    && attr()->has_default_values(
+                            primitive_attr_t::skip_mask_t::post_ops, dst_type)
+                    && !has_zero_dim_memory();
+            if (!ok) return status::unimplemented;
+
+            status_t status = jit_sve_512_conv_fwd_kernel::init_conf(jcp_,
+                    *desc(), src_md_, weights_md_, dst_md_, bias_md_, *attr(),
+                    dnnl_get_max_threads());
+            if (status != status::success) return status;
+
+            auto scratchpad = scratchpad_registry().registrar();
+            jit_sve_512_conv_fwd_kernel::init_scratchpad(scratchpad, jcp_);
+
+            return status;
+        }
+
+        jit_conv_conf_t jcp_;
+    };
+
+    jit_sve_512_convolution_fwd_t(const pd_t *apd) : primitive_t(apd) {}
+
+    typedef typename prec_traits<src_type>::type src_data_t;
+    typedef typename prec_traits<wei_type>::type wei_data_t;
+    typedef typename prec_traits<dst_type>::type dst_data_t;
+
+    status_t init(engine_t *engine) override {
+        CHECK(safe_ptr_assign(kernel_,
+                new jit_sve_512_conv_fwd_kernel(pd()->jcp_, *pd()->attr())));
+        return kernel_->create_kernel();
+    }
+
+    status_t execute(const exec_ctx_t &ctx) const override {
+        if (pd()->ndims() == 3)
+            execute_forward_1d(ctx);
+        else if (pd()->ndims() == 4)
+            execute_forward_2d(ctx);
+        else if (pd()->ndims() == 5)
+            execute_forward_3d(ctx);
+        else
+            assert(false);
+
+        if (pd()->wants_zero_pad_dst()) ctx.zero_pad_output(DNNL_ARG_DST);
+
+        return status::success;
+    }
+
+private:
+    void prepare_padded_bias(const dst_data_t *&bias,
+            const memory_tracking::grantor_t &scratchpad) const;
+    void execute_forward_1d(const exec_ctx_t &ctx) const;
+    void execute_forward_2d(const exec_ctx_t &ctx) const;
+    void execute_forward_3d(const exec_ctx_t &ctx) const;
+    const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); }
+
+    std::unique_ptr<jit_sve_512_conv_fwd_kernel> kernel_;
+};
+
+template <impl::data_type_t diff_dst_type,
+        impl::data_type_t wei_type = diff_dst_type,
+        impl::data_type_t diff_src_type = diff_dst_type>
+struct jit_sve_512_convolution_bwd_data_t : public primitive_t {
+    struct pd_t : public cpu_convolution_bwd_data_pd_t {
+        pd_t(const convolution_desc_t *adesc, const primitive_attr_t *attr,
+                const convolution_fwd_pd_t *hint_fwd_pd)
+            : cpu_convolution_bwd_data_pd_t(adesc, attr, hint_fwd_pd), jcp_() {}
+
+        DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("jit:", sve_512, ""),
+                jit_sve_512_convolution_bwd_data_t);
+
+        status_t init(engine_t *engine) {
+            bool ok = true && desc()->prop_kind == prop_kind::backward_data
+                    && set_default_alg_kind(alg_kind::convolution_direct)
+                    && expect_data_types(diff_src_type, wei_type,
+                            data_type::undef, diff_dst_type, data_type::undef)
+                    && attr()->has_default_values() && !has_zero_dim_memory();
+            if (!ok) return status::unimplemented;
+
+            status_t status = jit_sve_512_conv_bwd_data_kernel_f32::init_conf(
+                    jcp_, *desc(), diff_src_md_, weights_md_, diff_dst_md_,
+                    dnnl_get_max_threads());
+            if (status != status::success) return status;
+
+            auto scratchpad = scratchpad_registry().registrar();
+            jit_sve_512_conv_bwd_data_kernel_f32::init_scratchpad(
+                    scratchpad, jcp_);
+
+            return status::success;
+        }
+
+        jit_conv_conf_t jcp_;
+    };
+
+    jit_sve_512_convolution_bwd_data_t(const pd_t *apd) : primitive_t(apd) {}
+
+    typedef typename prec_traits<diff_dst_type>::type diff_dst_data_t;
+    typedef typename prec_traits<wei_type>::type wei_data_t;
+    typedef typename prec_traits<diff_src_type>::type diff_src_data_t;
+
+    status_t init(engine_t *engine) override {
+        CHECK(safe_ptr_assign(
+                kernel_, new jit_sve_512_conv_bwd_data_kernel_f32(pd()->jcp_)));
+        return kernel_->create_kernel();
+    }
+
+    status_t execute(const exec_ctx_t &ctx) const override {
+        if (pd()->ndims() == 3)
+            execute_backward_data_1d(ctx);
+        else if (pd()->ndims() == 4)
+            execute_backward_data_2d(ctx);
+        else if (pd()->ndims() == 5)
+            execute_backward_data_3d(ctx);
+        else
+            assert(false);
+        return status::success;
+    }
+
+private:
+    void execute_backward_data_1d(const exec_ctx_t &ctx) const;
+    void execute_backward_data_2d(const exec_ctx_t &ctx) const;
+    void execute_backward_data_3d(const exec_ctx_t &ctx) const;
+    const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); }
+
+    std::unique_ptr<jit_sve_512_conv_bwd_data_kernel_f32> kernel_;
+};
+
+template <impl::data_type_t src_type,
+        impl::data_type_t diff_dst_type = src_type,
+        impl::data_type_t diff_weights_type = src_type>
+struct jit_sve_512_convolution_bwd_weights_t : public primitive_t {
+    struct pd_t : public cpu_convolution_bwd_weights_pd_t {
+        pd_t(const convolution_desc_t *adesc, const primitive_attr_t *attr,
+                const convolution_fwd_pd_t *hint_fwd_pd)
+            : cpu_convolution_bwd_weights_pd_t(adesc, attr, hint_fwd_pd)
+            , jcp_() {}
+
+        DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("jit:", sve_512, ""),
+                jit_sve_512_convolution_bwd_weights_t);
+
+        status_t init(engine_t *engine) {
+            bool ok = true && desc()->prop_kind == prop_kind::backward_weights
+                    && set_default_alg_kind(alg_kind::convolution_direct)
+                    && expect_data_types(src_type, diff_weights_type,
+                            diff_weights_type, diff_dst_type, data_type::undef)
+                    && attr()->has_default_values() && !has_zero_dim_memory();
+            if (!ok) return status::unimplemented;
+
+            status_t status
+                    = jit_sve_512_conv_bwd_weights_kernel_f32::init_conf(jcp_,
+                            *desc(), src_md_, diff_weights_md_, diff_bias_md_,
+                            diff_dst_md_, dnnl_get_max_threads());
+            if (status != status::success) return status;
+
+            init_balancers();
+
+            auto scratchpad = scratchpad_registry().registrar();
+            jit_sve_512_conv_bwd_weights_kernel_f32::init_scratchpad(
+                    scratchpad, jcp_);
+
+            auto reducer_bia_scratchpad = memory_tracking::registrar_t(
+                    scratchpad, memory_tracking::names::prefix_reducer_bia);
+            reducer_bia_conf_.init_scratchpad(reducer_bia_scratchpad);
+
+            return status;
+        }
+
+        jit_conv_conf_t jcp_;
+        typename cpu_reducer_t<diff_weights_type>::conf_t reducer_bia_conf_;
+
+    private:
+        void init_balancers() {
+            const size_t max_buffer_size = jcp_.nthr * 3 * 5 * 5 * 16 * 16;
+            if (with_bias()) {
+                reducer_bia_conf_.init(reduce_balancer_t(jcp_.nthr,
+                        jcp_.oc_block, jcp_.ngroups * jcp_.nb_oc, jcp_.mb,
+                        max_buffer_size, true));
+            }
+        }
+    };
+
+    jit_sve_512_convolution_bwd_weights_t(const pd_t *apd) : primitive_t(apd) {}
+
+    typedef typename prec_traits<src_type>::type src_data_t;
+    typedef typename prec_traits<diff_dst_type>::type diff_dst_data_t;
+    typedef typename prec_traits<diff_weights_type>::type diff_weights_data_t;
+
+    status_t init(engine_t *engine) override;
+
+    status_t execute(const exec_ctx_t &ctx) const override {
+        execute_backward_weights(ctx);
+        return status::success;
+    }
+
+private:
+    void execute_backward_weights(const exec_ctx_t &ctx) const;
+    void prepare_scratchpad_data(const exec_ctx_t &ctx) const;
+    struct thread_info_t;
+    void compute_diff_weights(const thread_info_t *) const;
+    void compute_diff_weights_2d(const thread_info_t *) const;
+    void compute_diff_weights_3d(const thread_info_t *) const;
+    void reduce_diff_weights(const thread_info_t *) const;
+    void reduce_diff_weights_3d(const thread_info_t *) const;
+    void compute_diff_bias(const thread_info_t *) const;
+    void reduce_diff_bias(const thread_info_t *) const;
+
+    const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); }
+
+    int nthr_, nthr_mb_, nthr_g_, nthr_oc_b_, nthr_ic_b_;
+
+    jit_sve_512_conv_bwd_weights_kernel_f32 *kernel_;
+    cpu_accumulator_1d_t<diff_weights_type> *acc_ker_;
+    cpu_reducer_t<diff_weights_type> *reducer_bias_;
+};
+
+} // namespace aarch64
+} // namespace cpu
+} // namespace impl
+} // namespace dnnl
+
+#endif
+
+// vim: et ts=4 sw=4 cindent cino+=l0,\:4,N-s

miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_sve_512_core_x8s8s32x_deconvolution.hpp

@@ -0,0 +1,352 @@
+/*******************************************************************************
+* Copyright 2018-2022 Intel Corporation
+* Copyright 2022 FUJITSU LIMITED
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef CPU_AARCH64_JIT_SVE_512_CORE_X8S8S32X_DECONVOLUTION_HPP
+#define CPU_AARCH64_JIT_SVE_512_CORE_X8S8S32X_DECONVOLUTION_HPP
+
+#include <functional>
+#include <vector>
+
+#include "common/c_types_map.hpp"
+#include "common/dnnl_thread.hpp"
+#include "common/memory.hpp"
+#include "common/nstl.hpp"
+#include "common/primitive.hpp"
+#include "common/type_helpers.hpp"
+#include "common/utils.hpp"
+
+#include "cpu/aarch64/jit_generator.hpp"
+#include "cpu/aarch64/jit_primitive_conf.hpp"
+#include "cpu/aarch64/jit_uni_deconv_zp_pad_str_kernel.hpp"
+#include "cpu/cpu_deconvolution_pd.hpp"
+
+namespace dnnl {
+namespace impl {
+namespace cpu {
+namespace aarch64 {
+
+using namespace Xbyak_aarch64;
+
+typedef enum {
+    no_last_block = 0x1U,
+    last_ic_block = 0x2U,
+    last_sp_block = 0x4U,
+} ker_block_t;
+
+struct ur_w_blks_params_t {
+    struct single_ur_w_blk_params_t {
+        single_ur_w_blk_params_t(
+                int l_overflow, int r_overflow, bool process_sp_carefully)
+            : l_overflow(l_overflow)
+            , r_overflow(r_overflow)
+            , process_sp_carefully(process_sp_carefully) {}
+
+        // l_overflow - no. of spatial elements of weights standing out of
+        // src spatial when computing the 1st output pixel in the current blk
+        int l_overflow;
+        // r_overflow - no. of spatial elements of weights standing out of
+        // src spatial when computing the lst output pixel in the current blk
+        int r_overflow;
+        // process_sp_carefully - indicates if loading the last src sp
+        // for computation of the last dst sp of the block can't be done
+        // by fetching 4 src sp at once
+        bool process_sp_carefully;
+    };
+    std::vector<single_ur_w_blk_params_t> blks_params;
+    int num_pre_blks; // num of blocks with l_overflow>0
+    int num_post_blks; // num of blocks with r_overflow>0 or that need to be
+            // processed carefully
+};
+
+template <cpu_isa_t isa>
+struct jit_sve_512_core_x8s8s32x_deconv_fwd_kernel : public jit_generator {
+    DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_sve_512_core_x8s8s32x_deconv_fwd_ker_t);
+
+    jit_sve_512_core_x8s8s32x_deconv_fwd_kernel(const jit_conv_conf_t &ajcp,
+            const primitive_attr_t &attr, const memory_desc_t &dst_md);
+    ~jit_sve_512_core_x8s8s32x_deconv_fwd_kernel();
+
+    const jit_conv_conf_t &jcp;
+    const primitive_attr_t &attr_;
+
+private:
+    const int ic_sub_step = 4;
+    const uint64_t isa_sveLen = cpu_isa_traits<isa>::vlen;
+
+    /* data regs */
+    const XReg reg_src = x8;
+    const XReg reg_filt = x9;
+    const XReg reg_dst = x10;
+    const XReg param1 = abi_param1;
+    const XReg reg_kh = abi_param2;
+    const XReg reg_ki = x14;
+
+    const XReg reg_nur_w = x3;
+    const XReg reg_bias = x2;
+    const XReg reg_icb = reg_bias;
+    const XReg reg_ptr_scales = x16;
+    const WReg reg_ptr_saturation_ubound = w16;
+    const XReg reg_oc_blocks = x6;
+
+    const XReg aux_reg_src = x11;
+    const XReg aux_reg_filt = x12;
+
+    const XReg aux_reg_src_d = x13;
+    const XReg aux_reg_filt_d = x17;
+
+    const XReg reg_compensation = x14;
+    const XReg reg_bias_alpha = abi_not_param1;
+    const XReg reg_overflow = x16;
+    const XReg reg_comp_strides = reg_overflow;
+    const XReg reg_ker_long_offt = x17;
+    const XReg &reg_zp_dst_ = x17;
+    const XReg &reg_zp_src_ = x17;
+    const XReg &reg_zp_compensation = x11;
+    const XReg reg_zp_src_pad_comp = x20;
+
+    PReg ktail_mask = p2;
+    const PReg mask_tmp = p4;
+
+    const ZReg vmm_tmp0 = z28;
+    const ZReg vmm_tmp1 = z29;
+    /* used during write-out section of store_output */
+    const ZReg vmm_saturation = z31;
+    const ZReg vmm_wei = z31;
+
+    /* unsigned input */
+    const ZReg vmm_shift = z30;
+    const ZReg vmm_comp = z30;
+    ///
+
+    ZReg vmm_out(int i_ur, int i_oc) {
+        int idx = i_ur * jcp.nb_oc_blocking + i_oc;
+        assert(idx < 31);
+        return ZReg(idx);
+    }
+
+    ZReg vmm_inp(int i_ic, int nb_x_blocking) const {
+        int idx = i_ic + nb_x_blocking * jcp.ur_w;
+        assert(idx < 31);
+        return ZReg(idx);
+    }
+    ZReg vmm_bias_alpha() { return ZReg(jcp.nb_oc_blocking * jcp.ur_w); }
+
+    template <typename T>
+    ZReg compress_addr(const XReg &base, T offt, const bool mask_flag = false,
+            const bool bcast = false) {
+        assert(bcast == false);
+        PReg mask = P_ALL_ONE;
+        XReg addr = base;
+
+        if (offt) {
+            add_imm(X_DEFAULT_ADDR, base, offt, X_TMP_0);
+            addr = X_DEFAULT_ADDR;
+        }
+
+        if (mask_flag) mask = PReg(ktail_mask.getIdx());
+
+        mov(X_TMP_0, 64);
+        ld1w(vmm_tmp0.s, mask / T_z, ptr(addr));
+        return vmm_tmp0;
+    }
+
+    int get_ow_start(int ki, int l_overflow) {
+        int res = (jcp.ow - 1 + jcp.r_pad) % jcp.stride_w
+                + l_overflow * jcp.stride_w
+                - (jcp.kw - 1 - ki) * (jcp.dilate_w + 1);
+        while (res < 0)
+            res += jcp.stride_w;
+        return res;
+    }
+
+    int get_ow_end(int ur_w, int ki, int r_overflow) {
+        if (utils::one_of(ur_w, jcp.ow, jcp.ur_w_tail))
+            ur_w += nstl::min(0, jcp.r_pad); // remove negative padding
+        int res = (ur_w - 1 + jcp.l_pad) % jcp.stride_w
+                + r_overflow * jcp.stride_w - ki * (jcp.dilate_w + 1);
+        while (res < 0)
+            res += jcp.stride_w;
+        return ur_w - res;
+    }
+
+    int get_blocking_size() const noexcept;
+    int get_tail_size() const noexcept;
+    void prepare_output(int ur_w);
+    void store_output(int ur_w, bool last_oc_block);
+    void compute(
+            const ZReg &vreg_acc, const ZReg &vreg_wei, const ZReg &vreg_src);
+    std::function<uint32_t()> prepare_round_robin_vmm_inp_generator(
+            int ur_w) const noexcept;
+    void apply_zp_src_pad_str_comp(
+            int ur_w, int l_overflow, int r_overflow, bool h_padded);
+    void append_zp_src_pad_str_comp(int ur_w, int l_overflow, int r_overflow,
+            bool h_padded, bool last_oc_block);
+    void compute_ker(int ur_w, int l_overflow, int r_overflow,
+            ker_block_t last_ic_block_flag, bool h_padded = false);
+    void kh_loop(int ur_w, int pad_l, int pad_r, ker_block_t last_ker_block);
+    void icb_loop(int ur_w, int pad_l, int pad_r, bool last_block);
+
+    ur_w_blks_params_t get_ur_w_blks_params();
+
+    void generate() override;
+    void cvt2ps(const data_type_t type_in, const ZReg &vmm_in, const ZReg &op,
+            const bool mask_flag);
+
+    void uni_ld1r(const VReg4S &d, const XReg &addr) { ld1r(d, ptr(addr)); }
+
+    void uni_ld1r(const ZRegS &d, const XReg &addr) {
+        ld1rw(d, P_ALL_ONE / T_z, ptr(addr));
+    }
+
+    void uni_fmin(const VReg4S &d, const VReg4S &s) { fmin(d, d, s); }
+
+    void uni_fmin(const ZRegS &d, const ZRegS &s) {
+        fmin(d, P_ALL_ONE / T_m, s);
+    }
+};
+
+struct _jit_sve_512_core_x8s8s32x_deconv_fwd_kernel {
+    _jit_sve_512_core_x8s8s32x_deconv_fwd_kernel(const jit_conv_conf_t &ajcp,
+            const primitive_attr_t &attr, const memory_desc_t &dst_md)
+        : kernel_(nullptr) {
+
+        int ch_block = ajcp.is_depthwise ? ajcp.ch_block : ajcp.ic_block;
+        switch (ch_block) {
+            case 16:
+                kernel_ = new jit_sve_512_core_x8s8s32x_deconv_fwd_kernel<
+                        sve_512>(ajcp, attr, dst_md);
+                return;
+            case 8:
+                kernel_ = new jit_sve_512_core_x8s8s32x_deconv_fwd_kernel<
+                        sve_256>(ajcp, attr, dst_md);
+                return;
+            case 4:
+                kernel_ = new jit_sve_512_core_x8s8s32x_deconv_fwd_kernel<
+                        sve_128>(ajcp, attr, dst_md);
+                return;
+            default: assert(!"invalid channel blocking");
+        }
+    }
+
+    status_t create_kernel() { return kernel_->create_kernel(); }
+
+    ~_jit_sve_512_core_x8s8s32x_deconv_fwd_kernel() { delete kernel_; }
+
+    void operator()(const jit_deconv_call_s *p) const { (*kernel_)(p); }
+
+    static status_t init_conf(jit_conv_conf_t &jcp,
+            const deconvolution_desc_t &cd, memory_desc_t &src_md,
+            memory_desc_t &weights_md, memory_desc_t &dst_md,
+            const bool with_bias, memory_desc_t &bias_md,
+            primitive_attr_t &attr, int nthreads);
+
+    static void init_scratchpad(memory_tracking::registrar_t &scratchpad,
+            const jit_conv_conf_t &jcp, const primitive_attr_t &attr);
+
+private:
+    DNNL_DISALLOW_COPY_AND_ASSIGN(_jit_sve_512_core_x8s8s32x_deconv_fwd_kernel);
+    jit_generator *kernel_;
+};
+
+struct jit_sve_512_core_x8s8s32x_deconvolution_fwd_t : public primitive_t {
+    struct pd_t : public cpu_deconvolution_fwd_pd_t {
+        using cpu_deconvolution_fwd_pd_t::cpu_deconvolution_fwd_pd_t;
+
+        DECLARE_COMMON_PD_T(
+                JIT_IMPL_NAME_HELPER("jit_deconvolution:", sve_512, ""),
+                jit_sve_512_core_x8s8s32x_deconvolution_fwd_t);
+
+        status_t init(engine_t *engine) {
+            using namespace data_type;
+            using skip_mask_t = primitive_attr_t::skip_mask_t;
+            const bool ok = mayiuse(sve_512) && is_fwd()
+                    && (desc()->alg_kind & alg_kind::deconvolution_direct)
+                    && utils::one_of(src_md(0)->data_type, s8, u8)
+                    && weights_md(0)->data_type == s8
+                    && IMPLICATION(with_bias(),
+                            utils::one_of(
+                                    weights_md(1)->data_type, f32, s32, s8, u8))
+                    && utils::one_of(dst_md(0)->data_type, f32, s32, s8, u8)
+                    && desc()->accum_data_type == s32
+                    && attr()->has_default_values(skip_mask_t::oscale_runtime
+                            | skip_mask_t::post_ops
+                            | skip_mask_t::zero_points_runtime);
+            if (!ok) return status::unimplemented;
+
+            CHECK(_jit_sve_512_core_x8s8s32x_deconv_fwd_kernel::init_conf(jcp_,
+                    *desc(), src_md_, weights_md_, dst_md_, with_bias(),
+                    bias_md_, attr_, dnnl_get_max_threads()));
+
+            auto scratchpad = scratchpad_registry().registrar();
+            _jit_sve_512_core_x8s8s32x_deconv_fwd_kernel::init_scratchpad(
+                    scratchpad, jcp_, *attr());
+
+            return status::success;
+        }
+
+        jit_conv_conf_t jcp_;
+    };
+
+    jit_sve_512_core_x8s8s32x_deconvolution_fwd_t(const pd_t *apd)
+        : primitive_t(apd) {}
+
+    status_t init(engine_t *engine) override {
+        CHECK(safe_ptr_assign(kernel_,
+                new _jit_sve_512_core_x8s8s32x_deconv_fwd_kernel(
+                        pd()->jcp_, *pd()->attr(), *pd()->dst_md(0))));
+
+        if (zp::should_calculate_deconv_zp_src_pad_str_comp(pd()->jcp_)) {
+            CHECK(safe_ptr_assign(zp_src_pad_comp_kernel_,
+                    zp::create_deconv_zp_pad_str_comp_ker<sve_512>(
+                            pd()->jcp_)));
+            const auto zp_kernel_status
+                    = zp_src_pad_comp_kernel_->create_kernel();
+            if (zp_kernel_status != status::success) return zp_kernel_status;
+        }
+
+        return kernel_->create_kernel();
+    }
+
+    status_t execute(const exec_ctx_t &ctx) const override {
+        auto ndims = pd()->ndims();
+        if (ndims == 3)
+            return execute_forward_1d(ctx);
+        else if (ndims == 4)
+            return execute_forward_2d(ctx);
+        else if (ndims == 5)
+            return execute_forward_3d(ctx);
+        return status::runtime_error;
+    }
+
+private:
+    status_t execute_forward_1d(const exec_ctx_t &ctx) const;
+    status_t execute_forward_2d(const exec_ctx_t &ctx) const;
+    status_t execute_forward_3d(const exec_ctx_t &ctx) const;
+    const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); }
+    std::unique_ptr<_jit_sve_512_core_x8s8s32x_deconv_fwd_kernel> kernel_;
+    std::unique_ptr<zp::jit_uni_deconv_zp_pad_str_kernel_base_t>
+            zp_src_pad_comp_kernel_;
+};
+
+} // namespace aarch64
+} // namespace cpu
+} // namespace impl
+} // namespace dnnl
+
+#endif
+
+// vim: et ts=4 sw=4 cindent cino+=l0,\:4,N-s

miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_sve_512_x8s8s32x_conv_kernel.hpp

@@ -0,0 +1,254 @@
+/*******************************************************************************
+* Copyright 2021 Intel Corporation
+* Copyright 2021 FUJITSU LIMITED
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef CPU_AARCH64_JIT_SVE_512_X8S8S32X_CONV_KERNEL_HPP
+#define CPU_AARCH64_JIT_SVE_512_X8S8S32X_CONV_KERNEL_HPP
+
+#include "common/c_types_map.hpp"
+#include "common/memory_tracking.hpp"
+
+#include "cpu/aarch64/jit_generator.hpp"
+#include "cpu/aarch64/jit_primitive_conf.hpp"
+
+namespace dnnl {
+namespace impl {
+namespace cpu {
+namespace aarch64 {
+
+using namespace Xbyak_aarch64;
+
+struct jit_sve_512_x8s8s32x_fwd_kernel : public jit_generator {
+    DECLARE_CPU_JIT_AUX_FUNCTIONS(_jit_sve_512_x8s8s32x_conv_fwd_ker_t)
+
+    enum { STATE_FIRST_DST_LOAD = 0x1U };
+
+    jit_sve_512_x8s8s32x_fwd_kernel(
+            const jit_conv_conf_t &ajcp, const primitive_attr_t &attr)
+        : jcp(ajcp), attr_(attr) {
+        if (jcp.with_eltwise) assert(!"not supported");
+
+        int ch_block = jcp.is_depthwise ? jcp.ch_block : jcp.ic_block;
+        switch (ch_block) {
+            case 16: sve_len_ = 64; break;
+            case 8: sve_len_ = 32; break;
+            case 4: sve_len_ = 16; break;
+            default: assert(!"unreachable"); break;
+        }
+    }
+
+    ~jit_sve_512_x8s8s32x_fwd_kernel() {}
+
+    jit_conv_conf_t jcp;
+    const primitive_attr_t &attr_;
+
+    static status_t init_conf(jit_conv_conf_t &jcp,
+            const convolution_desc_t &cd, memory_desc_t &src_pd,
+            memory_desc_t &weights_pd, memory_desc_t &dst_pd,
+            memory_desc_t &bias_pd, const primitive_attr_t &attr, int nthreads);
+    static void init_scratchpad(memory_tracking::registrar_t &scratchpad,
+            const jit_conv_conf_t &jcp, const primitive_attr_t &attr);
+
+private:
+    size_t sve_len_;
+
+    enum {
+        typesize = sizeof(float),
+        ker_reg_base_idx = 28,
+        ker_dw_reg_base_idx = 30,
+        ker_zp_reg_base_idx = 26,
+    };
+    typedef enum {
+        no_last_block,
+        last_ic_block,
+        last_sp_block,
+    } ic_block_t;
+
+    /* data regs */
+    const XReg reg_ptr_scales = x7;
+    const XReg aux_reg_saturation = x7;
+    const XReg reg_inp = x8;
+    const XReg reg_ker = x9;
+    const XReg reg_out = x10;
+    const XReg aux_reg_inp = x11;
+    const XReg reg_ptr_sum_scale = x11;
+    const XReg aux_reg_ker = x12;
+    const XReg reg_compensation = x14;
+    const XReg aux_reg_inp_d = x13;
+    const XReg aux_reg_ker_d = x15;
+    // Using 3d regs as depthwise_3d is not yet supported
+    const XReg reg_inp_buffer_ptr = aux_reg_inp_d;
+    const XReg aux_reg_inp_buffer_ptr = aux_reg_ker_d;
+
+    /* counter regs */
+    const XReg reg_bias_alpha = x1;
+    const XReg reg_param1 = x0;
+    const XReg reg_oi = x3;
+    const XReg reg_bias = x2;
+    const XReg reg_oc_blocks = x6;
+    const XReg reg_owb = aux_reg_ker;
+    const XReg reg_scratch = reg_compensation;
+    const XReg reg_kj = reg_ptr_scales;
+    const XReg reg_ki = reg_compensation;
+    const XReg reg_overflow = reg_ptr_scales;
+    const XReg reg_icb = reg_bias;
+    const XReg reg_jmp_tbl_base = reg_kj;
+
+    XReg reg_stack = x22; // translator stack register
+
+    /* Temporay registers */
+    XReg reg_tmp0_imm = x23; // tmp for add_imm
+    XReg reg_tmp1_imm = x24; // tmp for add_imm
+    XReg reg_tmp0_adr = x25; // tmp for address value
+
+    const PReg ktail_mask = p2;
+    const PReg kblend_mask = p8;
+
+    const PReg mask_tmp = p3;
+    const PReg mask_tmp2 = p9;
+    const PReg mask_all_one = p4;
+
+    const ZReg vmm_wei = ZReg(31);
+    /* used during bias section of store_output */
+    const ZReg vmm_comp = ZReg(30); // only for unsigned input
+    const ZReg vmm_bias = ZReg(31);
+    const ZReg vmm_pre_load = ZReg(30); // only for signed input
+    /* used during post_op sum section of store_output */
+    const ZReg vmm_prev_dst = ZReg(31);
+    /* used during write-out section of store_output */
+    const ZReg vmm_saturation = ZReg(30);
+    const ZReg vmm_zero = ZReg(31);
+
+    /* used in compute_ker (but set during prepare_output) */
+    const ZReg vmm_shift = vmm_comp; // only for unsigned input
+    const ZReg vmm_tmp = ZReg(28); // not used for depthwise
+    const ZReg vmm_one
+            = ZReg(29); // set at start of kernel, not used for depthwise.
+
+    /* registers use only for depthwise
+       groups are always blocked by 16(padded if needed),
+       hence use only ZReg registers */
+    const ZReg zmm_wei = ZReg(31);
+    ZReg zmm_tmp = ZReg(0);
+    ZReg zmm_src = ZReg(0);
+    ZReg zmm_shifted_zero = ZReg(0);
+    ZReg zmm_permute = ZReg(0);
+
+    bool mask_gflag;
+
+    ZReg vmm_out(int i_ur, int i_oc) {
+        int nb_x_blocking
+                = jcp.is_depthwise ? jcp.nb_ch_blocking : jcp.nb_oc_blocking;
+        int idx = i_ur * nb_x_blocking + i_oc;
+        assert(idx
+                < (jcp.is_depthwise ? ker_dw_reg_base_idx : ker_reg_base_idx));
+        return ZReg(idx);
+    }
+    ZReg zmm_out(int i_ur, int i_oc) {
+        int idx = vmm_out(i_ur, i_oc).getIdx();
+        assert(idx
+                < (jcp.is_depthwise ? ker_dw_reg_base_idx : ker_reg_base_idx));
+        return ZReg(idx);
+    }
+    ZReg vmm_inp(int i_ic, int nb_x_blocking) {
+        int idx = i_ic + nb_x_blocking * jcp.ur_w;
+        assert(idx < 31);
+        return ZReg(idx);
+    }
+    ZReg zmm_inp(int i_ic, int nb_x_blocking) {
+        int idx = i_ic + nb_x_blocking * jcp.ur_w;
+        const int max_idx = ker_dw_reg_base_idx;
+        assert(idx < max_idx);
+        MAYBE_UNUSED(max_idx);
+
+        return ZReg(idx);
+    }
+    ZReg vmm_bias_alpha() {
+        int nb_c_block
+                = jcp.is_depthwise ? jcp.nb_ch_blocking : jcp.nb_oc_blocking;
+        return ZReg(nb_c_block * jcp.ur_w);
+    }
+    ZReg xmm_bias_alpha() {
+        int nb_c_block
+                = jcp.is_depthwise ? jcp.nb_ch_blocking : jcp.nb_oc_blocking;
+        return ZReg(nb_c_block * jcp.ur_w);
+    }
+    int get_ow_start(int ki, int pad_l) {
+        return nstl::max(0,
+                utils::div_up(pad_l - ki * (jcp.dilate_w + 1), jcp.stride_w));
+    }
+    int get_ow_end(int ur_w, int ki, int pad_r) {
+        return ur_w
+                - nstl::max(0,
+                        utils::div_up(
+                                pad_r - (jcp.kw - 1 - ki) * (jcp.dilate_w + 1),
+                                jcp.stride_w));
+    }
+
+    void prepare_output(int ur_w);
+    void store_output(int ur_w, bool last_oc_block_flag);
+    void compute_ker_dw(int ur_w, int pad_l, int pad_r,
+            ic_block_t last_ic_block_flag, bool h_padded);
+    void compute_ker(int ur_w, int pad_l, int pad_r,
+            ic_block_t last_ic_block_flag, bool h_padded = false);
+    void kh_loop(int ur_w, int pad_l, int pad_r, ic_block_t last_ic_block_flag);
+    void icb_loop(int ur_w, int pad_l, int pad_r, bool is_last_spatial_block);
+    void generate() override;
+    void cvt2ps(data_type_t type_in, ZReg ymm_in, const XReg reg_base,
+            const int offset, bool mask_flag);
+    void vmm_mask_all_one();
+    void vmm_load_src(ZReg src, XReg reg_addr, bool mask_flag);
+
+    int get_offset(int raw_offt) {
+        auto offt = raw_offt;
+        int scale = 0;
+        const int EVEX_max_8b_offt = 0x200;
+        if (EVEX_max_8b_offt <= offt && offt < 3 * EVEX_max_8b_offt) {
+            offt = offt - 2 * EVEX_max_8b_offt;
+            scale = 1;
+        } else if (3 * EVEX_max_8b_offt <= offt
+                && offt < 5 * EVEX_max_8b_offt) {
+            offt = offt - 4 * EVEX_max_8b_offt;
+            scale = 2;
+        }
+
+        auto re = offt;
+        if (scale) re = re + (2 * EVEX_max_8b_offt) * scale;
+
+        return re;
+    }
+
+    XReg get_comp_addr_reg(XReg base, int offset = 0) {
+        auto offt = get_offset(offset);
+
+        if (offt == 0) return base;
+
+        auto reg_tmp_adr = reg_tmp0_adr;
+        auto reg_tmp_imm = reg_tmp0_imm;
+        add_imm(reg_tmp_adr, base, offt, reg_tmp_imm);
+
+        return reg_tmp_adr;
+    }
+
+    static bool post_ops_ok(jit_conv_conf_t &jcp, const primitive_attr_t &attr);
+};
+
+} // namespace aarch64
+} // namespace cpu
+} // namespace impl
+} // namespace dnnl
+
+#endif

miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_sve_512_x8s8s32x_convolution.hpp

@@ -0,0 +1,122 @@
+/*******************************************************************************
+* Copyright 2021 Intel Corporation
+* Copyright 2021 FUJITSU LIMITED
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef CPU_AARCH64_JIT_SVE_X8S8S32X_CONVOLUTION_HPP
+#define CPU_AARCH64_JIT_SVE_X8S8S32X_CONVOLUTION_HPP
+
+#include "common/c_types_map.hpp"
+#include "common/dnnl_thread.hpp"
+#include "common/memory_tracking.hpp"
+#include "common/primitive.hpp"
+#include "common/utils.hpp"
+
+#include "cpu/cpu_convolution_pd.hpp"
+
+#include "cpu/aarch64/jit_sve_512_x8s8s32x_conv_kernel.hpp"
+
+namespace dnnl {
+namespace impl {
+namespace cpu {
+namespace aarch64 {
+
+template <impl::data_type_t src_type, impl::data_type_t dst_type>
+struct jit_sve_512_x8s8s32x_convolution_fwd_t : public primitive_t {
+    struct pd_t : public cpu_convolution_fwd_pd_t {
+        pd_t(const convolution_desc_t *adesc, const primitive_attr_t *attr,
+                const typename pd_t::base_class *hint_fwd_pd)
+            : cpu_convolution_fwd_pd_t(adesc, attr, hint_fwd_pd), jcp_() {}
+
+        DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("jit_int8:", sve_512, ""),
+                jit_sve_512_x8s8s32x_convolution_fwd_t);
+
+        status_t init(engine_t *engine) {
+            using smask_t = primitive_attr_t::skip_mask_t;
+            bool ok = true && is_fwd()
+                    && set_default_alg_kind(alg_kind::convolution_direct)
+                    && expect_data_types(src_type, data_type::s8,
+                            data_type::undef, dst_type, data_type::s32)
+                    && IMPLICATION(with_bias(),
+                            utils::one_of(bias_md_.data_type, data_type::f32,
+                                    data_type::s32, data_type::s8,
+                                    data_type::u8))
+                    && attr()->has_default_values(
+                            smask_t::oscale_runtime | smask_t::post_ops,
+                            dst_type)
+                    && !has_zero_dim_memory();
+            if (!ok) return status::unimplemented;
+
+            status_t status = jit_sve_512_x8s8s32x_fwd_kernel::init_conf(jcp_,
+                    *desc(), src_md_, weights_md_, dst_md_, bias_md_, *attr(),
+                    dnnl_get_max_threads());
+            if (status != status::success) return status;
+
+            auto scratchpad = scratchpad_registry().registrar();
+            jit_sve_512_x8s8s32x_fwd_kernel::init_scratchpad(
+                    scratchpad, jcp_, *attr());
+
+            return status;
+        }
+
+        jit_conv_conf_t jcp_;
+    };
+
+    jit_sve_512_x8s8s32x_convolution_fwd_t(const pd_t *apd)
+        : primitive_t(apd) {}
+
+    typedef typename prec_traits<src_type>::type src_data_t;
+    typedef typename prec_traits<data_type::s8>::type wei_data_t;
+    typedef typename prec_traits<dst_type>::type dst_data_t;
+
+    status_t init(engine_t *engine) override {
+        CHECK(safe_ptr_assign(kernel_,
+                new jit_sve_512_x8s8s32x_fwd_kernel(
+                        pd()->jcp_, *pd()->attr())));
+        return kernel_->create_kernel();
+    }
+
+    status_t execute(const exec_ctx_t &ctx) const override {
+        const auto &_pd = pd();
+        if (_pd->ndims() == 3)
+            return execute_forward_1d(ctx);
+        else if (_pd->ndims() == 4)
+            if (_pd->jcp_.is_depthwise)
+                return execute_forward_2d_dw(ctx);
+            else
+                return execute_forward_2d(ctx);
+        else if (_pd->ndims() == 5)
+            return execute_forward_3d(ctx);
+        return status::unimplemented;
+    }
+
+private:
+    status_t execute_forward_1d(const exec_ctx_t &ctx) const;
+    status_t execute_forward_2d(const exec_ctx_t &ctx) const;
+    status_t execute_forward_2d_dw(const exec_ctx_t &ctx) const;
+    status_t execute_forward_3d(const exec_ctx_t &ctx) const;
+    const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); }
+
+    std::unique_ptr<jit_sve_512_x8s8s32x_fwd_kernel> kernel_;
+};
+
+} // namespace aarch64
+} // namespace cpu
+} // namespace impl
+} // namespace dnnl
+
+#endif
+
+// vim: et ts=4 sw=4 cindent cino+=l0,\:4,N-s

miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_uni_1x1_conv_utils.hpp

@@ -0,0 +1,680 @@
+/*******************************************************************************
+* Copyright 2021-2023 Intel Corporation
+* Copyright 2021-2023 FUJITSU LIMITED
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef CPU_AARCH64_JIT_UNI_1X1_CONV_UTILS_HPP
+#define CPU_AARCH64_JIT_UNI_1X1_CONV_UTILS_HPP
+
+#include "common/convolution_pd.hpp"
+#include "common/dnnl_thread.hpp"
+#include "common/memory_tracking.hpp"
+#include "common/nstl.hpp"
+#include "common/primitive_desc_iterator.hpp"
+#include "common/type_helpers.hpp"
+#include "common/utils.hpp"
+
+#include "cpu/aarch64/jit_generator.hpp"
+#include "cpu/aarch64/jit_primitive_conf.hpp"
+
+namespace dnnl {
+namespace impl {
+namespace cpu {
+namespace aarch64 {
+
+struct reduce_to_unit_stride_t {
+    convolution_desc_t conv_d_;
+    bool reduce_src_;
+    size_t space_per_thread_;
+};
+
+/* 1x1-kernel does not support non-unit strides so far, so the idea is:
+ *  - for fwd or bwd_weights: to copy src to a scratch memory (with strides
+ *    equal to 1) and then call the kernel
+ *  - for bwd_data: reduce the problem to the one with unit stride by
+ *    performing computations in a scratch memory (with strides equal to 1)
+ *    and then copy the result to diff_src */
+template <typename conv_pd_t>
+inline void rtus_prepare(conv_pd_t *self, const convolution_desc_t *&conv_d,
+        const memory_desc_t *&src_d, const memory_desc_t *dst_d) {
+    const int ndims = src_d->ndims;
+
+    bool rtus_applicable = utils::one_of(ndims, 3, 4);
+    if (ndims == 3)
+        rtus_applicable = rtus_applicable && conv_d->strides[0] != 1
+                && conv_d->src_desc.data_type != data_type::s32;
+    else
+        rtus_applicable = rtus_applicable
+                && (conv_d->strides[0] != 1 || conv_d->strides[1] != 1);
+    for (int d = 2; d < ndims; ++d) {
+        /* TODO: relax these conditions (by improving reducer) */
+        rtus_applicable = rtus_applicable && conv_d->padding[0][d - 2] == 0
+                && dst_d->dims[d] * conv_d->strides[d - 2] == src_d->dims[d];
+    }
+    if (!rtus_applicable) return;
+
+    const auto dat_tag = ndims == 3
+            ? memory_desc_wrapper(src_d).matches_one_of_tag(
+                    format_tag::nCw8c, format_tag::nCw16c, format_tag::nwc)
+            : memory_desc_wrapper(src_d).matches_one_of_tag(
+                    format_tag::nChw8c, format_tag::nChw16c, format_tag::nhwc);
+    if (dat_tag == format_tag::undef) return;
+
+    const bool is_nspc
+            = utils::one_of(dat_tag, format_tag::nwc, format_tag::nhwc);
+    if (is_nspc && !mayiuse(sve_128)) return;
+
+    // rtus is applicable, configure it.
+    self->rtus_.reduce_src_ = true;
+    conv_d = &(self->rtus_.conv_d_ = *conv_d);
+    self->rtus_.conv_d_.strides[0] = 1;
+    if (ndims == 4) self->rtus_.conv_d_.strides[1] = 1;
+    utils::array_set(self->rtus_.conv_d_.padding[0], 0, 2);
+    if (ndims == 4) utils::array_set(self->rtus_.conv_d_.padding[1], 0, 2);
+    const int ic = src_d->dims[1];
+    if (self->desc()->prop_kind == prop_kind::backward_data) {
+        data_type_t data_type = self->rtus_.conv_d_.diff_src_desc.data_type;
+        src_d = &(self->rtus_.conv_d_.diff_src_desc = *dst_d);
+        self->rtus_.conv_d_.diff_src_desc.dims[1] = ic;
+        self->rtus_.conv_d_.diff_src_desc.data_type = data_type;
+        memory_desc_wrapper::compute_blocking(
+                self->rtus_.conv_d_.diff_src_desc, dat_tag);
+    } else {
+        data_type_t data_type = self->rtus_.conv_d_.src_desc.data_type;
+        src_d = &(self->rtus_.conv_d_.src_desc = *dst_d);
+        self->rtus_.conv_d_.src_desc.dims[1] = ic;
+        self->rtus_.conv_d_.src_desc.data_type = data_type;
+        memory_desc_wrapper::compute_blocking(
+                self->rtus_.conv_d_.src_desc, dat_tag);
+    }
+}
+
+template <typename conv_pd_t>
+inline void rtus_prepare_space_info(conv_pd_t *self,
+        memory_tracking::registrar_t &scratchpad, int max_threads) {
+    if (!self->rtus_.reduce_src_) return;
+    const auto &jcp = self->jcp_;
+    const bool is_nspc
+            = utils::one_of(jcp.src_tag, format_tag::nhwc, format_tag::nwc);
+
+    const size_t factor = utils::pick_by_prop_kind(self->desc()->prop_kind,
+            jcp.nb_reduce, jcp.nb_load_blocking_max, jcp.nb_bcast_blocking);
+    size_t typesize
+            = types::data_type_size(self->invariant_src_md()->data_type);
+
+    self->rtus_.space_per_thread_
+            = is_nspc ? jcp.is * jcp.ic : factor * jcp.is * jcp.ic_block;
+    scratchpad.book(memory_tracking::names::key_conv_rtus_space,
+            max_threads * self->rtus_.space_per_thread_, typesize);
+}
+
+template <cpu_isa_t isa>
+struct rtus_driver_t : public jit_generator {
+
+    struct call_params_t {
+        const void *ws; /* reduced image (w/ strides = 1) */
+        const void *src; /* source image (w/ non-unit strides) */
+        size_t icb;
+        size_t os;
+        size_t iw_start;
+    };
+
+    DECLARE_CPU_JIT_AUX_FUNCTIONS(rtus_driver_t)
+
+    Xbyak_aarch64::XReg reg_ws = x5;
+    Xbyak_aarch64::XReg reg_src = x6;
+    Xbyak_aarch64::XReg reg_icb = x7;
+    Xbyak_aarch64::XReg reg_os = x8;
+    Xbyak_aarch64::XReg reg_iw_start = x9;
+
+    Xbyak_aarch64::XReg reg_cur_os = x10;
+    Xbyak_aarch64::XReg reg_cur_iw = x11;
+    Xbyak_aarch64::XReg reg_cur_src = x12;
+    Xbyak_aarch64::XReg reg_cur_src_fin = reg_cur_iw; /* just reuse */
+
+    Xbyak_aarch64::PReg tail_mask = p1;
+
+    // nspc section
+    Xbyak_aarch64::XReg reg_cur_icb = x13;
+    Xbyak_aarch64::XReg reg_tail_mask = x14;
+    Xbyak_aarch64::XReg reg_icb_remainder = x15;
+    Xbyak_aarch64::XReg reg_ws_copy = x16;
+
+    int iw_, stride_w_;
+    int src_step_h_, src_step_icb_, ws_step_icb_, vlen_, vlen_shift_;
+    bool src_to_ws_;
+    size_t typesize_;
+    int ic_, ic_tail_;
+    bool is_nspc_;
+
+    Xbyak_aarch64::ZReg reg_zero = Xbyak_aarch64::ZReg(0);
+    Xbyak_aarch64::ZReg reg_v = Xbyak_aarch64::ZReg(1);
+
+    rtus_driver_t(int iw, int stride_w, int src_step_h, int src_step_icb,
+            int ws_step_icb, bool src_to_ws, size_t typesize, int ic,
+            bool is_nspc = false)
+        : iw_(iw)
+        , stride_w_(stride_w)
+        , src_step_h_(src_step_h)
+        , src_step_icb_(src_step_icb)
+        , ws_step_icb_(ws_step_icb)
+        , src_to_ws_(src_to_ws)
+        , typesize_(typesize)
+        , ic_(ic)
+        , is_nspc_(is_nspc) {
+        using namespace Xbyak_aarch64;
+
+        assert(ic_ > 0);
+
+        auto Vmm = [=](int idx, size_t typesize) {
+            ZReg res = ZReg(idx);
+            if (is_nspc_) {
+                switch (isa) {
+                    case sve_512: res = ZReg(idx); break;
+                    default: assert(!"Not supported isa"); res = ZReg(idx);
+                }
+                return res;
+            }
+            switch (isa) {
+                case sve_512:
+                    switch (typesize) {
+                        case 4: res = ZReg(idx); break;
+                        default:
+                            assert(!"Not supported typesize");
+                            res = ZReg(idx);
+                    }
+            }
+            return res;
+        };
+
+        reg_zero = Vmm(0, typesize);
+        reg_v = Vmm(1, typesize);
+
+        vlen_ = reg_v.getBit() / 8;
+        vlen_shift_ = 0;
+
+        int tvlen = is_nspc_ ? typesize_ : vlen_;
+        while (tvlen > 1) {
+            tvlen /= 2;
+            vlen_shift_++;
+        }
+
+        const int simd_w = vlen_ / sizeof(float);
+        ic_tail_ = ic_ % simd_w;
+    }
+
+    void loop_is() {
+        using namespace Xbyak_aarch64;
+
+        mov(reg_cur_src, reg_src);
+        mov(reg_cur_iw, reg_iw_start);
+        mov(reg_cur_os, reg_os);
+
+        Label is_loop;
+        L(is_loop);
+
+        if (src_to_ws_) {
+            ldr(reg_v, ptr(reg_cur_src));
+            str(reg_v, ptr(reg_ws));
+        } else {
+            ldr(reg_v, ptr(reg_ws));
+            str(reg_v, ptr(reg_cur_src));
+            for (int w = 1; w < stride_w_; ++w) {
+                add_imm(X_TMP_3, reg_cur_src, w * vlen_, X_TMP_4);
+                str(reg_zero, ptr(X_TMP_3));
+            }
+        }
+
+        add_imm(reg_ws, reg_ws, vlen_, X_TMP_4);
+        add_imm(reg_cur_src, reg_cur_src, stride_w_ * vlen_, X_TMP_4);
+
+        // for 1d or stride_h=1 convolutions the loop over h should be skipped
+        if (!(src_step_icb_ == iw_ || src_step_h_ == iw_)) {
+            Label skip_h_step;
+            add_imm(reg_cur_iw, reg_cur_iw, stride_w_, X_TMP_4);
+            cmp(reg_cur_iw, iw_);
+            b(LT, skip_h_step);
+
+            if (src_to_ws_) {
+                add_imm(reg_cur_src, reg_cur_src, (src_step_h_ - iw_) * vlen_,
+                        X_TMP_4);
+            } else {
+                mov(reg_cur_src_fin, reg_cur_src);
+                add_imm(reg_cur_src_fin, reg_cur_src_fin,
+                        (src_step_h_ - iw_) * vlen_, X_TMP_4);
+                Label ih_loop;
+                L(ih_loop);
+
+                for (int w = 0; w < stride_w_; ++w) {
+                    add_imm(X_TMP_3, reg_cur_src, w * vlen_, X_TMP_4);
+                    str(reg_zero, ptr(X_TMP_3));
+                }
+
+                add_imm(reg_cur_src, reg_cur_src, stride_w_ * vlen_, X_TMP_4);
+                cmp(reg_cur_src, reg_cur_src_fin);
+                b(LT, ih_loop);
+            }
+            mov(reg_cur_iw, 0);
+            L(skip_h_step);
+        }
+
+        subs_imm(reg_cur_os, reg_cur_os, vlen_, X_TMP_4);
+        b(NE, is_loop);
+
+        /* restore dst */
+        sub(reg_ws, reg_ws, reg_os);
+    }
+
+    void loop_is_nspc() {
+        using namespace Xbyak_aarch64;
+
+        assert(is_nspc_);
+
+        mov(reg_cur_src, reg_src);
+        mov(reg_cur_iw, reg_iw_start);
+
+        if (isa == sve_512) {
+            and_(reg_icb_remainder, reg_icb, (vlen_ / typesize_) - 1);
+            mov_imm(X_TMP_0, 0);
+            whilelt(tail_mask.s, X_TMP_0, reg_icb_remainder);
+        }
+
+        auto load_reg = [=](const ZReg &vreg, const XReg &reg,
+                                const int64_t offset, bool tail = false) {
+            if (is_superset(isa, sve_128)) {
+                add_imm(X_DEFAULT_ADDR, reg, offset, X_TMP_0);
+                switch (typesize_) {
+                    case 4:
+                        if (tail)
+                            ld1w(vreg.s, tail_mask / T_z, ptr(X_DEFAULT_ADDR));
+                        else
+                            ld1w(vreg.s, P_ALL_ONE / T_z, ptr(X_DEFAULT_ADDR));
+                        break;
+                    case 2:
+                        if (tail)
+                            ld1h(vreg.h, tail_mask / T_z, ptr(X_DEFAULT_ADDR));
+                        else
+                            ld1h(vreg.h, P_ALL_ONE / T_z, ptr(X_DEFAULT_ADDR));
+                        break;
+                    case 1:
+                        if (tail)
+                            ld1b(vreg.b, tail_mask / T_z, ptr(X_DEFAULT_ADDR));
+                        else
+                            ld1b(vreg.b, P_ALL_ONE / T_z, ptr(X_DEFAULT_ADDR));
+                        break;
+                    default: assert(!"Unsupported typesize");
+                }
+            } else {
+                assert("!Unsupported isa");
+            }
+        };
+
+        auto store_reg = [=](const XReg &reg, const ZReg &vreg,
+                                 const int64_t offset, bool tail = false) {
+            if (is_superset(isa, sve_128)) {
+                add_imm(X_DEFAULT_ADDR, reg, offset, X_TMP_0);
+                switch (typesize_) {
+                    case 4:
+                        if (tail)
+                            st1w(vreg.s, tail_mask / T_z, ptr(X_DEFAULT_ADDR));
+                        else
+                            st1w(vreg.s, P_ALL_ONE / T_z, ptr(X_DEFAULT_ADDR));
+                        break;
+                    case 2:
+                        if (tail)
+                            st1h(vreg.h, tail_mask / T_z, ptr(X_DEFAULT_ADDR));
+                        else
+                            st1h(vreg.h, P_ALL_ONE / T_z, ptr(X_DEFAULT_ADDR));
+                        break;
+                    case 1:
+                        if (tail)
+                            st1b(vreg.b, tail_mask / T_z, ptr(X_DEFAULT_ADDR));
+                        else
+                            st1b(vreg.b, P_ALL_ONE / T_z, ptr(X_DEFAULT_ADDR));
+                        break;
+                    default: assert(!"Unsupported typesize");
+                }
+            } else {
+                assert("!Unsupported isa");
+            }
+        };
+
+        mov(reg_ws_copy, reg_ws);
+        lsl(reg_icb, reg_icb, vlen_shift_);
+
+        const size_t w_step_factor = ic_ * typesize_;
+        const size_t max_load_store_bytes = typesize_ == 4 ? 32 : 16;
+        const size_t load_store_size
+                = isa == sve_512 ? vlen_ : max_load_store_bytes;
+
+        Label is_loop, ic_loop, ic_loop_tail, ic_loop_finish;
+        L(is_loop);
+        {
+            mov(reg_cur_src, reg_src);
+            mov(reg_ws, reg_ws_copy);
+            mov(reg_cur_icb, reg_icb);
+
+            L(ic_loop);
+            {
+                cmp(reg_cur_icb, load_store_size);
+                b(LT, ic_loop_tail);
+
+                if (src_to_ws_) {
+                    load_reg(reg_v, reg_cur_src, 0);
+                    store_reg(reg_ws, reg_v, 0);
+                } else {
+                    load_reg(reg_v, reg_ws, 0);
+                    store_reg(reg_cur_src, reg_v, 0);
+                    for (int w = 1; w < stride_w_; ++w)
+                        store_reg(reg_cur_src, reg_zero, w * w_step_factor);
+                }
+                add_imm(reg_ws, reg_ws, load_store_size, X_TMP_0);
+                add_imm(reg_cur_src, reg_cur_src, load_store_size, X_TMP_0);
+
+                sub_imm(reg_cur_icb, reg_cur_icb, load_store_size, X_TMP_0);
+                b(ic_loop);
+            }
+
+            L(ic_loop_tail);
+            {
+                cmp(reg_cur_icb, 0);
+                b(EQ, ic_loop_finish);
+
+                if (src_to_ws_) {
+                    load_reg(reg_v, reg_cur_src, 0, true);
+                    store_reg(reg_ws, reg_v, 0, true);
+                } else {
+                    load_reg(reg_v, reg_ws, 0, true);
+                    store_reg(reg_cur_src, reg_v, 0, true);
+                    for (int w = 1; w < stride_w_; ++w)
+                        store_reg(
+                                reg_cur_src, reg_zero, w * w_step_factor, true);
+                }
+            }
+            L(ic_loop_finish);
+
+            add_imm(reg_ws_copy, reg_ws_copy, w_step_factor, X_TMP_0);
+            add_imm(reg_src, reg_src, stride_w_ * w_step_factor, X_TMP_0);
+
+            // for 1d or stride_h=1 convolutions the loop over h should be skipped
+            const bool skip_oh_step = src_step_h_ == iw_;
+            if (!skip_oh_step) {
+                mov(reg_cur_src, reg_src);
+                Label skip_h_step;
+                add_imm(reg_cur_iw, reg_cur_iw, stride_w_, X_TMP_0);
+                cmp(reg_cur_iw, iw_);
+                b(LT, skip_h_step);
+
+                if (src_to_ws_) {
+                    add_imm(reg_src, reg_src,
+                            (src_step_h_ - iw_) * w_step_factor, X_TMP_0);
+                } else {
+                    mov(reg_cur_src_fin, reg_cur_src);
+                    add_imm(reg_cur_src_fin, reg_cur_src_fin,
+                            (src_step_h_ - iw_) * w_step_factor, X_TMP_0);
+                    Label ih_loop_nhwc, ic_ih_loop_nhwc, ic_tail_ih_loop_nhwc,
+                            ic_finish_ih_loop_nhwc;
+                    L(ih_loop_nhwc);
+                    mov(reg_cur_src, reg_src);
+                    mov(reg_cur_icb, reg_icb);
+                    L(ic_ih_loop_nhwc);
+                    cmp(reg_cur_icb, load_store_size);
+                    b(LT, ic_tail_ih_loop_nhwc);
+
+                    for (int w = 0; w < stride_w_; ++w)
+                        store_reg(reg_cur_src, reg_zero, w * w_step_factor);
+
+                    add_imm(reg_cur_src, reg_cur_src, load_store_size, X_TMP_0);
+                    subs_imm(
+                            reg_cur_icb, reg_cur_icb, load_store_size, X_TMP_0);
+                    b(NE, ic_ih_loop_nhwc);
+
+                    L(ic_tail_ih_loop_nhwc);
+                    cmp(reg_cur_icb, 0);
+                    b(LE, ic_finish_ih_loop_nhwc);
+
+                    for (int w = 0; w < stride_w_; ++w)
+                        store_reg(
+                                reg_cur_src, reg_zero, w * w_step_factor, true);
+
+                    L(ic_finish_ih_loop_nhwc);
+
+                    add_imm(reg_src, reg_src, stride_w_ * w_step_factor,
+                            X_TMP_0);
+                    cmp(reg_src, reg_cur_src_fin);
+                    b(LT, ih_loop_nhwc);
+                }
+                eor(reg_cur_iw, reg_cur_iw, reg_cur_iw);
+                L(skip_h_step);
+            }
+
+            subs(reg_os, reg_os, 1);
+            b(NE, is_loop);
+        }
+    }
+
+    void generate() override {
+        using namespace Xbyak_aarch64;
+        assert(isa == sve_512);
+
+        preamble();
+#define READ_PARAM(what) \
+    ldr(reg_##what, \
+            ptr(abi_param1, \
+                    static_cast<int32_t>(offsetof(call_params_t, what))))
+        READ_PARAM(src);
+        READ_PARAM(icb);
+        READ_PARAM(os);
+        READ_PARAM(iw_start);
+        READ_PARAM(ws);
+#undef READ_PARAM
+
+        if (!src_to_ws_) {
+            switch (reg_zero.getBit() / 8) {
+                case 64 /*ZReg*/: {
+                    Xbyak_aarch64::ZRegS zreg_s(reg_zero.getIdx());
+                    fmov(zreg_s); // zero clear
+                    break;
+                }
+                default: assert(!"rtus kernel failure");
+            }
+        }
+        if (is_nspc_) {
+            loop_is_nspc();
+        } else {
+            lsl(reg_os, reg_os, vlen_shift_);
+
+            Label icb_loop;
+            L(icb_loop);
+
+            loop_is();
+
+            add_imm(reg_ws, reg_ws, ws_step_icb_ * vlen_, X_TMP_4);
+            add_imm(reg_src, reg_src, src_step_icb_ * vlen_, X_TMP_4);
+
+            subs_imm(reg_icb, reg_icb, vlen_ / typesize_, X_TMP_4);
+            b(NE, icb_loop);
+        }
+
+        postamble();
+    }
+};
+
+template <cpu_isa_t isa, typename conv_t>
+inline status_t init_rtus_driver(conv_t *self) {
+    const auto &conf = *self->pd();
+    if (!conf.rtus_.reduce_src_) return status::success;
+
+    const auto &cd = *conf.desc();
+    const int ndims = conf.ndims();
+    const int stride_h = (conf.ndims() == 3) ? 1 : cd.strides[0];
+    const int stride_w = cd.strides[ndims - 3];
+
+    const bool is_bwd_data = cd.prop_kind == prop_kind::backward_data;
+    const auto &src_d = is_bwd_data ? *conf.diff_src_md() : *conf.src_md();
+
+    const int ih = ndims == 3 ? 1 : src_d.dims[2];
+    const int iw = src_d.dims[ndims - 1];
+    const int ic = src_d.dims[1];
+
+    const auto src_tag = memory_desc_wrapper(src_d).matches_one_of_tag(
+            format_tag::nhwc, format_tag::nwc);
+    const bool is_nspc = src_tag != format_tag::undef;
+    const int src_step_h = stride_h * iw;
+    const int src_step_icb = !is_nspc ? ih * iw : 1;
+    const int ws_step_icb = !is_nspc ? conf.jcp_.is : 1;
+    const bool src_to_ws = !is_bwd_data;
+    const size_t typesize
+            = types::data_type_size(self->pd()->invariant_src_md()->data_type);
+
+    CHECK(safe_ptr_assign(self->rtus_driver_,
+            new rtus_driver_t<isa>(iw, stride_w, src_step_h, src_step_icb,
+                    ws_step_icb, src_to_ws, typesize, ic, is_nspc)));
+
+    return self->rtus_driver_->create_kernel();
+}
+
+inline int best_divider(int value, int min_divider, int max_divider,
+        bool find_max, int step = 1) {
+    using namespace dnnl::impl::utils;
+    max_divider = nstl::max(1, nstl::min(max_divider, value));
+    min_divider = nstl::max(1, nstl::min(min_divider, max_divider));
+
+    auto loss_ratio = [](int total, int chunk) {
+        return float(rnd_up(total, chunk) - total) / rnd_up(total, chunk);
+    };
+
+    float min_loss = FLT_MAX;
+    int x_divider = max_divider;
+    for (int divider = max_divider; divider >= min_divider; divider -= step) {
+        const float loss = loss_ratio(value, divider);
+        if ((find_max && loss < min_loss) || (!find_max && loss <= min_loss)) {
+            min_loss = loss;
+            x_divider = divider;
+        }
+    }
+    return x_divider;
+}
+
+typedef jit_1x1_conv_conf_t jcp_t;
+
+inline bool is_bcast_layout_nxc(const jcp_t &jcp) {
+    switch (jcp.prop_kind) {
+        case prop_kind::forward_training:
+        case prop_kind::forward_inference:
+        case prop_kind::backward_weights:
+            return utils::one_of(jcp.src_tag, format_tag::ndhwc,
+                    format_tag::nhwc, format_tag::nwc);
+        case prop_kind::backward_data:
+            return utils::one_of(jcp.dst_tag, format_tag::ndhwc,
+                    format_tag::nhwc, format_tag::nwc);
+        default: assert(!"invalid prop_kind"); return false;
+    }
+}
+
+inline bool is_load_layout_nxc(const jcp_t &jcp) {
+    return jcp.prop_kind == prop_kind::backward_weights
+            && utils::one_of(jcp.dst_tag, format_tag::ndhwc, format_tag::nhwc,
+                    format_tag::nwc);
+}
+
+inline bool is_out_layout_nxc(const jcp_t &jcp) {
+    switch (jcp.prop_kind) {
+        case prop_kind::forward_training:
+        case prop_kind::forward_inference:
+            return utils::one_of(jcp.dst_tag, format_tag::ndhwc,
+                    format_tag::nhwc, format_tag::nwc);
+        case prop_kind::backward_data:
+            return utils::one_of(jcp.src_tag, format_tag::ndhwc,
+                    format_tag::nhwc, format_tag::nwc);
+        case prop_kind::backward_weights: return false;
+        default: assert(!"invalid prop_kind"); return false;
+    }
+}
+
+inline size_t get_bcast_u_offset(const jcp_t &jcp) {
+    return is_bcast_layout_nxc(jcp) ? jcp.ic : jcp.ic_block;
+}
+
+inline size_t get_bcast_j_offset(const jcp_t &jcp) {
+    return is_bcast_layout_nxc(jcp) ? jcp.reduce_dim : jcp.reduce_loop_unroll;
+}
+
+inline size_t get_bcast_offset(const jcp_t &jcp, int u, int j) {
+    size_t offset;
+    if (utils::one_of(jcp.prop_kind, prop_kind::forward_training,
+                prop_kind::forward_inference, prop_kind::backward_data)) {
+        assert(jcp.reduce_loop_unroll == jcp.reduce_block);
+        if (is_bcast_layout_nxc(jcp) || u != jcp.reduce_loop_unroll) {
+            offset = j * get_bcast_j_offset(jcp) + u;
+        } else {
+            offset = (jcp.bcast_dim + j) * get_bcast_j_offset(jcp);
+        }
+    } else {
+        offset = u * get_bcast_u_offset(jcp) + j;
+    }
+    return sizeof(float) * offset;
+}
+
+inline size_t get_load_u_offset(const jcp_t &jcp) {
+    return is_load_layout_nxc(jcp) ? jcp.oc : jcp.oc_block;
+}
+
+inline size_t get_load_i_offset(const jcp_t &jcp) {
+    return is_load_layout_nxc(jcp) ? jcp.oc_block : jcp.os;
+}
+
+inline size_t get_load_bwd_w_offset(const jcp_t &jcp, int i, int u0) {
+    if (is_load_layout_nxc(jcp)) {
+        return i * get_load_i_offset(jcp) + u0 * get_load_u_offset(jcp);
+    } else {
+        return (i * get_load_i_offset(jcp) + u0) * get_load_u_offset(jcp);
+    }
+}
+
+inline size_t get_output_i_offset(const jcp_t &jcp) {
+    if (is_out_layout_nxc(jcp)) {
+        return jcp.load_block;
+    } else {
+        return (jcp.with_dw_conv ? jcp.ow : jcp.bcast_dim) * jcp.load_block;
+    }
+}
+
+inline size_t get_output_j_offset(const jcp_t &jcp) {
+    return is_out_layout_nxc(jcp) ? jcp.load_dim : jcp.load_block;
+}
+
+inline size_t get_load_loop_output_fwd_offset(
+        const jcp_t &jcp, int load_loop_blk) {
+    size_t offset = load_loop_blk * jcp.oc_block * sizeof(float);
+    if (!is_out_layout_nxc(jcp)) {
+        offset *= jcp.with_dw_conv ? jcp.ow : jcp.os;
+    }
+    return offset;
+}
+
+inline size_t get_load_loop_output_bwd_d_offset(
+        const jcp_t &jcp, int load_loop_blk) {
+    size_t offset = load_loop_blk * jcp.ic_block * sizeof(float);
+    if (!is_out_layout_nxc(jcp)) { offset *= jcp.os; }
+    return offset;
+}
+
+} // namespace aarch64
+} // namespace cpu
+} // namespace impl
+} // namespace dnnl
+
+#endif

miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_uni_batch_normalization.hpp

@@ -0,0 +1,105 @@
+/*******************************************************************************
+* Copyright 2017-2022 Intel Corporation
+* Copyright 2020-2022 FUJITSU LIMITED
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef CPU_AARCH64_JIT_UNI_BATCH_NORMALIZATION_HPP
+#define CPU_AARCH64_JIT_UNI_BATCH_NORMALIZATION_HPP
+
+#include <assert.h>
+
+#include "common/c_types_map.hpp"
+#include "common/primitive.hpp"
+#include "common/type_helpers.hpp"
+#include "common/utils.hpp"
+
+#include "cpu/cpu_batch_normalization_pd.hpp"
+
+#include "cpu/aarch64/cpu_isa_traits.hpp"
+
+namespace dnnl {
+namespace impl {
+namespace cpu {
+namespace aarch64 {
+
+namespace bnorm_impl {
+template <cpu_isa_t isa>
+struct driver_t;
+}
+
+template <cpu_isa_t isa>
+struct jit_uni_batch_normalization_fwd_t : public primitive_t {
+    struct pd_t : public cpu_batch_normalization_fwd_pd_t {
+        pd_t(const batch_normalization_desc_t *adesc,
+                const primitive_attr_t *attr,
+                const batch_normalization_fwd_pd_t *hint_fwd_pd)
+            : cpu_batch_normalization_fwd_pd_t(adesc, attr, hint_fwd_pd) {}
+
+        DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("bnorm_jit:", isa, ""),
+                jit_uni_batch_normalization_fwd_t);
+
+        status_t init(engine_t *engine);
+        int nthr_; // To not exceed the limit in execute used for set up.
+    };
+
+    jit_uni_batch_normalization_fwd_t(const pd_t *apd);
+    ~jit_uni_batch_normalization_fwd_t();
+
+    status_t init(engine_t *engine) override;
+
+    status_t execute(const exec_ctx_t &ctx) const override;
+
+private:
+    const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); }
+
+    bnorm_impl::driver_t<isa> *bnorm_driver_;
+};
+
+template <cpu_isa_t isa>
+struct jit_uni_batch_normalization_bwd_t : public primitive_t {
+    struct pd_t : public cpu_batch_normalization_bwd_pd_t {
+        pd_t(const batch_normalization_desc_t *adesc,
+                const primitive_attr_t *attr,
+                const batch_normalization_fwd_pd_t *hint_fwd_pd)
+            : cpu_batch_normalization_bwd_pd_t(adesc, attr, hint_fwd_pd) {}
+
+        DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("bnorm_jit:", isa, ""),
+                jit_uni_batch_normalization_bwd_t);
+
+        status_t init(engine_t *engine);
+        int nthr_; // To not exceed the limit in execute used for set up.
+    };
+
+    jit_uni_batch_normalization_bwd_t(const pd_t *apd);
+    ~jit_uni_batch_normalization_bwd_t();
+
+    status_t init(engine_t *engine) override;
+
+    status_t execute(const exec_ctx_t &ctx) const override;
+
+private:
+    const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); }
+
+    bnorm_impl::driver_t<isa> *bnorm_driver_;
+};
+
+} // namespace aarch64
+} // namespace cpu
+} // namespace impl
+} // namespace dnnl
+
+#endif
+
+// vim: et ts=4 sw=4 cindent cino+=l0,\:4,N-s

miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_uni_batch_normalization_s8.hpp

@@ -0,0 +1,77 @@
+/*******************************************************************************
+* Copyright 2021 Intel Corporation
+* Copyright 2021 FUJITSU LIMITED
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef CPU_AARCH64_JIT_UNI_BATCH_NORMALIZATION_S8_HPP
+#define CPU_AARCH64_JIT_UNI_BATCH_NORMALIZATION_S8_HPP
+
+#include <assert.h>
+
+#include "common/c_types_map.hpp"
+#include "common/primitive.hpp"
+#include "common/type_helpers.hpp"
+#include "common/utils.hpp"
+
+#include "cpu/aarch64/cpu_isa_traits.hpp"
+#include "cpu/cpu_batch_normalization_pd.hpp"
+
+namespace dnnl {
+namespace impl {
+namespace cpu {
+namespace aarch64 {
+
+namespace bnorm_s8_impl {
+template <cpu_isa_t isa>
+struct driver_t;
+}
+
+template <cpu_isa_t isa>
+struct jit_uni_batch_normalization_s8_fwd_t : public primitive_t {
+    struct pd_t : public cpu_batch_normalization_fwd_pd_t {
+        pd_t(const batch_normalization_desc_t *adesc,
+                const primitive_attr_t *attr,
+                const batch_normalization_fwd_pd_t *hint_fwd_pd)
+            : cpu_batch_normalization_fwd_pd_t(adesc, attr, hint_fwd_pd) {}
+
+        DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("bnorm_s8_jit:", isa, ""),
+                jit_uni_batch_normalization_s8_fwd_t);
+
+        status_t init(engine_t *engine);
+    };
+
+    typedef int8_t data_t;
+
+    jit_uni_batch_normalization_s8_fwd_t(const pd_t *apd);
+    ~jit_uni_batch_normalization_s8_fwd_t();
+
+    status_t init(engine_t *engine) override;
+
+    status_t execute(const exec_ctx_t &ctx) const override;
+
+private:
+    const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); }
+
+    bnorm_s8_impl::driver_t<isa> *bnorm_driver_;
+};
+
+} // namespace aarch64
+} // namespace cpu
+} // namespace impl
+} // namespace dnnl
+
+#endif
+
+// vim: et ts=4 sw=4 cindent cino+=l0,\:4,N-s

miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_uni_binary.hpp

@@ -0,0 +1,116 @@
+/*******************************************************************************
+* Copyright 2019-2023 Intel Corporation
+* Copyright 2022-2023 FUJITSU LIMITED
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef CPU_AARCH64_JIT_UNI_BINARY_HPP
+#define CPU_AARCH64_JIT_UNI_BINARY_HPP
+
+#include "common/primitive.hpp"
+
+#include "cpu/cpu_eltwise_pd.hpp"
+
+#include "cpu/aarch64/jit_uni_binary_kernel.hpp"
+
+namespace dnnl {
+namespace impl {
+namespace cpu {
+namespace aarch64 {
+
+struct binary_kernel_t;
+
+using op_t = binary_op_t;
+using bcast_t = binary_bcast_t;
+
+struct jit_uni_binary_t : public primitive_t {
+    struct pd_t : public cpu_binary_pd_t {
+        using cpu_binary_pd_t::cpu_binary_pd_t;
+
+        DECLARE_COMMON_PD_T("jit:uni", jit_uni_binary_t);
+
+        status_t init(engine_t *engine);
+
+        jit_binary_conf_t get_conf() const { return conf_; };
+
+    private:
+        op_t get_op_type(const memory_desc_wrapper &src0_d);
+        bool is_only_dim0_bcasted(const dims_t &bcast_dims, const int ndims);
+        bcast_t get_bcast_type(
+                const memory_desc_wrapper &src1_d, const dims_t &bcast_dims);
+
+        // alg_preserves_zero returns true if operation preserves zero in case
+        // of both inputs contain zero.
+        bool alg_preserves_zero() const;
+        bool check_scales_mask() const;
+        bool is_bcast_pattern(const dims_t &bcast_dims, const dim_t ndims,
+                const dim_t N_bcast, const dim_t C_bcast,
+                const dim_t W_bcast) const;
+        bool is_bcast_pattern(const dims_t &bcast_dims, const dim_t N_bcast,
+                const dim_t C_bcast) const;
+        bool is_bcast_allowed(const int ndims) const;
+        bool is_format_non_blocked(const memory_desc_wrapper &mdw) const;
+        bool is_different_layouts_allowed(const memory_desc_wrapper &src0_d,
+                const memory_desc_wrapper &src1_d) const;
+        bool is_applicable();
+
+        jit_binary_conf_t conf_;
+    };
+
+    jit_uni_binary_t(const pd_t *apd);
+    ~jit_uni_binary_t() = default;
+
+    status_t init(engine_t *engine) override;
+
+    using data_t = int8_t;
+
+    void execute_no_bcast_strategy(const data_t *src0, const data_t *src1,
+            data_t *dst, const float *scale0, const float *scale1,
+            const std::vector<const void *> &post_ops_binary_rhs_arg_vec,
+            const bcast_t bcast_type) const;
+    void execute_bcast_per_batch_strategy(const data_t *src0,
+            const data_t *src1, data_t *dst, const float *scale0,
+            const float *scale1,
+            const std::vector<const void *> &post_ops_binary_rhs_arg_vec) const;
+    void execute_bcast_per_c_strategy(const data_t *src0, const data_t *src1,
+            data_t *dst, const float *scale0, const float *scale1,
+            const std::vector<const void *> &post_ops_binary_rhs_arg_vec,
+            const op_t op_type, const bcast_t bcast_type,
+            const bool blocked_oc_tail) const;
+    void execute_bcast_per_w_strategy(const data_t *src0, const data_t *src1,
+            data_t *dst, const float *scale0, const float *scale1,
+            const std::vector<const void *> &post_ops_binary_rhs_arg_vec,
+            const op_t op_type, const bool blocked_oc_tail) const;
+
+    status_t execute(const exec_ctx_t &ctx) const override;
+
+private:
+    const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); }
+    static bool post_ops_ok(const primitive_attr_t *attr,
+            const memory_desc_wrapper &src0_d, const memory_desc_wrapper &dst_d,
+            const bool is_src1_different_layouts, const cpu_isa_t isa);
+
+    std::unique_ptr<binary_kernel_t> kernel_;
+    // used only in bcast_c_blocked strategy if tail exists
+    std::unique_ptr<binary_kernel_t> kernel_tail_;
+};
+
+} // namespace aarch64
+} // namespace cpu
+} // namespace impl
+} // namespace dnnl
+
+#endif
+
+// vim: et ts=4 sw=4 cindent cino+=l0,\:4,N-s

miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_uni_binary_kernel.hpp

@@ -0,0 +1,164 @@
+/*******************************************************************************
+* Copyright 2021-2023 Intel Corporation
+* Copyright 2022-2023 FUJITSU LIMITED
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef CPU_AARCH64_UNI_BINARY_KERNEL_HPP
+#define CPU_AARCH64_UNI_BINARY_KERNEL_HPP
+
+#include <cassert>
+
+#include "common/c_types_map.hpp"
+#include "common/type_helpers.hpp"
+#include "common/utils.hpp"
+
+#include "cpu/aarch64/cpu_isa_traits.hpp"
+#include "cpu/aarch64/injectors/jit_uni_postops_injector.hpp"
+#include "cpu/aarch64/jit_generator.hpp"
+#include "cpu/aarch64/jit_primitive_conf.hpp"
+#include "cpu/aarch64/utils/jit_io_helper.hpp"
+
+#include "cpu/cpu_binary_pd.hpp"
+
+namespace dnnl {
+namespace impl {
+namespace cpu {
+namespace aarch64 {
+
+using namespace Xbyak_aarch64;
+
+struct binary_kernel_t : public jit_generator {
+    using op_t = binary_op_t;
+    using bcast_t = binary_bcast_t;
+
+    binary_kernel_t(const size_t vlen, const binary_pd_t *pd,
+            const jit_binary_conf_t conf, bool tail_kernel = false);
+    ~binary_kernel_t() override = default;
+
+    void operator()(jit_binary_call_s *p) { jit_generator::operator()(p); }
+
+    size_t simd_w() const noexcept { return simd_w_; }
+    size_t vlen() const noexcept { return vlen_; }
+
+protected:
+    size_t get_tail_size() const;
+
+    const size_t vlen_;
+    const size_t simd_w_;
+    constexpr static int vmm_start_idx_ = 1;
+    const binary_pd_t *pd_;
+    const jit_binary_conf_t conf_;
+    const bool is_tail_kernel_;
+    const bool is_src1_outer_dims_tail_;
+    const size_t tail_size_;
+    const size_t padding_tail_size_;
+};
+
+template <cpu_isa_t isa>
+struct jit_uni_binary_kernel_t : public binary_kernel_t {
+    DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_uni_binary_kernel_t)
+
+    using Vmm = typename cpu_isa_traits<isa>::TReg;
+
+    const XReg reg_param_ = abi_param1;
+    const XReg reg_src0_ = x8;
+    const XReg reg_src1_ = x9;
+    const XReg reg_dst_ = x10;
+    const XReg reg_offt_src0_ = x11;
+    const XReg reg_outer_dims_range_ = x12;
+    const XReg reg_offt_src1_ = x1;
+    const XReg reg_src1_stride_range_ = x15;
+    const XReg reg_reverse_src1_stride_range_ = x1;
+    const XReg reg_reverse_spat_offt_ = x13;
+    const XReg reg_tmp_ = x14;
+    const XReg reg_tmp1_ = x6;
+    const XReg reg_elt_inj_table_ = x15;
+    const XReg reg_off_rhs_postops_ = x2;
+    const XReg reg_scales_src0_ = x3;
+    const XReg reg_scales_src1_ = x5;
+    const XReg reg_offt_dst_ = x2;
+    const PReg tail_opmask_ = p2;
+    const PReg cmp_mask = p3;
+    const PReg full_mask_ = p4;
+    const Vmm vmm_tail_vmask_ = Vmm(0);
+    const Vmm vreg_sum_scale_ = Vmm(17);
+    const VReg xreg_sum_scale_ = VReg(9);
+    const Vmm vreg_zero_ = Vmm(18);
+    const Vmm vreg_one_ = Vmm(19);
+    const Vmm vreg_saturation_ubound_ = Vmm(20);
+    const Vmm vreg_bcast_src1_ = Vmm(21);
+    const VReg xreg_bcast_src1_ = VReg(13);
+    const Vmm vreg_scales_src0_ = Vmm(22);
+    const Vmm vreg_scales_src1_ = Vmm(23);
+
+    const Vmm vmm_full_mask_ = Vmm(24);
+    const Vmm vmm_tmp_gather_ = Vmm(25);
+    const Vmm vmm_indices_ = Vmm(30);
+    const Vmm vmm_gathered_src_ = Vmm(31);
+
+    const size_t unroll_regs_ = 8;
+    const size_t offt_src0_;
+    const size_t offt_src1_;
+
+    static constexpr cpu_isa_t inject_isa = isa;
+    io::jit_io_multi_dt_helper_t<Vmm> io_;
+    std::unique_ptr<injector::jit_uni_postops_injector_t<inject_isa>>
+            postops_injector_;
+    const PReg elt_inj_opmask_ = p1;
+    const PReg elt_inj_p_tmp0_ = p2;
+    const PReg elt_inj_p_all_ = p3;
+
+    void init();
+    void init_post_ops_injector();
+    void apply_postops(int unroll, bool tail);
+    void load_kernel_params();
+    XReg src0_ptr(size_t offt = 0);
+    XReg src1_ptr(size_t offt = 0);
+    XReg dst_ptr(size_t offt = 0);
+    unsigned int cmp_predicate(alg_kind_t alg);
+    void perform_op(
+            const Vmm &v0, const Vmm &v1, const Vmm &s_src0, const Vmm &s_src1);
+    void prepare_isa_kernel();
+    void compute_bcast(bool tail);
+    void load_src1(const Vmm &vreg_src1, const int offt, bool tail);
+    void store(int unroll, bool tail);
+    void compute_dst_body(int unroll, bool tail);
+    void compute_dst(int unroll, bool tail);
+    void forward();
+    void forward_over_outer_dims();
+    void generate() override;
+
+    void compute_cmp_mask(const Xbyak_aarch64::PReg &cmp_dst,
+            const Vmm &cmp_src, const Vmm &cmp_src2, const unsigned int uimm);
+
+    void push(const XReg &reg);
+    void pop(const XReg &reg);
+
+    void uni_broadcast(const Vmm &dst, const Xbyak_aarch64::XReg &addr);
+
+    jit_uni_binary_kernel_t(const binary_pd_t *pd, const jit_binary_conf_t conf,
+            bool tail_kernel = false);
+    ~jit_uni_binary_kernel_t() override = default;
+
+    std::map<data_type_t, io::io_saturation_conf_t>
+    create_saturation_vmm_map() const;
+};
+
+} // namespace aarch64
+} // namespace cpu
+} // namespace impl
+} // namespace dnnl
+
+#endif

miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_uni_deconv_zp_pad_str_kernel.hpp

@@ -0,0 +1,124 @@
+/*******************************************************************************
+* Copyright 2021-2022 Intel Corporation
+* Copyright 2022 FUJITSU LIMITED
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef CPU_AARCH64_JIT_UNI_DECONV_ZP_PAD_STR_KERNEL_HPP
+#define CPU_AARCH64_JIT_UNI_DECONV_ZP_PAD_STR_KERNEL_HPP
+
+#include "cpu/aarch64/jit_generator.hpp"
+
+namespace dnnl {
+namespace impl {
+namespace cpu {
+namespace aarch64 {
+
+struct jit_conv_conf_t;
+
+namespace zp {
+
+struct jit_uni_deconv_zp_pad_str_call_params_t {
+    const int8_t *wei;
+    const int32_t *src_zero_point;
+    int32_t *dst_scratchpad;
+    bool last_oc_block;
+};
+
+/*
+ * Compute zero point source compensation applied during filter application on
+ * the padding as well as stride holes.
+ *
+ * zp_pad_str_compensation = conv(1, weights_s8) * zero_point_source
+ *
+ * output_format - dhwc
+ */
+class jit_uni_deconv_zp_pad_str_kernel_base_t : public jit_generator {
+public:
+    jit_uni_deconv_zp_pad_str_kernel_base_t(const jit_conv_conf_t &jcp);
+
+    void operator()(const jit_uni_deconv_zp_pad_str_call_params_t *params) {
+        jit_generator::operator()(params);
+    }
+
+    DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_uni_deconv_zp_pad_str_kernel_base_t);
+
+private:
+    DNNL_DISALLOW_COPY_AND_ASSIGN(jit_uni_deconv_zp_pad_str_kernel_base_t);
+
+    void generate() override;
+    void load_addresses();
+    void compute();
+    virtual void compute_step(const dim_t icb_offset) = 0;
+    virtual void apply_zero_point() = 0;
+    virtual void store_result() = 0;
+    virtual void init() = 0;
+
+protected:
+    size_t number_reserved_vmms_ = 0;
+    size_t reserve_vmm();
+
+    const jit_conv_conf_t &jcp_;
+
+    const Xbyak_aarch64::XReg &reg_src_zp_ = x8;
+    const Xbyak_aarch64::XReg &reg_wei_ = x9;
+    const Xbyak_aarch64::XReg &reg_dst_ = x10;
+    const Xbyak_aarch64::WReg &reg_last_oc_block_ = w12;
+    const size_t tail_size_;
+};
+
+template <cpu_isa_t isa>
+class jit_uni_deconv_zp_pad_str_kernel_t
+    : public jit_uni_deconv_zp_pad_str_kernel_base_t {
+public:
+    jit_uni_deconv_zp_pad_str_kernel_t(const jit_conv_conf_t &jcp);
+
+private:
+    using TReg = typename cpu_isa_traits<isa>::TReg;
+
+    void init() override;
+    void compute_step(const dim_t icb_offset) override;
+    void apply_zero_point() override;
+    void store_result() override;
+
+    uint32_t get_next_vmm_idx();
+
+    const TReg result_acc_;
+    const TReg vmm_tmp_;
+    const TReg vmm_one_bytes_;
+    const TReg vmm_one_words_;
+
+    const Xbyak_aarch64::PReg &ktail_mask_ = p2;
+    dim_t current_vmm_;
+};
+
+bool should_calculate_deconv_zp_src_pad_str_comp(
+        const jit_conv_conf_t &jcp) noexcept;
+
+template <cpu_isa_t isa>
+jit_uni_deconv_zp_pad_str_kernel_base_t *create_deconv_zp_pad_str_comp_ker(
+        const jit_conv_conf_t &jcp);
+
+void compute_deconv_zp_pad_str_comp_ker(const jit_conv_conf_t &jcp_,
+        const bool with_groups, const memory_desc_wrapper &wei_d,
+        const int8_t *wei, const int32_t *src_zp, int32_t *dst,
+        jit_uni_deconv_zp_pad_str_kernel_base_t *ker);
+
+} // namespace zp
+} // namespace aarch64
+} // namespace cpu
+} // namespace impl
+} // namespace dnnl
+
+#endif

miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_uni_dw_conv_kernel_f32.hpp

@@ -0,0 +1,268 @@
+/*******************************************************************************
+* Copyright 2021-2022 Intel Corporation
+* Copyright 2021-2022 FUJITSU LIMITED
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef CPU_AARCH64_JIT_UNI_DW_CONV_KERNEL_F32_HPP
+#define CPU_AARCH64_JIT_UNI_DW_CONV_KERNEL_F32_HPP
+
+#include "common/c_types_map.hpp"
+#include "common/memory_tracking.hpp"
+
+#include "cpu/aarch64/jit_generator.hpp"
+#include "cpu/aarch64/jit_primitive_conf.hpp"
+
+#include "cpu/aarch64/injectors/jit_uni_eltwise_injector.hpp"
+
+using namespace Xbyak_aarch64;
+
+namespace dnnl {
+namespace impl {
+namespace cpu {
+namespace aarch64 {
+
+template <cpu_isa_t isa>
+struct jit_uni_dw_conv_fwd_kernel_f32 : public jit_generator {
+    DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_uni_dw_conv_fwd_kernel_f32)
+
+    jit_uni_dw_conv_fwd_kernel_f32(jit_conv_conf_t ajcp)
+        : jcp(ajcp), eltwise_injector_(nullptr) {
+        if (jcp.with_eltwise)
+            eltwise_injector_ = new jit_uni_eltwise_injector_f32<sve_512>(
+                    this, jcp.eltwise);
+    }
+
+    ~jit_uni_dw_conv_fwd_kernel_f32() { delete eltwise_injector_; }
+
+    jit_conv_conf_t jcp;
+
+private:
+    using reg64_t = const XReg;
+    const int vlen = cpu_isa_traits<isa>::vlen;
+
+    // dw convolution
+    reg64_t reg_input = x1;
+    reg64_t aux_reg_input = x2;
+    reg64_t reg_kernel = x3;
+    reg64_t aux_reg_kernel = x5;
+    reg64_t reg_ch_blocks = x6;
+    reg64_t reg_output = x7;
+    reg64_t reg_bias = x8;
+    reg64_t reg_kh = x9;
+    reg64_t iter_kh = x10;
+    reg64_t reg_oi = x11;
+    reg64_t aux_reg_ch_blocks = x12;
+    // fused convolution
+    reg64_t reg_input_buffer_ptr = x13;
+    reg64_t aux_reg_input_buffer_ptr = x14;
+    reg64_t reg_iw_offset = reg_input;
+
+    /* Temprary regs */
+    reg64_t reg_tmp_imm = x15;
+    reg64_t reg_kernel_stack = x16;
+    reg64_t reg_input_stack = x17;
+    reg64_t reg_output_stack = x27;
+    reg64_t reg_bias_stack = x19;
+    reg64_t reg_tmp_addr = x20;
+
+    inline void load_src(int ur_ch_blocks, int ur_w);
+    inline void compute_loop(int ur_w, int ur_ch_blocks, int pad_l, int pad_r);
+    inline void ow_loop(int ur_ch_blocks);
+    inline void apply_filter_unrolled(
+            int ur_ch_blocks, int ur_w, int pad_l, int pad_r);
+    inline void apply_activation(int ur_ch_blocks, int ur_w);
+    inline void store_dst(int ur_ch_blocks, int ur_w);
+
+    inline ZReg get_ker_reg(int idx) {
+        assert(idx <= 31);
+        return ZReg(idx + 0);
+    }
+    inline ZRegS get_ker_reg_s(int idx) {
+        assert(idx <= 31);
+        return ZRegS(idx + 0);
+    }
+    inline ZReg get_src_reg(int idx) {
+        assert((idx + 1) <= 31);
+        return ZReg(idx + 1);
+    }
+    inline ZRegS get_src_reg_s(int idx) {
+        assert((idx + 1) <= 31);
+        return ZRegS(idx + 1);
+    }
+
+    inline ZReg get_acc_reg(int idx) {
+        assert((idx + 4) <= 31);
+        return ZReg(idx + 4);
+    }
+    inline ZRegS get_acc_reg_s(int idx) {
+        assert((idx + 4) <= 31);
+        return ZRegS(idx + 4);
+    }
+
+    int get_ow_start(int ki, int pad_l) {
+        return nstl::max(0,
+                utils::div_up(pad_l - ki * (jcp.dilate_w + 1), jcp.stride_w));
+    }
+
+    int get_ow_end(int ur_w, int ki, int pad_r) {
+        return ur_w
+                - nstl::max(0,
+                        utils::div_up(
+                                pad_r - (jcp.kw - 1 - ki) * (jcp.dilate_w + 1),
+                                jcp.stride_w));
+    }
+
+    inline bool is_src_layout_nxc() {
+        return utils::one_of(jcp.src_tag, format_tag::ndhwc, format_tag::nhwc,
+                format_tag::nwc);
+    }
+    inline bool is_dst_layout_nxc() {
+        return utils::one_of(jcp.dst_tag, format_tag::ndhwc, format_tag::nhwc,
+                format_tag::nwc);
+    }
+
+    jit_uni_eltwise_injector_f32<sve_512> *eltwise_injector_;
+    void generate() override;
+};
+
+template <cpu_isa_t isa>
+struct jit_uni_dw_conv_bwd_data_kernel_f32 : public jit_generator {
+    DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_uni_dw_conv_bwd_data_kernel_f32)
+
+    jit_uni_dw_conv_bwd_data_kernel_f32(jit_conv_conf_t ajcp) : jcp(ajcp) {}
+    jit_conv_conf_t jcp;
+
+private:
+    using reg64_t = const XReg;
+
+    inline ZReg get_ker_reg(int idx) { return ZReg(idx + 0); }
+    inline ZReg get_src_reg(int idx) { return ZReg(idx + 1); }
+    inline ZReg get_acc_reg(int idx) { return ZReg(idx + 4); }
+    inline ZRegS get_ker_reg_s(int idx) { return ZRegS(idx + 0); }
+    inline ZRegS get_src_reg_s(int idx) { return ZRegS(idx + 1); }
+    inline ZRegS get_acc_reg_s(int idx) { return ZRegS(idx + 4); }
+
+    reg64_t reg_ddst = x1;
+    reg64_t aux_reg_ddst = x2;
+    reg64_t aux1_reg_ddst = x3;
+    reg64_t reg_kernel = x5;
+    reg64_t aux_reg_kernel = x6;
+    reg64_t aux1_reg_kernel = x7;
+    reg64_t reg_dsrc = x8;
+
+    reg64_t reg_ur_str_w = x9;
+    reg64_t reg_ch_blocks = x10;
+
+    reg64_t iter_kh = x11;
+    reg64_t iter_kw = x12;
+    reg64_t reg_kh = x13;
+    reg64_t reg_kw = x14;
+
+    /* Temprary regs */
+    reg64_t reg_tmp_imm = x15;
+    reg64_t reg_tmp_addr = x16;
+
+    inline void loop_body(int ur_ch_blocks);
+    inline void load_ddst(int ur_ch_blocks, int ur_str_w);
+    inline void apply_filter(int ur_ch_blocks, int ur_str_w);
+    inline void store_dsrc(int ur_ch_blocks, int ur_str_w);
+
+    void generate() override;
+};
+
+template <cpu_isa_t isa>
+struct jit_uni_dw_conv_bwd_weights_kernel_f32 : public jit_generator {
+
+    DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_uni_dw_conv_bwd_weights_kernel_f32)
+
+    jit_uni_dw_conv_bwd_weights_kernel_f32(jit_conv_conf_t ajcp) : jcp(ajcp) {}
+
+    jit_conv_conf_t jcp;
+
+private:
+    using reg64_t = const XReg;
+    int simd_w = cpu_isa_traits<isa>::vlen / sizeof(float);
+
+    inline ZReg get_bias_reg(int idx = 0) { return ZReg(idx); }
+    inline ZReg get_output_reg(int idx) { return ZReg(idx + 1); }
+    inline ZReg get_input_reg(int idx) { return ZReg(idx + 5); }
+    inline ZReg get_acc_reg(int idx) { return ZReg(idx + 2); }
+    inline ZReg get_aux_reg() { return ZReg(0); }
+    inline ZRegS get_bias_reg_s(int idx = 0) { return ZRegS(idx); }
+    inline ZRegS get_output_reg_s(int idx) { return ZRegS(idx + 1); }
+    inline ZRegS get_input_reg_s(int idx) { return ZRegS(idx + 5); }
+    inline ZRegS get_acc_reg_s(int idx) { return ZRegS(idx + 2); }
+    inline ZRegS get_aux_reg_s() { return ZRegS(0); }
+
+    reg64_t reg_tmp_input = x1;
+    reg64_t reg_tmp_output = x2;
+    reg64_t reg_tmp_filter = x3;
+    reg64_t reg_kh_offset = x5;
+
+    /* parameter passed by driver into kernel */
+    reg64_t reg_exec_flags = x14;
+
+    reg64_t reg_oh_worksize = x6;
+    reg64_t reg_oh = x5;
+
+    reg64_t reg_iter_ow_blk = x7;
+
+    reg64_t reg_kh = x8;
+    reg64_t reg_kh_count = x9;
+
+    /* Base addresses for convolution parameters. */
+    reg64_t reg_input_baddr = x10;
+    reg64_t reg_output_baddr = x11;
+    reg64_t reg_filter_baddr = x12;
+    reg64_t reg_bias_baddr = x13;
+
+    /* Temporary regs */
+    reg64_t reg_tmp_imm = x15;
+    reg64_t reg_tmp_addr = x16;
+
+    /* Micro-kernel JIT'ing, fusing 'kw' and 'ow_block' loops into unrolled FMAs
+     */
+    inline void compute_ow_step_unroll(
+            int unroll_w, int l_pad, int pad_offset, int ow_block);
+
+    /* JIT'ing the outer loops for the micro-kernel -> {kh, oh_block} */
+    inline void compute_h_step(
+            int unroll_w, int l_pad, int pad_offset, int ow_block);
+    inline void compute_h_loop(
+            int unroll_w, int l_pad, int pad_offset, int ow_block);
+
+    /* Write 'width' micro-kernel JITs; depending on the padding and convolution
+     * size, write a micro-kernel for the left ow-block, middle ow-block(s), and
+     * right ow-block.*/
+    inline void compute_ow_block_unroll();
+
+    inline void compute_zero_filter();
+    inline void load_filter();
+    inline void zero_filter();
+    inline void load_bias();
+    inline void zero_bias();
+    inline void compute_bias_step_unroll(const int unroll_w);
+    inline void compute_bias_loop(const int block_size);
+    inline void store_filter();
+    inline void store_bias();
+
+    void generate() override;
+};
+} // namespace aarch64
+} // namespace cpu
+} // namespace impl
+} // namespace dnnl
+
+#endif

miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_uni_dw_conv_kernel_utils.hpp

@@ -0,0 +1,596 @@
+/*******************************************************************************
+* Copyright 2021-2022 Intel Corporation
+* Copyright 2021-2022 FUJITSU LIMITED
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef CPU_AARCH64_JIT_UNI_DW_CONV_KERNEL_UTILS_HPP
+#define CPU_AARCH64_JIT_UNI_DW_CONV_KERNEL_UTILS_HPP
+
+#include "common/nstl.hpp"
+#include "common/type_helpers.hpp"
+#include "common/utils.hpp"
+
+#include "common/c_types_map.hpp"
+#include "common/memory_tracking.hpp"
+
+#include "cpu/aarch64/jit_generator.hpp"
+#include "cpu/aarch64/jit_primitive_conf.hpp"
+#include "cpu/aarch64/jit_uni_dw_conv_kernel_f32.hpp"
+
+#include "cpu/aarch64/injectors/jit_uni_eltwise_injector.hpp"
+
+namespace dnnl {
+namespace impl {
+namespace cpu {
+namespace aarch64 {
+
+template <cpu_isa_t isa, data_type_t kernel_dt>
+struct jit_uni_dw_conv_fwd_kernel {
+
+    jit_uni_dw_conv_fwd_kernel(jit_conv_conf_t ajcp) : ker_(nullptr) {
+        ker_ = new jit_uni_dw_conv_fwd_kernel_f32<isa>(ajcp);
+    }
+    status_t create_kernel() { return ker_->create_kernel(); }
+    ~jit_uni_dw_conv_fwd_kernel() { delete ker_; }
+
+    static bool post_ops_ok(jit_conv_conf_t &jcp, const primitive_attr_t &attr);
+
+    static status_t init_conf(jit_conv_conf_t &jcp,
+            const convolution_desc_t &cd, memory_desc_t &src_md,
+            memory_desc_t &weights_md, memory_desc_t &bias_md,
+            memory_desc_t &dst_md, const primitive_attr_t &attr);
+
+    static void init_scratchpad(memory_tracking::registrar_t &scratchpad,
+            const jit_conv_conf_t &jcp);
+
+    jit_generator *ker() const { return ker_; }
+    void operator()(const jit_conv_call_s *p) const { (*ker_)(p); }
+
+private:
+    jit_uni_dw_conv_fwd_kernel_f32<isa> *ker_;
+};
+
+template <cpu_isa_t isa, data_type_t kernel_dt>
+bool jit_uni_dw_conv_fwd_kernel<isa, kernel_dt>::post_ops_ok(
+        jit_conv_conf_t &jcp, const primitive_attr_t &attr) {
+    const auto &p = attr.post_ops_;
+
+    auto is_eltwise = [&](int idx) {
+        return p.entry_[idx].is_eltwise()
+                && eltwise_injector::is_supported(
+                        isa, p.entry_[idx].eltwise.alg);
+    };
+    auto is_sum = [&](int idx) { return p.entry_[idx].is_sum(); };
+
+    switch (p.len()) {
+        case 0: return true; // no post_ops
+        case 1: return is_eltwise(0) || is_sum(0); // sum OR eltwise
+        case 2: return is_sum(0) && is_eltwise(1); // sum -> eltwise
+        default: return false;
+    }
+
+    return false;
+}
+
+template <cpu_isa_t isa, data_type_t kernel_dt>
+status_t jit_uni_dw_conv_fwd_kernel<isa, kernel_dt>::init_conf(
+        jit_conv_conf_t &jcp, const convolution_desc_t &cd,
+        memory_desc_t &src_md, memory_desc_t &weights_md,
+        memory_desc_t &bias_md, memory_desc_t &dst_md,
+        const primitive_attr_t &attr) {
+
+    using namespace dnnl::impl::format_tag;
+    using namespace dnnl::impl::utils;
+
+    const memory_desc_wrapper src_d(&src_md);
+    const memory_desc_wrapper weights_d(&weights_md);
+    const memory_desc_wrapper dst_d(&dst_md);
+    const memory_desc_wrapper bias_d(&bias_md);
+
+    const int ndims = src_d.ndims();
+    // Currently this kernel only supports 2D convolutions.
+    if (ndims != 4) return status::unimplemented;
+
+    const auto blocked_tag = isa == sve_512 ? nChw16c : nChw8c;
+    const auto wei_tag = isa == sve_512 ? Goihw16g : Goihw8g;
+    const auto nxc_tag = nhwc;
+    jcp.with_bias = cd.bias_desc.format_kind != format_kind::undef;
+    if ((blocked_tag != nChw16c) || (wei_tag != Goihw16g))
+        return status::unimplemented;
+
+    if (src_d.format_kind() == format_kind::any) {
+        CHECK(memory_desc_init_by_tag(src_md, blocked_tag));
+        jcp.src_tag = blocked_tag;
+    } else {
+        jcp.src_tag = src_d.matches_one_of_tag(blocked_tag, nxc_tag);
+    }
+
+    if (weights_d.format_kind() == format_kind::any) {
+        CHECK(memory_desc_init_by_tag(weights_md, wei_tag));
+        jcp.wei_tag = wei_tag;
+    } else {
+        jcp.wei_tag = weights_d.matches_one_of_tag(wei_tag);
+    }
+
+    if (dst_d.format_kind() == format_kind::any) {
+        CHECK(memory_desc_init_by_tag(dst_md, blocked_tag));
+        jcp.dst_tag = blocked_tag;
+    } else {
+        jcp.dst_tag = dst_d.matches_one_of_tag(blocked_tag, nxc_tag);
+    }
+
+    if (jcp.with_bias) {
+        if (bias_d.format_kind() == format_kind::any)
+            CHECK(memory_desc_init_by_tag(bias_md, format_tag::x));
+    }
+
+    if (jcp.dst_tag != jcp.src_tag) return status::unimplemented;
+    const auto data_tag = jcp.src_tag;
+    const bool is_data_layout_nxc = data_tag == nxc_tag;
+
+    jcp.dst_dt = cd.dst_desc.data_type;
+    jcp.isa = isa;
+
+    if (!mayiuse(isa)) return status::unimplemented;
+
+    const int simd_w = isa == sve_512 ? 16 : 8;
+    if (simd_w != 16) return status::unimplemented;
+
+    jcp.prop_kind = cd.prop_kind;
+
+    const bool with_groups = weights_d.ndims() == src_d.ndims() + 1;
+    if (!with_groups) return status::unimplemented;
+
+    jcp.ngroups = weights_d.dims()[0];
+    jcp.mb = src_d.dims()[0];
+
+    jcp.oc = dst_d.dims()[1];
+    jcp.oc_without_padding = jcp.oc;
+    jcp.ic = src_d.dims()[1];
+
+    jcp.ih = src_d.dims()[2];
+    jcp.iw = src_d.dims()[3];
+    jcp.oh = dst_d.dims()[2];
+    jcp.ow = dst_d.dims()[3];
+
+    jcp.kh = weights_d.dims()[3];
+    jcp.kw = weights_d.dims()[4];
+
+    jcp.t_pad = cd.padding[0][0];
+    jcp.l_pad = cd.padding[0][1];
+    jcp.b_pad = cd.padding[1][0];
+    jcp.r_pad = cd.padding[1][1];
+
+    jcp.stride_h = cd.strides[0];
+    jcp.stride_w = cd.strides[1];
+
+    jcp.dilate_h = cd.dilates[0];
+    jcp.dilate_w = cd.dilates[1];
+
+    int ext_kw = calculate_extended_filter_size(jcp.kw, jcp.dilate_w);
+    int ext_kh = calculate_extended_filter_size(jcp.kh, jcp.dilate_h);
+    jcp.r_pad = calculate_end_padding(
+            jcp.l_pad, jcp.ow, jcp.iw, jcp.stride_w, ext_kw);
+    jcp.b_pad = calculate_end_padding(
+            jcp.t_pad, jcp.oh, jcp.ih, jcp.stride_h, ext_kh);
+    bool kernel_outside_src = false || ext_kw <= jcp.l_pad
+            || ext_kw <= jcp.r_pad || ext_kh <= jcp.t_pad
+            || ext_kh <= jcp.b_pad;
+    if (kernel_outside_src) return status::unimplemented;
+
+    jcp.typesize_out = types::data_type_size(dst_d.data_type());
+    jcp.typesize_in = types::data_type_size(src_d.data_type());
+
+    jcp.loop_order = loop_ngcw;
+
+    jcp.ur_w = isa == sve_512 ? 6 : isa == sve_256 ? 4 : 3;
+    jcp.ur_w = nstl::min(jcp.ur_w, jcp.ow);
+
+    jcp.ch_block = simd_w;
+    jcp.nb_ch = div_up(jcp.oc, jcp.ch_block);
+    jcp.nb_ch_blocking = isa == sve_512 ? 4 : isa == sve_256 ? 3 : 2;
+    if (jcp.nb_ch < jcp.nb_ch_blocking) jcp.nb_ch_blocking = jcp.nb_ch;
+
+    if (is_data_layout_nxc) {
+        jcp.loop_order = loop_nhwcg;
+        bool cache_aliasing
+                = (jcp.ngroups * jcp.iw * jcp.typesize_in) % 1024 == 0;
+        if (cache_aliasing) {
+            // currently only tuned for mobilenet-v1 shapes
+            const int limit = jcp.ow > 7 ? 7 : 4;
+            jcp.ur_w = nstl::min(jcp.ur_w, limit);
+        }
+    } else {
+        const size_t max_ch_off
+                = static_cast<size_t>(jcp.nb_ch_blocking - 1) * jcp.ch_block;
+        constexpr size_t max_ex_off = 0;
+
+        // check that input offsets fit into s32
+        const size_t max_ic_off = max_ch_off * jcp.ih * jcp.iw;
+        const size_t max_iw_idx
+                = static_cast<size_t>(jcp.ur_w - 1) * jcp.stride_w
+                + (ext_kw - 1);
+        const size_t max_iw_off = max_iw_idx * jcp.ch_block;
+        const size_t max_input_offset
+                = (max_ic_off + max_iw_off + max_ex_off) * jcp.typesize_in;
+        if (max_input_offset > INT_MAX) return status::unimplemented;
+
+        // check that output offsets fit into s32
+        const size_t max_oc_off = max_ch_off * jcp.oh * jcp.ow;
+        const size_t max_ow_off
+                = static_cast<size_t>(jcp.ur_w - 1) * jcp.ch_block;
+        const size_t max_output_offset
+                = (max_oc_off + max_ow_off + max_ex_off) * jcp.typesize_out;
+        if (max_output_offset > INT_MAX) return status::unimplemented;
+    }
+
+    jcp.ur_w_tail = jcp.ow % jcp.ur_w;
+
+    int r_pad_no_tail = nstl::max(0,
+            calculate_end_padding(jcp.l_pad, jcp.ow - jcp.ur_w_tail, jcp.iw,
+                    jcp.stride_w, ext_kw));
+    if (jcp.l_pad > jcp.ur_w || r_pad_no_tail > jcp.ur_w)
+        return status::unimplemented;
+
+    if (!post_ops_ok(jcp, attr)) return status::unimplemented;
+
+    const auto &p = attr.post_ops_;
+    jcp.with_sum = p.find(primitive_kind::sum) != -1;
+    const int eltwise_ind = p.find(primitive_kind::eltwise);
+    jcp.with_eltwise = eltwise_ind != -1;
+
+    if (jcp.with_eltwise) {
+        jcp.eltwise = p.entry_[eltwise_ind].eltwise;
+        if (jcp.eltwise.alg == alg_kind::eltwise_pow)
+            return status::unimplemented;
+        if (dst_d.data_type() == data_type::s32) return status::unimplemented;
+    }
+    bool ok_to_pad_channels = true && jcp.oc == jcp.ngroups
+            && jcp.ic == jcp.ngroups && isa == sve_512;
+    if (ok_to_pad_channels) {
+        jcp.oc = rnd_up(jcp.oc, simd_w);
+        jcp.ic = rnd_up(jcp.oc, simd_w);
+        jcp.ngroups = rnd_up(jcp.ngroups, simd_w);
+    }
+
+    bool args_ok = true && jcp.oc == jcp.ngroups && jcp.ic == jcp.ngroups
+            && jcp.ngroups % simd_w == 0 && jcp.wei_tag == wei_tag
+            && data_tag != format_tag::undef && jcp.ic <= src_d.padded_dims()[1]
+            && jcp.oc <= dst_d.padded_dims()[1]
+            && jcp.ngroups <= weights_d.padded_dims()[0];
+    if (!args_ok) return status::unimplemented;
+
+    jcp.bia_dt = jcp.with_bias ? cd.bias_desc.data_type : data_type::undef;
+
+    return status::success;
+}
+
+template <cpu_isa_t isa, data_type_t kernel_dt>
+void jit_uni_dw_conv_fwd_kernel<isa, kernel_dt>::init_scratchpad(
+        memory_tracking::registrar_t &scratchpad, const jit_conv_conf_t &jcp) {
+    using namespace dnnl::impl::memory_tracking::names;
+    if (jcp.with_bias && jcp.oc_without_padding != jcp.oc)
+        scratchpad.book<float>(key_conv_padded_bias, jcp.oc);
+}
+
+template struct jit_uni_dw_conv_fwd_kernel<sve_512, data_type::f32>;
+
+template <cpu_isa_t isa, data_type_t kernel_dt>
+struct jit_uni_dw_conv_bwd_data_kernel {
+
+    jit_uni_dw_conv_bwd_data_kernel(jit_conv_conf_t ajcp) : ker_(nullptr) {
+        ker_ = new jit_uni_dw_conv_bwd_data_kernel_f32<isa>(ajcp);
+    }
+
+    status_t create_kernel() { return ker_->create_kernel(); }
+    ~jit_uni_dw_conv_bwd_data_kernel() { delete ker_; }
+
+    static status_t init_conf(jit_conv_conf_t &jcp,
+            const convolution_desc_t &cd, const memory_desc_wrapper &diff_src_d,
+            const memory_desc_wrapper &weights_d,
+            const memory_desc_wrapper &diff_dst_d);
+
+    static void init_scratchpad(memory_tracking::registrar_t &scratchpad,
+            const jit_conv_conf_t &jcp);
+
+    void operator()(const jit_conv_call_s *p) const { (*ker_)(p); }
+
+private:
+    jit_uni_dw_conv_bwd_data_kernel_f32<isa> *ker_;
+
+    DNNL_DISALLOW_COPY_AND_ASSIGN(jit_uni_dw_conv_bwd_data_kernel);
+};
+
+template <cpu_isa_t isa, data_type_t kernel_dt>
+status_t jit_uni_dw_conv_bwd_data_kernel<isa, kernel_dt>::init_conf(
+        jit_conv_conf_t &jcp, const convolution_desc_t &cd,
+        const memory_desc_wrapper &diff_src_d,
+        const memory_desc_wrapper &weights_d,
+        const memory_desc_wrapper &diff_dst_d) {
+    using namespace dnnl::impl::format_tag;
+    using namespace dnnl::impl::utils;
+
+    jcp.dsrc_dt = cd.diff_src_desc.data_type;
+    jcp.isa = isa;
+
+    if (!mayiuse(isa)) return status::unimplemented;
+
+    const int simd_w = isa == sve_512 ? 16 : 8;
+
+    const bool with_groups = weights_d.ndims() == diff_src_d.ndims() + 1;
+    if (!with_groups) return status::unimplemented;
+
+    jcp.ngroups = weights_d.dims()[0];
+    jcp.mb = diff_src_d.dims()[0];
+
+    jcp.oc = diff_dst_d.dims()[1];
+    jcp.oc_without_padding = jcp.oc;
+    jcp.ic = diff_src_d.dims()[1];
+
+    jcp.ih = diff_src_d.dims()[2];
+    jcp.iw = diff_src_d.dims()[3];
+    jcp.oh = diff_dst_d.dims()[2];
+    jcp.ow = diff_dst_d.dims()[3];
+
+    jcp.kh = weights_d.dims()[3];
+    jcp.kw = weights_d.dims()[4];
+
+    jcp.t_pad = cd.padding[0][0];
+    jcp.l_pad = cd.padding[0][1];
+    jcp.b_pad = cd.padding[1][0];
+    jcp.r_pad = cd.padding[1][1];
+
+    jcp.stride_h = cd.strides[0];
+    jcp.stride_w = cd.strides[1];
+
+    jcp.dilate_h = cd.dilates[0];
+    jcp.dilate_w = cd.dilates[1];
+    int ext_kw = calculate_extended_filter_size(jcp.kw, jcp.dilate_w);
+    int ext_kh = calculate_extended_filter_size(jcp.kh, jcp.dilate_h);
+    jcp.r_pad = calculate_end_padding(
+            jcp.l_pad, jcp.ow, jcp.iw, jcp.stride_w, ext_kw);
+    jcp.b_pad = calculate_end_padding(
+            jcp.t_pad, jcp.oh, jcp.ih, jcp.stride_h, ext_kh);
+    bool kernel_outside_src = false || ext_kw <= jcp.l_pad
+            || ext_kw <= jcp.r_pad || ext_kh <= jcp.t_pad
+            || ext_kh <= jcp.b_pad;
+    if (kernel_outside_src) { return status::unimplemented; }
+
+    jcp.ihp = jcp.ih + jcp.t_pad + jcp.b_pad;
+    jcp.iwp = jcp.iw + jcp.l_pad + jcp.r_pad;
+
+    bool ok_to_pad_channels = true && jcp.oc == jcp.ngroups
+            && jcp.ic == jcp.ngroups && isa == sve_512;
+    if (ok_to_pad_channels) {
+        jcp.oc = rnd_up(jcp.oc, simd_w);
+        jcp.ic = rnd_up(jcp.oc, simd_w);
+        jcp.ngroups = rnd_up(jcp.ngroups, simd_w);
+    }
+
+    auto dat_tag = isa == sve_512 ? nChw16c : nChw8c;
+    auto wei_tag = isa == sve_512 ? Goihw16g : Goihw8g;
+
+    jcp.src_tag = diff_src_d.matches_one_of_tag(dat_tag);
+    jcp.wei_tag = weights_d.matches_one_of_tag(wei_tag);
+    jcp.dst_tag = diff_dst_d.matches_one_of_tag(dat_tag);
+
+    bool args_ok = true && jcp.oc == jcp.ngroups && jcp.ic == jcp.ngroups
+            && jcp.ngroups % simd_w == 0 && jcp.src_tag == dat_tag
+            && jcp.wei_tag == wei_tag && jcp.dst_tag == dat_tag
+            && jcp.dilate_h == 0 && jcp.dilate_w == 0
+            && jcp.oh == (jcp.ihp - jcp.kh) / jcp.stride_h + 1
+            && jcp.ow == (jcp.iwp - jcp.kw) / jcp.stride_w + 1
+            && jcp.ic <= diff_src_d.padded_dims()[1]
+            && jcp.oc <= diff_dst_d.padded_dims()[1]
+            && jcp.ngroups <= weights_d.padded_dims()[0];
+    if (!args_ok) return status::unimplemented;
+
+    jcp.typesize_out = types::data_type_size(diff_src_d.data_type());
+    jcp.typesize_in = types::data_type_size(diff_dst_d.data_type());
+
+    jcp.ur_w = isa == sve_512 ? 6 : isa == sve_256 ? 4 : 3;
+
+    jcp.ch_block = simd_w;
+    jcp.nb_ch = jcp.ic / jcp.ch_block;
+    jcp.nb_ch_blocking = isa == sve_512 ? 4 : isa == sve_256 ? 3 : 2;
+    if (jcp.nb_ch < jcp.nb_ch_blocking) jcp.nb_ch_blocking = jcp.nb_ch;
+
+    return status::success;
+}
+
+template <cpu_isa_t isa, data_type_t kernel_dt>
+void jit_uni_dw_conv_bwd_data_kernel<isa, kernel_dt>::init_scratchpad(
+        memory_tracking::registrar_t &scratchpad, const jit_conv_conf_t &jcp) {
+    UNUSED(scratchpad);
+    UNUSED(jcp);
+}
+
+template struct jit_uni_dw_conv_bwd_data_kernel<sve_512, data_type::f32>;
+
+template <cpu_isa_t isa, data_type_t kernel_dt>
+struct jit_uni_dw_conv_bwd_weights_kernel {
+
+    jit_uni_dw_conv_bwd_weights_kernel(jit_conv_conf_t ajcp) : ker_(nullptr) {
+        ker_ = new jit_uni_dw_conv_bwd_weights_kernel_f32<isa>(ajcp);
+    }
+
+    status_t create_kernel() { return ker_->create_kernel(); }
+    ~jit_uni_dw_conv_bwd_weights_kernel() { delete ker_; }
+
+    static status_t init_conf(jit_conv_conf_t &jcp,
+            const convolution_desc_t &cd, const memory_desc_wrapper &src_d,
+            const memory_desc_wrapper &diff_weights_d,
+            const memory_desc_wrapper &diff_dst_d, int nthreads);
+
+    static void init_scratchpad(memory_tracking::registrar_t &scratchpad,
+            const jit_conv_conf_t &jcp);
+
+    static void balance(jit_conv_conf_t &jcp, int nthreads);
+
+    void operator()(const jit_dw_conv_call_s *p) const { (*ker_)(p); }
+
+private:
+    jit_uni_dw_conv_bwd_weights_kernel_f32<isa> *ker_;
+};
+
+template <cpu_isa_t isa, data_type_t kernel_dt>
+status_t jit_uni_dw_conv_bwd_weights_kernel<isa, kernel_dt>::init_conf(
+        jit_conv_conf_t &jcp, const convolution_desc_t &cd,
+        const memory_desc_wrapper &src_d,
+        const memory_desc_wrapper &diff_weights_d,
+        const memory_desc_wrapper &diff_dst_d, int nthreads) {
+    using namespace dnnl::impl::format_tag;
+    using namespace dnnl::impl::utils;
+
+    jcp.dwei_dt = cd.diff_weights_desc.data_type;
+    jcp.isa = isa;
+
+    if (!mayiuse(isa)) return status::unimplemented;
+
+    jcp.ngroups = diff_weights_d.dims()[0];
+    jcp.oc = diff_dst_d.dims()[1] / jcp.ngroups;
+    jcp.ic = src_d.dims()[1] / jcp.ngroups;
+
+    const bool with_groups = diff_weights_d.ndims() == src_d.ndims() + 1;
+
+    jcp.is_depthwise = true && with_groups && everyone_is(1, jcp.oc, jcp.ic);
+
+    if (!jcp.is_depthwise) return status::unimplemented;
+
+    jcp.ch_block = isa == sve_512 ? 16 : 8;
+    jcp.simd_w = jcp.ch_block;
+
+    jcp.mb = src_d.dims()[0];
+
+    jcp.ih = src_d.dims()[2];
+    jcp.iw = src_d.dims()[3];
+    jcp.oh = diff_dst_d.dims()[2];
+    jcp.ow = diff_dst_d.dims()[3];
+
+    jcp.kh = diff_weights_d.dims()[3];
+    jcp.kw = diff_weights_d.dims()[4];
+
+    jcp.stride_h = cd.strides[0];
+    jcp.stride_w = cd.strides[1];
+
+    jcp.t_pad = cd.padding[0][0];
+    jcp.b_pad = cd.padding[1][0];
+
+    jcp.l_pad = cd.padding[0][1];
+    jcp.r_pad = cd.padding[1][1];
+
+    jcp.dilate_h = cd.dilates[0];
+    jcp.dilate_w = cd.dilates[1];
+
+    jcp.ihp = jcp.ih + jcp.t_pad + jcp.b_pad;
+    jcp.iwp = jcp.iw + jcp.l_pad + jcp.r_pad;
+
+    jcp.with_bias = cd.diff_bias_desc.format_kind != format_kind::undef;
+
+    auto dat_tag = isa == sve_512 ? nChw16c : nChw8c;
+    auto wei_tag = isa == sve_512 ? Goihw16g : Goihw8g;
+
+    jcp.src_tag = src_d.matches_one_of_tag(dat_tag);
+    jcp.wei_tag = diff_weights_d.matches_one_of_tag(wei_tag);
+    jcp.dst_tag = diff_dst_d.matches_one_of_tag(dat_tag);
+
+    bool args_ok = true && jcp.src_tag == dat_tag && jcp.wei_tag == wei_tag
+            && jcp.dst_tag == dat_tag && jcp.ngroups % jcp.ch_block == 0
+            && jcp.dilate_h == 0 && jcp.dilate_w == 0 && jcp.kw <= 3
+            && jcp.stride_w <= jcp.kw // no gaps in kernel
+            && jcp.oh == (jcp.ihp - jcp.kh) / jcp.stride_h + 1
+            && jcp.ow == (jcp.iwp - jcp.kw) / jcp.stride_w + 1;
+    if (!args_ok) return status::unimplemented;
+
+    jcp.nb_ch = jcp.ngroups / jcp.ch_block;
+
+    /* kernel applicability check wrt boundaries
+     * the conditions are quite general across the kernels we have,
+     * but ideally the check should belong to a specific kernel... */
+    const int max_hpad = (jcp.kh - 1 + 1) / 2;
+    const int max_wpad = (jcp.kw - 1 + 1) / 2;
+    const int min_ih = jcp.kh + nstl::modulo(-jcp.t_pad, jcp.stride_h);
+    const bool boundaries_ok = true && jcp.t_pad <= max_hpad
+            && jcp.b_pad <= max_hpad && jcp.l_pad <= max_wpad
+            && jcp.r_pad <= max_wpad
+            // input must fully accommodate the filter
+            && jcp.ih >= min_ih
+            // non-unit padding must be a multiple of the stride
+            && IMPLICATION(jcp.t_pad > 1, jcp.t_pad % jcp.stride_h == 0)
+            && IMPLICATION(jcp.b_pad > 1, jcp.b_pad % jcp.stride_h == 0);
+    if (!boundaries_ok) return status::unimplemented;
+
+    /* BF16: accumulation of output happens in f32, down-conversion to bf16
+     * happens during the reduction phase. */
+    jcp.typesize_out = sizeof(float);
+    jcp.typesize_in = types::data_type_size(src_d.data_type());
+    jcp.bia_dt = jcp.with_bias ? cd.diff_bias_desc.data_type : data_type::undef;
+
+    balance(jcp, nthreads);
+
+    return status::success;
+}
+
+template <cpu_isa_t isa, data_type_t kernel_dt>
+void jit_uni_dw_conv_bwd_weights_kernel<isa, kernel_dt>::init_scratchpad(
+        memory_tracking::registrar_t &scratchpad, const jit_conv_conf_t &jcp) {
+    using namespace dnnl::impl::memory_tracking::names;
+    /* Notes: if splitting thread work on 'mb', then a reduction has to take
+     * place. Hence, book a per-thread, local weights-buffer for the
+     * reduction */
+    if (jcp.nthr_mb > 1) {
+        const size_t mb = jcp.dwei_dt == data_type::bf16 ? jcp.nthr_mb
+                                                         : jcp.nthr_mb - 1;
+        const size_t wei_size = jcp.ngroups * jcp.kh * jcp.kw;
+        scratchpad.book<float>(key_conv_wei_reduction, wei_size * mb);
+
+        if (jcp.with_bias)
+            scratchpad.book<float>(
+                    key_conv_bia_reduction, jcp.ngroups * (jcp.nthr_mb - 1));
+    } else if (jcp.nthr_mb == 1 && jcp.dwei_dt == data_type::bf16) {
+        const size_t wei_size = jcp.ngroups * jcp.kh * jcp.kw;
+        scratchpad.book<float>(key_conv_wei_reduction, wei_size);
+    }
+    if (jcp.bia_dt == data_type::bf16)
+        scratchpad.book<float>(key_conv_bias_bf16_convert_wsp, jcp.ngroups);
+}
+
+template <cpu_isa_t isa, data_type_t kernel_dt>
+void jit_uni_dw_conv_bwd_weights_kernel<isa, kernel_dt>::balance(
+        jit_conv_conf_t &jcp, int nthreads) {
+    jcp.nthr = nthreads;
+    jcp.nthr_g = jcp.nthr_mb = 1;
+
+    /* Basic-Heuristics for parallel strategy:
+     * 1) Tries to parallel on the number of Groups (g) where tasks are
+     * independent. Otherwise,
+     * 2) Tries to split the work across g and MiniBatch (mb).
+     * Parallelizing on mb requires computing a reduction for weights.
+     *
+     * NOTE: because of 'task partitioning' scheme, there will be unbalanced
+     * per-thread load when the number of threads is high (e.g. > 16).
+     */
+    jcp.nthr_g = nstl::min(jcp.nb_ch, jcp.nthr);
+    jcp.nthr_mb = nstl::min(nstl::max(1, jcp.nthr / jcp.nthr_g), jcp.mb);
+
+    jcp.nthr = jcp.nthr_g * jcp.nthr_mb;
+}
+
+template struct jit_uni_dw_conv_bwd_weights_kernel<sve_512, data_type::f32>;
+} // namespace aarch64
+} // namespace cpu
+} // namespace impl
+} // namespace dnnl
+#endif /* CPU_X64_JIT_UNI_DW_CONV_KERNEL_UTILS_HPP */

miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_uni_dw_convolution.hpp

@@ -0,0 +1,277 @@
+/*******************************************************************************
+* Copyright 2021 Intel Corporation
+* Copyright 2021 FUJITSU LIMITED
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef CPU_AARCH64_JIT_UNI_DW_CONVOLUTION_HPP
+#define CPU_AARCH64_JIT_UNI_DW_CONVOLUTION_HPP
+
+#include "common/c_types_map.hpp"
+#include "common/memory_tracking.hpp"
+#include "common/primitive.hpp"
+
+#include "cpu/aarch64/cpu_barrier.hpp"
+#include "cpu/aarch64/cpu_reducer.hpp"
+#include "cpu/cpu_convolution_pd.hpp"
+
+#include "cpu/aarch64/jit_uni_dw_conv_kernel_utils.hpp"
+
+namespace dnnl {
+namespace impl {
+namespace cpu {
+namespace aarch64 {
+
+template <cpu_isa_t isa, data_type_t src_type, data_type_t dst_type = src_type>
+struct jit_uni_dw_convolution_fwd_t : public primitive_t {
+    struct pd_t : public cpu_convolution_fwd_pd_t {
+        pd_t(const convolution_desc_t *adesc, const primitive_attr_t *attr,
+                const typename pd_t::base_class *hint_fwd_pd)
+            : cpu_convolution_fwd_pd_t(adesc, attr, hint_fwd_pd), jcp_() {}
+
+        DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("jit_dw:", jcp_.isa, ""),
+                jit_uni_dw_convolution_fwd_t);
+
+        status_t init(engine_t *engine) {
+            bool ok = true && is_fwd()
+                    && set_default_alg_kind(alg_kind::convolution_direct)
+                    && expect_data_types(src_type, src_type, data_type::undef,
+                            dst_type, data_type::f32)
+                    && IMPLICATION(this->with_bias(),
+                            utils::one_of(this->desc()->bias_desc.data_type,
+                                    data_type::f32, data_type::bf16))
+                    && attr()->has_default_values(
+                            primitive_attr_t::skip_mask_t::post_ops, dst_type)
+                    && !has_zero_dim_memory();
+            if (!ok) return status::unimplemented;
+
+            status_t status
+                    = jit_uni_dw_conv_fwd_kernel<isa, src_type>::init_conf(jcp_,
+                            *desc(), src_md_, weights_md_, bias_md_, dst_md_,
+                            *attr());
+            if (status != status::success) return status;
+
+            auto scratchpad = scratchpad_registry().registrar();
+            jit_uni_dw_conv_fwd_kernel<isa, src_type>::init_scratchpad(
+                    scratchpad, jcp_);
+
+            return status::success;
+        }
+
+        jit_conv_conf_t jcp_;
+    };
+
+    jit_uni_dw_convolution_fwd_t(const pd_t *apd) : primitive_t(apd) {}
+
+    typedef typename prec_traits<data_type::f32>::type f32_data_t;
+    typedef typename prec_traits<data_type::bf16>::type bf16_data_t;
+    typedef typename prec_traits<src_type>::type data_t;
+    typedef typename prec_traits<dst_type>::type dst_data_t;
+
+    status_t init(engine_t *engine) override {
+        CHECK(safe_ptr_assign(kernel_,
+                new jit_uni_dw_conv_fwd_kernel<isa, src_type>(pd()->jcp_)));
+        return kernel_->create_kernel();
+    }
+
+    status_t execute(const exec_ctx_t &ctx) const override {
+        execute_forward(ctx);
+        return status::success;
+    }
+
+private:
+    void execute_forward(const exec_ctx_t &ctx) const;
+    const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); }
+
+    std::unique_ptr<jit_uni_dw_conv_fwd_kernel<isa, src_type>> kernel_;
+};
+
+using jit_sve_512_dw_convolution_fwd_t
+        = jit_uni_dw_convolution_fwd_t<sve_512, data_type::f32>;
+
+template <cpu_isa_t isa, data_type_t diff_dst_type,
+        data_type_t diff_src_type = diff_dst_type>
+struct jit_uni_dw_convolution_bwd_data_t : public primitive_t {
+    struct pd_t : public cpu_convolution_bwd_data_pd_t {
+        pd_t(const convolution_desc_t *adesc, const primitive_attr_t *attr,
+                const convolution_fwd_pd_t *hint_fwd_pd)
+            : cpu_convolution_bwd_data_pd_t(adesc, attr, hint_fwd_pd), jcp_() {}
+
+        DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("jit_dw:", jcp_.isa, ""),
+                jit_uni_dw_convolution_bwd_data_t);
+
+        status_t init(engine_t *engine) {
+            bool ok = true && desc()->prop_kind == prop_kind::backward_data
+                    && set_default_alg_kind(alg_kind::convolution_direct)
+                    && expect_data_types(diff_src_type, diff_dst_type,
+                            data_type::undef, diff_dst_type, data_type::f32)
+                    && attr()->has_default_values() && !has_zero_dim_memory()
+                    && set_default_formats();
+
+            if (!ok) return status::unimplemented;
+
+            status_t status = jit_uni_dw_conv_bwd_data_kernel<isa,
+                    diff_dst_type>::init_conf(jcp_, *desc(), *diff_src_md(),
+                    *weights_md(), *diff_dst_md());
+            if (status != status::success) return status;
+
+            auto scratchpad = scratchpad_registry().registrar();
+            jit_uni_dw_conv_bwd_data_kernel<isa,
+                    diff_dst_type>::init_scratchpad(scratchpad, jcp_);
+
+            return status::success;
+        }
+
+        jit_conv_conf_t jcp_;
+
+    protected:
+        bool set_default_formats() {
+            using namespace format_tag;
+
+            auto dat_tag = nChw16c;
+            auto wei_tag = Goihw16g;
+
+            return set_default_formats_common(dat_tag, wei_tag, dat_tag);
+        }
+    };
+
+    jit_uni_dw_convolution_bwd_data_t(const pd_t *apd) : primitive_t(apd) {}
+
+    typedef typename prec_traits<diff_src_type>::type diff_src_data_t;
+    typedef typename prec_traits<diff_dst_type>::type diff_dst_data_t;
+    typedef typename prec_traits<diff_dst_type>::type wei_data_t;
+
+    status_t init(engine_t *engine) override {
+        CHECK(safe_ptr_assign(kernel_,
+                new jit_uni_dw_conv_bwd_data_kernel<isa, diff_dst_type>(
+                        pd()->jcp_)));
+        return kernel_->create_kernel();
+    }
+
+    status_t execute(const exec_ctx_t &ctx) const override {
+        execute_backward_data(ctx);
+        return status::success;
+    }
+
+private:
+    void execute_backward_data(const exec_ctx_t &ctx) const;
+    const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); }
+
+    std::unique_ptr<jit_uni_dw_conv_bwd_data_kernel<isa, diff_dst_type>>
+            kernel_;
+};
+
+using jit_sve_512_dw_convolution_bwd_data_t
+        = jit_uni_dw_convolution_bwd_data_t<sve_512, data_type::f32>;
+
+template <cpu_isa_t isa, data_type_t src_type,
+        data_type_t diff_weights_type = src_type>
+struct jit_uni_dw_convolution_bwd_weights_t : public primitive_t {
+    struct pd_t : public cpu_convolution_bwd_weights_pd_t {
+        pd_t(const convolution_desc_t *adesc, const primitive_attr_t *attr,
+                const convolution_fwd_pd_t *hint_fwd_pd)
+            : cpu_convolution_bwd_weights_pd_t(adesc, attr, hint_fwd_pd)
+            , jcp_() {}
+        using jit_uni_dw_convolution_bwd_weights
+                = jit_uni_dw_convolution_bwd_weights_t<isa, src_type,
+                        diff_weights_type>;
+        DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("jit_dw:", jcp_.isa, ""),
+                jit_uni_dw_convolution_bwd_weights);
+
+        status_t init(engine_t *engine) {
+            bool ok = true && desc()->prop_kind == prop_kind::backward_weights
+                    && set_default_alg_kind(alg_kind::convolution_direct)
+                    && expect_data_types(src_type, diff_weights_type,
+                            data_type::undef, src_type, data_type::f32)
+                    && IMPLICATION(this->with_bias(),
+                            utils::one_of(
+                                    this->desc()->diff_bias_desc.data_type,
+                                    data_type::f32, data_type::bf16))
+                    && attr()->has_default_values() && !has_zero_dim_memory()
+                    && set_default_formats();
+            if (!ok) return status::unimplemented;
+
+            const int max_threads
+                    = dnnl_in_parallel() ? 1 : dnnl_get_max_threads();
+
+            status_t status = jit_uni_dw_conv_bwd_weights_kernel<isa,
+                    src_type>::init_conf(jcp_, *desc(), *src_md(),
+                    *diff_weights_md(), *diff_dst_md(), max_threads);
+            if (status != status::success) return status;
+
+            auto scratchpad = scratchpad_registry().registrar();
+            jit_uni_dw_conv_bwd_weights_kernel<isa, src_type>::init_scratchpad(
+                    scratchpad, jcp_);
+
+            return status::success;
+        }
+
+        jit_conv_conf_t jcp_;
+
+    protected:
+        bool set_default_formats() {
+            using namespace format_tag;
+
+            auto dat_tag = isa == sve_512 ? nChw16c : nChw8c;
+            auto wei_tag = isa == sve_512 ? Goihw16g : Goihw8g;
+
+            return set_default_formats_common(dat_tag, wei_tag, dat_tag);
+        }
+    };
+
+    jit_uni_dw_convolution_bwd_weights_t(const pd_t *apd);
+
+    typedef typename prec_traits<data_type::bf16>::type bf16_data_t;
+    typedef typename prec_traits<data_type::f32>::type f32_data_t;
+    typedef typename prec_traits<src_type>::type src_data_t;
+    typedef typename prec_traits<src_type>::type diff_dst_data_t;
+    typedef typename prec_traits<diff_weights_type>::type diff_weights_data_t;
+
+    status_t init(engine_t *engine) override {
+        CHECK(safe_ptr_assign(kernel_,
+                new jit_uni_dw_conv_bwd_weights_kernel<isa, src_type>(
+                        pd()->jcp_)));
+        CHECK(kernel_->create_kernel());
+
+        if (pd()->jcp_.nthr_mb > 1) {
+            CHECK(safe_ptr_assign(
+                    acc_ker_, new cpu_accumulator_1d_t<data_type::f32>()));
+            CHECK(acc_ker_->create_kernel());
+        }
+        return status::success;
+    }
+
+    status_t execute(const exec_ctx_t &ctx) const override {
+        execute_backward_weights(ctx);
+        execute_reduction(ctx);
+        return status::success;
+    }
+
+private:
+    void execute_backward_weights(const exec_ctx_t &ctx) const;
+    void execute_reduction(const exec_ctx_t &ctx) const;
+    const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); }
+
+    std::unique_ptr<cpu_accumulator_1d_t<data_type::f32>> acc_ker_;
+    std::unique_ptr<jit_uni_dw_conv_bwd_weights_kernel<isa, src_type>> kernel_;
+};
+
+using jit_sve_512_dw_convolution_bwd_weights_t
+        = jit_uni_dw_convolution_bwd_weights_t<sve_512, data_type::f32>;
+} // namespace aarch64
+} // namespace cpu
+} // namespace impl
+} // namespace dnnl
+
+#endif

miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_uni_eltwise.hpp

@@ -0,0 +1,94 @@
+/*******************************************************************************
+* Copyright 2017-2021 Intel Corporation
+* Copyright 2021 FUJITSU LIMITED
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef CPU_AARCH64_JIT_UNI_ELTWISE_HPP
+#define CPU_AARCH64_JIT_UNI_ELTWISE_HPP
+
+#include <assert.h>
+
+#include "common/c_types_map.hpp"
+#include "common/primitive.hpp"
+#include "common/type_helpers.hpp"
+#include "common/utils.hpp"
+
+#include "cpu/cpu_eltwise_pd.hpp"
+
+#include "cpu/aarch64/cpu_isa_traits.hpp"
+
+namespace dnnl {
+namespace impl {
+namespace cpu {
+namespace aarch64 {
+
+struct jit_uni_eltwise_kernel;
+
+template <cpu_isa_t isa, impl::data_type_t d_type>
+struct jit_uni_eltwise_fwd_t : public primitive_t {
+    struct pd_t : public cpu_eltwise_fwd_pd_t {
+        using cpu_eltwise_fwd_pd_t::cpu_eltwise_fwd_pd_t;
+
+        DECLARE_COMMON_PD_T(
+                JIT_IMPL_NAME_HELPER("jit:", isa, ""), jit_uni_eltwise_fwd_t);
+
+        status_t init(engine_t *engine);
+    };
+
+    jit_uni_eltwise_fwd_t(const pd_t *apd);
+    virtual ~jit_uni_eltwise_fwd_t();
+
+    typedef typename prec_traits<d_type>::type data_t;
+
+    status_t init(engine_t *engine) override;
+
+    status_t execute(const exec_ctx_t &ctx) const override;
+
+private:
+    const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); }
+    std::unique_ptr<jit_uni_eltwise_kernel> kernel_;
+};
+
+template <cpu_isa_t isa, impl::data_type_t d_type>
+struct jit_uni_eltwise_bwd_t : public primitive_t {
+    struct pd_t : public cpu_eltwise_bwd_pd_t {
+        using cpu_eltwise_bwd_pd_t::cpu_eltwise_bwd_pd_t;
+
+        DECLARE_COMMON_PD_T(
+                JIT_IMPL_NAME_HELPER("jit:", isa, ""), jit_uni_eltwise_bwd_t);
+
+        status_t init(engine_t *engine);
+    };
+
+    jit_uni_eltwise_bwd_t(const pd_t *apd);
+    virtual ~jit_uni_eltwise_bwd_t();
+
+    typedef typename prec_traits<d_type>::type data_t;
+
+    status_t init(engine_t *engine) override;
+
+    status_t execute(const exec_ctx_t &ctx) const override;
+
+private:
+    const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); }
+    std::unique_ptr<jit_uni_eltwise_kernel> kernel_;
+};
+
+} // namespace aarch64
+} // namespace cpu
+} // namespace impl
+} // namespace dnnl
+
+#endif

miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_uni_eltwise_int.hpp

@@ -0,0 +1,72 @@
+/*******************************************************************************
+* Copyright 2021 Intel Corporation
+* Copyright 2021 FUJITSU LIMITED
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef CPU_AARCH64_JIT_UNI_ELTWISE_INT_HPP
+#define CPU_AARCH64_JIT_UNI_ELTWISE_INT_HPP
+
+#include <assert.h>
+
+#include "common/c_types_map.hpp"
+#include "common/primitive.hpp"
+#include "common/type_helpers.hpp"
+#include "common/utils.hpp"
+
+#include "cpu/cpu_eltwise_pd.hpp"
+
+#include "cpu/aarch64/cpu_isa_traits.hpp"
+
+namespace dnnl {
+namespace impl {
+namespace cpu {
+namespace aarch64 {
+
+struct jit_uni_eltwise_int_kernel;
+
+template <cpu_isa_t isa, impl::data_type_t d_type>
+struct jit_uni_eltwise_int_fwd_t : public primitive_t {
+    struct pd_t : public cpu_eltwise_fwd_pd_t {
+        using cpu_eltwise_fwd_pd_t::cpu_eltwise_fwd_pd_t;
+
+        DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("jit_int8:", isa, ""),
+                jit_uni_eltwise_int_fwd_t);
+
+        status_t init(engine_t *engine);
+    };
+
+    jit_uni_eltwise_int_fwd_t(const pd_t *apd);
+    ~jit_uni_eltwise_int_fwd_t();
+
+    typedef typename prec_traits<d_type>::type data_t;
+
+    status_t init(engine_t *engine) override;
+
+    status_t execute(const exec_ctx_t &ctx) const override {
+        return execute_forward(ctx);
+    }
+
+private:
+    status_t execute_forward(const exec_ctx_t &ctx) const;
+    const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); }
+    jit_uni_eltwise_int_kernel *kernel_ = nullptr;
+};
+
+} // namespace aarch64
+} // namespace cpu
+} // namespace impl
+} // namespace dnnl
+
+#endif

miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_uni_i8i8_pooling.hpp

@@ -0,0 +1,99 @@
+/*******************************************************************************
+* Copyright 2020 Intel Corporation
+* Copyright 2020-2021 FUJITSU LIMITED
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef CPU_AARCH64_JIT_UNI_I8I8_POOLING_HPP
+#define CPU_AARCH64_JIT_UNI_I8I8_POOLING_HPP
+
+#include "common/c_types_map.hpp"
+#include "common/primitive.hpp"
+#include "common/type_helpers.hpp"
+
+#include "cpu/cpu_pooling_pd.hpp"
+
+#include "cpu/aarch64/cpu_isa_traits.hpp"
+#include "cpu/aarch64/jit_primitive_conf.hpp"
+
+namespace dnnl {
+namespace impl {
+namespace cpu {
+namespace aarch64 {
+
+template <cpu_isa_t isa>
+struct jit_uni_i8i8_pooling_fwd_ker_t;
+
+template <cpu_isa_t isa>
+struct jit_uni_i8i8_pooling_fwd_t : public primitive_t {
+    struct pd_t : public cpu_pooling_fwd_pd_t {
+        using cpu_pooling_fwd_pd_t::cpu_pooling_fwd_pd_t;
+
+        DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("jit_int:", isa, ""),
+                jit_uni_i8i8_pooling_fwd_t);
+
+        status_t init(engine_t *engine) {
+            bool ok = true && mayiuse(isa) && utils::one_of(ndims(), 3, 4, 5)
+                    && set_default_params() == status::success
+                    && desc()->prop_kind == prop_kind::forward_inference
+                    && utils::one_of(desc()->alg_kind, alg_kind::pooling_max,
+                            alg_kind::pooling_avg_include_padding,
+                            alg_kind::pooling_avg_exclude_padding)
+                    && utils::one_of(src_md()->data_type, data_type::s32,
+                            data_type::s8, data_type::u8)
+                    && src_md()->data_type == dst_md()->data_type
+                    && attr()->has_default_values(
+                            primitive_attr_t::skip_mask_t::post_ops)
+                    && memory_desc_matches_one_of_tag(*src_md(),
+                               format_tag::nwc, format_tag::nhwc,
+                               format_tag::ndhwc)
+                            != format_tag::undef
+                    && memory_desc_matches_one_of_tag(*dst_md(),
+                               format_tag::nwc, format_tag::nhwc,
+                               format_tag::ndhwc)
+                            != format_tag::undef
+                    && !is_dilated();
+            if (!ok) return status::unimplemented;
+
+            return jit_conf();
+        }
+
+        jit_pool_conf_t jpp_;
+
+    protected:
+        status_t jit_conf();
+    };
+
+    jit_uni_i8i8_pooling_fwd_t(const pd_t *apd);
+    ~jit_uni_i8i8_pooling_fwd_t();
+
+    status_t init(engine_t *engine) override;
+
+    status_t execute(const exec_ctx_t &ctx) const override {
+        return execute_forward(ctx);
+    }
+
+private:
+    status_t execute_forward(const exec_ctx_t &ctx) const;
+    const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); }
+
+    std::unique_ptr<jit_uni_i8i8_pooling_fwd_ker_t<isa>> ker_;
+};
+
+} // namespace aarch64
+} // namespace cpu
+} // namespace impl
+} // namespace dnnl
+
+#endif

miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_uni_pool_kernel.hpp

@@ -0,0 +1,178 @@
+/*******************************************************************************
+* Copyright 2017-2022 Intel Corporation
+* Copyright 2018 YANDEX LLC
+* Copyright 2020-2022 FUJITSU LIMITED
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef CPU_AARCH64_JIT_UNI_POOL_KERNEL_HPP
+#define CPU_AARCH64_JIT_UNI_POOL_KERNEL_HPP
+
+#include <cfloat>
+#include <functional>
+#include <memory>
+
+#include "common/memory_tracking.hpp"
+
+#include "cpu/aarch64/injectors/jit_uni_postops_injector.hpp"
+#include "cpu/aarch64/jit_generator.hpp"
+#include "cpu/aarch64/jit_primitive_conf.hpp"
+
+using namespace Xbyak_aarch64;
+
+namespace dnnl {
+namespace impl {
+namespace cpu {
+namespace aarch64 {
+
+template <cpu_isa_t isa>
+struct jit_uni_pool_kernel : public jit_generator {
+
+    jit_uni_pool_kernel(
+            const jit_pool_conf_t &ajpp, const memory_desc_t *dst_md);
+    jit_pool_conf_t jpp;
+    ~jit_uni_pool_kernel();
+
+    DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_uni_pool_kernel)
+
+    static status_t init_conf(jit_pool_conf_t &jbp,
+            memory_tracking::registrar_t &scratchpad, primitive_attr_t &attr,
+            const pooling_pd_t *ppd);
+
+private:
+    using TReg = typename cpu_isa_traits<isa>::TReg;
+    using TRegS = typename cpu_isa_traits<isa>::TRegS;
+
+    int vmm_idx_upper_bound() const noexcept { return 31; }
+
+    int reg_idx(int idx) const noexcept { return vmm_idx_upper_bound() - idx; }
+
+    VReg xreg(int idx) const noexcept { return VReg(reg_idx(idx)); }
+    ZReg yreg(int idx) const noexcept { return ZReg(reg_idx(idx)); }
+    ZReg zreg(int idx) const noexcept { return ZReg(reg_idx(idx)); }
+    TReg vreg(int idx) const noexcept { return TReg(reg_idx(idx)); }
+
+    VReg vmm_mask = VReg(0);
+    ZReg ymm_tmp_1 = ZReg(0);
+    TRegS vmm_tmp_1 = TRegS(0);
+
+    TReg vmm_c_tail_mask = TReg(2);
+
+    VReg xmm_ker_area_h = VReg(2);
+    VReg xmm_one = VReg(2);
+    VReg xmm_tmp = VReg(3);
+
+    TRegS vmm_ker_area_h = TRegS(2);
+    TRegS vmm_one = TRegS(2);
+    TReg vmm_tmp = TReg(3);
+    ZReg ymm_tmp = ZReg(3);
+
+    TRegS vmm_k_offset = TRegS(1);
+
+    inline uint32_t reg_idx() {
+        if (!jpp.is_backward) {
+            return (jpp.is_training) ? 4 : 1;
+        } else
+            return 4;
+    }
+
+    ZReg z_tmp0 = z4;
+
+    PReg k_c_tail_mask_s = p4;
+    PReg k_c_tail_mask_s_not = p2;
+    PReg k_c_tail_mask_b = p7;
+    PReg k_mask_cvt = p5;
+    PReg k_store_mask = p6;
+
+    /* Caution: Chose predicate registers not used by x64's implementation. */
+    PReg p_all_zero = p1;
+    PReg p_tmp0 = p3;
+
+    using xreg_t = const XReg;
+    xreg_t reg_param = x0;
+    xreg_t reg_input = x4;
+    xreg_t aux_reg_input = x5;
+    xreg_t reg_index = x10;
+    xreg_t reg_output = x12;
+    xreg_t reg_kd_pad_shift = x13;
+
+    xreg_t kj = x14;
+    xreg_t oi_iter = x15;
+    xreg_t reg_kh = x7;
+    const WReg reg_k_shift = w3;
+    xreg_t tmp_gpr = x6;
+    xreg_t reg_ker_area_h = x2;
+    xreg_t reg_nbc = x1;
+
+    xreg_t reg_zero_ptr = x5;
+    xreg_t reg_zero_id = x13;
+    xreg_t reg_zero_ih = x14;
+    xreg_t aux_reg_zero_ih = x15;
+    xreg_t ki = x12;
+    xreg_t aux_reg_input_d = x4;
+
+    int prev_kw;
+
+    void prepare_tail_mask();
+    void push_vmm_val(const int idx);
+    void pop_vmm_val(const int idx);
+    void load(const int idx, const xreg_t &reg_ptr, const int offset,
+            const bool is_c_tail_proccessing);
+    void store(const int idx, const xreg_t &reg_ptr, const int offset,
+            const bool is_c_tail_proccessing);
+
+    void maybe_recalculate_divisor(int jj, int ur_w, int pad_l, int pad_r,
+            bool with_c_tail_proccessing);
+    void avg_step(int ur_w, int ur_bc, int pad_l, int pad_r,
+            bool with_c_tail_proccessing);
+    void max_step_fwd(int ur_w, int ur_bc, int pad_l, int pad_r,
+            bool with_c_tail_proccessing);
+    void max_step_bwd(int ur_w, int ur_bc, int pad_l, int pad_r,
+            bool with_c_tail_proccessing);
+
+    void zero_diff_src(int ur_bc, bool with_c_tail_proccessing);
+
+    void step(int ur_w, int ur_bc, int pad_l, int pad_r,
+            bool with_c_tail_proccessing) {
+        if (jpp.alg == alg_kind::pooling_max) {
+            if (jpp.is_backward)
+                max_step_bwd(
+                        ur_w, ur_bc, pad_l, pad_r, with_c_tail_proccessing);
+            else
+                max_step_fwd(
+                        ur_w, ur_bc, pad_l, pad_r, with_c_tail_proccessing);
+        } else
+            avg_step(ur_w, ur_bc, pad_l, pad_r, with_c_tail_proccessing);
+    }
+
+    void generate() override;
+
+    void apply_postops(int ur_bc, int ur_w, int c_block,
+            const std::function<bool(int)> &is_tail_predicate);
+
+    static bool post_ops_ok(jit_pool_conf_t &jpp, const primitive_attr_t &attr,
+            const memory_desc_wrapper &dst_d);
+
+    std::unique_ptr<injector::jit_uni_postops_injector_t<isa>>
+            postops_injector_;
+};
+
+} // namespace aarch64
+} // namespace cpu
+} // namespace impl
+} // namespace dnnl
+
+#endif
+
+// vim: et ts=4 sw=4 cindent cino+=l0,\:4,N-s

miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_uni_pooling.hpp

@@ -0,0 +1,191 @@
+/*******************************************************************************
+* Copyright 2017-2022 Intel Corporation
+* Copyright 2020-2022 FUJITSU LIMITED
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef CPU_AARCH64_JIT_UNI_POOLING_HPP
+#define CPU_AARCH64_JIT_UNI_POOLING_HPP
+
+#include <assert.h>
+#include <memory>
+
+#include "common/c_types_map.hpp"
+#include "common/dnnl_thread.hpp"
+#include "common/primitive.hpp"
+#include "common/type_helpers.hpp"
+#include "common/utils.hpp"
+
+#include "cpu/cpu_pooling_pd.hpp"
+
+#include "cpu/aarch64/jit_uni_pool_kernel.hpp"
+#include "cpu/aarch64/jit_uni_reorder.hpp"
+
+namespace dnnl {
+namespace impl {
+namespace cpu {
+namespace aarch64 {
+
+namespace jit_uni_pooling_utils {
+struct trans_wrapper_t;
+struct trans_context_t;
+} // namespace jit_uni_pooling_utils
+
+template <cpu_isa_t isa, impl::data_type_t d_type>
+struct jit_uni_pooling_fwd_t : public primitive_t {
+    struct pd_t : public cpu_pooling_fwd_pd_t {
+        using cpu_pooling_fwd_pd_t::cpu_pooling_fwd_pd_t;
+
+        DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("jit:", jpp_.isa, ""),
+                jit_uni_pooling_fwd_t);
+
+        status_t init(engine_t *engine) {
+            using namespace utils;
+
+            const bool ok = is_fwd() && !has_zero_dim_memory()
+                    && everyone_is(
+                            d_type, src_md()->data_type, dst_md()->data_type)
+                    && attr()->has_default_values(
+                            primitive_attr_t::skip_mask_t::post_ops, d_type)
+                    && !is_dilated() && set_default_params() == status::success;
+            if (!ok) return status::unimplemented;
+
+            const bool is_training
+                    = desc_.prop_kind == prop_kind::forward_training;
+            if (desc()->alg_kind == alg_kind::pooling_max && is_training)
+                init_default_ws();
+
+            auto scratchpad = scratchpad_registry().registrar();
+
+            CHECK(jit_uni_pool_kernel<isa>::init_conf(
+                    jpp_, scratchpad, attr_, this));
+
+            return status::success;
+        }
+
+        jit_pool_conf_t jpp_;
+    };
+
+    explicit jit_uni_pooling_fwd_t(const pd_t *apd);
+    jit_uni_pooling_fwd_t(jit_uni_pooling_fwd_t &&) = default;
+    jit_uni_pooling_fwd_t &operator=(jit_uni_pooling_fwd_t &&) = default;
+    ~jit_uni_pooling_fwd_t();
+
+    using data_t = typename prec_traits<d_type>::type;
+
+    status_t init(engine_t *engine) override;
+
+    status_t execute(const exec_ctx_t &ctx) const override {
+        auto src = CTX_IN_MEM(const data_t *, DNNL_ARG_SRC);
+        auto dst = CTX_OUT_MEM(data_t *, DNNL_ARG_DST);
+        auto ws = CTX_OUT_MEM(char *, DNNL_ARG_WORKSPACE);
+
+        if (pd()->ndims() == 5)
+            execute_forward_3d(src, dst, ws, ctx);
+        else
+            execute_forward(src, dst, ws, ctx);
+
+        return status::success;
+    }
+
+private:
+    void execute_forward(const data_t *src, data_t *dst, char *indices,
+            const exec_ctx_t &ctx) const;
+    void execute_forward_3d(const data_t *src, data_t *dst, char *indices,
+            const exec_ctx_t &ctx) const;
+    const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); }
+    status_t init_ncsp_trans_ctx();
+
+    std::unique_ptr<jit_uni_pool_kernel<isa>> kernel_;
+    std::unique_ptr<jit_uni_pooling_utils::trans_context_t> trans_ctx_;
+    static constexpr data_type_t wsp_dt_ = data_type::f32;
+};
+
+template <cpu_isa_t isa, impl::data_type_t d_type>
+struct jit_uni_pooling_bwd_t : public primitive_t {
+    struct pd_t : public cpu_pooling_bwd_pd_t {
+        using cpu_pooling_bwd_pd_t::cpu_pooling_bwd_pd_t;
+
+        DECLARE_COMMON_PD_T(JIT_IMPL_NAME_HELPER("jit:", jpp_.isa, ""),
+                jit_uni_pooling_bwd_t);
+
+        status_t init(engine_t *engine) {
+            using namespace utils;
+
+            const bool ok = true && set_default_params() == status::success
+                    && !is_fwd() && !has_zero_dim_memory()
+                    && everyone_is(d_type, diff_src_md()->data_type,
+                            diff_dst_md()->data_type)
+                    && attr()->has_default_values() && !is_dilated();
+            if (!ok) return status::unimplemented;
+
+            if (desc()->alg_kind == alg_kind::pooling_max) {
+                init_default_ws();
+                if (!compare_ws(hint_fwd_pd_)) return status::unimplemented;
+            }
+
+            auto scratchpad = scratchpad_registry().registrar();
+
+            CHECK(jit_uni_pool_kernel<isa>::init_conf(
+                    jpp_, scratchpad, attr_, this));
+
+            return status::success;
+        }
+
+        jit_pool_conf_t jpp_;
+    };
+
+    explicit jit_uni_pooling_bwd_t(const pd_t *apd);
+    jit_uni_pooling_bwd_t(jit_uni_pooling_bwd_t &&) = default;
+    jit_uni_pooling_bwd_t &operator=(jit_uni_pooling_bwd_t &&) = default;
+    ~jit_uni_pooling_bwd_t();
+
+    using data_t = typename prec_traits<d_type>::type;
+
+    status_t init(engine_t *engine) override;
+
+    status_t execute(const exec_ctx_t &ctx) const override {
+        auto diff_dst = CTX_IN_MEM(const data_t *, DNNL_ARG_DIFF_DST);
+        auto ws = CTX_IN_MEM(const char *, DNNL_ARG_WORKSPACE);
+        auto diff_src = CTX_OUT_MEM(data_t *, DNNL_ARG_DIFF_SRC);
+
+        if (pd()->ndims() == 5)
+            execute_backward_3d(diff_dst, ws, diff_src, ctx);
+        else
+            execute_backward(diff_dst, ws, diff_src, ctx);
+
+        return status::success;
+    }
+
+private:
+    void execute_backward(const data_t *diff_dst, const char *indices,
+            data_t *diff_src, const exec_ctx_t &ctx) const;
+    void execute_backward_3d(const data_t *diff_dst, const char *indices,
+            data_t *diff_src, const exec_ctx_t &ctx) const;
+    const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); }
+    status_t init_ncsp_trans_ctx();
+
+    std::unique_ptr<jit_uni_pool_kernel<isa>> kernel_;
+    std::unique_ptr<jit_uni_pooling_utils::trans_context_t> trans_ctx_;
+    static constexpr data_type_t wsp_dt_ = data_type::f32;
+};
+
+} // namespace aarch64
+} // namespace cpu
+} // namespace impl
+} // namespace dnnl
+
+#endif
+
+// vim: et ts=4 sw=4 cindent cino+=l0,\:4,N-s

miniconda3/envs/active_proaction/lib/python3.10/site-packages/tensorflow/include/external/onednn/src/cpu/aarch64/jit_uni_reorder.hpp

@@ -0,0 +1,314 @@
+/*******************************************************************************
+* Copyright 2018-2023 Intel Corporation
+* Copyright 2020-2023 FUJITSU LIMITED
+* Copyright 2022 Arm Ltd. and affiliates
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef CPU_AARCH64_JIT_UNI_REORDER_HPP
+#define CPU_AARCH64_JIT_UNI_REORDER_HPP
+
+#include <assert.h>
+
+#include "common/c_types_map.hpp"
+#include "common/type_helpers.hpp"
+
+#include "cpu/reorder/cpu_reorder_pd.hpp"
+
+namespace dnnl {
+namespace impl {
+namespace cpu {
+namespace aarch64 {
+
+namespace tr {
+
+constexpr int max_ndims = DNNL_MAX_NDIMS;
+
+struct node_t {
+    static constexpr int64_t empty_field = -1;
+
+    size_t n = 0;
+    size_t tail_size = 0;
+    int dim_id = empty_field;
+    int parent_node_id = empty_field;
+    bool is_zero_pad_needed = false;
+    ptrdiff_t is = 0; // input stride
+    ptrdiff_t os = 0; // output stride
+    ptrdiff_t ss = 0; // scale stride
+    ptrdiff_t cs = 0; // compensation stride
+
+    bool is_dim_id_empty() const { return dim_id == empty_field; }
+    bool is_parent_empty() const { return parent_node_id == empty_field; }
+};
+
+enum class scale_type_t { NONE, COMMON, MANY };
+
+struct prb_t {
+    /* The compensation mask value indicates how big an additional buffer should be.
+     * Possible values for reorder:
+     *     1) standard compensation = 1 = 0b01
+     *     2) asymmetric compensation = 2 = 0b10
+     *     3) compensation if tensor contains group = 3 = 0b11 */
+    static constexpr int invalid_comp_mask = 0;
+    static constexpr int standard_comp_mask = 0b1;
+    static constexpr int asymmetric_comp_mask = 0b10;
+    static constexpr int comp_mask_with_groups
+            = standard_comp_mask + asymmetric_comp_mask;
+
+    bool is_tail_in_one_of_child_nodes(int parent_node_id) const {
+        for (int i = parent_node_id; i >= 0; i--) {
+            if (nodes[i].parent_node_id == parent_node_id) {
+                if (nodes[i].tail_size != 0)
+                    return true;
+                else
+                    parent_node_id = i;
+            }
+        }
+
+        return false;
+    }
+
+    int tail(int d) const {
+        assert(d < ndims);
+        return static_cast<int>(nodes[d].tail_size);
+    }
+
+    int n(int d) const {
+        assert(d < ndims);
+        return static_cast<int>(nodes[d].n);
+    }
+    int is(int d) const {
+        assert(d < ndims);
+        return static_cast<int>(nodes[d].is);
+    }
+    int os(int d) const {
+        assert(d < ndims);
+        return static_cast<int>(nodes[d].os);
+    }
+    int ss(int d) const {
+        assert(d < ndims);
+        return static_cast<int>(nodes[d].ss);
+    }
+
+    int cs(int d) const {
+        assert(d < ndims);
+        return static_cast<int>(nodes[d].cs);
+    }
+
+    data_type_t itype;
+    data_type_t otype;
+    int ndims;
+    node_t nodes[max_ndims];
+    ptrdiff_t ioff;
+    ptrdiff_t ooff;
+    scale_type_t src_scale_type;
+    scale_type_t dst_scale_type;
+    float beta;
+    int full_ndims;
+    bool is_tail_present = false;
+    float scale_adjust = 1.f;
+    int compensation_mask = invalid_comp_mask;
+    bool req_s8s8_comp = false;
+    bool req_asymmetric_comp = false;
+    bool req_src_zp = false;
+    bool req_dst_zp = false;
+};
+
+status_t prb_init(prb_t &prb, const memory_desc_t &imd,
+        const memory_desc_t &omd, const primitive_attr_t *attr);
+
+/** sorts the problem nodes so that output strides come in ascending order */
+void prb_normalize(prb_t &p);
+
+/** fill parent node info for blocked nodes */
+void prb_node_dependency(prb_t &p);
+
+/** folds nodes together if possible */
+void prb_simplify(prb_t &p);
+
+/** splits the node dim into two of sizes n1 and n / n1
+ * @warning n must be multiple of n1 */
+void prb_node_split(prb_t &p, int dim, size_t n1);
+
+/** swaps d0 and d1 nodes */
+void prb_node_swap(prb_t &p, int d0, int d1);
+
+/** moves node d0 to the d1 position.
+ * nodes (d0, d1] are shifted to the left if d0 < d1 or
+ * to the right if d0 > d1 */
+void prb_node_move(prb_t &p, int d0, int d1);
+
+/** dumps the problem to stdout */
+void prb_dump(const prb_t &p);
+
+struct call_param_t {
+    const void *in = nullptr;
+    void *out = nullptr;
+    const float *src_scales = nullptr;
+    const float *dst_scales = nullptr;
+    int32_t src_zp = 0;
+    int32_t dst_zp = 0;
+    int32_t *compensation_scratch = nullptr;
+};
+
+// The additional structure is needed because
+// using a data structure with tail processing
+// data for non-tail cases reduces kernel
+// performance. This is because there is too
+// much data that has to be transferred to the kernel.
+struct tail_call_param_t {
+    call_param_t base_params;
+    int64_t curr_data_chunks[DNNL_MAX_NDIMS] = {-1};
+    int64_t zeroing_data = static_cast<int64_t>(false);
+    int64_t skip_kernel_execution = static_cast<int64_t>(false);
+};
+
+struct kernel_t {
+    struct desc_t {
+        int id;
+        prb_t prb;
+    };
+
+    kernel_t(const desc_t &desc)
+        : desc_(desc)
+        , compensation_needed_(
+                  desc.prb.req_s8s8_comp || desc.prb.req_asymmetric_comp) {}
+    virtual void operator()(const call_param_t *c) const = 0;
+    virtual void operator()(const tail_call_param_t *c) const = 0;
+    virtual status_t create_kernel() = 0;
+    virtual ~kernel_t() {}
+
+    /** inits kernel descriptor:
+     *      desc            -- kernel descriptor (output)
+     *      prb             -- transposition problem (input)
+     *      ndims_ker_max   -- limit the maximum number of dimensions kernel
+     *                         will process (optional, 0 -- no limitation) */
+    static status_t desc_init(
+            desc_t &desc, const prb_t &prb, int ndims_ker_max = 0);
+
+    /** creates kernel for the problem described in desc */
+    static kernel_t *create(const desc_t &desc);
+
+protected:
+    const desc_t desc_;
+    const prb_t &prb_ = desc_.prb;
+    bool compensation_needed_ = false;
+};
+
+/* TODO: add trans_t class */
+
+struct jit_single_blk_kernel_t;
+
+} // namespace tr
+
+struct jit_uni_reorder_t : public primitive_t {
+    using primitive_t::primitive_t;
+    struct pd_t : public cpu_reorder_pd_t {
+        using cpu_reorder_pd_t::cpu_reorder_pd_t;
+
+        DECLARE_COMMON_PD_T("jit:uni", jit_uni_reorder_t);
+
+        tr::prb_t prb_;
+        tr::kernel_t::desc_t ker_desc_;
+        int nthr_;
+        bool with_groups_ = false;
+        dim_t D_mask_ = 0;
+
+        status_t init(
+                engine_t *engine, engine_t *src_engine, engine_t *dst_engine);
+
+    private:
+        status_t init_scratchpad();
+        static status_t create(reorder_pd_t **reorder_pd, engine_t *engine,
+                const primitive_attr_t *attr, engine_t *src_engine,
+                const memory_desc_t *src_md, engine_t *dst_engine,
+                const memory_desc_t *dst_md);
+
+        friend dnnl::impl::impl_list_item_t;
+    };
+
+    status_t init(engine_t *engine) override;
+    status_t execute(const exec_ctx_t &ctx) const override;
+
+    enum { ndims_driver_max = 4 };
+
+private:
+    void omp_driver_0d(int off, const char *in, char *out,
+            const float *src_scales, const float *dst_scales, int src_zp,
+            int dst_zp, int32_t *compensation_scratch) const;
+    void omp_driver_1d(int ithr, int nthr, int off, const char *in, char *out,
+            const float *src_scales, const float *dst_scales, int src_zp,
+            int dst_zp, int32_t *compensation_scratch) const;
+    void omp_driver_2d(int ithr, int nthr, int off, const char *in, char *out,
+            const float *src_scales, const float *dst_scales, int src_zp,
+            int dst_zp, int32_t *compensation_scratch) const;
+    void omp_driver_3d(int ithr, int nthr, int off, const char *in, char *out,
+            const float *src_scales, const float *dst_scales, int src_zp,
+            int dst_zp, int32_t *compensation_scratch) const;
+    void omp_driver_4d(int ithr, int nthr, int off, const char *in, char *out,
+            const float *src_scales, const float *dst_scales, int src_zp,
+            int dst_zp, int32_t *compensation_scratch) const;
+
+    void omp_driver(const char *in, char *out, const float *src_scales,
+            const float *dst_scales, int src_zp, int dst_zp,
+            const memory_tracking::grantor_t &scratchpad) const;
+
+    void fill_curr_data_chunks(const tr::prb_t &prb, const int off,
+            const ptrdiff_t *omp_data_chunks, const int omp_ndims,
+            tr::tail_call_param_t &c) const;
+
+    void reduce_compensation(char *out,
+            const int32_t *compensation_reduce_scratch, const int nthr,
+            const dim_t wspace_per_thr_size) const;
+
+    const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); }
+    std::unique_ptr<tr::kernel_t> kernel_;
+};
+
+struct jit_blk_reorder_t : public primitive_t {
+    using primitive_t::primitive_t;
+    struct pd_t : public cpu_reorder_pd_t {
+        using cpu_reorder_pd_t::cpu_reorder_pd_t;
+        DECLARE_COMMON_PD_T("jit:blk", jit_blk_reorder_t);
+
+        tr::prb_t prb_;
+
+    private:
+        static status_t create(reorder_pd_t **reorder_pd, engine_t *engine,
+                const primitive_attr_t *attr, engine_t *src_engine,
+                const memory_desc_t *src_md, engine_t *dst_engine,
+                const memory_desc_t *dst_md);
+
+        // Swap last two nodes, put block 4, 8, 16 nodes to first
+        static void prb_tile_normalize(tr::prb_t &p);
+        friend dnnl::impl::impl_list_item_t;
+    };
+
+    status_t init(engine_t *engine) override;
+    status_t execute(const exec_ctx_t &ctx) const override;
+
+    jit_blk_reorder_t(const pd_t *apd);
+    ~jit_blk_reorder_t();
+
+private:
+    const pd_t *pd() const { return (const pd_t *)primitive_t::pd().get(); }
+    std::unique_ptr<tr::jit_single_blk_kernel_t> kernel_;
+};
+
+} // namespace aarch64
+} // namespace cpu
+} // namespace impl
+} // namespace dnnl
+
+#endif