Datasets:

sangramrout
/

Chip_Design

pretty_name: AURA-1 Edge-AI Headphone Chip Design
license: other
license_name: mixed-see-readme
license_link: https://huggingface.co/datasets/sangramrout/Chip_Design/blob/main/README.md
language:
  - en
tags:
  - chip-design
  - asic
  - npu
  - edge-ai
  - tinyml
  - hearables
  - requirements-engineering
  - sky130
  - openlane
  - yosys
  - gdsii
  - fpga
  - riscv
  - tiny-gpu
  - hardware
size_categories:
  - n<1K

AURA-1: designing an edge-AI chip for a neckband headphone

Working files from a solo, from-scratch attempt to specify and prototype an edge-AI inference SoC for wireless neckband headphones: a resident, speech-native conversational model on the device, the cloud called as a tool for facts. The novel block is the NPU; Wi-Fi, Bluetooth, codec, ANC and PMU are sourced, not designed.

The author is a process engineer learning chip design. The archive is deliberately complete: the requirements spec and its revision history, the feasibility and power derivations, a survey of ~100 edge-AI silicon vendors with the patents and datasheets they cite, and the hands-on work of pushing an open teaching GPU through synthesis, FPGA sizing and OpenLane place-and-route on SKY130. Read the blog post first:

blog/aura1-chip-design-journey.md

Snapshot: 2026-09-09 · 1302 files · 823.0 MB

The design in one line

The device holds the conversation; the web supplies the facts.

Time to first audio ≤ 300 ms with Wi-Fi off, Wi-Fi idle-connected ≤ 4 mW, a ~160 M-parameter INT4 model ceiling set by PSRAM bandwidth (400 MB/s ÷ 5 tok/s), a 512–1024-MAC array sized by ASR rather than by the language model, and a 308 mAh cell chosen because 1.4 × 0.9 × 0.8 ≈ 1.0.

Start here

Path	What it is
`docs/requirements-v0.3.md`	Current requirements specification, rev 0.3 (rev 0.2 kept for history)
`docs/feasibility-solo-build.md`	L0–L4 development ladder; what one person can and cannot build
`docs/architecture-v0.1.md`	NPU architecture, first cut: arithmetic intensity, compute-bound vs bandwidth-bound
`docs/power-budget-optimal.md`	Energy waterfall, 8 h allocation, local-chip vs thin-client test, reproducible Python
`docs/SKR.md`	Power-class ladder, node choice (sky130 vs 22FDX), condensed design basis, build order
`docs/edge-ai-accelerator-taxonomy.md`	Edge-AI accelerators organised by how they move data; what AURA-1 borrows from each
`edge_chip_companies.md`	~100-company survey of edge-inference silicon
`docs/tools.md`	Bottom-up toolchain, open vs commercial, per stage
`docs/competitors.md`, `docs/comparables-battery-runtime.md`	Direct comparables and market references
`tiny-gpu/`	Synthesis findings, FPGA sizing across five families, netlistsvg schematics, the OpenLane-built GDS
`gds-viewer-vscode/`	VS Code extension that renders `.gds` files in 3D (source + `.vsix`)
`asic-puzzle-2026/SKR_solution/`	GDS → Verilog netlist extractor (KLayout LayoutToNetlist) for the Jane Street puzzle
`MANIFEST.md`	Every file in this dataset, grouped by folder, with provenance
`THIRD_PARTY.md` + `recreate_third_party.sh`	The 60 external repositories used, pinned to exact commits, not mirrored here

Layout

docs/                 the design documents (original work)
blog/                 the write-up
tiny-gpu/             my additions to adam-maj/tiny-gpu: findings, FPGA.md, schematics, built GDS
gds-viewer-vscode/    my VS Code GDS viewer extension
asic-puzzle-2026/     my netlist extractor for the Jane Street ASIC puzzle
<vendor folders>/     research on one company or architecture each:
                      AXELERA, CoralNPU, DMatrix, E_GPU, EdgeCortix, Ergo, Fortell,
                      Fury_GPU, Olix, Taalas, TensTorrent, etched_patents, greenwaves,
                      humoa_ai, imagination, lamb_labs, memryX, mW_class, wafer_AI, ...
                      Each has my notes (*.md) plus the public PDFs they cite.

Provenance and licensing

This is a private reference archive. Licenses are mixed, hence license: other.
Original work (all *.md notes and docs, scripts, the extension, the built GDS, schematics, images I made): CC BY 4.0. Code files: MIT.
Collected reference material (patents, arXiv papers, vendor datasheets, product briefs, brochures, a PhD thesis) is redistributed as downloaded from public sources and remains under its original terms. Patents are public record. If you hold rights to a document here and want it removed, open a discussion on this repo. Documents whose owners mark them as NDA-restricted are deliberately excluded (see MANIFEST.md).
Third-party source repositories are not mirrored. THIRD_PARTY.md lists every clone with its origin URL and the exact commit used; recreate_third_party.sh restores them. Local edits to those clones are described in THIRD_PARTY.md.
Files derived from adam-maj/tiny-gpu (schematics, netlist stats, the GDS) are derivatives of that MIT-licensed project.

Status

Draft, pre-silicon requirements capture. Open before spec freeze: the A-4a gate (can a ≤ 160 M speech-native model carry conversational form?), battery 220 vs 308 mAh, mute switch type, single die vs 2-die SiP, audio tokens vs text on the wire. The build order is: close A-4a, profile the workloads, microarchitecture, then RTL. No RTL for the AURA-1 NPU exists yet.

Citation

@misc{rout2026aura1,
  author = {Sangram Rout},
  title  = {AURA-1: designing an edge-AI chip for a neckband headphone},
  year   = {2026},
  url    = {https://huggingface.co/datasets/sangramrout/Chip_Design}
}