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Chip_Design

Chips in (or near) the same class as AURA-1: milliwatt power budget, tiny BGA package, neural inference for audio/vision at the extreme edge. Last updated: 2026-08-11.

Perceive Ergo / Ergo 2 (acquired by Amazon, Oct 2024)

The closest historical comparable to an in-ear AI chip: NPU + SRAM-resident weights + sensor I/O, no external DRAM, ~7×7 mm BGA package.

What it is: Dedicated NN inference accelerator (NPU), not a CPU or GPU. Spun out of Xperi in 2018; sold to Amazon for $80M (closed Oct 2, 2024), team folded into Amazon Devices & Services (Echo/Ring). SDK was proprietary/NDA; nothing open source.
Ergo 1 (2020): 4 TOPS sustained, ~20 mW typical, claimed 55 TOPS/W. GlobalFoundries 22FDX. Targets: CNNs, RNNs, LSTMs (vision + audio). No external RAM.
Ergo 2 (2023): Same 7×7 mm package, ~4× performance. Added hardware for transformers — demoed RoBERTa (110M params) on-chip at CES 2023. General fabric with transformer support retrofitted, not a transformer-only ASIC.
Architecture (from patents — no papers published):
- Hardware: distributed fabric of small dot-product cores (input + weight buffers, partial dot products aggregated over a dot-product bus), time-multiplexed; no monolithic MAC/systolic array. Aggressive clock/power gating exploiting the branch-free, compile-time-deterministic nature of NN workloads.
- Software: quantization-aware training to binary/ternary weights {−1, 0, +1} with per-layer scale factors → 50–100× model compression → entire model fits in on-die SRAM. Ternary weights need no multiplier (add/subtract/skip), which is why the hardware gets away without conventional MACs.
- Plus: microcontroller-class control CPU, MIPI camera lanes, I2S/PDM audio, SPI/I2C, security/crypto block for encrypted models.
Key patents (assignee "Perceive Corporation", 100+ US patents; transferred to Amazon):
- Inference circuit family: US 11,205,115; US 11,295,200 (time-multiplexed dot products); US 11,170,289; US 11,222,257 (non-dot-product ops: pooling/activation).
- Quantized training family: US 11,995,555; US 12,093,816; US 12,288,163; US 12,536,413 (probabilistic projection of network parameters).
- Browse: https://patents.justia.com/assignee/perceive-corporation

Current competitors (same form factor / power class)

GreenWaves GAP9

Most direct Ergo analog for hearables. RISC-V compute cluster + NE16 NPU.
Full neural audio pipelines (ANC, neural codecs, voice) at ~50 mW.
Shipping in tier-1 TWS earbuds — dedicated NN silicon is now table stakes in consumer audio.
Handles transformer-style workloads; sweet spot is still conv/recurrent audio nets.

Syntiant NDP series (NDP120 → NDP250)

Tiny audio-first NPUs, microwatts to tens of milliwatts.
NDP250: 5× tensor throughput vs. predecessor; pitched as an "LLM companion" — always-on speech front-end (wake word, VAD, speech-to-intent, transformer speech models) that wakes a bigger processor only when needed.
Philosophically closest to Perceive: weight-quantized, memory-centric, audio-led.

Arm Ethos-U85 (licensable NPU IP) + MCUs built on it (e.g. Alif Ensemble)

First MCU-class NPU with native transformer operator support (TOSA-native).
Up to 4 TOPS at 1 GHz; 20% more efficient than Ethos-U65.
Arm demo: small language model at ~7.5–8 tokens/s; INT8 LLM blocks in <256 MB DRAM.
Relevant if AURA-1 integrates a licensed NPU block instead of a custom fabric.

Ambiq Apollo510

MCU-class SoC, same power envelope, always-on edge AI incl. speech.
Differentiator is sub-threshold/near-threshold circuit design, not a novel NN fabric.
270M devices shipped as of early 2025.

Takeaways for AURA-1

"LLM in the earbud" does not exist yet. What runs at this power class are small language models and transformer speech models (tens to a few hundred M params); conversational AI still offloads to phone/cloud.
No-external-DRAM is rare and was Ergo's defining trick. Ethos-U85-class parts assume external memory for language models; only audio-first parts (Syntiant/GreenWaves style) stay fully on-die, by capping model size.
The central sizing decision: SRAM-resident weights vs. model capacity. It sets die area, power floor, and model-size ceiling simultaneously.
Patents describe claims, not verified silicon — use them for mechanism and design space, not as a reproducible recipe.

Competitor Landscape — Tiny Edge-AI Inference Chips (AURA-1 comparables)