nntkim0612/REFINE-VerilogV2-Generator-random

REFINE-VerilogV2 Generator, retrained (random corpus)

Control model for Table IV of REFINE-VerilogV2: Enhancement in Verilog Generation with Small Language Model and EDA Debugging (RIVF 2026). Same recipe as the released Generator (LoRA r = alpha = 912, merged, bf16), trained on 230,177 rows of PyraNet rows drawn uniformly (seed 3407), same stage sizes, no synthesis or cell-count filter, without the VerilogEval problems and without the 733 PyraNet rows that match a benchmark reference. Code, index files and evaluation: https://github.com/tkim-061203/REFINE-VerilogV2