Daily Papers

Correlated electron systems are among the centerpieces of modern condensed matter sciences, where many interesting physical phenomena, such as metal-insulator transition and high-Tc superconductivity appear. Recent efforts have been focused on electrostatic doping of such materials to probe the underlying physics without introducing disorder as well as to build field-effect transistors that may complement conventional semiconductor metal-oxide-semiconductor field effect transistor (MOSFET) technology. This review focuses on metal-insulator transition mechanisms in correlated electron materials and three-terminal field effect devices utilizing such correlated oxides as the channel layer. We first describe how electron-disorder interaction, electron-phonon interaction and/or electron correlation in solids could modify the electronic properties of materials and lead to metal-insulator transitions. Then we analyze experimental efforts toward utilizing these transitions in field effect transistors and their underlying principles. It is pointed out that correlated electron systems show promise among these various materials displaying phase transitions for logic technologies. Furthermore, novel phenomena emerging from electronic correlation could enable new functionalities in field effect devices. We then briefly review unconventional electrostatic gating techniques, such as ionic liquid gating and ferroelectric gating, which enables ultra large carrier accumulation density in the correlated materials which could in turn lead to phase transitions. The review concludes with a brief discussion on the prospects and suggestions for future research directions in correlated oxide electronics for information processing.

Complementary metal-oxide semiconductor (CMOS) technology has radically reshaped the world by taking humanity to the digital age. Cramming more transistors into the same physical space has enabled an exponential increase in computational performance, a strategy that has been recently hampered by the increasing complexity and cost of miniaturization. To continue achieving significant gains in computing performance, new computing paradigms, such as quantum computing, must be developed. However, finding the optimal physical system to process quantum information, and scale it up to the large number of qubits necessary to build a general-purpose quantum computer, remains a significant challenge. Recent breakthroughs in nanodevice engineering have shown that qubits can now be manufactured in a similar fashion to silicon field-effect transistors, opening an opportunity to leverage the know-how of the CMOS industry to address the scaling challenge. In this article, we focus on the analysis of the scaling prospects of quantum computing systems based on CMOS technology.

Methylammonium lead iodide perovskite has attracted intensive interest for its diverse optoelectronic applications. However, most studies to date have been limited to bulk thin films that are difficult to implement for integrated device arrays because of their incompatibility with typical lithography processes. We report the first patterned growth of regular arrays of perovskite microplate crystals for functional electronics and optoelectronics. We show that large arrays of lead iodide microplates can be grown from an aqueous solution through a seeded growth process and can be further intercalated with methylammonium iodide to produce perovskite crystals. Structural and optical characterizations demonstrate that the resulting materials display excellent crystalline quality and optical properties. We further show that perovskite crystals can be selectively grown on prepatterned electrode arrays to create independently addressable photodetector arrays and functional field effect transistors. The ability to grow perovskite microplates and to precisely place them at specific locations offers a new material platform for the fundamental investigation of the electronic and optical properties of perovskite materials and opens a pathway for integrated electronic and optoelectronic systems.

We demonstrate an all solid state semiconductor device, based on epitaxial single crystalline metal halide perovskites, enabling reversible control of a perovskite photoluminescence with a gate voltage. Fundamentally distinct from electroluminescent diodes, such a photoluminescence field effect transistor uses the gate electric field to electrostatically modulate the interfacial density of mobile charges, thereby affecting the radiative and nonradiative recombination channels of photocarriers. Varying the gate voltage in such transistors efficiently changes the rate of nonradiative interfacial recombination and modulates the photoluminescence intensity by 65 to 98 percent (depending on temperature). At favorable gating, nearly complete elimination of non-radiative losses can be achieved. This functionality, coupled with the strong visible-range absorption and emission, possible due to the high absorption coefficient, as well as controllable thickness and macroscopically homogeneous morphology of epitaxial perovskite films, leads to high external photoluminescence quantum efficiencies realized in large-area, thin-film devices. Such high-efficiency, scalable, electrostatically tunable optoelectronic switches broaden the potential applications of metal-halide perovskites in photonics and optoelectronics.

We present a deep learning approach to extract physical parameters (e.g., mobility, Schottky contact barrier height, defect profiles) of two-dimensional (2D) transistors from electrical measurements, enabling automated parameter extraction and technology computer-aided design (TCAD) fitting. To facilitate this task, we implement a simple data augmentation and pre-training approach by training a secondary neural network to approximate a physics-based device simulator. This method enables high-quality fits after training the neural network on electrical data generated from physics-based simulations of ~500 devices, a factor >40times fewer than other recent efforts. Consequently, fitting can be achieved by training on physically rigorous TCAD models, including complex geometry, self-consistent transport, and electrostatic effects, and is not limited to computationally inexpensive compact models. We apply our approach to reverse-engineer key parameters from experimental monolayer WS_2 transistors, achieving a median coefficient of determination (R^2) = 0.99 when fitting measured electrical data. We also demonstrate that this approach generalizes and scales well by reverse-engineering electrical data on high-electron-mobility transistors while fitting 35 parameters simultaneously. To facilitate future research on deep learning approaches for inverse transistor design, we have published our code and sample data sets online.

The emergence of two-dimensional (2D) materials has attracted a great deal of attention due to their fascinating physical properties and potential applications for future nanoelectronic devices. Since the first isolation of graphene, a Dirac material, a large family of new functional 2D materials have been discovered and characterized, including insulating 2D boron nitride, semiconducting 2D transition metal dichalcogenides and black phosphorus, and superconducting 2D bismuth strontium calcium copper oxide, molybdenum disulphide and niobium selenide, etc. Here, we report the identification of ferromagnetic thin flakes of Cr2Ge2Te6 (CGT) with thickness down to a few nanometers, which provides a very important piece to the van der Waals structures consisting of various 2D materials. We further demonstrate the giant modulation of the channel resistance of 2D CGT devices via electric field effect. Our results illustrate the gate voltage tunability of 2D CGT and the potential of CGT, a ferromagnetic 2D material, as a new functional quantum material for applications in future nanoelectronics and spintronics.

This paper explores the potential of cryogenic semiconductor computing and superconductor electronics as promising alternatives to traditional semiconductor devices. As semiconductor devices face challenges such as increased leakage currents and reduced performance at higher temperatures, these novel technologies offer high performance and low power computation. Conventional semiconductor electronics operating at cryogenic temperatures (below -150{\deg}C or 123.15 K) can benefit from reduced leakage currents and improved electron mobility. On the other hand, superconductor electronics, operating below 10 K, allow electrons to flow without resistance, offering the potential for ultra-low-power, high-speed computation. This study presents a comprehensive performance modeling and analysis of these technologies and provides insights into their potential benefits and limitations. We implement models of in-order and out-of-order cores operating at high clock frequencies associated with superconductor electronics and cryogenic semiconductor computing in gem5. We evaluate the performance of these components using workloads representative of real-world applications like NPB, SPEC CPU2006, and GAPBS. Our results show the potential speedups achievable by these components and the limitations posed by cache bandwidth. This work provides valuable insights into the performance implications and design trade-offs associated with cryogenic and superconductor technologies, laying the foundation for future research in this field using gem5.

Conventional semiconductor-based integrated circuits are gradually approaching fundamental scaling limits. Many prospective solutions have recently emerged to supplement or replace both the technology on which basic devices are built and the architecture of data processing. Neuromorphic circuits are a promising approach to computing where techniques used by the brain to achieve high efficiency are exploited. Many existing neuromorphic circuits rely on unconventional and useful properties of novel technologies to better mimic the operation of the brain. One such technology is single flux quantum (SFQ) logic -- a cryogenic superconductive technology in which the data are represented by quanta of magnetic flux (fluxons) produced and processed by Josephson junctions embedded within inductive loops. The movement of a fluxon within a circuit produces a quantized voltage pulse (SFQ pulse), resembling a neuronal spiking event. These circuits routinely operate at clock frequencies of tens to hundreds of gigahertz, making SFQ a natural technology for processing high frequency pulse trains. Prior proposals for SFQ neural networks often require energy-expensive fluxon conversions, involve heterogeneous technologies, or exclusively focus on device level behavior. In this paper, a design methodology for deep single flux quantum neuromorphic networks is presented. Synaptic and neuronal circuits based on SFQ technology are presented and characterized. Based on these primitives, a deep neuromorphic XOR network is evaluated as a case study, both at the architectural and circuit levels, achieving wide classification margins. The proposed methodology does not employ unconventional superconductive devices or semiconductor transistors. The resulting networks are tunable by an external current, making this proposed system an effective approach for scalable cryogenic neuromorphic computing.

Over the past two decades, 2D materials have rapidly evolved into a diverse and expanding family of material platforms. Many members of this materials class have demonstrated their potential to deliver transformative impact on fundamental research and technological applications across different fields. In this roadmap, we provide an overview of the key aspects of 2D material research and development, spanning synthesis, properties and commercial applications. We specifically present roadmaps for high impact 2D materials, including graphene and its derivatives, transition metal dichalcogenides, MXenes as well as their heterostructures and moiré systems. The discussions are organized into thematic sections covering emerging research areas (e.g., twisted electronics, moiré nano-optoelectronics, polaritronics, quantum photonics, and neuromorphic computing), breakthrough applications in key technologies (e.g., 2D transistors, energy storage, electrocatalysis, filtration and separation, thermal management, flexible electronics, sensing, electromagnetic interference shielding, and composites) and other important topics (computational discovery of novel materials, commercialization and standardization). This roadmap focuses on the current research landscape, future challenges and scientific and technological advances required to address, with the intent to provide useful references for promoting the development of 2D materials.

This work presents a novel monolithic 3D (M3D) FPGA architecture that leverages stackable back-end-of-line (BEOL) transistors to implement configuration memory and pass gates, significantly improving area, latency, and power efficiency. By integrating n-type (W-doped In_2O_3) and p-type (SnO) amorphous oxide semiconductor (AOS) transistors in the BEOL, Si SRAM configuration bits are substituted with a less leaky equivalent that can be programmed at logic-compatible voltages. BEOL-compatible AOS transistors are currently under extensive research and development in the device community, with investment by leading foundries, from which reported data is used to develop robust physics-based models in TCAD that enable circuit design. The use of AOS pass gates reduces the overhead of reconfigurable circuits by mapping FPGA switch block (SB) and connection block (CB) matrices above configurable logic blocks (CLBs), thereby increasing the proximity of logic elements and reducing latency. By interfacing with the latest Verilog-to-Routing (VTR) suite, an AOS-based M3D FPGA design implemented in 7 nm technology is demonstrated with 3.4x lower area-time squared product (AT^2), 27% lower critical path latency, and 26% lower reconfigurable routing block power on benchmarks including hyperdimensional computing and large language models (LLMs).

The massive and large-scale design of foundational semiconductor integrated circuits (ICs) is crucial to sustaining the advancement of many emerging and future technologies, such as generative AI, 5G/6G, and quantum computing. Excitingly, recent studies have shown the great capabilities of foundational models in expediting the design of digital ICs. Yet, applying generative AI techniques to accelerate the design of analog ICs remains a significant challenge due to critical domain-specific issues, such as the lack of a comprehensive dataset and effective representation methods for analog circuits. This paper proposes, AnalogGenie, a textbf{Gen}erattextbf{i}ve textbf{e}ngine for automatic design/discovery of textbf{Analog} circuit topologies--the most challenging and creative task in the conventional manual design flow of analog ICs. AnalogGenie addresses two key gaps in the field: building a foundational comprehensive dataset of analog circuit topology and developing a scalable sequence-based graph representation universal to analog circuits. Experimental results show the remarkable generation performance of AnalogGenie in broadening the variety of analog ICs, increasing the number of devices within a single design, and discovering unseen circuit topologies far beyond any prior arts. Our work paves the way to transform the longstanding time-consuming manual design flow of analog ICs to an automatic and massive manner powered by generative AI. Our source code is available at https://github.com/xz-group/AnalogGenie.

We simulate the electronic and transport properties of metal/two-dimensional material/metal vertical heterostructures, with a focus on graphene, hexagonal boron nitride and two phases of molybdenum diselenide. Using density functional theory and non-equilibrium Green's function, we assess how stacking configurations and material thickness impact important properties, such as density of states, potential barriers and conductivity. For monolayers, strong orbital hybridization with the metallic electrodes significantly alters the electronic characteristics, with the formation of states within the gap of the semiconducting 2D materials. Trilayers reveal the critical role of interlayer coupling, where the middle layer retains its intrinsic properties, thus influencing the overall conductivity. Our findings highlight the potential for customized multilayer designs to optimize electronic device performance based on two-dimensional materials.

Superconductor electronics (SCE) is a promising complementary and beyond CMOS technology. However, despite its practical benefits, the realization of SCE logic faces a significant challenge due to the absence of dense and scalable nonvolatile memory designs. While various nonvolatile memory technologies, including Non-destructive readout, vortex transitional memory (VTM), and magnetic memory, have been explored, achieving a superconductor random-access memory (RAM) crossbar array remains challenging. This paper introduces a novel, nonvolatile, high-density, and scalable VTM cell design for SCE applications. Our proposed design addresses scaling issues while boasting zero static power consumption characteristics. Our design leverages current summation, enabling analog multiply-accumulate operations -an essential feature for many in-memory computational tasks. We demonstrate the efficacy of our approach with a 32 x 32 superconductor memory array operating at 20 GHz. This design effectively addresses scaling issues and utilizes current summation that can be used for analog multiply-accumulate operations. Additionally, we showcase the accumulation property of the memory through analog simulations conducted on an 8 x 8 superconductor crossbar array.

High magnetic field and low temperature transport is carried out in order to characterize the charge carriers of PtSe_2. In particular, the Shubnikov-de Haas oscillations arising at applied magnetic field strengths gtrsim 4.5,T are found to occur exclusively in plane and emerge at a layer thickness of approx 18,nm, increasing in amplitude and decreasing in frequency for thinner PtSe_2 flakes. Moreover, the quantum transport time, Berry phase, Dingle temperature and cyclotron mass of the charge carriers are ascertained. The emergence of weak antilocalization (WAL) lies in contrast to the presence of magnetic moments from Pt vacancies. An explanation is provided on how WAL and the Kondo effect can be observed within the same material. Detailed information about the charge carriers and transport phenomena in PtSe_2 is obtained, which is relevant for the design of prospective spintronic and orbitronic devices and for the realization of orbital Hall effect-based architectures.

Two-dimensional (2D) materials are among the most promising candidates for next-generation electronics due to their atomic thinness, allowing for flexible transparent electronics and ultimate length scaling. Thus far, atomically-thin p-n junctions, metal-semiconductor contacts, and metal-insulator barriers have been demonstrated. While 2D materials achieve the thinnest possible devices, precise nanoscale control over the lateral dimensions is also necessary. Here, we report the direct synthesis of sub-nanometer-wide 1D MoS2 channels embedded within WSe2 monolayers, using a dislocation-catalyzed approach. The 1D channels have edges free of misfit dislocations and dangling bonds, forming a coherent interface with the embedding 2D matrix. Periodic dislocation arrays produce 2D superlattices of coherent MoS2 1D channels in WSe2. Using molecular dynamics simulations, we have identified other combinations of 2D materials where 1D channels can also be formed. The electronic band structure of these 1D channels offer the promise of carrier confinement in a direct-gap material and charge separation needed to access the ultimate length scales necessary for future electronic applications.

As the conventional scaling of logic devices comes to an end, functional wafer backside and 3D transistor stacking are consensus for next-generation logic technology, offering considerable design space extension for powers, signals or even devices on the wafer backside. The Flip FET (FFET), a novel transistor architecture combining 3D transistor stacking and fully functional wafer backside, was recently proposed. With symmetric dual-sided standard cell design, the FFET can deliver around 12.5% cell area scaling and faster but more energy-efficient libraries beyond other stacked transistor technologies such as CFET. Besides, thanks to the novel cell design with dual-sided pins, the FFET supports dual-sided signal routing, delivering better routability and larger backside design space. In this work, we demonstrated a comprehensive FFET evaluation framework considering physical implementation and block-level power-performance-area (PPA) assessment for the first time, in which key functions are dual-sided routing and dual-sided RC extraction. A 32-bit RISC-V core was used for the evaluation here. Compared to the CFET with single-sided signals, the FFET with single-sided signals achieved 23.3% post-P&R core area reduction, 25.0% higher frequency and 11.9% lower power at the same utilization, and 16.0 % higher frequency at the same core area. Meanwhile, the FFET supports dual-sided signals, which can further benefit more from flexible allocation of cell input pins on both sides. By optimizing the input pin density and BEOL routing layer number on each side, 10.6% frequency gain was realized without power degradation compared to the one with single-sided signal routing. Moreover, the routability and power efficiency of FFET barely degrades even with the routing layer number reduced from 12 to 5 on each side, validating the great space for cost-friendly design enabled by FFET.

Printed Electronics (PE) feature distinct and remarkable characteristics that make them a prominent technology for achieving true ubiquitous computing. This is particularly relevant in application domains that require conformal and ultra-low cost solutions, which have experienced limited penetration of computing until now. Unlike silicon-based technologies, PE offer unparalleled features such as non-recurring engineering costs, ultra-low manufacturing cost, and on-demand fabrication of conformal, flexible, non-toxic, and stretchable hardware. However, PE face certain limitations due to their large feature sizes, that impede the realization of complex circuits, such as machine learning classifiers. In this work, we address these limitations by leveraging the principles of Approximate Computing and Bespoke (fully-customized) design. We propose an automated framework for designing ultra-low power Multilayer Perceptron (MLP) classifiers which employs, for the first time, a holistic approach to approximate all functions of the MLP's neurons: multiplication, accumulation, and activation. Through comprehensive evaluation across various MLPs of varying size, our framework demonstrates the ability to enable battery-powered operation of even the most intricate MLP architecture examined, significantly surpassing the current state of the art.

Molecular ferroelectric materials have attracted widespread attention due to their abundant chemical diversity, structural tunability, low synthesis temperature, and high flexibility. Meanwhile, the integration of molecular ferroelectric materials and Si is still challenging, while the fundamental understanding of the ferroelectric switching process is still lacking. Herein, we have successfully synthesized the imidazole perchlorate (ImClO4) single crystals and a series of high-quality highly-oriented thin films on a Si substrate. A high inverse piezoelectric coefficient (55.7 pm/V) is demonstrated for the thin films. Two types of domain bands can be observed (in the size of a few microns): type-I band tilts ~60{\deg} with respect to the horizontal axis, while the type-II band is perpendicular to the horizontal axis. Most of the domain walls (DWs) are 180{\deg} DWs for the two bands, while some 109{\deg} DWs can also be observed. Interestingly, the DWs in type-I band are curved, charged domain walls; while the 180{\deg} DWs in type-II band are straight, noncharged domain walls. After applying +20 V for 5 s through a PFM tip, the 180{\deg} DWs in type-I band shrink first, then disconnect from the band boundary, forming a needle-like domain with a size of ~100 nm. The needle-like domain will extend toward the band boundary after an inverse bias is applied (-20 V), and expand along the band boundary after touching the boundary. Whereas for the type-II domain band, the 180{\deg} DWs are more mobile than the 109{\deg} domain walls, which displaces ~500 nm after applying +20 V. While such displacement is much shorter after the application of a negative bias for the same duration, starting from the positively poled sample. We hope to spur further interest in the on-chip design of the molecular ferroelectrics based electronic devices.

CONSPECTUS: Two-dimensional (2D) compound materials are promising materials for use in electronics, optoelectronics, flexible devices, etc. because they are ultrathin and cover a wide range of properties. Among all methods to prepare 2D materials, chemical vapor deposition (CVD) is promising because it produces materials with a high quality and reasonable cost. So far, much efforts have been made to produce 2D compound materials with large domain size, controllable number of layers, fast-growth rate, and high quality features, etc. However, due to the complicated growth mechanism like sublimation and diffusion processes of multiple precursors, maintaining the controllability, repeatability, and high quality of CVD grown 2D binary and ternary materials is still a big challenge, which prevents their widespread use. Here, taking 2D transition metal dichalcogenides (TMDCs) as examples, we review current progress and highlight some promising growth strategies for the growth of 2D compound materials. The key technology issues which affect the CVD process, including non-metal precursor, metal precursor, substrate engineering, temperature, and gas flow, are discussed. Also, methods in improving the quality of CVD-grown 2D materials and current understanding on their growth mechanism are highlighted. Finally, challenges and opportunities in this field are proposed. We believe this review will guide the future design of controllable CVD systems for the growth of 2D compound materials with good controllability and high quality, laying the foundations for their potential applications.

The development of selective high precision chemical functionalization strategies for device fabrication, in conjunction with associated techniques for patterning graphene wafers with atomic accuracy would provide the necessary basis for a post-CMOS manufacturing technology. This requires a thorough understanding of the principles governing the reactivity and patterning of graphene at the sub-nanometer length scale. This article reviews our quest to delineate the principles of graphene chemistry - that is, the chemistry at the Dirac point and beyond, and the effect of covalent chemistry on the electronic structure, electrical transport and magnetic properties of this low-dimensional material in order to enable the scalable production of graphene-based devices for low- and high-end technology applications.

Advances in scaling down heterostructures and having an improved interface quality together with atomically-thin two-dimensional materials suggest a novel approach to systematically design materials. A given material can be transformed through proximity effects whereby it acquires properties of its neighbors, for example, becoming superconducting, magnetic, topologically nontrivial, or with an enhanced spin-orbit coupling. Such proximity effects not only complement the conventional methods of designing materials by doping or functionalization, but can also overcome their various limitations. In proximitized materials it is possible to realize properties that are not present in any constituent region of the considered heterostructure. While the focus is on magnetic and spin-orbit proximity effects with their applications in spintronics, the outlined principles provide also a broader framework for employing other proximity effects to tailor materials and realize novel phenomena.

In this paper, we describe a design of a mixed signal circuit for a binary neuron (a.k.a perceptron, threshold logic gate) and a methodology for automatically embedding such cells in ASICs. The binary neuron, referred to as an FTL (flash threshold logic) uses floating gate or flash transistors whose threshold voltages serve as a proxy for the weights of the neuron. Algorithms for mapping the weights to the flash transistor threshold voltages are presented. The threshold voltages are determined to maximize both the robustness of the cell and its speed. The performance, power, and area of a single FTL cell are shown to be significantly smaller (79.4%), consume less power (61.6%), and operate faster (40.3%) compared to conventional CMOS logic equivalents. Also included are the architecture and the algorithms to program the flash devices of an FTL. The FTL cells are implemented as standard cells, and are designed to allow commercial synthesis and P&R tools to automatically use them in synthesis of ASICs. Substantial reductions in area and power without sacrificing performance are demonstrated on several ASIC benchmarks by the automatic embedding of FTL cells. The paper also demonstrates how FTL cells can be used for fixing timing errors after fabrication.

Significant progress on parameter-free calculations of carrier mobilities in real materials has been made during the past decade; however, the role of various approximations remains unclear and a unified methodology is lacking. Here, we present and analyse a comprehensive and efficient approach to compute the intrinsic, phonon-limited drift and Hall carrier mobilities of semiconductors, within the framework of the first-principles Boltzmann transport equation. The methodology exploits a novel approach for estimating quadrupole tensors and including them in the electron-phonon interactions, and capitalises on a rigorous and efficient procedure for numerical convergence. The accuracy reached in this work allows to assess common approximations, including the role of exchange and correlation functionals, spin-orbit coupling, pseudopotentials, Wannier interpolation, Brillouin-zone sampling, dipole and quadrupole corrections, and the relaxation-time approximation. A detailed analysis is showcased on ten prototypical semiconductors, namely diamond, silicon, GaAs, 3C-SiC, AlP, GaP, c-BN, AlAs, AlSb, and SrO. By comparing this extensive dataset with available experimental data, we explore the intrinsic nature of phonon-limited carrier transport and magnetotransport phenomena in these compounds. We find that the most accurate calculations predict Hall mobilities up to a factor of two larger than experimental data; this could point to promising experimental improvements in the samples quality, or to the limitations of density-function theory in predicting the carrier effective masses and overscreening the electron-phonon matrix elements. By setting tight standards for reliability and reproducibility, the present work aims to facilitate validation and verification of data and software towards predictive calculations of transport phenomena in semiconductors.

Artificial Neural Networks are computational network models inspired by signal processing in the brain. These models have dramatically improved the performance of many learning tasks, including speech and object recognition. However, today's computing hardware is inefficient at implementing neural networks, in large part because much of it was designed for von Neumann computing schemes. Significant effort has been made to develop electronic architectures tuned to implement artificial neural networks that improve upon both computational speed and energy efficiency. Here, we propose a new architecture for a fully-optical neural network that, using unique advantages of optics, promises a computational speed enhancement of at least two orders of magnitude over the state-of-the-art and three orders of magnitude in power efficiency for conventional learning tasks. We experimentally demonstrate essential parts of our architecture using a programmable nanophotonic processor.

The proliferation of probabilistic AI has promoted proposals for specialized stochastic computers. Despite promising efficiency gains, these proposals have failed to gain traction because they rely on fundamentally limited modeling techniques and exotic, unscalable hardware. In this work, we address these shortcomings by proposing an all-transistor probabilistic computer that implements powerful denoising models at the hardware level. A system-level analysis indicates that devices based on our architecture could achieve performance parity with GPUs on a simple image benchmark using approximately 10,000 times less energy.

Neuromorphic spintronics combines two advanced fields in technology, neuromorphic computing and spintronics, to create brain-inspired, efficient computing systems that leverage the unique properties of the electron's spin. In this book chapter, we first introduce both fields - neuromorphic computing and spintronics and then make a case for neuromorphic spintronics. We discuss concrete examples of neuromorphic spintronics, including computing based on fluctuations, artificial neural networks, and reservoir computing, highlighting their potential to revolutionize computational efficiency and functionality.

Machine learning, particularly in the form of deep learning, has driven most of the recent fundamental developments in artificial intelligence. Deep learning is based on computational models that are, to a certain extent, bio-inspired, as they rely on networks of connected simple computing units operating in parallel. Deep learning has been successfully applied in areas such as object/pattern recognition, speech and natural language processing, self-driving vehicles, intelligent self-diagnostics tools, autonomous robots, knowledgeable personal assistants, and monitoring. These successes have been mostly supported by three factors: availability of vast amounts of data, continuous growth in computing power, and algorithmic innovations. The approaching demise of Moore's law, and the consequent expected modest improvements in computing power that can be achieved by scaling, raise the question of whether the described progress will be slowed or halted due to hardware limitations. This paper reviews the case for a novel beyond CMOS hardware technology, memristors, as a potential solution for the implementation of power-efficient in-memory computing, deep learning accelerators, and spiking neural networks. Central themes are the reliance on non-von-Neumann computing architectures and the need for developing tailored learning and inference algorithms. To argue that lessons from biology can be useful in providing directions for further progress in artificial intelligence, we briefly discuss an example based reservoir computing. We conclude the review by speculating on the big picture view of future neuromorphic and brain-inspired computing systems.

Historically, VLSI designers have focused on increasing the speed and reducing the area of digital systems. However, the evolution of portable systems and advanced Deep Sub-Micron fabrication technologies have brought power dissipation as another critical design factor. Low power design reduces cooling cost and increases reliability especially for high density systems. Moreover, it reduces the weight and size of portable devices. The power dissipation in CMOS circuits consists of static and dynamic components. Since dynamic power is proportional to V2 dd and static power is proportional to Vdd, lowering the supply voltage and device dimensions, the transistor threshold voltage also has to be scaled down to achieve the required performance. In case of static power, the power is consumed during the steady state condition i.e when there are no input/output transitions. Static power has two sources: DC power and Leakage power. Consecutively to facilitate voltage scaling without disturbing the performance, threshold voltage has to be minimized. Furthermore it leads to better noise margins and helps to avoid the hot carrier effects in short channel devices. In this paper we have been proposed the new CMOS library for the complex digital design using scaling the supply voltage and device dimensions and also suggest the methods to control the leakage current to obtain the minimum power dissipation at optimum value of supply voltage and transistor threshold. In this paper CMOS Cell library has been implemented using TSMC (0.18um) and TSMC (90nm) technology using HEP2 tool of IC designing from Mentor Graphics for various analysis and simulations.

The electronic design automation of analog circuits has been a longstanding challenge in the integrated circuit field due to the huge design space and complex design trade-offs among circuit specifications. In the past decades, intensive research efforts have mostly been paid to automate the transistor sizing with a given circuit topology. By recognizing the graph nature of circuits, this paper presents a Circuit Graph Neural Network (CktGNN) that simultaneously automates the circuit topology generation and device sizing based on the encoder-dependent optimization subroutines. Particularly, CktGNN encodes circuit graphs using a two-level GNN framework (of nested GNN) where circuits are represented as combinations of subgraphs in a known subgraph basis. In this way, it significantly improves design efficiency by reducing the number of subgraphs to perform message passing. Nonetheless, another critical roadblock to advancing learning-assisted circuit design automation is a lack of public benchmarks to perform canonical assessment and reproducible research. To tackle the challenge, we introduce Open Circuit Benchmark (OCB), an open-sourced dataset that contains 10K distinct operational amplifiers with carefully-extracted circuit specifications. OCB is also equipped with communicative circuit generation and evaluation capabilities such that it can help to generalize CktGNN to design various analog circuits by producing corresponding datasets. Experiments on OCB show the extraordinary advantages of CktGNN through representation-based optimization frameworks over other recent powerful GNN baselines and human experts' manual designs. Our work paves the way toward a learning-based open-sourced design automation for analog circuits. Our source code is available at https://github.com/zehao-dong/CktGNN.

The rising demand for energy-efficient edge AI systems (e.g., mobile agents/robots) has increased the interest in neuromorphic computing, since it offers ultra-low power/energy AI computation through spiking neural network (SNN) algorithms on neuromorphic processors. However, their efficient implementation strategy has not been comprehensively studied, hence limiting SNN deployments for edge AI systems. Toward this, we propose a design methodology to enable efficient SNN processing on commodity neuromorphic processors. To do this, we first study the key characteristics of targeted neuromorphic hardware (e.g., memory and compute budgets), and leverage this information to perform compatibility analysis for network selection. Afterward, we employ a mapping strategy for efficient SNN implementation on the targeted processor. Furthermore, we incorporate an efficient on-chip learning mechanism to update the systems' knowledge for adapting to new input classes and dynamic environments. The experimental results show that the proposed methodology leads the system to achieve low latency of inference (i.e., less than 50ms for image classification, less than 200ms for real-time object detection in video streaming, and less than 1ms in keyword recognition) and low latency of on-chip learning (i.e., less than 2ms for keyword recognition), while incurring less than 250mW of processing power and less than 15mJ of energy consumption across the respective different applications and scenarios. These results show the potential of the proposed methodology in enabling efficient edge AI systems for diverse application use-cases.

Analog IC design relies on human experts to search for parameters that satisfy circuit specifications with their experience and intuitions, which is highly labor intensive, time consuming and suboptimal. Machine learning is a promising tool to automate this process. However, supervised learning is difficult for this task due to the low availability of training data: 1) Circuit simulation is slow, thus generating large-scale dataset is time-consuming; 2) Most circuit designs are propitiatory IPs within individual IC companies, making it expensive to collect large-scale datasets. We propose Learning to Design Circuits (L2DC) to leverage reinforcement learning that learns to efficiently generate new circuits data and to optimize circuits. We fix the schematic, and optimize the parameters of the transistors automatically by training an RL agent with no prior knowledge about optimizing circuits. After iteratively getting observations, generating a new set of transistor parameters, getting a reward, and adjusting the model, L2DC is able to optimize circuits. We evaluate L2DC on two transimpedance amplifiers. Trained for a day, our RL agent can achieve comparable or better performance than human experts trained for a quarter. It first learns to meet hard-constraints (eg. gain, bandwidth), and then learns to optimize good-to-have targets (eg. area, power). Compared with grid search-aided human design, L2DC can achieve 250times higher sample efficiency with comparable performance. Under the same runtime constraint, the performance of L2DC is also better than Bayesian Optimization.

Hybrid superconductor-semiconductor systems have received a great deal of attention in the last few years because of their potential for quantum engineering, including novel qubits and topological devices. The proximity effect, the process by which the semiconductor inherits superconducting correlations, is an essential physical mechanism of such hybrids. Recent experiments have demonstrated the proximity effect in hole-based semiconductors, but, in contrast to electrons, the precise mechanism by which the hole bands acquire superconducting correlations remains an open question. In addition, hole spins exhibit a complex strong spin-orbit interaction, with largely anisotropic responses to electric and magnetic fields, further motivating the importance of understanding the interplay between such effects and the proximity effect. In this work, we analyze this physics with focus on germanium-based two-dimensional gases. Specifically, we develop an effective theory supported by full numerics, allowing us to extract various analytical expressions and predict different types of superconducting correlations including non-standard forms of singlet and triplet pairing mechanisms with non-trivial momentum dependence; as well as different Zeeman and Rashba spin-orbit contributions. This, together with their precise dependence on electric and magnetic fields, allows us to make specific experimental predictions, including the emergence of f-type superconductivity, Bogoliubov Fermi surfaces, and gapless regimes caused by large in-plane magnetic fields.

Printed Electronics (PE) stands out as a promisingtechnology for widespread computing due to its distinct attributes, such as low costs and flexible manufacturing. Unlike traditional silicon-based technologies, PE enables stretchable, conformal,and non-toxic hardware. However, PE are constrained by larger feature sizes, making it challenging to implement complex circuits such as machine learning (ML) classifiers. Approximate computing has been proven to reduce the hardware cost of ML circuits such as Multilayer Perceptrons (MLPs). In this paper, we maximize the benefits of approximate computing by integrating hardware approximation into the MLP training process. Due to the discrete nature of hardware approximation, we propose and implement a genetic-based, approximate, hardware-aware training approach specifically designed for printed MLPs. For a 5% accuracy loss, our MLPs achieve over 5x area and power reduction compared to the baseline while outperforming state of-the-art approximate and stochastic printed MLPs.

The emergence of new nanoscale technologies has imposed significant challenges to designing reliable electronic systems in radiation environments. A few types of radiation like Total Ionizing Dose (TID) effects often cause permanent damages on such nanoscale electronic devices, and current state-of-the-art technologies to tackle TID make use of expensive radiation-hardened devices. This paper focuses on a novel and different approach: using machine learning algorithms on consumer electronic level Field Programmable Gate Arrays (FPGAs) to tackle TID effects and monitor them to replace before they stop working. This condition has a research challenge to anticipate when the board results in a total failure due to TID effects. We observed internal measurements of the FPGA boards under gamma radiation and used three different anomaly detection machine learning (ML) algorithms to detect anomalies in the sensor measurements in a gamma-radiated environment. The statistical results show a highly significant relationship between the gamma radiation exposure levels and the board measurements. Moreover, our anomaly detection results have shown that a One-Class Support Vector Machine with Radial Basis Function Kernel has an average Recall score of 0.95. Also, all anomalies can be detected before the boards stop working.

Neuromorphic computing, which exploits Spiking Neural Networks (SNNs) on neuromorphic chips, is a promising energy-efficient alternative to traditional AI. CNN-based SNNs are the current mainstream of neuromorphic computing. By contrast, no neuromorphic chips are designed especially for Transformer-based SNNs, which have just emerged, and their performance is only on par with CNN-based SNNs, offering no distinct advantage. In this work, we propose a general Transformer-based SNN architecture, termed as ``Meta-SpikeFormer", whose goals are: 1) Lower-power, supports the spike-driven paradigm that there is only sparse addition in the network; 2) Versatility, handles various vision tasks; 3) High-performance, shows overwhelming performance advantages over CNN-based SNNs; 4) Meta-architecture, provides inspiration for future next-generation Transformer-based neuromorphic chip designs. Specifically, we extend the Spike-driven Transformer in yao2023spike into a meta architecture, and explore the impact of structure, spike-driven self-attention, and skip connection on its performance. On ImageNet-1K, Meta-SpikeFormer achieves 80.0\% top-1 accuracy (55M), surpassing the current state-of-the-art (SOTA) SNN baselines (66M) by 3.7\%. This is the first direct training SNN backbone that can simultaneously supports classification, detection, and segmentation, obtaining SOTA results in SNNs. Finally, we discuss the inspiration of the meta SNN architecture for neuromorphic chip design. Source code and models are available at https://github.com/BICLab/Spike-Driven-Transformer-V2.

The discovery of van der Waals magnets has established a new domain in the field of magnetism, opening novel pathways for the electrical control of magnetic properties. In this context, Fe3GeTe2 (FGT) emerges as an exemplary candidate owing to its intrinsic metallic properties, which facilitate the interplay of both charge and spin degrees of freedom. Here, the bidirectional voltage control of exchange bias (EB) effect in a perpendicularly magnetized all-van der Waals FGT/O-FGT/hBN heterostructure is demonstrated. The antiferromagnetic O-FGT layer is formed by naturally oxidizing the FGT surface. The observed EB magnitude reaches 1.4 kOe with a blocking temperature (150 K) reaching close to the Curie temperature of FGT. Both the exchange field and the blocking temperature values are among the highest in the context of layered materials. The EB modulation exhibits a linear dependence on the gate voltage and its polarity, observable in both positive and negative field cooling (FC) experiments. Additionally, gate voltage-controlled magnetization switching, highlighting the potential of FGT-based heterostructures is demonstrated in advanced spintronic devices. These findings display a methodology to modulate the magnetism of van der Waals magnets offering new avenues for the development of high-performance magnetic devices.

In electronic design, engineers often manually search through extensive documents to retrieve component parameters required for constructing SPICE models, a process that is both labor-intensive and time-consuming. To address this challenge, we present an automated framework called D2S-FLOW that leverages large language models (LLMs) to extract electrical parameters from datasheets and generate SPICE models with high precision and efficiency, significantly reducing the need for manual intervention. Unlike traditional RAG systems, D2S-FLOW employs a workflow to enhance precision in handling unstructured documents and inconsistent naming conventions through three innovative mechanisms: Attention-Guided Document Focusing (AGDF), Hierarchical Document-Enhanced Retrieval (HDER), and Heterogeneous Named Entity Normalization (HNEN). AGDF narrows retrieval to user-selected documents, HDER utilizes document structure for precise parameter localization, and HNEN standardizes terminology via semantic inference. Experimental results demonstrate that the framework achieves an Exact Match (EM) of 0.86, an F1 score of 0.92, and an Exact Correctness (EC) of 0.96, outperforming the strongest baseline by 19.4%, 5.7%, and 13.1%, respectively. Additionally, it reduces API token consumption by 38% and minimizes the irrelevant information ratio to 4%, showcasing substantial improvements in resource efficiency. This research provides an effective automated solution for circuit design.

Superconducting Digital (SCD) technology offers significant potential for enhancing the performance of next generation large scale compute workloads. By leveraging advanced lithography and a 300 mm platform, SCD devices can reduce energy consumption and boost computational power. This paper presents a cross-layer modeling approach to evaluate the system-level performance benefits of SCD architectures for Large Language Model (LLM) training and inference. Our findings, based on experimental data and Pulse Conserving Logic (PCL) design principles, demonstrate substantial performance gain in both training and inference. We are, thus, able to convincingly show that the SCD technology can address memory and interconnect limitations of present day solutions for next-generation compute systems.

Graph representation learning on Analog-Mixed Signal (AMS) circuits is crucial for various downstream tasks, e.g., parasitic estimation. However, the scarcity of design data, the unbalanced distribution of labels, and the inherent diversity of circuit implementations pose significant challenges to learning robust and transferable circuit representations. To address these limitations, we propose CircuitGCL, a novel graph contrastive learning framework that integrates representation scattering and label rebalancing to enhance transferability across heterogeneous circuit graphs. CircuitGCL employs a self-supervised strategy to learn topology-invariant node embeddings through hyperspherical representation scattering, eliminating dependency on large-scale data. Simultaneously, balanced mean squared error (BMSE) and balanced softmax cross-entropy (BSCE) losses are introduced to mitigate label distribution disparities between circuits, enabling robust and transferable parasitic estimation. Evaluated on parasitic capacitance estimation (edge-level task) and ground capacitance classification (node-level task) across TSMC 28nm AMS designs, CircuitGCL outperforms all state-of-the-art (SOTA) methods, with the R^2 improvement of 33.64% sim 44.20% for edge regression and F1-score gain of 0.9times sim 2.1times for node classification. Our code is available at https://github.com/ShenShan123/CircuitGCL.

Deep neural networks have made significant progress in the field of computer vision. Recent studies have shown that depth, width and shortcut connections of neural network architectures play a crucial role in their performance. One of the most advanced neural network architectures, DenseNet, has achieved excellent convergence rates through dense connections. However, it still has obvious shortcomings in the usage of amount of memory. In this paper, we introduce a new type of pruning tool, threshold, which refers to the principle of the threshold voltage in MOSFET. This work employs this method to connect blocks of different depths in different ways to reduce the usage of memory. It is denoted as ThresholdNet. We evaluate ThresholdNet and other different networks on datasets of CIFAR10. Experiments show that HarDNet is twice as fast as DenseNet, and on this basis, ThresholdNet is 10% faster and 10% lower error rate than HarDNet.

Hall effect thrusters are one of the most versatile and popular electric propulsion systems for space use. Industry trends towards interplanetary missions arise advances in design development of such propulsion systems. It is understood that correct sizing of discharge channel in Hall effect thruster impact performance greatly. Since the complete physics model of such propulsion system is not yet optimized for fast computations and design iterations, most thrusters are being designed using so-called scaling laws. But this work focuses on rather novel approach, which is outlined less frequently than ordinary scaling design approach in literature. Using deep machine learning it is possible to create predictive performance model, which can be used to effortlessly get design of required hall thruster with required characteristics using way less computational power than design from scratch and way more flexible than usual scaling approach.

Front-end electronics equipped with high-speed digitizers are being used and proposed for future nuclear detectors. Recent literature reveals that deep learning models, especially one-dimensional convolutional neural networks, are promising when dealing with digital signals from nuclear detectors. Simulations and experiments demonstrate the satisfactory accuracy and additional benefits of neural networks in this area. However, specific hardware accelerating such models for online operations still needs to be studied. In this work, we introduce PulseDL-II, a system-on-chip (SoC) specially designed for applications of event feature (time, energy, etc.) extraction from pulses with deep learning. Based on the previous version, PulseDL-II incorporates a RISC CPU into the system structure for better functional flexibility and integrity. The neural network accelerator in the SoC adopts a three-level (arithmetic unit, processing element, neural network) hierarchical architecture and facilitates parameter optimization of the digital design. Furthermore, we devise a quantization scheme compatible with deep learning frameworks (e.g., TensorFlow) within a selected subset of layer types. We validate the correct operations of PulseDL-II on field programmable gate arrays (FPGA) alone and with an experimental setup comprising a direct digital synthesis (DDS) and analog-to-digital converters (ADC). The proposed system achieved 60 ps time resolution and 0.40% energy resolution at signal to noise ratio (SNR) of 47.4 dB.

The increasing use of two-dimensional (2D) materials in nanoelectronics demands robust metrology techniques for electrical characterization, especially for large-scale production. While atomic force microscopy (AFM) techniques like conductive AFM (C-AFM) offer high accuracy, they suffer from slow data acquisition speeds due to the raster scanning process. To address this, we introduce SparseC-AFM, a deep learning model that rapidly and accurately reconstructs conductivity maps of 2D materials like MoS_2 from sparse C-AFM scans. Our approach is robust across various scanning modes, substrates, and experimental conditions. We report a comparison between (a) classic flow implementation, where a high pixel density C-AFM image (e.g., 15 minutes to collect) is manually parsed to extract relevant material parameters, and (b) our SparseC-AFM method, which achieves the same operation using data that requires substantially less acquisition time (e.g., under 5 minutes). SparseC-AFM enables efficient extraction of critical material parameters in MoS_2, including film coverage, defect density, and identification of crystalline island boundaries, edges, and cracks. We achieve over 11x reduction in acquisition time compared to manual extraction from a full-resolution C-AFM image. Moreover, we demonstrate that our model-predicted samples exhibit remarkably similar electrical properties to full-resolution data gathered using classic-flow scanning. This work represents a significant step toward translating AI-assisted 2D material characterization from laboratory research to industrial fabrication. Code and model weights are available at github.com/UNITES-Lab/sparse-cafm.

Circuit link prediction, which identifies missing component connections from incomplete netlists, is crucial in analog circuit design automation. However, existing methods face three main challenges: 1) Insufficient use of topological patterns in circuit graphs reduces prediction accuracy; 2) Data scarcity due to the complexity of annotations hinders model generalization; 3) Limited adaptability to various netlist formats restricts model flexibility. We propose Graph Neural Networks Based Analog Circuit Link Prediction (GNN-ACLP), a graph neural networks (GNNs) based method featuring three innovations to tackle these challenges. First, we introduce the SEAL (learning from Subgraphs, Embeddings, and Attributes for Link prediction) framework and achieve port-level accuracy in circuit link prediction. Second, we propose Netlist Babel Fish, a netlist format conversion tool that leverages retrieval-augmented generation (RAG) with a large language model (LLM) to enhance the compatibility of netlist formats. Finally, we build a comprehensive dataset, SpiceNetlist, comprising 775 annotated circuits of 7 different types across 10 component classes. Experiments demonstrate accuracy improvements of 16.08% on SpiceNetlist, 11.38% on Image2Net, and 16.01% on Masala-CHAI compared to the baseline in intra-dataset evaluation, while maintaining accuracy from 92.05% to 99.07% in cross-dataset evaluation, demonstrating robust feature transfer capabilities. However, its linear computational complexity makes processing large-scale netlists challenging and requires future addressing.

Accurate spatial prediction of power integrity issues, such as IR drop, is critical for reliable VLSI design. However, traditional simulation-based solvers are computationally expensive and difficult to scale. We address this challenge by reformulating IR drop estimation as a pixel-wise regression task on heterogeneous multi-channel physical maps derived from circuit layouts. Prior learning-based methods treat all input layers (e.g., metal, via, and current maps) equally, ignoring their varying importance to prediction accuracy. To tackle this, we propose a novel Weakness-Aware Channel Attention (WACA) mechanism, which recursively enhances weak feature channels while suppressing over-dominant ones through a two-stage gating strategy. Integrated into a ConvNeXtV2-based attention U-Net, our approach enables adaptive and balanced feature representation. On the public ICCAD-2023 benchmark, our method outperforms the ICCAD-2023 contest winner by reducing mean absolute error by 61.1% and improving F1-score by 71.0%. These results demonstrate that channel-wise heterogeneity is a key inductive bias in physical layout analysis for VLSI.

Neuromorphic models take inspiration from the human brain by adopting bio-plausible neuron models to build alternatives to traditional Machine Learning (ML) and Deep Learning (DL) solutions. The scarce availability of dedicated hardware able to actualize the emulation of brain-inspired computation, which is otherwise only simulated, yet still hinders the wide adoption of neuromorphic computing for edge devices and embedded systems. With this premise, we adopt the perspective of neuromorphic computing for conventional hardware and we present the L2MU, a natively neuromorphic Legendre Memory Unit (LMU) which entirely relies on Leaky Integrate-and-Fire (LIF) neurons. Specifically, the original recurrent architecture of LMU has been redesigned by modelling every constituent element with neural populations made of LIF or Current-Based (CuBa) LIF neurons. To couple neuromorphic computing and off-the-shelf edge devices, we equipped the L2MU with an input module for the conversion of real values into spikes, which makes it an encoding-free implementation of a Recurrent Spiking Neural Network (RSNN) able to directly work with raw sensor signals on non-dedicated hardware. As a use case to validate our network, we selected the task of Human Activity Recognition (HAR). We benchmarked our L2MU on smartwatch signals from hand-oriented activities, deploying it on three different commercial edge devices in compressed versions too. The reported results remark the possibility of considering neuromorphic models not only in an exclusive relationship with dedicated hardware but also as a suitable choice to work with common sensors and devices.

In recent years, AI-assisted IC design methods have demonstrated great potential, but the availability of circuit design data is extremely limited, especially in the public domain. The lack of circuit data has become the primary bottleneck in developing AI-assisted IC design methods. In this work, we make the first attempt, SynCircuit, to generate new synthetic circuits with valid functionalities in the HDL format. SynCircuit automatically generates synthetic data using a framework with three innovative steps: 1) We propose a customized diffusion-based generative model to resolve the Directed Cyclic Graph (DCG) generation task, which has not been well explored in the AI community. 2) To ensure our circuit is valid, we enforce the circuit constraints by refining the initial graph generation outputs. 3) The Monte Carlo tree search (MCTS) method further optimizes the logic redundancy in the generated graph. Experimental results demonstrate that our proposed SynCircuit can generate more realistic synthetic circuits and enhance ML model performance in downstream circuit design tasks.

A stochastic energetics framework is applied to examine how periodically shifting the frequency of a time-dependent oscillating temperature gradient affects heat transport in a nanoscale molecular model. We specifically examine the effects that frequency switching, i.e., instantaneously changing the oscillation frequency of the temperature gradient, has on the shape of the heat transport hysteresis curves generated by a particle connected to two thermal baths, each with a temperature that is oscillating in time. Analytical expressions are derived for the energy fluxes in/out of the system and the baths, with excellent agreement observed between the analytical expressions and the results from nonequilibrium molecular dynamics simulations. We find that the shape of the heat transport hysteresis curves can be significantly altered by shifting the frequency between fast and slow oscillation regimes. We also observe the emergence of features in the hysteresis curves such as pinched loops and complex multi-loop patterns due to the frequency shifting. The presented results have implications in the design of thermal neuromorphic devices such as thermal memristors and thermal memcapacitors.

The presence of point defects such as vacancies plays an important role in material design. Here, we demonstrate that a graph neural network (GNN) model trained only on perfect materials can also be used to predict vacancy formation energies (E_{vac}) of defect structures without the need for additional training data. Such GNN-based predictions are considerably faster than density functional theory (DFT) calculations with reasonable accuracy and show the potential that GNNs are able to capture a functional form for energy predictions. To test this strategy, we developed a DFT dataset of 508 E_{vac} consisting of 3D elemental solids, alloys, oxides, nitrides, and 2D monolayer materials. We analyzed and discussed the applicability of such direct and fast predictions. We applied the model to predict 192494 E_{vac} for 55723 materials in the JARVIS-DFT database.

Single walled carbon nanotubes exhibit advanced electrical and surface properties useful for high performance nanoelectronics. Important to future manufacturing of nanotube circuits is large scale assembly of SWNTs into aligned forms. Despite progress in assembly and oriented synthesis, pristine SWNTs in aligned and close-packed form remain elusive and needed for high current, speed and density devices through collective operations of parallel SWNTs. Here, we develop a Langmuir Blodgett method achieving monolayers of aligned SWNTs with dense packing, central to which is a non covalent polymer functionalization by PmPV imparting high solubility and stability of SWNTs in an organic solvent DCE. Pressure cycling or annealing during LB film compression reduces hysteresis and facilitates high degree alignment and packing of SWNTs characterized by microscopy and polarized Raman spectroscopy. The monolayer SWNTs are readily patterned for device integration by microfabrication, enabling the highest currents 3mA through the narrowest regions packed with aligned SWNTs thus far.

In this paper, we propose a learning rule based on a back-propagation (BP) algorithm that can be applied to a hardware-based deep neural network (HW-DNN) using electronic devices that exhibit discrete and limited conductance characteristics. This adaptive learning rule, which enables forward, backward propagation, as well as weight updates in hardware, is helpful during the implementation of power-efficient and high-speed deep neural networks. In simulations using a three-layer perceptron network, we evaluate the learning performance according to various conductance responses of electronic synapse devices and weight-updating methods. It is shown that the learning accuracy is comparable to that obtained when using a software-based BP algorithm when the electronic synapse device has a linear conductance response with a high dynamic range. Furthermore, the proposed unidirectional weight-updating method is suitable for electronic synapse devices which have nonlinear and finite conductance responses. Because this weight-updating method can compensate the demerit of asymmetric weight updates, we can obtain better accuracy compared to other methods. This adaptive learning rule, which can be applied to full hardware implementation, can also compensate the degradation of learning accuracy due to the probable device-to-device variation in an actual electronic synapse device.

We introduce the use of Crystal Graph Convolutional Neural Networks (CGCNN), Fully Connected Neural Networks (FCNN) and XGBoost to predict thermoelectric properties. The dataset for the CGCNN is independent of Density Functional Theory (DFT) and only relies on the crystal and atomic information, while that for the FCNN is based on a rich attribute list mined from Materialsproject.org. The results show that the optimized FCNN is three layer deep and is able to predict the scattering-time independent thermoelectric powerfactor much better than the CGCNN (or XGBoost), suggesting that bonding and density of states descriptors informed from materials science knowledge obtained partially from DFT are vital to predict functional properties.

Spiking Neural Networks (SNNs) are promising energy-efficient models for neuromorphic computing. For training the non-differentiable SNN models, the backpropagation through time (BPTT) with surrogate gradients (SG) method has achieved high performance. However, this method suffers from considerable memory cost and training time during training. In this paper, we propose the Spatial Learning Through Time (SLTT) method that can achieve high performance while greatly improving training efficiency compared with BPTT. First, we show that the backpropagation of SNNs through the temporal domain contributes just a little to the final calculated gradients. Thus, we propose to ignore the unimportant routes in the computational graph during backpropagation. The proposed method reduces the number of scalar multiplications and achieves a small memory occupation that is independent of the total time steps. Furthermore, we propose a variant of SLTT, called SLTT-K, that allows backpropagation only at K time steps, then the required number of scalar multiplications is further reduced and is independent of the total time steps. Experiments on both static and neuromorphic datasets demonstrate superior training efficiency and performance of our SLTT. In particular, our method achieves state-of-the-art accuracy on ImageNet, while the memory cost and training time are reduced by more than 70% and 50%, respectively, compared with BPTT.

In this paper, we propose AnalogSeeker, an effort toward an open-source foundation language model for analog circuit design, with the aim of integrating domain knowledge and giving design assistance. To overcome the scarcity of data in this field, we employ a corpus collection strategy based on the domain knowledge framework of analog circuits. High-quality, accessible textbooks across relevant subfields are systematically curated and cleaned into a textual domain corpus. To address the complexity of knowledge of analog circuits, we introduce a granular domain knowledge distillation method. Raw, unlabeled domain corpus is decomposed into typical, granular learning nodes, where a multi-agent framework distills implicit knowledge embedded in unstructured text into question-answer data pairs with detailed reasoning processes, yielding a fine-grained, learnable dataset for fine-tuning. To address the unexplored challenges in training analog circuit foundation models, we explore and share our training methods through both theoretical analysis and experimental validation. We finally establish a fine-tuning-centric training paradigm, customizing and implementing a neighborhood self-constrained supervised fine-tuning algorithm. This approach enhances training outcomes by constraining the perturbation magnitude between the model's output distributions before and after training. In practice, we train the Qwen2.5-32B-Instruct model to obtain AnalogSeeker, which achieves 85.04% accuracy on AMSBench-TQA, the analog circuit knowledge evaluation benchmark, with a 15.67% point improvement over the original model and is competitive with mainstream commercial models. Furthermore, AnalogSeeker also shows effectiveness in the downstream operational amplifier design task. AnalogSeeker is open-sourced at https://huggingface.co/analogllm/analogseeker for research use.

We present an open-source database of superconducting quantum device designs that may be used as the starting point for customized devices. Each design can be generated programmatically using the open-source Qiskit Metal package, and simulated using finite-element electromagnetic solvers. We present a robust workflow for achieving high accuracy on design simulations. Many designs in the database are experimentally validated, showing excellent agreement between simulated and measured parameters. Our database includes a front-end interface that allows users to generate ``best-guess'' designs based on desired circuit parameters. This project lowers the barrier to entry for research groups seeking to make a new class of devices by providing them a well-characterized starting point from which to refine their designs.

Freestanding thin films, a class of low-dimensional materials capable of maintaining structural integrity without substrates, have emerged as a forefront research focus. Their unique advantages-circumventing substrate clamping, liberating intrinsic material properties, and enabling cross-platform heterogeneous integration-underpin this prominence. This review systematically summarizes core fabrication techniques, including physical delamination (e.g., laser lift-off, mechanical exfoliation) and chemical etching, alongside associated transfer strategies. It further explores the induced strain modulation mechanisms, extreme mechanical properties and interface decoupling effects enabled by these films. Representative case studies demonstrate breakthrough applications in flexible/ultrathin electronics, ultrahigh-sensitivity sensors and the exploration of novel quantum states. Critical challenges regarding scalable fabrication, precise interface control, and long-term stability are analyzed, concluding with prospects for emerging applications in bio-inspired intelligent devices, quantum precision sensing, and brain-inspired neural networks.

As neural computation is revolutionizing the field of Artificial Intelligence (AI), rethinking the ideal neural hardware is becoming the next frontier. Fast and reliable von Neumann architecture has been the hosting platform for neural computation. Although capable, its separation of memory and computation creates the bottleneck for the energy efficiency of neural computation, contrasting the biological brain. The question remains: how can we efficiently combine memory and computation, while exploiting the physics of the substrate, to build intelligent systems? In this thesis, I explore an alternative way with memristive devices for neural computation, where the unique physical dynamics of the devices are used for inference, learning and routing. Guided by the principles of gradient-based learning, we selected functions that need to be materialized, and analyzed connectomics principles for efficient wiring. Despite non-idealities and noise inherent in analog physics, I will provide hardware evidence of adaptability of local learning to memristive substrates, new material stacks and circuit blocks that aid in solving the credit assignment problem and efficient routing between analog crossbars for scalable architectures.

Hall-effect thrusters (HETs) are widely used for modern near-earth spacecraft propulsion and are vital for future deep-space missions. Methods of modeling HETs are developing rapidly. However, such methods are not yet precise enough and cannot reliably predict the parameters of a newly designed thruster, mostly due to the enormous computational cost of a HET plasma simulation. Another approach is to use scaling techniques based on available experimental data. This paper proposes an approach for scaling HETs using neural networks and other modern machine learning methods. The new scaling model was built with information from an extensive database of HET parameters collected from published papers. Predictions of the new scaling model are valid for the operating parameters domain covered by the database. During the design, this model can help HET developers estimate the performance of a newly-designed thruster. At the stage of experimental research, the model can be used to compare the achieved characteristics of the studied thruster with the level obtained by other developers. A comparison with the state-of-the-art HET scaling model is also presented.

Among a huge variety of known two-dimensional materials, some of them have anisotropic crystal structures; examples include so different systems as a few-layer black phoshphorus (phosphorene), beryllium nitride BeN_4, van der Waals magnet CrSBr, rhenium dichalgogenides ReX_2. As a consequence, their optical and electronic properties turn out to be highly anisotropic as well. In some cases, the anisotropy results not just in a smooth renormalization of observable properties in comparison with the isotropic case but in the appearance of dramatically new physics. The examples are hyperbolic plasmons and excitons, strongly anisotropic ordering of adatoms at the surface of two-dimensional or van der Waals materials, essential change of transport and superconducting properties. Here, we present a systematic review of electronic structure, transport and optical properties of several representative groups of anisotropic two-dimensional materials including semiconductors, anisotropic Dirac and semi-Dirac materials, as well as superconductors.

Materials combining both a high refractive index and a wide band gap are of great interest for optoelectronic and sensor applications. However, these two properties are typically described by an inverse correlation with high refractive index appearing in small gap materials and vice-versa. Here, we conduct a first-principles high-throughput study on more than 4000 semiconductors (with a special focus on oxides). Our data confirm the general inverse trend between refractive index and band gap but interesting outliers are also identified. The data are then analyzed through a simple model involving two main descriptors: the average optical gap and the effective frequency. The former can be determined directly from the electronic structure of the compounds, but the latter cannot. This calls for further analysis in order to obtain a predictive model. Nonetheless, it turns out that the negative effect of a large band gap on the refractive index can counterbalanced in two ways: (i) by limiting the difference between the direct band gap and the average optical gap which can be realized by a narrow distribution in energy of the optical transitions and (ii) by increasing the effective frequency which can be achieved through either a high number of transitions from the top of the valence band to the bottom of the conduction or a high average probability for these transitions. Focusing on oxides, we use our data to investigate how the chemistry influences this inverse relationship and rationalize why certain classes of materials would perform better. Our findings can be used to search for new compounds in many optical applications both in the linear and non-linear regime (waveguides, optical modulators, laser, frequency converter, etc.).

Automatic generation of device-level analog circuit topologies remains a fundamental challenge in analog design automation. Recent transformer-based approaches have shown promise, yet they often suffer from limited functional controllability, memorization of training data, and the generation of electrically invalid circuits. We propose AnalogToBi, a device-level analog circuit topology generation framework that addresses these limitations. AnalogToBi enables explicit functional control via a circuit type token and adopts a bipartite graph-based circuit representation that decouples positional ordering from functional semantics, encouraging structural reasoning over sequence memorization. In addition, grammar-guided decoding enforces electrical validity during generation, while apply device renaming-based data augmentation improves generalization by increasing sequence diversity without altering circuit functionality. Experimental results show that AnalogToBi achieves 97.8% validity and 92.1% novelty, resulting in 89.9% valid and novel circuits under conditional generation, without human expert involvement. We further present that generated circuits can be automatically translated into SPICE netlists, and SPICE simulations confirm that AnalogToBi discovers high-quality analog topologies that outperform prior methods. For code and supplementary materials, see https://github.com/Seungmin0825/AnalogToBi

This study systematically investigates the photoconductive properties of low-temperature-grown Beryllium (Be)-doped InGaAs/InAlAs strain-balanced superlattices (SLs) grown by molecular beam epitaxy under stationary growth conditions on semi-insulating InP:Fe substrates. The stationary growth approach enabled precise control over lateral gradients in layer strain, composition, and thickness across a single wafer, while strain-balancing facilitated pseudomorphic growth to explore a wide range of structural parameters, providing a robust platform to study their influence on photoconductive performance. Structural characterization confirmed high crystalline quality and smooth surface morphology in all samples. Time-resolved pump-probe spectroscopy revealed subpicosecond carrier lifetimes, validating the effectiveness of strain balancing and Be doping in tuning ultrafast recombination dynamics. Hall effect measurements supported by 8-band k.p modeling revealed enhanced carrier mobility in strain-balanced SLs compared to lattice-matched structures, primarily due to reduced electron and hole effective masses and stronger quantum confinement. Additionally, optical absorption under 1550 nm excitation showed improved absorption coefficients for the strain-balanced structure, consistent with the reduction in bandgap energy predicted by theoretical modeling, thereby enhancing photon-to-carrier conversion efficiency. Furthermore, transmission electron microscopy provided first-time evidence of significant Be-induced interdiffusion at the strained SL interfaces, an important factor influencing carrier transport and dynamics. These findings position low-temperature-grown Be-doped InGaAs/InAlAs strain-balanced SLs as promising materials for high-performance broadband THz photoconductive detectors operating at telecom-compatible wavelengths.

Printed Circuit Board (PCB) schematic design plays an essential role in all areas of electronic industries. Unlike prior works that focus on digital or analog circuits alone, PCB design must handle heterogeneous digital, analog, and power signals while adhering to real-world IC packages and pin constraints. Automated PCB schematic design remains unexplored due to the scarcity of open-source data and the absence of simulation-based verification. We introduce PCBSchemaGen, the first training-free framework for PCB schematic design that comprises LLM agent and Constraint-guided synthesis. Our approach makes three contributions: 1. an LLM-based code generation paradigm with iterative feedback with domain-specific prompts. 2. a verification framework leveraging a real-world IC datasheet derived Knowledge Graph (KG) and Subgraph Isomorphism encoding pin-role semantics and topological constraints. 3. an extensive experiment on 23 PCB schematic tasks spanning digital, analog, and power domains. Results demonstrate that PCBSchemaGen significantly improves design accuracy and computational efficiency.

Collective modes of doped two-dimensional crystalline materials, namely graphene, MoS_2 and phosphorene, both monolayer and bilayer structures, are explored using the density functional theory simulations together with the random phase approximation. The many-body dielectric functions of the materials are calculated using an {\it ab initio} based model involving material-realistic physical properties. Having calculated the electron energy-loss, we calculate the collective modes of each material considering the in-phase and out-of-phase modes for bilayer structures. Furthermore, owing to many band structures and intreband transitions, we also find high-energy excitations in the systems. We explain that the material-specific dielectric function considering the polarizability of the crystalline material such as MoS_2 are needed to obtain realistic plasmon dispersions. For each material studied here, we find different collective modes and describe their physical origins.

Artificial transmission lines built with lumped-element inductors and capacitors form the backbone of broadband, nearly quantum-limited traveling-wave parametric amplifiers (TWPAs). However, systematic design methods for TWPAs, and more generally artificial transmission lines, are lacking. Here, I develop a general synthesis framework for lossless artificial transmission lines by borrowing from periodic structure theory and passive network synthesis. These complementary approaches divide the design space: periodic loading synthesis employs spatial modulation of frequency-independent components, while filter synthesis employs frequency-dependent responses in spatially-uniform components. When tailoring transmission lines for parametric processes, nonlinear elements are added, typically nonlinear inductances in superconducting circuits, while ensuring energy and momentum conservation between interacting tones. Applying this framework, I design a kinetic inductance TWPA with a novel phase-matching architecture, and a backward-pumped Josephson TWPA exploiting an ambidextrous i.e., right-left-handed transmission line.

Printed circuit board (PCB) schematic design defines nearly all electronic hardware, but it remains manual and expertise-intensive. While generative AI has advanced digital and analog IC design, PCB schematic generation from natural-language intent is largely unexplored. This paper presents SchGen, the first large language model that generates editable PCB schematics from natural-language requests. The key challenge lies in the lack of an LLM-suited representation and a large-scale dataset. Current schematic formats are dominated by verbose, tool-specific syntax and geometry-heavy descriptions, making them difficult to generate reliably. We introduce a semantically grounded code representation that encodes schematic editing primitives with relative placement and pin-name-based wiring, transforming a geometry-driven generation problem into a semantics-driven matching task amenable to LLMs. We further construct a large-scale dataset of PCB schematics paired with user prompts via a human-agent collaborative pipeline that converts open-source hardware designs into our representation. Experiments show that SchGen significantly outperforms alternative representations and even larger general-purpose LLMs on wire connectivity accuracy and functional correctness. Our results highlight the critical role of representation design in enabling generative models for complex hardware design tasks.

Organic Solar Cells are a promising technology for solving the clean energy crisis in the world. However, generating candidate chemical compounds for solar cells is a time-consuming process requiring thousands of hours of laboratory analysis. For a solar cell, the most important property is the power conversion efficiency which is dependent on the highest occupied molecular orbitals (HOMO) values of the donor molecules. Recently, machine learning techniques have proved to be very useful in building predictive models for HOMO values of donor structures of Organic Photovoltaic Cells (OPVs). Since experimental datasets are limited in size, current machine learning models are trained on data derived from calculations based on density functional theory (DFT). Molecular line notations such as SMILES or InChI are popular input representations for describing the molecular structure of donor molecules. The two types of line representations encode different information, such as SMILES defines the bond types while InChi defines protonation. In this work, we present an ensemble deep neural network architecture, called SINet, which harnesses both the SMILES and InChI molecular representations to predict HOMO values and leverage the potential of transfer learning from a sizeable DFT-computed dataset- Harvard CEP to build more robust predictive models for relatively smaller HOPV datasets. Harvard CEP dataset contains molecular structures and properties for 2.3 million candidate donor structures for OPV while HOPV contains DFT-computed and experimental values of 350 and 243 molecules respectively. Our results demonstrate significant performance improvement from the use of transfer learning and leveraging both molecular representations.

The exploration of thermoelectric materials is challenging considering the large materials space, combined with added exponential degrees of freedom coming from doping and the diversity of synthetic pathways. Here we seek to incorporate historical data and update and refine it using experimental feedback by employing error-correction learning (ECL). We thus learn from prior datasets and then adapt the model to differences in synthesis and characterization that are otherwise difficult to parameterize. We then apply this strategy to discovering thermoelectric materials where we prioritize synthesis at temperatures < 300{\deg}C. We document a previously unreported chemical family of thermoelectric materials, PbSe:SnSb, finding that the best candidate in this chemical family, 2 wt% SnSb doped PbSe, exhibits a power factor more than 2x that of PbSe. Our investigations show that our closed-loop experimentation strategy reduces the required number of experiments to find an optimized material by as much as 3x compared to high-throughput searches powered by state-of-the-art machine learning models. We also observe that this improvement is dependent on the accuracy of prior in a manner that exhibits diminishing returns, and after a certain accuracy is reached, it is factors associated with experimental pathways that dictate the trends.

The automation of analog integrated circuit (IC) design remains a longstanding challenge, primarily due to the intricate interdependencies among physical layout, parasitic effects, and circuit-level performance. These interactions impose complex constraints that are difficult to accurately capture and optimize using conventional design methodologies. Although recent advances in machine learning (ML) have shown promise in automating specific stages of the analog design flow, the development of holistic, end-to-end frameworks that integrate these stages and iteratively refine layouts using post-layout, parasitic-aware performance feedback is still in its early stages. Furthermore, progress in this direction is hindered by the limited availability of open, high-quality datasets tailored to the analog domain, restricting both the benchmarking and the generalizability of ML-based techniques. To address these limitations, we present OSIRIS, a scalable dataset generation pipeline for analog IC design. OSIRIS systematically explores the design space of analog circuits while producing comprehensive performance metrics and metadata, thereby enabling ML-driven research in electronic design automation (EDA). In addition, we release a dataset consisting of 87,100 circuit variations generated with OSIRIS, accompanied by a reinforcement learning (RL)-based baseline method that exploits OSIRIS for analog design optimization.

Accelerated materials discovery is an urgent demand to drive advancements in fields such as energy conversion, storage, and catalysis. Property-directed generative design has emerged as a transformative approach for rapidly discovering new functional inorganic materials with multiple desired properties within vast and complex search spaces. However, this approach faces two primary challenges: data scarcity for functional properties and the multi-objective optimization required to balance competing tasks. Here, we present a multi-property-directed generative framework designed to overcome these limitations and enhance site symmetry-compliant crystal generation beyond P1 (translational) symmetry. By incorporating Wyckoff-position-based data augmentation and transfer learning, our framework effectively handles sparse and small functional datasets, enabling the generation of new stable materials simultaneously conditioned on targeted space group, band gap, and formation energy. Using this approach, we identified previously unknown thermodynamically and lattice-dynamically stable semiconductors in tetragonal, trigonal, and cubic systems, with bandgaps ranging from 0.13 to 2.20 eV, as validated by density functional theory (DFT) calculations. Additionally, we assessed their thermoelectric descriptors using DFT, indicating their potential suitability for thermoelectric applications. We believe our integrated framework represents a significant step forward in generative design of inorganic materials.

Inverse design of solid-state materials with desired properties represents a formidable challenge in materials science. Although recent generative models have demonstrated potential, their adoption has been hindered by limitations such as inefficiency, architectural constraints and restricted open-source availability. The representation of crystal structures using the SLICES (Simplified Line-Input Crystal-Encoding System) notation as a string of characters enables the use of state-of-the-art natural language processing models, such as Transformers, for crystal design. Drawing inspiration from the success of GPT models in generating coherent text, we trained a generative Transformer on the next-token prediction task to generate solid-state materials with targeted properties. We demonstrate MatterGPT's capability to generate de novo crystal structures with targeted single properties, including both lattice-insensitive (formation energy) and lattice-sensitive (band gap) properties. Furthermore, we extend MatterGPT to simultaneously target multiple properties, addressing the complex challenge of multi-objective inverse design of crystals. Our approach showcases high validity, uniqueness, and novelty in generated structures, as well as the ability to generate materials with properties beyond the training data distribution. This work represents a significant step forward in computational materials discovery, offering a powerful and open tool for designing materials with tailored properties for various applications in energy, electronics, and beyond.

Large language models (LLMs) such as generative pretrained transformers (GPTs) have shown potential for various commercial applications, but their applicability for materials design remains underexplored. In this article, we introduce AtomGPT, a model specifically developed for materials design based on transformer architectures, to demonstrate the capability for both atomistic property prediction and structure generation. We show that a combination of chemical and structural text descriptions can efficiently predict material properties with accuracy comparable to graph neural network models, including formation energies, electronic bandgaps from two different methods and superconducting transition temperatures. Furthermore, we demonstrate that AtomGPT can generate atomic structures for tasks such as designing new superconductors, with the predictions validated through density functional theory calculations. This work paves the way for leveraging LLMs in forward and inverse materials design, offering an efficient approach to the discovery and optimization of materials.

We study the effect of perpendicular magnetic fields on a single-electron system with a strongly time-dependent electrostatic potential. Continuous improvements to the current quantization in these electron pumps are revealed by high-resolution measurements. Simulations show that the sensitivity of tunnel rates to the barrier potential is enhanced, stabilizing particular charge states. Nonadiabatic excitations are also suppressed due to a reduced sensitivity of the Fock-Darwin states to electrostatic potential. The combination of these effects leads to significantly more accurate current quantization.

The human brain is a complex spiking neural network (SNN) that learns multimodal signals in a zero-shot manner by generalizing existing knowledge. Remarkably, the brain achieves this with minimal power consumption, using event-based signals that propagate within its structure. However, mimicking the human brain in neuromorphic hardware presents both hardware and software challenges. Hardware limitations, such as the slowdown of Moore's law and the von Neumann bottleneck, hinder the efficiency of digital computers. On the software side, SNNs are known for their difficult training, especially when learning multimodal signals. To overcome these challenges, we propose a hardware-software co-design that combines a fixed and random liquid state machine (LSM) SNN encoder with trainable artificial neural network (ANN) projections. The LSM is physically implemented using analogue resistive memory, leveraging the inherent stochasticity of resistive switching to generate random weights. This highly efficient and nanoscale in-memory computing approach effectively addresses the von Neumann bottleneck and the slowdown of Moore's law. The ANN projections are implemented digitally, allowing for easy optimization using contrastive loss, which helps to overcome the difficulties associated with SNN training. We experimentally implement this co-design on a 40nm 256Kb in-memory computing macro. We first demonstrate LSM-based event encoding through supervised classification and linear probing on the N-MNIST and N-TIDIGITS datasets.

Characterizing materials with electron micrographs poses significant challenges for automated labeling due to the complex nature of nanomaterial structures. To address this, we introduce a fully automated, end-to-end pipeline that leverages recent advances in Generative AI. It is designed for analyzing and understanding the microstructures of semiconductor materials with effectiveness comparable to that of human experts, contributing to the pursuit of Artificial General Intelligence (AGI) in nanomaterial identification. Our approach utilizes Large MultiModal Models (LMMs) such as GPT-4V, alongside text-to-image models like DALLE-3. We integrate a GPT-4 guided Visual Question Answering (VQA) method to analyze nanomaterial images, generate synthetic nanomaterial images via DALLE-3, and employ in-context learning with few-shot prompting in GPT-4V for accurate nanomaterial identification. Our method surpasses traditional techniques by enhancing the precision of nanomaterial identification and optimizing the process for high-throughput screening.

We review theoretical and experimental highlights in transport in two-dimensional materials focussing on key developments over the last five years. Topological insulators are finding applications in magnetic devices, while Hall transport in doped samples and the general issue of topological protection remain controversial. In transition metal dichalcogenides valley-dependent electrical and optical phenomena continue to stimulate state-of-the-art experiments. In Weyl semimetals the properties of Fermi arcs are being actively investigated. A new field, expected to grow in the near future, focuses on the non-linear electrical and optical responses of topological materials, where fundamental questions are once more being asked about the intertwining roles of the Berry curvature and disorder scattering. In topological superconductors the quest for chiral superconductivity, Majorana fermions and topological quantum computing is continuing apace.

In 2021 Nature Physics published a paper by Vaitiekenas, Liu, Krogstrup and Marcus titled "Zero-bias peaks at zero magnetic field in ferromagnetic hybrid nanowires". The paper reports low temperature transport measurements on semiconductor InAs nanowires with two partly overlapping shells -- a shell of EuS, a magnetic insulator, and a shell of Al, a metal that becomes superconducting at temperatures below 1.2K. The paper claims that (1) the data are consistent with induced topological superconductivity and Majorana zero modes (MZMs), and (2) that this is facilitated by the breaking of the time reversal symmetry through a direct magnetic interaction with the EuS shell. In this Matters Arising, we present an alternative explanation which is based on trivial effects that are likely to appear in the reported geometry. Specifically, first, we find that data the authors present in support of the topological superconductivity claim can originate from unintended quantum dots in their devices, a widely known likely explanation that is not being discussed in the paper. Second, our analysis of the setup, supported by our numerical micromagnetic simulations, shows similar effects could be obtained due to stray magnetic fields from the region of the EuS shell damaged during Al etching. This basic picture should come before the exotic interpretation in terms of magnetic exchange interaction with a ferromagnetic insulator.

The long term scaling prospects for solid-state quantum computing architectures relies heavily on the ability to simply and reliably measure and control the coherent electron interaction strength, known as the tunnel coupling, t_c. Here, we describe a method to extract the t_c between two quantum dots (QDs) utilising their different tunnel rates to a reservoir. We demonstrate the technique on a few donor triple QD tunnel coupled to a nearby single-electron transistor (SET) in silicon. The device was patterned using scanning tunneling microscopy-hydrogen lithography allowing for a direct measurement of the tunnel coupling for a given inter-dot distance. We extract {t}_{{c}}=5.5pm 1.8;{GHz} and {t}_{{c}}=2.2pm 1.3;{GHz} between each of the nearest-neighbour QDs which are separated by 14.5 nm and 14.0 nm, respectively. The technique allows for an accurate measurement of t_c for nanoscale devices even when it is smaller than the electron temperature and is an ideal characterisation tool for multi-dot systems with a charge sensor.

While many piezoelectric materials are known, there is still great potential to improve on the figures of merit of existing materials through compositional doping, forming solid solutions. Specifically, it has been shown that doping and alloying wurtzite-structured materials can improve the piezoelectric response; however, a vast compositional space has remained unexplored. In this work, we apply a multi-level screening protocol combining machine learning, chemical intuition, and thermodynamics to systematically discover dopant combinations in wurtzite material space that improve the desired piezoelectric response. Through our protocol, we use computationally inexpensive screening calculations to consider more than 3000 possible ternary wurtzite solid solutions from 9 different wurtzite base systems: AlN, BeO, CdS, CdSe, GaN, ZnO, ZnS, ZnSe, and AgI. Finally, based on thermodynamic analysis and explicit piezoelectric response calculations, we predict 11 materials with improved piezoelectric response, due to the incorporation of electropositive dopants.

Recent years have seen a phenomenal rise in performance and applications of transformer neural networks. The family of transformer networks, including Bidirectional Encoder Representations from Transformer (BERT), Generative Pretrained Transformer (GPT) and Vision Transformer (ViT), have shown their effectiveness across Natural Language Processing (NLP) and Computer Vision (CV) domains. Transformer-based networks such as ChatGPT have impacted the lives of common men. However, the quest for high predictive performance has led to an exponential increase in transformers' memory and compute footprint. Researchers have proposed techniques to optimize transformer inference at all levels of abstraction. This paper presents a comprehensive survey of techniques for optimizing the inference phase of transformer networks. We survey techniques such as knowledge distillation, pruning, quantization, neural architecture search and lightweight network design at the algorithmic level. We further review hardware-level optimization techniques and the design of novel hardware accelerators for transformers. We summarize the quantitative results on the number of parameters/FLOPs and accuracy of several models/techniques to showcase the tradeoff exercised by them. We also outline future directions in this rapidly evolving field of research. We believe that this survey will educate both novice and seasoned researchers and also spark a plethora of research efforts in this field.

The demand for machine intelligence capable of processing continuous, long-context inputs on local devices is growing rapidly. However, the quadratic complexity and memory requirements of traditional Transformer architectures make them inefficient and often unusable for these tasks. This has spurred a paradigm shift towards new architectures like State Space Models (SSMs) and hybrids, which promise near-linear scaling. While most current research focuses on the accuracy and theoretical throughput of these models, a systematic performance characterization on practical consumer hardware is critically needed to guide system-level optimization and unlock new applications. To address this gap, we present a comprehensive, comparative benchmarking of carefully selected Transformer, SSM, and hybrid models specifically for long-context inference on consumer and embedded GPUs. Our analysis reveals that SSMs are not only viable but superior for this domain, capable of processing sequences up to 220K tokens on a 24GB consumer GPU-approximately 4x longer than comparable Transformers. While Transformers may be up to 1.8x faster at short sequences, SSMs demonstrate a dramatic performance inversion, becoming up to 4x faster at very long contexts (~57K tokens). Our operator-level analysis reveals that custom, hardware-aware SSM kernels dominate the inference runtime, accounting for over 55% of latency on edge platforms, identifying them as a primary target for future hardware acceleration. We also provide detailed, device-specific characterization results to guide system co-design for the edge. To foster further research, we will open-source our characterization framework.

Over the past decade, the dominance of deep learning has prevailed across various domains of artificial intelligence, including natural language processing, computer vision, and biomedical signal processing. While there have been remarkable improvements in model accuracy, deploying these models on lightweight devices, such as mobile phones and microcontrollers, is constrained by limited resources. In this survey, we provide comprehensive design guidance tailored for these devices, detailing the meticulous design of lightweight models, compression methods, and hardware acceleration strategies. The principal goal of this work is to explore methods and concepts for getting around hardware constraints without compromising the model's accuracy. Additionally, we explore two notable paths for lightweight deep learning in the future: deployment techniques for TinyML and Large Language Models. Although these paths undoubtedly have potential, they also present significant challenges, encouraging research into unexplored areas.

In this work, we generalize the reaction-diffusion equation in statistical physics, Schr\"odinger equation in quantum mechanics, Helmholtz equation in paraxial optics into the neural partial differential equations (NPDE), which can be considered as the fundamental equations in the field of artificial intelligence research. We take finite difference method to discretize NPDE for finding numerical solution, and the basic building blocks of deep neural network architecture, including multi-layer perceptron, convolutional neural network and recurrent neural networks, are generated. The learning strategies, such as Adaptive moment estimation, L-BFGS, pseudoinverse learning algorithms and partial differential equation constrained optimization, are also presented. We believe it is of significance that presented clear physical image of interpretable deep neural networks, which makes it be possible for applying to analog computing device design, and pave the road to physical artificial intelligence.

There can be numerous electronic components on a given PCB, making the task of visual inspection to detect defects very time-consuming and prone to error, especially at scale. There has thus been significant interest in automatic PCB component detection, particularly leveraging deep learning. However, deep neural networks typically require high computational resources, possibly limiting their feasibility in real-world use cases in manufacturing, which often involve high-volume and high-throughput detection with constrained edge computing resource availability. As a result of an exploration of efficient deep neural network architectures for this use case, we introduce PCBDet, an attention condenser network design that provides state-of-the-art inference throughput while achieving superior PCB component detection performance compared to other state-of-the-art efficient architecture designs. Experimental results show that PCBDet can achieve up to 2times inference speed-up on an ARM Cortex A72 processor when compared to an EfficientNet-based design while achieving sim2-4\% higher mAP on the FICS-PCB benchmark dataset.

Advances in research have sparked an increasing curiosity in understanding the plasmonic excitation properties of molecular-scale systems. Polycyclic aromatic hydrocarbons, as the fundamental building blocks of graphene, have been documented to possess plasmonic properties through experimental observations, making them prime candidates for investigation. By doping different elements, the conjugated structure of the molecule can be altered. In this study, the plasmonic excitation properties influenced by conjugated structures in peropyrene and its derivatives are investigated through first-principles calculations that combine the plasmonicity index, generalized plasmonicity index and transition contribution maps. For molecular plasmonic excitation, the conjugated structure can influence the oscillation modes of valence electrons, which is pivotal in yielding distinct field enhancement characteristics. Furthermore, charge doping can lead to a certain degree of alteration in the conjugated structures, and the doping of elements will result in varying degrees of such alteration, thereby initiating different trends in the evolution of plasmonic resonance. This further enhances the tunability of molecular plasmonic resonance. The results provide novel insights into the development and utilization of molecular plasmonic devices in practical applications.

In the context of quantum thermodynamics, quantum batteries have emerged as promising devices for energy storage and manipulation. Over the past decade, substantial progress has been made in understanding the fundamental properties of quantum batteries, with several experimental implementations showing great promise. This Perspective provides an overview of the solid-state materials platforms that could lead to fully operational quantum batteries. After briefly introducing the basic features of quantum batteries, we discuss organic microcavities, where superextensive charging has already been demonstrated experimentally. We then explore other materials, including inorganic nanostructures (such as quantum wells and dots), perovskite systems, and (normal and high-temperature) superconductors. Key achievements in these areas, relevant to the experimental realization of quantum batteries, are highlighted. We also address challenges and future research directions. Despite their enormous potential for energy storage devices, research into advanced materials for quantum batteries is still in its infancy. This paper aims to stimulate interdisciplinarity and convergence among different materials science research communities to accelerate the development of new materials and device architectures for quantum batteries.

The Orbital Hall effect, which originates from materials with weak spin-orbit coupling, has attracted considerable interest for spin-orbitronic applications. Here, we demonstrate the inverse effect of the orbital Hall effect and observe orbitronic terahertz emission in the Ti and Mn materials. Through spin-orbit transition in the ferromagnetic layer, the generated orbital current can be converted to charge current in the Ti and Mn layers via the inverse orbital Hall effect. Furthermore, the inserted W layer provides an additional conversion of the orbital-charge current in the Ti and Mn layers, significantly enhancing the orbitronic terahertz emission. Moreover, the orbitronic terahertz emission can be manipulated by cooperating with the inverse orbital Hall effect and the inverse spin Hall effect in the different sample configurations. Our results not only discover the physical mechanism of condensed matter physics but also pave the way for designing promising spin-orbitronic devices and terahertz emitters.

IR drop analysis is essential in physical chip design to ensure the power integrity of on-chip power delivery networks. Traditional Electronic Design Automation (EDA) tools have become slow and expensive as transistor density scales. Recent works have introduced machine learning (ML)-based methods that formulate IR drop analysis as an image prediction problem. These existing ML approaches fail to capture both local and long-range dependencies and ignore crucial geometrical and topological information from physical layouts and logical connectivity. To address these limitations, we propose GIF, a Generative IR drop Framework that uses both geometrical and topological information to generate IR drop images. GIF fuses image and graph features to guide a conditional diffusion process, producing high-quality IR drop images. For instance, On the CircuitNet-N28 dataset, GIF achieves 0.78 SSIM, 0.95 Pearson correlation, 21.77 PSNR, and 0.026 NMAE, outperforming prior methods. These results demonstrate that our framework, using diffusion based multimodal conditioning, reliably generates high quality IR drop images. This shows that IR drop analysis can effectively leverage recent advances in generative modeling when geometric layout features and logical circuit topology are jointly modeled. By combining geometry aware spatial features with logical graph representations, GIF enables IR drop analysis to benefit from recent advances in generative modeling for structured image generation.

Transition metal dichalcogenides (TMDs) and their Weyl semimetal phases, such as MoTe_2, have attracted significant attention for spin-orbit torque applications due to their efficient charge-to-spin conversion. However, whether this conversion originates predominantly from the bulk or the interface remains unclear. Here, we investigate spin-charge interconversion in MoTe_2 using spin-pumping and spin-torque ferromagnetic resonance (SP-FMR and ST-FMR). Thickness-dependent measurements reveal large spin-to-charge conversion and spin-torque efficiencies that are essentially independent of MoTe_2 thickness, indicating that the conversion is predominantly governed by the Rashba-Edelstein effect at the Py/MoTe_2 interface rather than by bulk spin transport. This behavior contrasts with the characteristic thickness dependence observed in Pt heterostructures and is further supported by bidirectional SP-FMR and interface-separation measurements. Our results highlight the dominant role of the Py/MoTe_2 interface in enabling efficient spin-charge conversion and spin-orbit torques in TMD-based spintronic devices. These findings highlight the potential of sputtered MoTe_2/Py heterostructures for low-power spintronic applications, including magnetic memory and logic devices.

Printed circuit boards (PCBs) are fundamental to modern electronic systems, yet AI-driven PCB design automation remains constrained by the lack of large-scale paired schematic-netlist datasets. PCB schematics are particularly challenging due to diverse component types, complex wiring topologies, and noisy textual annotations. To address this gap, we present PCBnet, a large-scale PCB schematic dataset comprising over 300 real-world designs with annotated pins and paired SPICE netlists. It contains more than 50,000 component instances, 150,000 wires, 100,000 text regions, and 400,000 characters. We further develop an automated schematic-to-netlist pipeline that combines visual recognition, topology construction, and domain-knowledge-guided multi-agent correction. The proposed method achieves 94.54% component detection mAP, 98.57% text recognition accuracy, and 84.47% end-to-end connectivity accuracy. PCBnet provides a benchmark and data foundation for future AI-driven PCB design automation.

The superconducting materials that make up an MKID have a significant effect on its performance. The T_c and normal state resistivity ρ_N of the film determine the penetration depth λ and therefore how much kinetic inductance it has. The ratio of kinetic inductance to total inductance (α), the volume of the inductor, and Q_m determines the magnitude of the response to incoming energy. The quasiparticle lifetime τ_qp is the characteristic time during which the MKID's surface impedance is modified by the incoming energy. Many materials have been explored for use in superconducting resonators and MKIDs, but that information is often not published or scattered around the literature. This chapter contains information and references on the work that has been done with thin film lithographed circuits for MKIDs over the last two decades. Note that measured material properties such as the internal loss quality factor Q_i and quasiparticle lifetime τ_qp vary significantly depending on how the MKID superconducting thin film is made and the system they are measured in, so it is best to interpret all stated values as typical but not definitive. Values are omitted in cases when there aren't enough measurements or there is too much disagreement in the literature to estimate a typical value. In order to be as complete as possible some unpublished results from the author's lab are included and can be identified by the lack of a reference. Unless noted all films are polycrystalline or amorphous.

Inverse design of RF passive components from S-parameters is a high-dimensional, ill-posed problem, and prior generative approaches are limited to single-layer binary-metallization structures. This paper presents an inverse design approach that generates passive components from partial S-parameter inputs on an 8times8 mm board discretized at 64times64 pixels with sub-pixel grayscale metallization across 1-20 GHz. The framework generates two-layer copper layouts with vias, with hard physical constraints on feed locations enforced through annealed Langevin projection, flexible multi-modal conditioning on partial S-parameter specifications, port locations, dielectric properties, reference topology, and variable port placement. Candidate designs are generated in seconds, with surrogate-predicted S-parameters matching targets to within 0.77 pm 1.28 dB weighted mean absolute error. We validate the approach with two fabricated designs on RO4003C: a manufacturable alternative to a hairpin filter whose coupling gaps violate fabrication rules, and a combline bandpass filter designed from scratch given only target S-parameters.

Consumer electronics used to follow the miniaturization trend described by Moore's Law. Despite increased processing power in Microcontroller Units (MCUs), MCUs used in the smallest appliances are still not capable of running even moderately big, state-of-the-art artificial neural networks (ANNs) especially in time-sensitive scenarios. In this work, we present a novel method called Scattered Online Inference (SOI) that aims to reduce the computational complexity of ANNs. SOI leverages the continuity and seasonality of time-series data and model predictions, enabling extrapolation for processing speed improvements, particularly in deeper layers. By applying compression, SOI generates more general inner partial states of ANN, allowing skipping full model recalculation at each inference.

Atomic layer deposition (ALD) is widely studied for numerous applications and is commercially employed in the semiconductor industry, where planar substrates are the norm. However, the inherent ALD feature of coating virtually any surface geometry with atomistic thickness control is equally attractive for coating particulate materials (supports). In this review, we provide a comprehensive overview of the developments in this decades-old field of ALD on particulate materials, drawing on a bottom-up and quantitative analysis of 799 articles from this field. The obtained dataset is the basis for abstractions regarding reactor types (specifically for particles), coating materials, reactants, supports and processing conditions. Furthermore, the dataset enables direct access to specific processing conditions (for a given material, surface functionality, application etc.) and increases accessibility of the respective literature. We also review fundamental concepts of ALD on particles, and discuss the most common applications, i.e., catalysis (thermo-, electro-, photo-), batteries, luminescent phosphors and healthcare. Finally, we identify historical trends, and provide an outlook on prospective developments.

A bilayer formed by stacking two distinct materials creates a moiré lattice, which can serve as a platform for novel electronic phases. In this work we study a unique example of such a system: the graphene-black phosphorus heterostructure (G/BP), which has been suggested to have an intricate band structure. Most notably, the valence band hosts a quasi-one-dimensional region in the Brillouin zone of high density of states, suggesting that various many-body electronic phases are likely to emerge. We derive an effective tight-binding model that reproduces this band structure, and explore the emergent broken-symmetry phases when interactions are introduced. Employing a mean-field analysis, we find that the favored ground-state exhibits a striped spin density wave (SDW) order, characterized by either one of two-fold degenerate wave-vectors that are tunable by gating. Further exploring the phase-diagram controlled by gate voltage and the interaction strength, we find that the SDW-ordered state undergoes a metal to insulator transition via an intermediate metallic phase which supports striped SDW correlations. Possible experimental signatures are discussed, in particular a highly anisotropic dispersion of the collective excitations which should be manifested in electric and thermal transport.

Standing as one of the most significant barriers to reaching quantum advantage, state-preparation fidelities on noisy intermediate-scale quantum processors suffer from quantum-gate errors, which accumulate over time. A potential remedy is pulse-based state preparation. We numerically investigate the minimal evolution times (METs) attainable by optimizing (microwave and exchange) pulses on silicon hardware. We investigate two state preparation tasks. First, we consider the preparation of molecular ground states and find the METs for H_2, HeH^+, and LiH to be 2.4 ns, 4.4 ns, and 27.2 ns, respectively. Second, we consider transitions between arbitrary states and find the METs for transitions between arbitrary four-qubit states to be below 50 ns. For comparison, connecting arbitrary two-qubit states via one- and two-qubit gates on the same silicon processor requires approximately 200 ns. This comparison indicates that pulse-based state preparation is likely to utilize the coherence times of silicon hardware more efficiently than gate-based state preparation. Finally, we quantify the effect of silicon device parameters on the MET. We show that increasing the maximal exchange amplitude from 10 MHz to 1 GHz accelerates the METs, e.g., for H_2 from 84.3 ns to 2.4 ns. This demonstrates the importance of fast exchange. We also show that increasing the maximal amplitude of the microwave drive from 884 kHz to 56.6 MHz shortens state transitions, e.g., for two-qubit states from 1000 ns to 25 ns. Our results bound both the state-preparation times for general quantum algorithms and the execution times of variational quantum algorithms with silicon spin qubits.

Transformers have gained popularity in machine learning due to their application in the field of natural language processing. They manipulate and process text efficiently, capturing long-range dependencies among data and performing the next word prediction. On the other hand, gate-based quantum computing is based on controlling the register of qubits in the quantum hardware by applying a sequence of gates, a process which can be interpreted as a low level text programming language. We develop a transformer model capable of transpiling quantum circuits from the qasm standard to other sets of gates native suited for a specific target quantum hardware, in our case the set for the trapped-ion quantum computers of IonQ. The feasibility of a translation up to five qubits is demonstrated with a percentage of correctly transpiled target circuits equal or superior to 99.98%. Regardless the depth of the register and the number of gates applied, we prove that the complexity of the transformer model scales, in the worst case scenario, with a polynomial trend by increasing the depth of the register and the length of the circuit, allowing models with a higher number of parameters to be efficiently trained on HPC infrastructures.

Stresses caused by thermal expansion coefficients mismatch of anodically bonded glass and silicon samples are studied. An analytical model to determine graphically the optimum bonding temperature is presented. It is essentially a model for thin-film stress but uses integration of the linear coefficient of thermal expansion difference between the bonding temperature and the working temperature. Recommendations for choosing the bonding temperature of silicon to two brands of glass (Corning 7740 and LK5) are made. Keywords: anodic bonding, field assisted bonding, thermal expansion, stress.

We have systematically investigated the grain boundary (GB) angle dependence of transport properties for NdFeAs(O,F) fabricated on [001]-tilt symmetric MgO bicrystal substrates. In our previous study, NdFeAs(O,F) bicrystal films showed a weak-link behaviour even at a GB angle of 6°. However, this was caused by an extrinsic effect originating from the damage to both NdFeAs(O,F) and MgO substrate by excess F-diffusion along the grain boundary. To investigate the intrinsic nature of grain boundaries, we minimized the damage to NdFeAs(O,F) and MgO by reducing the deposition temperature of NdOF over-layer needed for F-doping. The resultant NdFeAs(O,F) bicrystal films have a critical angle of 8.5°, above which Jc starts to decrease exponentially. This critical angle is almost the same as those of other Fe-based superconductors.

As large language models continue to scale in size rapidly, so too does the computational power required to run them. Event-based networks on neuromorphic devices offer a potential way to reduce energy consumption for inference significantly. However, to date, most event-based networks that can run on neuromorphic hardware, including spiking neural networks (SNNs), have not achieved task performance even on par with LSTM models for language modeling. As a result, language modeling on neuromorphic devices has seemed a distant prospect. In this work, we demonstrate the first-ever implementation of a language model on a neuromorphic device - specifically the SpiNNaker 2 chip - based on a recently published event-based architecture called the EGRU. SpiNNaker 2 is a many-core neuromorphic chip designed for large-scale asynchronous processing, while the EGRU is architected to leverage such hardware efficiently while maintaining competitive task performance. This implementation marks the first time a neuromorphic language model matches LSTMs, setting the stage for taking task performance to the level of large language models. We also demonstrate results on a gesture recognition task based on inputs from a DVS camera. Overall, our results showcase the feasibility of this neuro-inspired neural network in hardware, highlighting significant gains versus conventional hardware in energy efficiency for the common use case of single batch inference.

The rapid advancement of artificial intelligence (AI) technologies has led to an increasing deployment of AI models on edge and terminal devices, driven by the proliferation of the Internet of Things (IoT) and the need for real-time data processing. This survey comprehensively explores the current state, technical challenges, and future trends of on-device AI models. We define on-device AI models as those designed to perform local data processing and inference, emphasizing their characteristics such as real-time performance, resource constraints, and enhanced data privacy. The survey is structured around key themes, including the fundamental concepts of AI models, application scenarios across various domains, and the technical challenges faced in edge environments. We also discuss optimization and implementation strategies, such as data preprocessing, model compression, and hardware acceleration, which are essential for effective deployment. Furthermore, we examine the impact of emerging technologies, including edge computing and foundation models, on the evolution of on-device AI models. By providing a structured overview of the challenges, solutions, and future directions, this survey aims to facilitate further research and application of on-device AI, ultimately contributing to the advancement of intelligent systems in everyday life.

Quality of epitaxial films strongly depends on their structural and chemical match with the substrates: the more closely they match, the better the film quality is. Topological insulators (TI) such as Bi2Se3 thin films are of no exception. However, there do not exist commercial substrates that match with TI films both structurally and chemically, at the level commonly available for other electronic materials. Here, we introduce BiInSe3 bulk crystal as the best substrate for Bi2Se3 thin films. These films exhibit superior surface morphology, lower defect density and higher Hall mobility than those on other substrates, due to structural and chemical match provided by the BiInSe3 substrate. BiInSe3 substrate could accelerate the advance of TI research and applications.

Large Language Models (LLMs) have demonstrated the potential to address some issues within the semiconductor industry. However, they are often general-purpose models that lack the specialized knowledge needed to tackle the unique challenges of this sector, such as the intricate physics and chemistry of semiconductor devices and processes. SemiKong, the first industry-specific LLM for the semiconductor domain, provides a foundation that can be used to develop tailored proprietary models. With SemiKong 1.0, we aim to develop a foundational model capable of understanding etching problems at an expert level. Our key contributions include (a) curating a comprehensive corpus of semiconductor-related texts, (b) creating a foundational model with in-depth semiconductor knowledge, and (c) introducing a framework for integrating expert knowledge, thereby advancing the evaluation process of domain-specific AI models. Through fine-tuning a pre-trained LLM using our curated dataset, we have shown that SemiKong outperforms larger, general-purpose LLMs in various semiconductor manufacturing and design tasks. Our extensive experiments underscore the importance of developing domain-specific LLMs as a foundation for company- or tool-specific proprietary models, paving the way for further research and applications in the semiconductor domain. Code and dataset will be available at https://github.com/aitomatic/semikong

While neural network hardware accelerators provide a substantial amount of raw compute throughput, the models deployed on them must be co-designed for the underlying hardware architecture to obtain the optimal system performance. We present a class of computer vision models designed using hardware-aware neural architecture search and customized to run on the Edge TPU, Google's neural network hardware accelerator for low-power, edge devices. For the Edge TPU in Coral devices, these models enable real-time image classification performance while achieving accuracy typically seen only with larger, compute-heavy models running in data centers. On Pixel 4's Edge TPU, these models improve the accuracy-latency tradeoff over existing SoTA mobile models.

Strong correlation brings a rich array of emergent phenomena, as well as a daunting challenge to theoretical physics study. In condensed matter physics, the fractional quantum Hall effect is a prominent example of strong correlation, with Landau level mixing being one of the most challenging aspects to address using traditional computational methods. Deep learning real-space neural network wavefunction methods have emerged as promising architectures to describe electron correlations in molecules and materials, but their power has not been fully tested for exotic quantum states. In this work, we employ real-space neural network wavefunction techniques to investigate fractional quantum Hall systems. On both 1/3 and 2/5 filling systems, we achieve energies consistently lower than exact diagonalization results which only consider the lowest Landau level. We also demonstrate that the real-space neural network wavefunction can naturally capture the extent of Landau level mixing up to a very high level, overcoming the limitations of traditional methods. Our work underscores the potential of neural networks for future studies of strongly correlated systems and opens new avenues for exploring the rich physics of the fractional quantum Hall effect.

Electronic band structure (BS) and crystal structure are the two complementary identifiers of solid state materials. While convenient instruments and reconstruction algorithms have made large, empirical, crystal structure databases possible, extracting quasiparticle dispersion (closely related to BS) from photoemission band mapping data is currently limited by the available computational methods. To cope with the growing size and scale of photoemission data, we develop a pipeline including probabilistic machine learning and the associated data processing, optimization and evaluation methods for band structure reconstruction, leveraging theoretical calculations. The pipeline reconstructs all 14 valence bands of a semiconductor and shows excellent performance on benchmarks and other materials datasets. The reconstruction uncovers previously inaccessible momentum-space structural information on both global and local scales, while realizing a path towards integration with materials science databases. Our approach illustrates the potential of combining machine learning and domain knowledge for scalable feature extraction in multidimensional data.

Neural Architecture Search (NAS) has demonstrated its power on various AI accelerating platforms such as Field Programmable Gate Arrays (FPGAs) and Graphic Processing Units (GPUs). However, it remains an open problem, how to integrate NAS with Application-Specific Integrated Circuits (ASICs), despite them being the most powerful AI accelerating platforms. The major bottleneck comes from the large design freedom associated with ASIC designs. Moreover, with the consideration that multiple DNNs will run in parallel for different workloads with diverse layer operations and sizes, integrating heterogeneous ASIC sub-accelerators for distinct DNNs in one design can significantly boost performance, and at the same time further complicate the design space. To address these challenges, in this paper we build ASIC template set based on existing successful designs, described by their unique dataflows, so that the design space is significantly reduced. Based on the templates, we further propose a framework, namely NASAIC, which can simultaneously identify multiple DNN architectures and the associated heterogeneous ASIC accelerator design, such that the design specifications (specs) can be satisfied, while the accuracy can be maximized. Experimental results show that compared with successive NAS and ASIC design optimizations which lead to design spec violations, NASAIC can guarantee the results to meet the design specs with 17.77%, 2.49x, and 2.32x reductions on latency, energy, and area and with 0.76% accuracy loss. To the best of the authors' knowledge, this is the first work on neural architecture and ASIC accelerator design co-exploration.

Due to the high activation sparsity and use of accumulates (AC) instead of expensive multiply-and-accumulates (MAC), neuromorphic spiking neural networks (SNNs) have emerged as a promising low-power alternative to traditional DNNs for several computer vision (CV) applications. However, most existing SNNs require multiple time steps for acceptable inference accuracy, hindering real-time deployment and increasing spiking activity and, consequently, energy consumption. Recent works proposed direct encoding that directly feeds the analog pixel values in the first layer of the SNN in order to significantly reduce the number of time steps. Although the overhead for the first layer MACs with direct encoding is negligible for deep SNNs and the CV processing is efficient using SNNs, the data transfer between the image sensors and the downstream processing costs significant bandwidth and may dominate the total energy. To mitigate this concern, we propose an in-sensor computing hardware-software co-design framework for SNNs targeting image recognition tasks. Our approach reduces the bandwidth between sensing and processing by 12-96x and the resulting total energy by 2.32x compared to traditional CV processing, with a 3.8% reduction in accuracy on ImageNet.

Dielectric materials, with high tunability at microwave frequencies, are key components in the design of microwave communication systems. Dense Ba0.6Sr0.4TiO3 (BST) ceramics, with different grain sizes, were prepared in order to optimise the dielectric tunability via polar nano cluster effects. Dielectric permittivity and loss measurements were carried at both high and low frequencies and were supported by results from X-ray powder diffraction, scanning and transmission electron microscopies, Raman spectroscopy and piezoresponse force microscopy. The concentration of polar nano clusters, whose sizes are found to be in the range 20 to 50 nm, and the dielectric tunability increase with increasing grain size. A novel method for measurement of the microwave tunability in bulk dielectrics is presented. The highest tunability of 32% is achieved in ceramics with an average grain size of 10 um. The tunability of BST ceramics with applied DC field is demonstrated in a prototype small resonant antenna.

The brain is the perfect place to look for inspiration to develop more efficient neural networks. The inner workings of our synapses and neurons provide a glimpse at what the future of deep learning might look like. This paper serves as a tutorial and perspective showing how to apply the lessons learnt from several decades of research in deep learning, gradient descent, backpropagation and neuroscience to biologically plausible spiking neural neural networks. We also explore the delicate interplay between encoding data as spikes and the learning process; the challenges and solutions of applying gradient-based learning to spiking neural networks (SNNs); the subtle link between temporal backpropagation and spike timing dependent plasticity, and how deep learning might move towards biologically plausible online learning. Some ideas are well accepted and commonly used amongst the neuromorphic engineering community, while others are presented or justified for the first time here. The fields of deep learning and spiking neural networks evolve very rapidly. We endeavour to treat this document as a 'dynamic' manuscript that will continue to be updated as the common practices in training SNNs also change. A series of companion interactive tutorials complementary to this paper using our Python package, snnTorch, are also made available. See https://snntorch.readthedocs.io/en/latest/tutorials/index.html .

Identifying Majorana zero modes in semiconductor--superconductor nanowires requires ultra-low temperature transport measurements in dilution refrigerators, making device screening slow and resource-intensive. Here, we investigate whether high-temperature conductance data can be used to infer low-temperature Majorana nanowire properties before committing devices to dilution-refrigerator characterization. We generate paired high- and low-temperature conductance simulations for disordered Majorana nanowires and train neural networks to perform two related tasks. First, we use a Shifted Window U-Net Transformer diffusion-inspired architecture to reconstruct low-temperature conductance from thermally broadened high-temperature measurements, achieving high-fidelity recovery with R^2 0.95 for local conductance and R^2 0.91 for nonlocal conductance. Second, we train a Video Vision Transformer-based network to predict the low-temperature topological visibility directly from high-temperature conductance, obtaining R^2 0.80. These results demonstrate that machine-learning models can recover and infer low-temperature Majorana features from experimentally easier high-temperature data, providing a practical route for rejecting poor devices early thus avoiding slow and resource-intensive dilution refrigeration for non-promising devices. This high-temperature screening approach could substantially accelerate the experimental feedback loop for Majorana nanowire device development.

The prediction of material degradation is an important problem to solve in many industries. Environmental conditions, such as humidity and temperature, are important drivers of degradation processes, with corrosion being one of the most prominent ones. Quantum machine learning is a promising research field but suffers from well known deficits such as barren plateaus and measurement overheads. To address this problem, recent research has examined quantum reservoir computing to address time-series prediction tasks. Although a promising idea, developing circuits that are expressive enough while respecting the limited depths available on current devices is challenging. In classical reservoir computing, the onion echo state network model (ESN) [https://doi.org/10.1007/978-3-031-72359-9_9] was introduced to increase the interpretability of the representation structure of the embeddings. This onion ESN model utilizes a concatenation of smaller reservoirs that describe different time scales by covering different regions of the eigenvalue spectrum. Here, we use the same idea in the realm of quantum reservoir computing by simultaneously evolving smaller quantum reservoirs to better capture all the relevant time-scales while keeping the circuit depth small. We do this by modifying the rotation angles which we show alters the eigenvalues of the quantum evolution, but also note that modifying the number of mid-circuit measurements accomplishes the same goals of changing the long-term or short-term memory. This onion QRC outperforms a simple model and a single classical reservoir for predicting the degradation of aluminum alloys in different environmental conditions. By combining the onion QRC with an additional classical reservoir layer, the prediction accuracy is further improved.

Atomically thin metallic chains serve as pivotal systems for studying quantum transport, with their conductance strongly linked to the orbital picture. Here, we report a non-monotonic electro-mechanical response in a gold-ferrocene junction, characterized by an unexpected conductance increase over a factor of ten upon stretching. This response is detected in the formation of ferrocene-assisted atomic gold chain in a mechanically controllable break junction at a cryogenic temperature. DFT based calculations show that tilting of molecules inside the chain modifies the orbital overlap and the transmission spectra, leading to such non-monotonic conductance evolution with stretching. This behavior, unlike typical flat conductance plateaus observed in metal atomic chains, pinpoints the unique role of conformational rearrangements during chain elongation. Our findings provide a deeper understanding of the role of orbital hybridization in transport properties and offer new opportunities for designing nanoscale devices with tailored electro-mechanical characteristics.

RF/Analog design is essential for bridging digital technologies with real-world signals, ensuring the functionality and reliability of a wide range of electronic systems. However, analog design procedures are often intricate, time-consuming and reliant on expert intuition, and hinder the time and cost efficiency of circuit development. To overcome the limitations of the manual circuit design, we introduce MenTeR - a multiagent workflow integrated into an end-to-end analog design framework. By employing multiple specialized AI agents that collaboratively address different aspects of the design process, such as specification understanding, circuit optimization, and test bench validation, MenTeR reduces the dependency on frequent trial-and-error-style intervention. MenTeR not only accelerates the design cycle time but also facilitates a broader exploration of the design space, demonstrating robust capabilities in handling real-world analog systems. We believe that MenTeR lays the groundwork for future "RF/Analog Copilots" that can collaborate seamlessly with human designers.

Spiking neural networks (SNNs) can be used in low-power and embedded systems (such as emerging neuromorphic chips) due to their event-based nature. Also, they have the advantage of low computation cost in contrast to conventional artificial neural networks (ANNs), while preserving ANN's properties. However, temporal coding in layers of convolutional spiking neural networks and other types of SNNs has yet to be studied. In this paper, we provide insight into spatio-temporal feature extraction of convolutional SNNs in experiments designed to exploit this property. The shallow convolutional SNN outperforms state-of-the-art spatio-temporal feature extractor methods such as C3D, ConvLstm, and similar networks. Furthermore, we present a new deep spiking architecture to tackle real-world problems (in particular classification tasks) which achieved superior performance compared to other SNN methods on NMNIST (99.6%), DVS-CIFAR10 (69.2%) and DVS-Gesture (96.7%) and ANN methods on UCF-101 (42.1%) and HMDB-51 (21.5%) datasets. It is also worth noting that the training process is implemented based on variation of spatio-temporal backpropagation explained in the paper.

Spiking neural networks (SNNs) are well suited for spatio-temporal learning and implementations on energy-efficient event-driven neuromorphic processors. However, existing SNN error backpropagation (BP) methods lack proper handling of spiking discontinuities and suffer from low performance compared with the BP methods for traditional artificial neural networks. In addition, a large number of time steps are typically required to achieve decent performance, leading to high latency and rendering spike-based computation unscalable to deep architectures. We present a novel Temporal Spike Sequence Learning Backpropagation (TSSL-BP) method for training deep SNNs, which breaks down error backpropagation across two types of inter-neuron and intra-neuron dependencies and leads to improved temporal learning precision. It captures inter-neuron dependencies through presynaptic firing times by considering the all-or-none characteristics of firing activities and captures intra-neuron dependencies by handling the internal evolution of each neuronal state in time. TSSL-BP efficiently trains deep SNNs within a much shortened temporal window of a few steps while improving the accuracy for various image classification datasets including CIFAR10.

Transformers are ubiquitous in Natural Language Processing (NLP) tasks, but they are difficult to be deployed on hardware due to the intensive computation. To enable low-latency inference on resource-constrained hardware platforms, we propose to design Hardware-Aware Transformers (HAT) with neural architecture search. We first construct a large design space with arbitrary encoder-decoder attention and heterogeneous layers. Then we train a SuperTransformer that covers all candidates in the design space, and efficiently produces many SubTransformers with weight sharing. Finally, we perform an evolutionary search with a hardware latency constraint to find a specialized SubTransformer dedicated to run fast on the target hardware. Extensive experiments on four machine translation tasks demonstrate that HAT can discover efficient models for different hardware (CPU, GPU, IoT device). When running WMT'14 translation task on Raspberry Pi-4, HAT can achieve 3times speedup, 3.7times smaller size over baseline Transformer; 2.7times speedup, 3.6times smaller size over Evolved Transformer with 12,041times less search cost and no performance loss. HAT code is https://github.com/mit-han-lab/hardware-aware-transformers.git

Earlier, in the CINT program at Los Alamos National Laboratory, we focused ultrafast mode-locked lasers on the tip-sample junction of a scanning tunneling microscope to generate currents at hundreds of harmonics of the laser pulse repetition frequency. Each harmonic has a signal-to-noise ratio of 20 dB with a 10-dB linewidth of only 3 Hz. Now we model closed quantum nanocircuits with rectangular, triangular, or delta-function barrier, shunted by a beryllium filament for quasi-coherent electron transport over mean-free paths as great as 68 nm. The time-independent Schrödinger equation is solved with the boundary conditions that the wavefunction and its derivative are continuous at both connections. These four boundary conditions are used to form a four-by-four complex matrix equation with only zeros in the right-hand column vector which is required to have a non-trivial solution with each of the closed nanocircuits. Each model has four parameters: (1) the barrier length, (2) the height and shape of the barrier, (3) the length of the pre-barrier, and (4) the electron energy. Any three of these may be specified and then the fourth is varied to bring the determinant to zero to find the solutions on lines or surfaces in the space defined by the four parameters. First, we use a simplistic model having a rectangular barrier. The second model has a triangular barrier as a first approximation to field emission, and we are considering applying this approach for a self-contained nanoscale extension of our earlier effort to generate the harmonics at Los Alamos. The third model has a delta-function barrier, and the fourth model is an extension of the first one where the width of the rectangular barrier is varied inversely with its height.

Precision in identifying nanometer-scale device-killer defects is crucial in both semiconductor research and development as well as in production processes. The effectiveness of existing ML-based approaches in this context is largely limited by the scarcity of data, as the production of real semiconductor wafer data for training these models involves high financial and time costs. Moreover, the existing simulation methods fall short of replicating images with identical noise characteristics, surface roughness and stochastic variations at advanced nodes. We propose a method for generating synthetic semiconductor SEM images using a diffusion model within a limited data regime. In contrast to images generated through conventional simulation methods, SEM images generated through our proposed DL method closely resemble real SEM images, replicating their noise characteristics and surface roughness adaptively. Our main contributions, which are validated on three different real semiconductor datasets, are: i) proposing a patch-based generative framework utilizing DDPM to create SEM images with intended defect classes, addressing challenges related to class-imbalance and data insufficiency, ii) demonstrating generated synthetic images closely resemble real SEM images acquired from the tool, preserving all imaging conditions and metrology characteristics without any metadata supervision, iii) demonstrating a defect detector trained on generated defect dataset, either independently or combined with a limited real dataset, can achieve similar or improved performance on real wafer SEM images during validation/testing compared to exclusive training on a real defect dataset, iv) demonstrating the ability of the proposed approach to transfer defect types, critical dimensions, and imaging conditions from one specified CD/Pitch and metrology specifications to another, thereby highlighting its versatility.

Continuous solid electrolyte interface (SEI) formation remains the limiting factor of the lifetime of silicon nanoparticles (SiNPs) based negative electrodes. Methods that could provide clear diagnosis of the electrode degradation are of utmost necessity to streamline further developments. We demonstrate that electron energy-loss spectroscopy (EELS) in a scanning transmission electron microscope (STEM) can be used to quickly map SEI components and quantify LixSi alloys from single experiments, with resolutions down to 5 nm. Exploiting the low-loss part of the EEL spectrum allowed us to circumvent the degradation phenomena that have so far crippled the application of this technique on such beam-sensitive compounds. Our results provide unprecedented insight into silicon aging mechanisms in full cell configuration. We observe the morphology of the SEI to be extremely heterogeneous at the particle scale but with clear chemical evolutions with extended cycling coming from both SEI accumulation and a transition from lithium-rich carbonate-like compounds to lithium-poor ones. Thanks to the retrieval of several results from a single dataset, we were able to correlate local discrepancies in lithiation to the initial crystallinity of silicon as well as to the local SEI chemistry and morphology. This study emphasizes how initial heterogeneities in the percolating electronic network and the porosity affect SiNPs aggregates along cycling. These findings pinpoint the crucial role of an optimized formulation in silicon-based thick electrodes.