Removed the plot assets

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  1. README.md +1 -15
README.md CHANGED
@@ -116,7 +116,7 @@ hardware, wall-clock time, and energy consumption are not documented in the
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  current release artifacts. These should be added when verified records become
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  available.
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- ![TwiL-LM data creation, training, and evaluation workflow](card_assets/data_workflow_v2.png)
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  ## Evaluation
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@@ -128,16 +128,11 @@ over the eligible objectives. `mcq_answer` and `procedural` use
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  `max(accuracy, loose_match)`. `lean_prove` and perplexity corpora are excluded
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  from the macro score.
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- ![Macro accuracy compared with base models](card_assets/macro_vs_bases.png)
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-
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- ![Macro accuracy compared across Base and LoRA models](card_assets/macro_vs_bases_and_lora.png)
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  The broader comparison includes checkpoints with different parameter counts,
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  training procedures, and adaptation methods. It is useful for context but is not
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  a controlled architecture or scaling study.
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- ![TwiL-LM compared with SmolLM2-1.7B by objective](card_assets/objectives_vs_smollm2.png)
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-
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  TwiL-LM performs best on entailment labeling (**0.655**) and improves FOL
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  translation (**0.235**, compared with approximately zero for the base). Lean
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  formalization, Lean proving, and procedural reasoning remain weak.
@@ -147,22 +142,13 @@ formalization, Lean proving, and procedural reasoning remain weak.
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  OOD transfer was measured on GSM8K, ARC-Challenge chain-of-thought,
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  ARC-Challenge 25-shot log-likelihood (`acc_norm`), and LogicBench BQA.
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- ![TwiL-LM and SmolLM2-1.7B on OOD benchmarks](card_assets/unseen_benchmarks.png)
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-
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  Compared with SmolLM2-1.7B, TwiL-LM improves LogicBench BQA
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  (**0.590 vs 0.563**) but is lower on GSM8K (**0.380 vs 0.413**), ARC-C
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  chain-of-thought (**0.463 vs 0.587**), and ARC-C 25-shot log-likelihood
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  (**0.460 vs 0.490**).
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- ![OOD benchmark macro accuracy for Base, FT, and PS variants](card_assets/unseen_macro_no_gsm8k.png)
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-
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- These results indicate mixed transfer outside the formal-logic training
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- distribution. Larger general reasoning models remain stronger on several OOD
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- benchmarks.
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-
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  ### Throughput evaluation
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- ![Aggregate generation throughput](card_assets/throughput.png)
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  The formal-logic run generated 422,627 tokens in 1,152.34 generation seconds,
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  or **366.8 aggregate tokens per second**. The configuration used a maximum of
 
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  current release artifacts. These should be added when verified records become
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  available.
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+
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  ## Evaluation
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  `max(accuracy, loose_match)`. `lean_prove` and perplexity corpora are excluded
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  from the macro score.
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  The broader comparison includes checkpoints with different parameter counts,
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  training procedures, and adaptation methods. It is useful for context but is not
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  a controlled architecture or scaling study.
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  TwiL-LM performs best on entailment labeling (**0.655**) and improves FOL
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  translation (**0.235**, compared with approximately zero for the base). Lean
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  formalization, Lean proving, and procedural reasoning remain weak.
 
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  OOD transfer was measured on GSM8K, ARC-Challenge chain-of-thought,
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  ARC-Challenge 25-shot log-likelihood (`acc_norm`), and LogicBench BQA.
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  Compared with SmolLM2-1.7B, TwiL-LM improves LogicBench BQA
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  (**0.590 vs 0.563**) but is lower on GSM8K (**0.380 vs 0.413**), ARC-C
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  chain-of-thought (**0.463 vs 0.587**), and ARC-C 25-shot log-likelihood
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  (**0.460 vs 0.490**).
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  ### Throughput evaluation
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  The formal-logic run generated 422,627 tokens in 1,152.34 generation seconds,
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  or **366.8 aggregate tokens per second**. The configuration used a maximum of