repo_name stringlengths 1 62 | dataset stringclasses 1
value | lang stringclasses 11
values | pr_id int64 1 20.1k | owner stringlengths 2 34 | reviewer stringlengths 2 39 | diff_hunk stringlengths 15 262k | code_review_comment stringlengths 1 99.6k |
|---|---|---|---|---|---|---|---|
ipex-llm-tutorial | github_2023 | others | 6 | intel | shane-huang | @@ -0,0 +1,215 @@
+{
+ "cells": [
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "# Notebook 6.2: Baichuan-13B"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "## 6.2.1 Overview\n",
+ "\n",
+ "This is an example shows how to run [Baichuan-13B](ht... | This example shows |
ipex-llm-tutorial | github_2023 | others | 6 | intel | shane-huang | @@ -0,0 +1,215 @@
+{
+ "cells": [
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "# Notebook 6.2: Baichuan-13B"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "## 6.2.1 Overview\n",
+ "\n",
+ "This is an example shows how to run [Baichuan-13B](ht... | load Baichuan model with ... |
ipex-llm-tutorial | github_2023 | others | 6 | intel | shane-huang | @@ -0,0 +1,215 @@
+{
+ "cells": [
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "# Notebook 6.2: Baichuan-13B"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "## 6.2.1 Overview\n",
+ "\n",
+ "This is an example shows how to run [Baichuan-13B](ht... | A tokenizer is also needed for LLM inference. It is used to encode input texts to tensors to feed to LLMs, and decode the LLM output tensors to texts. You can use [Huggingface `transformers`]() API to load the tokenizer directly. It can be used seamlessly with models loaded w/ BigDL-LLM. |
ipex-llm-tutorial | github_2023 | others | 6 | intel | shane-huang | @@ -0,0 +1,215 @@
+{
+ "cells": [
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "# Notebook 6.2: Baichuan-13B"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "## 6.2.1 Overview\n",
+ "\n",
+ "This is an example shows how to run [Baichuan-13B](ht... | `from_pretrained` includes a conversion/quantization step, which can be particularly time-consuming for some large models. To expedite this process, you can use `save_low_bit` API to store the converted model after model is first loaded using `from_pretrained`. Later, you can opt to use the `load_low_bit` instead of `f... |
ipex-llm-tutorial | github_2023 | others | 6 | intel | shane-huang | @@ -0,0 +1,215 @@
+{
+ "cells": [
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "# Notebook 6.2: Baichuan-13B"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "## 6.2.1 Overview\n",
+ "\n",
+ "This is an example shows how to run [Baichuan-13B](ht... | we show an example template for question and answering here. |
ipex-llm-tutorial | github_2023 | others | 12 | intel | shane-huang | @@ -0,0 +1,9 @@
+# Chapter 6 Multi-Language Support
+
+This chapter we will explore the ability of large languange models in handling multiple languages. Multi-language support is of great importance for a large language model due to its far-reaching implications and real-world applications. This capability has opened ... | We provide two notebook examples showing the usage of two popular multi-language models, using Chinese for illustration.
- [ChatGLM2-6B]()
- [Baichuan-13B]() |
ipex-llm-tutorial | github_2023 | others | 4 | intel | shane-huang | @@ -0,0 +1,379 @@
+{
+ "cells": [
+ {
+ "attachments": {},
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "# Notebook 4.1: Run Transformer Models\n",
+ "\n",
+ "BigDL-LLM supports the optimization of any Hugging Face *transformers* model, allowing for efficient inference with significant... | No need to print prompt. It may be confusing to users. just OUTPUT is okay. |
ipex-llm-tutorial | github_2023 | others | 4 | intel | shane-huang | @@ -0,0 +1,379 @@
+{
+ "cells": [
+ {
+ "attachments": {},
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "# Notebook 4.1: Run Transformer Models\n",
+ "\n",
+ "BigDL-LLM supports the optimization of any Hugging Face *transformers* model, allowing for efficient inference with significant... | `load_in_4bit=True` is equivalent to `load_in_low_bit='sym_int4'`. |
ipex-llm-tutorial | github_2023 | others | 4 | intel | shane-huang | @@ -0,0 +1,379 @@
+{
+ "cells": [
+ {
+ "attachments": {},
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "# Notebook 4.1: Run Transformer Models\n",
+ "\n",
+ "BigDL-LLM supports the optimization of any Hugging Face *transformers* model, allowing for efficient inference with significant... | Follow instructions in [Chapter 2]() to setup your environment if you haven't done so. Then install `bigdl-llm`:
|
ipex-llm-tutorial | github_2023 | others | 3 | intel | shane-huang | @@ -0,0 +1,79 @@
+# Chapter 2 Quick Start
+
+This chapter offers a step-by-step tutorial that allows for hands-on learning. We will begin by setting up required environment and then proceed to develop an application with BigDL-LLM INT4 optimizations. This application will allow us to conduct inferences on a large langu... | make them into 3 tabs. Linux/Windows/Win+WSL |
ipex-llm-tutorial | github_2023 | others | 3 | intel | shane-huang | @@ -0,0 +1,79 @@
+# Chapter 2 Quick Start
+
+This chapter offers a step-by-step tutorial that allows for hands-on learning. We will begin by setting up required environment and then proceed to develop an application with BigDL-LLM INT4 optimizations. This application will allow us to conduct inferences on a large langu... | maybe 2.1.3.1 and 2.1.3.2 into two tabs Client/Server |
ipex-llm-tutorial | github_2023 | others | 3 | intel | shane-huang | @@ -0,0 +1,181 @@
+{
+ "cells": [
+ {
+ "attachments": {},
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "# Notebook 2: Quick Start\n",
+ "\n",
+ "With the environment set up, we now move into the hands-on tutorial to build an application for infering on a large language model with BigD... | You can also download the model from [huggingface repo](https://huggingface.co/openlm-research/open_llama_3b) to a local folder, and then specify `pretrained_model_name_or_path` parameter with the corresponding local path. |
ipex-llm-tutorial | github_2023 | others | 3 | intel | shane-huang | @@ -0,0 +1,181 @@
+{
+ "cells": [
+ {
+ "attachments": {},
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "# Notebook 2: Quick Start\n",
+ "\n",
+ "With the environment set up, we now move into the hands-on tutorial to build an application for infering on a large language model with BigD... | This quick start will help you get started with BigDL-LLM, and show you how to load a pretrained large language model and run it. |
ipex-llm-tutorial | github_2023 | others | 3 | intel | shane-huang | @@ -0,0 +1,181 @@
+{
+ "cells": [
+ {
+ "attachments": {},
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "# Notebook 2: Quick Start\n",
+ "\n",
+ "With the environment set up, we now move into the hands-on tutorial to build an application for infering on a large language model with BigD... | ## 2.2 BigDL-LLM Installation
Install BigDL-LLM in your activated conda environment:
```python
pip install bigdl-llm[all]
```
This will install bigdl-llm with all the dependencies for common LM application development. |
ipex-llm-tutorial | github_2023 | others | 2 | intel | jason-dai | @@ -0,0 +1,44 @@
+# Chapter 1 Introduction
+
+## What is BigDL-LLM
+[BigDL-LLM](https://github.com/intel-analytics/BigDL/tree/main/python/llm) is a library that makes LLMs (language language models) run fast on mid-to-low-end PCs. It is released as part of the open source project [BigDL](https://github.com/intel-analyt... | [BigDL-LLM](https://github.com/intel-analytics/BigDL/tree/main/python/llm) is a library that makes LLMs (language language models) run fast on low-cost PCs (without the need of discrete GPU). It is released as part of the open source [BigDL](https://github.com/intel-analytics/bigdl) project under Apache 2.0 License. |
ipex-llm-tutorial | github_2023 | others | 2 | intel | jason-dai | @@ -0,0 +1,44 @@
+# Chapter 1 Introduction
+
+## What is BigDL-LLM
+[BigDL-LLM](https://github.com/intel-analytics/BigDL/tree/main/python/llm) is a library that makes LLMs (language language models) run fast on mid-to-low-end PCs. It is released as part of the open source project [BigDL](https://github.com/intel-analyt... | You can use BigDL-LLM to run _any [HuggingFace transformer](https://huggingface.co/docs/transformers/index) model_. It automatically optimizes and accelerates the LLM using low-precision techniques, modern hardware accelerations and latest software optimizations. |
ipex-llm-tutorial | github_2023 | others | 2 | intel | jason-dai | @@ -0,0 +1,44 @@
+# Chapter 1 Introduction
+
+## What is BigDL-LLM
+[BigDL-LLM](https://github.com/intel-analytics/BigDL/tree/main/python/llm) is a library that makes LLMs (language language models) run fast on mid-to-low-end PCs. It is released as part of the open source project [BigDL](https://github.com/intel-analyt... | HuggingFace transformers-based applications can run on BigDL-LLM with one-line code change, and you'll immediately observe significant speedup. |
ipex-llm-tutorial | github_2023 | others | 2 | intel | jason-dai | @@ -0,0 +1,44 @@
+# Chapter 1 Introduction
+
+## What is BigDL-LLM
+[BigDL-LLM](https://github.com/intel-analytics/BigDL/tree/main/python/llm) is a library that makes LLMs (language language models) run fast on mid-to-low-end PCs. It is released as part of the open source project [BigDL](https://github.com/intel-analyt... | BigDL-LLM provides a variety of low-precision optimizations (e.g., INT4/INT5/INT8), and allows you to run LLMs on PCs with limited resources. For example, you will be able to run a 7B or 13B model on a 16G memory laptop with very low latency. |
ipex-llm-tutorial | github_2023 | others | 2 | intel | jason-dai | @@ -0,0 +1,44 @@
+# Chapter 1 Introduction
+
+## What is BigDL-LLM
+[BigDL-LLM](https://github.com/intel-analytics/BigDL/tree/main/python/llm) is a library that makes LLMs (language language models) run fast on mid-to-low-end PCs. It is released as part of the open source project [BigDL](https://github.com/intel-analyt... | #### 7B model running on an Intel 12-Gen Core PC (real-time screen capture):
|
ipex-llm-tutorial | github_2023 | others | 2 | intel | jason-dai | @@ -0,0 +1,44 @@
+# Chapter 1 Introduction
+
+## What is BigDL-LLM
+[BigDL-LLM](https://github.com/intel-analytics/BigDL/tree/main/python/llm) is a library that makes LLMs (language language models) run fast on mid-to-low-end PCs. It is released as part of the open source project [BigDL](https://github.com/intel-analyt... | #### 13B model running on an Intel 12-Gen Core PC (real-time screen capture):
|
ipex-llm-tutorial | github_2023 | others | 2 | intel | jason-dai | @@ -0,0 +1,44 @@
+# Chapter 1 Introduction
+
+## What is BigDL-LLM
+[BigDL-LLM](https://github.com/intel-analytics/BigDL/tree/main/python/llm) is a library that makes LLMs (language language models) run fast on mid-to-low-end PCs. It is released as part of the open source project [BigDL](https://github.com/intel-analyt... | Add conda create/activate? |
ipex-llm-tutorial | github_2023 | others | 2 | intel | jason-dai | @@ -0,0 +1,44 @@
+# Chapter 1 Introduction
+
+## What is BigDL-LLM
+[BigDL-LLM](https://github.com/intel-analytics/BigDL/tree/main/python/llm) is a library that makes LLMs (language language models) run fast on mid-to-low-end PCs. It is released as part of the open source project [BigDL](https://github.com/intel-analyt... | The following chapters in this tutorial will explain in more details about how to use BigDL-LLM to build LLM application, e.g. transformers API, langchain APIs, non-English support, etc. Each chapter will provide runnable notebooks using popular open source models. Read along to learn more and run the code on your lapt... |
ipex-llm-tutorial | github_2023 | others | 2 | intel | jason-dai | @@ -0,0 +1,44 @@
+# Chapter 1 Introduction
+
+## What is BigDL-LLM
+[BigDL-LLM](https://github.com/intel-analytics/BigDL/tree/main/python/llm) is a library that makes LLMs (language language models) run fast on mid-to-low-end PCs. It is released as part of the open source project [BigDL](https://github.com/intel-analyt... | We have already verified many models on BigDL-LLM and provided ready-to-run examples, such as ... |
ipex-llm-tutorial | github_2023 | others | 2 | intel | jason-dai | @@ -0,0 +1,49 @@
+# Chapter 1 Introduction
+
+## What is BigDL-LLM
+[BigDL-LLM](https://github.com/intel-analytics/BigDL/tree/main/python/llm) is a library that makes LLMs (language language models) run fast on low-cost PCs (without the need of discrete GPU). It is released as part of the open source [BigDL](https://gi... | maybe change to multi-language support? |
intel-xpu-backend-for-triton | github_2023 | python | 3,717 | intel | whitneywhtsang | @@ -61,8 +61,10 @@ def benchmark(Z, H, N_CTX, D_HEAD, CAUSAL, MODE, provider):
quantiles = [0.5, 0.0, 1.0]
if provider == 'triton':
+ kernel_options = {'num_stages': 2, 'num_warps': 16 if D_HEAD == 128 else 8, 'BLOCKS_ARE_CONTIGUOUS': True} | What is `BLOCKS_ARE_CONTIGUOUS` for? |
intel-xpu-backend-for-triton | github_2023 | others | 3,717 | intel | whitneywhtsang | @@ -185,3 +185,80 @@ module attributes {"ttg.num-warps" = 32 : i32, "ttg.threads-per-warp" = 16 : i32
tt.return
}
}
+
+// -----
+
+// COM: Test that dependency between AdvanceOp and none-tensor load are not triggering a pipeline schedule order errror. | ```suggestion
// COM: Test that dependency between AdvanceOp and none-tensor load are not triggering a pipeline schedule order error.
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 3,715 | intel | jopperm | @@ -106,16 +105,35 @@ class SmallVectorBuffer : public std::streambuf {
SmallVectorBuffer(llvm::SmallVectorImpl<char> &O) : OS(O) {}
};
-std::string translateLLVMIRToSPIRV(llvm::Module &module) {
- // initLLVM();
+static SPIRV::TranslatorOpts getSPIRVOopts() {
+ SPIRV::TranslatorOpts SPIRVOpts;
+ std::vector<S... | Nit: No need to construct a vector, I believe this can be a `static constexpr std::array`. |
intel-xpu-backend-for-triton | github_2023 | cpp | 3,715 | intel | Naghasan | @@ -106,16 +105,35 @@ class SmallVectorBuffer : public std::streambuf {
SmallVectorBuffer(llvm::SmallVectorImpl<char> &O) : OS(O) {}
};
-std::string translateLLVMIRToSPIRV(llvm::Module &module) {
- // initLLVM();
+static SPIRV::TranslatorOpts getSPIRVOopts() {
+ SPIRV::TranslatorOpts SPIRVOpts; | Minor: you probably want to control the max SPIR-V version used, that can avoid some surprises ... I think 1.4 is a sweet spot at the moment. It'll include
- SPV_KHR_no_integer_wrap_decoration
- SPV_KHR_float_controls
|
intel-xpu-backend-for-triton | github_2023 | cpp | 3,715 | intel | Naghasan | @@ -106,16 +105,35 @@ class SmallVectorBuffer : public std::streambuf {
SmallVectorBuffer(llvm::SmallVectorImpl<char> &O) : OS(O) {}
};
-std::string translateLLVMIRToSPIRV(llvm::Module &module) {
- // initLLVM();
+static SPIRV::TranslatorOpts getSPIRVOopts() {
+ SPIRV::TranslatorOpts SPIRVOpts;
+ std::vector<S... | do you have issues if you enable this ? It is a bit of a hack, but that can allow more LLVM information to be processed by IGC. |
intel-xpu-backend-for-triton | github_2023 | cpp | 3,715 | intel | Naghasan | @@ -106,16 +105,35 @@ class SmallVectorBuffer : public std::streambuf {
SmallVectorBuffer(llvm::SmallVectorImpl<char> &O) : OS(O) {}
};
-std::string translateLLVMIRToSPIRV(llvm::Module &module) {
- // initLLVM();
+static SPIRV::TranslatorOpts getSPIRVOopts() {
+ SPIRV::TranslatorOpts SPIRVOpts;
+ std::vector<S... | nit, keeping this alphabetically ordered is better for review and maintenance |
intel-xpu-backend-for-triton | github_2023 | cpp | 3,715 | intel | Naghasan | @@ -106,16 +105,35 @@ class SmallVectorBuffer : public std::streambuf {
SmallVectorBuffer(llvm::SmallVectorImpl<char> &O) : OS(O) {}
};
-std::string translateLLVMIRToSPIRV(llvm::Module &module) {
- // initLLVM();
+static SPIRV::TranslatorOpts getSPIRVOopts() {
+ SPIRV::TranslatorOpts SPIRVOpts;
+ std::vector<S... | - any use of expect / assume in LLVM IR ? if so you should add `SPV_KHR_expect_assume`
- `SPV_KHR_non_semantic_info` can be useful (and needed if you limit to SPIR-V 1.4)
- `SPV_INTEL_unstructured_loop_controls` is probably needed to have loop control attributes if they were rotated or can't be canonicalized into a s... |
intel-xpu-backend-for-triton | github_2023 | others | 3,656 | intel | pbchekin | @@ -22,7 +22,7 @@ permissions: read-all
env:
PYTHONIOENCODING: utf-8
NEW_WORKSPACE: C:\gh${{ github.run_id }}
- ZE_PATH: C:\level_zero
+ LEVEL_ZERO_V1_SDK_PATH: C:\level_zero | Since we expect this is set by the installer, we should not have it in the workflow. While we are waiting for the installer, every windows runner will have this environment set. |
intel-xpu-backend-for-triton | github_2023 | others | 3,656 | intel | pbchekin | @@ -34,7 +34,7 @@ permissions: read-all
env:
PYTHONIOENCODING: utf-8
NEW_WORKSPACE: C:\gh${{ github.run_id }}
- ZE_PATH: C:\level_zero
+ LEVEL_ZERO_V1_SDK_PATH: C:\level_zero | Since we expect this is set by the installer, we should not have it in the workflow. While we are waiting for the installer, every windows runner will have this environment set. |
intel-xpu-backend-for-triton | github_2023 | others | 3,712 | intel | whitneywhtsang | @@ -1,4 +1,4 @@
-cmake_minimum_required(VERSION 3.0 FATAL_ERROR)
+cmake_minimum_required(VERSION 3.10 FATAL_ERROR) | why need to update cmake version? |
intel-xpu-backend-for-triton | github_2023 | others | 3,705 | intel | whitneywhtsang | @@ -160,6 +160,18 @@ jobs:
TAG="${TAG}-adv"
python ../../scripts/build_report.py $REPORTS/matmul-performance-adv-path.csv $REPORTS/gemm-triton-advanced-report.csv --benchmark gemm --compiler triton --param_cols "B,M,K,N" --tflops_col Triton-TFlops --hbm_col "Triton-GB/s" --tag $TAG
+ - name... | Given that this benchmark is only run once, why do we need to rename the csv file? |
intel-xpu-backend-for-triton | github_2023 | python | 3,705 | intel | whitneywhtsang | @@ -0,0 +1,379 @@
+"""
+Gemm benchmark (tensor of pointer)
+============================
+
+This benchmark is come from the Triton tutorial 03-matrix-multiplication.py (commit: 3f4fdd1)
+To compare the performance to XeTLA kernel.
+
+"""
+import os
+
+import torch
+import triton
+import triton.language as tl
+
+import ... | `ACTIVATION` is not used, we can remove it. |
intel-xpu-backend-for-triton | github_2023 | cpp | 3,692 | intel | etiotto | @@ -0,0 +1,31 @@
+#include "PatternTritonGPUOpToLLVM.h"
+#include "intel/include/Dialect/TritonIntelGPU/IR/Utils.h"
+
+namespace {
+
+using namespace mlir;
+using namespace mlir::triton;
+
+struct FixCallCConv : public ConvertOpToLLVMPattern<LLVM::CallOp> {
+ using ConvertOpToLLVMPattern::ConvertOpToLLVMPattern;
+
+ ... | [nit]: Given that the file contain a using declaration for "mlir::triton" here you can use:
if (gpu::intel::....)
alternatively remove the using declaration at line 7 |
intel-xpu-backend-for-triton | github_2023 | cpp | 3,692 | intel | ienkovich | @@ -0,0 +1,28 @@
+#include "PatternTritonGPUOpToLLVM.h"
+#include "intel/include/Dialect/TritonIntelGPU/IR/Utils.h"
+
+namespace {
+
+struct FixCallCConv : public ConvertOpToLLVMPattern<LLVM::CallOp> {
+ using ConvertOpToLLVMPattern::ConvertOpToLLVMPattern;
+
+ LogicalResult
+ matchAndRewrite(LLVM::CallOp op, LLVM::... | These patterns are SPIRV target specific, so maybe reflect it in the file name and/or method name. |
intel-xpu-backend-for-triton | github_2023 | cpp | 3,692 | intel | ienkovich | @@ -221,7 +221,8 @@ void TargetInfo::printf(RewriterBase &rewriter, Value formatStrStart,
operands.push_back(printfPromoteValue(
rewriter, arg, isSigned.empty() ? true : isSigned[i]));
}
- b.call(funcOp, operands);
+ auto callOp = b.call(funcOp, operands);
+ callOp.setCConv(LLVM::cconv::CConv::SPIR_... | Is it required? CC fix-up pattern should handle this. With this change, the code starts to target SPIRV only. |
intel-xpu-backend-for-triton | github_2023 | cpp | 3,692 | intel | ienkovich | @@ -61,6 +61,10 @@ class TritonLLVMConversionTarget : public ConversionTarget {
return !triton::gpu::intel::hasSpirvTargetArch(op) ||
spirv::lookupTargetEnv(op) != nullptr;
});
+ addDynamicallyLegalOp<LLVM::CallOp>([](LLVM::CallOp op) {
+ return !triton::gpu::intel::hasSpirvTargetArch(... | Maybe we should introduce some common source of the correct CConv for the target instead of using immediate constants in the code? It would allow writing more generic code. E.g.
```
return op.getCConv() == triton::gpu::intel::getRequiredCConv(op);
```
And in the fix-up pattern:
```
rewriter.startOpModificatio... |
intel-xpu-backend-for-triton | github_2023 | cpp | 3,586 | intel | mfrancepillois | @@ -159,15 +272,32 @@ class LoopVersioner {
// by \p collector unnecessary.
// TODO: Extend the versioning region to encompass the downward exposed uses
// of the return values.
- static bool version(scf::ForOp &forOp, MaskedOpsCollector &collector) {
- assert(collector.getVersioningCond() &&
- "... | ```suggestion
// Currently we can version the loop only if it doesn't have downward
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 3,586 | intel | mfrancepillois | @@ -234,46 +362,67 @@ class LoopVersioner {
}
forOp.erase();
-
return true;
}
- // Ensure the loop upper bound is in canonical form (N+END-1)/END.
- static bool hasValidUpperBound(scf::ForOp &forOp) {
- Value ub = tt::intel::getFinalValue(forOp.getUpperBound());
- Operation *defOp = ub.get... | Would that make sense to create a third (and fourth?) branch if only load (or store) masks can be removed?
I think that it is still interesting to use 2D block loads even if store operations cannot not use 2D block store.
WDYT? |
intel-xpu-backend-for-triton | github_2023 | python | 3,586 | intel | whitneywhtsang | @@ -224,6 +224,8 @@ def make_ttir(mod, metadata, opt):
pm.enable_debug()
passes.common.add_inliner(pm)
passes.ttir.add_combine(pm)
+ passes.common.add_cse(pm) | Please check performance impact on adding these two passes in the pipeline. |
intel-xpu-backend-for-triton | github_2023 | cpp | 3,586 | intel | whitneywhtsang | @@ -211,11 +336,14 @@ class LoopVersioner {
thenB.create<scf::YieldOp>(loc, pruneUnusedResults(forOp, thenForLoop));
elseB.create<scf::YieldOp>(loc, pruneUnusedResults(forOp, elseForLoop));
- // Drop the mask from candidate masked operations in the "then" region's
- // cloned loop.
+ // Drop the ma... | remove naked prints. |
intel-xpu-backend-for-triton | github_2023 | cpp | 3,586 | intel | whitneywhtsang | @@ -3,9 +3,9 @@
#include "mlir/Dialect/Arith/IR/Arith.h"
#include "mlir/Dialect/SCF/IR/SCF.h"
#include "mlir/IR/Verifier.h"
-// #include "mlir/Pass/Pass.h" | it is not yet removed. |
intel-xpu-backend-for-triton | github_2023 | python | 3,699 | intel | whitneywhtsang | @@ -902,9 +902,6 @@ def test_mxfp8_mxfp4_matmul(M, N, K, BLOCK_M, BLOCK_N, BLOCK_K, NUM_STAGES, B_TR
if (A_DATA_TYPE == 'float4' and not WITH_A_SCALE) or (B_DATA_TYPE == 'float4' and not WITH_B_SCALE):
pytest.skip("Float4 without scale is tested in test_block_scale_fp4")
- if B_DATA_TYPE != '... | LGTM, please add a comment about this in #3307. |
intel-xpu-backend-for-triton | github_2023 | python | 3,679 | intel | whitneywhtsang | @@ -347,9 +353,17 @@ def test_mxfp(M, N, K, BLOCK_M, BLOCK_N, BLOCK_K, NUM_STAGES, nonKDim, NUM_WARPS
kernel_kwargs = {}
if is_hip():
kernel_kwargs["matrix_instr_nonkdim"] = nonKDim
- out = mxfp_matmul[grid](a, b, output, a_scale, b_scale, M, N, K, a_scale.stride(0), a.stride(0), a.stride(1),
- ... | can we do something similar to https://github.com/intel/intel-xpu-backend-for-triton/blob/main/python/test/unit/language/test_core.py#L3417 |
intel-xpu-backend-for-triton | github_2023 | others | 3,578 | intel | pbchekin | @@ -37,8 +37,12 @@ runs:
ITEM_PATH="${{ inputs.root }}/${{ inputs.key }}"
echo "dest=$ITEM_PATH" >> $GITHUB_OUTPUT
if [[ -d ${{ inputs.path }} ]]; then
- echo "Directory ${{ inputs.path }} exists and will not be restored from cache"
- exit 1
+ if [[ ${{ inputs.repos... | I think we don't need it here. Just add `rm -rf pytorch` in the workflow. |
intel-xpu-backend-for-triton | github_2023 | others | 3,578 | intel | pbchekin | @@ -45,8 +45,14 @@ runs:
if: inputs.ref != ''
shell: bash
run: |
- echo "PYTORCH_REPO=${{ inputs.repository }}" | tee -a "$GITHUB_ENV"
- echo "PYTORCH_COMMIT_ID=${{ steps.commit-id.outputs.commit_id }}" | tee -a "$GITHUB_ENV"
+ if [[ ${{ inputs.repository == 'liangan1/pytorch' ... | In bash, this is always true. I think this can be fixed with
```suggestion
if [[ "${{ inputs.repository }}" = "liangan1/pytorch" ]]; then
``` |
intel-xpu-backend-for-triton | github_2023 | others | 3,578 | intel | pbchekin | @@ -99,7 +105,7 @@ runs:
path: pytorch
- name: Apply additional PR patches
- if: ${{ steps.pytorch-cache.outputs.status == 'miss' && inputs.repository == 'pytorch/pytorch' && inputs.mode == 'source' }}
+ if: ${{ steps.pytorch-cache.outputs.status == 'miss' && inputs.mode == 'source' && inputs... | Did you mean:
```suggestion
if: ${{ steps.pytorch-cache.outputs.status == 'miss' && inputs.mode == 'source' && (inputs.repository == 'pytorch/pytorch' || inputs.repository == 'liangan1/pytorch') }}
``` |
intel-xpu-backend-for-triton | github_2023 | others | 3,578 | intel | whitneywhtsang | @@ -37,8 +37,8 @@ runs:
ITEM_PATH="${{ inputs.root }}/${{ inputs.key }}"
echo "dest=$ITEM_PATH" >> $GITHUB_OUTPUT
if [[ -d ${{ inputs.path }} ]]; then
- echo "Directory ${{ inputs.path }} exists and will not be restored from cache"
- exit 1
+ echo "Directory ${{ inp... | Not sure I understand, will not be removed, then why remove on the next line? |
intel-xpu-backend-for-triton | github_2023 | others | 3,578 | intel | whitneywhtsang | @@ -283,3 +283,30 @@ jobs:
with:
name: benchmark-reports
path: reports
+
+ # Install Pytorch with FlexAttention XPU support enabled
+ - name: Setup PyTorch
+ uses: ./.github/actions/setup-pytorch
+ with:
+ repository: liangan1/pytorch
+ ref: liang... | We would like to track the performance of FlexAttention in grafana too, which needs to go through the `Upload benchmark reports` step I believe. |
intel-xpu-backend-for-triton | github_2023 | others | 3,578 | intel | etiotto | @@ -45,8 +45,14 @@ runs:
if: inputs.ref != ''
shell: bash
run: |
- echo "PYTORCH_REPO=${{ inputs.repository }}" | tee -a "$GITHUB_ENV"
- echo "PYTORCH_COMMIT_ID=${{ steps.commit-id.outputs.commit_id }}" | tee -a "$GITHUB_ENV"
+ if [[ "${{ inputs.repository }}" = "liangan1/pytor... | What is "liangan1" ? Why do we need to use a personal directory ? |
intel-xpu-backend-for-triton | github_2023 | others | 3,578 | intel | whitneywhtsang | @@ -283,3 +283,30 @@ jobs:
with:
name: benchmark-reports
path: reports
+
+ # Install Pytorch with FlexAttention XPU support enabled
+ - name: Setup PyTorch
+ uses: ./.github/actions/setup-pytorch
+ with:
+ repository: liangan1/pytorch
+ ref: liang... | can we keep a consistent way to reference the benchmarks, custom masks or scores masks? |
intel-xpu-backend-for-triton | github_2023 | python | 3,578 | intel | liangan1 | @@ -0,0 +1,139 @@
+# This benchmark requires a Pytorch version with FlexAttention support for XPU available
+from functools import lru_cache
+import os
+from torch.nn.attention.flex_attention import (
+ create_block_mask,
+ flex_attention,
+)
+
+import torch
+import torch.nn.functional as F
+import triton_kernels... | Suggest to align the requirements in the https://jira.devtools.intel.com/browse/TRITONXPU-172. e.g., GQA/MHA, paged kv cache. More head dim, sequence length converge. |
intel-xpu-backend-for-triton | github_2023 | python | 3,578 | intel | liangan1 | @@ -0,0 +1,151 @@
+# This benchmark requires a Pytorch version with FlexAttention support for XPU available
+from functools import lru_cache
+import os
+from torch.nn.attention.flex_attention import (
+ create_block_mask,
+ flex_attention,
+)
+
+import torch
+import torch.nn.functional as F
+import triton_kernels... | There are two kernel for Flexattention, flex-attention for prefill and flex-decoding for the decoding stages. Only the sequence length of 16384/z(query, key, value) is covered in this benchmar and this is only for the prefill stage. In the real case, there are prefill(len(q)=len(k)=len(v), decoding(len(q)=1<<=len(k)=le... |
intel-xpu-backend-for-triton | github_2023 | python | 3,578 | intel | Egor-Krivov | @@ -42,6 +43,9 @@ def transform_df(df, param_cols, tflops_col, hbm_col, benchmark, compiler, tag):
# int values.
# Changing it without changing dashboards and database will
# break comparison of old and new results
+ if mask:
+ df_results["mask"] = df[param_cols[-1]] | If we add this new column, we'll also need to change database.
What is the purpose of this new column? |
intel-xpu-backend-for-triton | github_2023 | python | 3,578 | intel | Egor-Krivov | @@ -42,6 +43,9 @@ def transform_df(df, param_cols, tflops_col, hbm_col, benchmark, compiler, tag):
# int values.
# Changing it without changing dashboards and database will
# break comparison of old and new results
+ if mask:
+ df_results["mask"] = df[param_cols[-1]]
+ param_cols = param... | ```suggestion
for p in param_cols:
df[p] = df[p].astype(int)
df_results["params"] = [json.dumps(j) for j in df[[*param_cols, "MASK"]].to_dict("records")]
```
We need to keep "MASK" in a list of parameters, because it is one of the parameters and our dashboards need to know about it. Dashboards lo... |
intel-xpu-backend-for-triton | github_2023 | python | 3,578 | intel | whitneywhtsang | @@ -0,0 +1,143 @@
+# This benchmark requires a Pytorch version with FlexAttention support for XPU available
+from functools import lru_cache
+import os
+from torch.nn.attention.flex_attention import (
+ create_block_mask,
+ flex_attention,
+)
+
+import torch
+import torch.nn.functional as F
+import triton_kernels... | IMO, we don't need these comments `# argument names to use as an x-axis for the plot`, `# argument name whose value corresponds to a different line in the plot`, etc. |
intel-xpu-backend-for-triton | github_2023 | python | 3,578 | intel | whitneywhtsang | @@ -0,0 +1,144 @@
+# This benchmark requires a Pytorch version with FlexAttention support for XPU available
+from functools import lru_cache
+import os
+from torch.nn.attention.flex_attention import (
+ create_block_mask,
+ create_mask,
+ flex_attention,
+)
+
+import torch
+import torch.nn.functional as F
+
+i... | ```suggestion
line_names=['Triton', 'OneDNN'],
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 3,628 | intel | whitneywhtsang | @@ -160,7 +160,15 @@ struct PrintOpConversion
auto elem = elems[i];
os << getFormatSubstr(elem, hex, /*width=*/std::nullopt, isSigned);
- printfOperands.push_back(elem);
+ if (isa<IntegerType>(elem.getType()) &&
+ elem.getType().getIntOrFloatBitWidth() == 1) {
+ // FIXME: There... | is the problem reported to IGC? |
intel-xpu-backend-for-triton | github_2023 | others | 3,651 | intel | pbchekin | @@ -0,0 +1,121 @@
+name: Third party benchmarks
+run-name: ${{ inputs.run_name }}
+
+on:
+ workflow_dispatch:
+ inputs:
+ runner_label:
+ description: Runner label, keep empty for default
+ type: string
+ default: ""
+ tag:
+ description: Tag for benchmark results
+ type... | ```suggestion
python transform.py $REPORTS/liger-raw.csv $REPORTS/liger-report.csv
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 3,614 | intel | chengjunlu | @@ -71,9 +71,9 @@ class DialectInferLayoutInterface
Attribute got, std::optional<Location> loc) const = 0;
virtual LogicalResult
- inferJoinOpEncoding(Attribute srcEnc, Attribute &dstEnc,
- ArrayRef<int64_t> shape,
- std::optional<Location> loc) c... | Why need to change the function name? |
intel-xpu-backend-for-triton | github_2023 | others | 3,482 | intel | alexbaden | @@ -0,0 +1,137 @@
+// RUN: triton-opt %s -split-input-file --intel-allocate-shared-memory --convert-triton-intel-gpu-to-llvm | FileCheck %s --implicit-check-not=llvm.inline_asm
+
+// CHECK: llvm.func spir_funccc @_Z41intel_sub_group_2d_block_read_16b_8r16x2cPU3AS1viiiDv2_iPt
+#mma = #triton_intel_gpu.dpas<{repeatCoun... | Do we need all this other code to get the 2D block load? Or is it possible to just use a load instruction, the dot op, and the other instructions necessary to feed parameters and the layouts. |
intel-xpu-backend-for-triton | github_2023 | cpp | 3,482 | intel | alexbaden | @@ -478,6 +478,495 @@ struct PrefetchOpConversion
}
};
+struct LoadOpToBlockIOConversion
+ : public ConvertTritonGPUOpToLLVMPattern<triton::LoadOp>,
+ public LoadStoreConversionBase {
+ using ConvertTritonGPUOpToLLVMPattern<
+ triton::LoadOp>::ConvertTritonGPUOpToLLVMPattern;
+
+ using ValueTable =... | since you have `dpasLayout` above you can probably remove this branch. Then again, will we eventually be able to sync this function w/ the code in rewrite tensor pointer load? |
intel-xpu-backend-for-triton | github_2023 | cpp | 3,482 | intel | alexbaden | @@ -478,6 +478,495 @@ struct PrefetchOpConversion
}
};
+struct LoadOpToBlockIOConversion
+ : public ConvertTritonGPUOpToLLVMPattern<triton::LoadOp>,
+ public LoadStoreConversionBase {
+ using ConvertTritonGPUOpToLLVMPattern<
+ triton::LoadOp>::ConvertTritonGPUOpToLLVMPattern;
+
+ using ValueTable =... | why is this loop opposite the one for rewrite tensor pointer, which starts with `outer`? |
intel-xpu-backend-for-triton | github_2023 | cpp | 3,482 | intel | etiotto | @@ -478,6 +478,495 @@ struct PrefetchOpConversion
}
};
+struct LoadOpToBlockIOConversion
+ : public ConvertTritonGPUOpToLLVMPattern<triton::LoadOp>,
+ public LoadStoreConversionBase {
+ using ConvertTritonGPUOpToLLVMPattern<
+ triton::LoadOp>::ConvertTritonGPUOpToLLVMPattern;
+
+ using ValueTable =... | remove |
intel-xpu-backend-for-triton | github_2023 | cpp | 3,482 | intel | etiotto | @@ -478,6 +478,495 @@ struct PrefetchOpConversion
}
};
+struct LoadOpToBlockIOConversion
+ : public ConvertTritonGPUOpToLLVMPattern<triton::LoadOp>,
+ public LoadStoreConversionBase {
+ using ConvertTritonGPUOpToLLVMPattern<
+ triton::LoadOp>::ConvertTritonGPUOpToLLVMPattern;
+
+ using ValueTable =... | override -> final |
intel-xpu-backend-for-triton | github_2023 | cpp | 3,482 | intel | etiotto | @@ -478,6 +478,495 @@ struct PrefetchOpConversion
}
};
+struct LoadOpToBlockIOConversion
+ : public ConvertTritonGPUOpToLLVMPattern<triton::LoadOp>,
+ public LoadStoreConversionBase {
+ using ConvertTritonGPUOpToLLVMPattern<
+ triton::LoadOp>::ConvertTritonGPUOpToLLVMPattern;
+
+ using ValueTable =... | ```suggestion
const bool hasDpasLayout = hasDpasEncoding(tensorType);
if (!hasDpasLayout && !hasDotDpasEncoding(tensorType))
return failure();
auto encoding = cast<DPASEncodingAttr>(tensorType.getEncoding());
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 3,482 | intel | etiotto | @@ -478,6 +478,495 @@ struct PrefetchOpConversion
}
};
+struct LoadOpToBlockIOConversion
+ : public ConvertTritonGPUOpToLLVMPattern<triton::LoadOp>,
+ public LoadStoreConversionBase {
+ using ConvertTritonGPUOpToLLVMPattern<
+ triton::LoadOp>::ConvertTritonGPUOpToLLVMPattern;
+
+ using ValueTable =... | ```suggestion
auto getOpIdx = [&]() -> DpasEncodingAttr::OpIdx {
if (hasDpasLayout)
return DpasEncodingAttr::OpIdx::OperandC;
assert(hasDotDpasEncoding(tensorType) && "Expecting dot layout);
auto dotLayout = getDotEncoding(tensorType).value();
return static_cast<Dpas... |
intel-xpu-backend-for-triton | github_2023 | cpp | 3,482 | intel | etiotto | @@ -478,6 +478,495 @@ struct PrefetchOpConversion
}
};
+struct LoadOpToBlockIOConversion
+ : public ConvertTritonGPUOpToLLVMPattern<triton::LoadOp>,
+ public LoadStoreConversionBase {
+ using ConvertTritonGPUOpToLLVMPattern<
+ triton::LoadOp>::ConvertTritonGPUOpToLLVMPattern;
+
+ using ValueTable =... | auto -> DpasEncodingAttr::OpIdx |
intel-xpu-backend-for-triton | github_2023 | cpp | 3,482 | intel | etiotto | @@ -478,6 +478,495 @@ struct PrefetchOpConversion
}
};
+struct LoadOpToBlockIOConversion
+ : public ConvertTritonGPUOpToLLVMPattern<triton::LoadOp>,
+ public LoadStoreConversionBase {
+ using ConvertTritonGPUOpToLLVMPattern<
+ triton::LoadOp>::ConvertTritonGPUOpToLLVMPattern;
+
+ using ValueTable =... | ```suggestion
auto llAttr =
LinearEncodingAttr::get(rewriter.getContext(), *llEncoding);
SmallVector<unsigned> threadOrder(llAttr.getThreadOrder());
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 3,482 | intel | etiotto | @@ -478,6 +478,495 @@ struct PrefetchOpConversion
}
};
+struct LoadOpToBlockIOConversion
+ : public ConvertTritonGPUOpToLLVMPattern<triton::LoadOp>,
+ public LoadStoreConversionBase {
+ using ConvertTritonGPUOpToLLVMPattern<
+ triton::LoadOp>::ConvertTritonGPUOpToLLVMPattern;
+
+ using ValueTable =... | ```suggestion
unsigned threadsPerWarp = triton::gpu::getWarpSize(dpasLayout);
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 3,482 | intel | etiotto | @@ -478,6 +478,495 @@ struct PrefetchOpConversion
}
};
+struct LoadOpToBlockIOConversion
+ : public ConvertTritonGPUOpToLLVMPattern<triton::LoadOp>,
+ public LoadStoreConversionBase {
+ using ConvertTritonGPUOpToLLVMPattern<
+ triton::LoadOp>::ConvertTritonGPUOpToLLVMPattern;
+
+ using ValueTable =... | ```suggestion
ArrayRef<unsigned> repCluster = dpasLayout.getRepCluster();
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 3,482 | intel | etiotto | @@ -478,6 +478,495 @@ struct PrefetchOpConversion
}
};
+struct LoadOpToBlockIOConversion
+ : public ConvertTritonGPUOpToLLVMPattern<triton::LoadOp>,
+ public LoadStoreConversionBase {
+ using ConvertTritonGPUOpToLLVMPattern<
+ triton::LoadOp>::ConvertTritonGPUOpToLLVMPattern;
+
+ using ValueTable =... | ```suggestion
assert(rank == 2 && "unexpected rank");
unsigned dimOuter = bool(opIdx) ? rank - 1 : rank - 2;
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 3,482 | intel | etiotto | @@ -478,6 +478,495 @@ struct PrefetchOpConversion
}
};
+struct LoadOpToBlockIOConversion
+ : public ConvertTritonGPUOpToLLVMPattern<triton::LoadOp>,
+ public LoadStoreConversionBase {
+ using ConvertTritonGPUOpToLLVMPattern<
+ triton::LoadOp>::ConvertTritonGPUOpToLLVMPattern;
+
+ using ValueTable =... | ```suggestion
if (isTensorPointerType(ptr.getType())) {
// TODO: move the tensor pointer rewrite code here.
return failure();
}
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 3,482 | intel | etiotto | @@ -478,6 +478,495 @@ struct PrefetchOpConversion
}
};
+struct LoadOpToBlockIOConversion
+ : public ConvertTritonGPUOpToLLVMPattern<triton::LoadOp>,
+ public LoadStoreConversionBase {
+ using ConvertTritonGPUOpToLLVMPattern<
+ triton::LoadOp>::ConvertTritonGPUOpToLLVMPattern;
+
+ using ValueTable =... | Add assert message |
intel-xpu-backend-for-triton | github_2023 | cpp | 3,482 | intel | etiotto | @@ -478,6 +478,495 @@ struct PrefetchOpConversion
}
};
+struct LoadOpToBlockIOConversion
+ : public ConvertTritonGPUOpToLLVMPattern<triton::LoadOp>,
+ public LoadStoreConversionBase {
+ using ConvertTritonGPUOpToLLVMPattern<
+ triton::LoadOp>::ConvertTritonGPUOpToLLVMPattern;
+
+ using ValueTable =... | ```suggestion
unsigned offsetOuter =
outer * repOuterStride +
rep * dpasInstShape[dimOuter] * numOperandsOuterDimPerLoad;
unsigned offsetInner = inner * dpasInstShape[dimInner];
unsigned offsetM = (isOperandA ? offsetOuter : offsetInner);
unsigne... |
intel-xpu-backend-for-triton | github_2023 | cpp | 3,482 | intel | etiotto | @@ -478,6 +478,495 @@ struct PrefetchOpConversion
}
};
+struct LoadOpToBlockIOConversion
+ : public ConvertTritonGPUOpToLLVMPattern<triton::LoadOp>,
+ public LoadStoreConversionBase {
+ using ConvertTritonGPUOpToLLVMPattern<
+ triton::LoadOp>::ConvertTritonGPUOpToLLVMPattern;
+
+ using ValueTable =... | ```suggestion
VectorType vecTy = vec_ty(eltTy, numValuesPerLoad * packedElemsNum);
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 3,482 | intel | etiotto | @@ -478,6 +478,495 @@ struct PrefetchOpConversion
}
};
+struct LoadOpToBlockIOConversion
+ : public ConvertTritonGPUOpToLLVMPattern<triton::LoadOp>,
+ public LoadStoreConversionBase {
+ using ConvertTritonGPUOpToLLVMPattern<
+ triton::LoadOp>::ConvertTritonGPUOpToLLVMPattern;
+
+ using ValueTable =... | ```suggestion
unsigned N = packedCol +
col * threadsPerWarp * numColPerPackedValue +
vblk * tileWidth + offsetN;
unsigned M = i + offsetM;
``` |
intel-xpu-backend-for-triton | github_2023 | others | 3,482 | intel | etiotto | @@ -0,0 +1,137 @@
+// RUN: triton-opt %s -split-input-file --intel-allocate-shared-memory --convert-triton-intel-gpu-to-llvm | FileCheck %s --implicit-check-not=llvm.inline_asm
+
+// CHECK: llvm.func spir_funccc @_Z41intel_sub_group_2d_block_read_16b_8r16x2cPU3AS1viiiDv2_iPt
+#mma = #triton_intel_gpu.dpas<{repeatCoun... | Rather long tests, can they be reduced and simplified please? |
intel-xpu-backend-for-triton | github_2023 | python | 1,905 | intel | chengjunlu | @@ -68,7 +68,7 @@ def do_bench(fn, warmup=25, rep=100, grad_to_none=None, quantiles=None, fast_flu
for _ in range(n_warmup):
fn()
# Benchmark
- with torch.autograd.profiler_legacy.profile(True, use_xpu=True) as prof:
+ with torch.profiler.profile() as prof: | Need to refer the Torch profiling step to capture the XPU kernel performance. |
intel-xpu-backend-for-triton | github_2023 | python | 1,905 | intel | chengjunlu | @@ -86,7 +86,7 @@ def do_bench(fn, warmup=25, rep=100, grad_to_none=None, quantiles=None, fast_flu
# Record clocks
synchronize()
- profiling_func_filter = filter(lambda x: x.name.startswith("__profile_kernel_of_func"), prof.function_events)
+ profiling_func_filter = filter(lambda x: x.name.sta... | Need to check how to profile the Triton kernel with the Kineto profilier. |
intel-xpu-backend-for-triton | github_2023 | python | 1,905 | intel | chengjunlu | @@ -10,15 +10,15 @@
from triton.runtime.build import _build, quiet
import torch
-import intel_extension_for_pytorch
+# import intel_extension_for_pytorch | We can simply remove this file as long as Kineto works by removing the usage of this file at here:
https://github.com/intel/intel-xpu-backend-for-triton/blob/c7c60809cccfee24a650708712d9cc5aecf3db9f/benchmarks/triton_kernels_benchmark/__init__.py#L12
|
intel-xpu-backend-for-triton | github_2023 | cpp | 1,905 | intel | chengjunlu | @@ -99,7 +107,7 @@ at::Tensor bf16_stream_k_gemm(const at::Tensor &a, const at::Tensor &b,
auto queue = get_current_sycl_queue();
auto evt = stream_k_gemm_run(a.data_ptr(), b.data_ptr(), c.data_ptr(),
acc.data_ptr(), cnt.data_ptr(), queue);
- xpu::profiler_record("xetla kernel", e... | There are two profilers in the Torch. `torch.autograd.profiler_legacy.profile` and `torch.profiler.profile`.
The `xpu::profiler_record` is to add the SYCL event to the first profile and the legacy profile can get the Triton kernel performance statistics for using.
The second profiler is based on Kineto and PTI. I... |
intel-xpu-backend-for-triton | github_2023 | others | 1,905 | intel | chengjunlu | @@ -29,13 +29,11 @@ endif()
add_library(xetla_kernel SHARED python_main.cpp)
set_target_properties(xetla_kernel PROPERTIES PREFIX "")
target_compile_options(xetla_kernel PRIVATE "-fPIC")
-target_compile_options(xetla_kernel PRIVATE "-fsycl")
+target_compile_options(xetla_kernel PRIVATE "-fsycl" "-fpreview-breaking-c... | @ZzEeKkAa The changes is required to run the XeTLA kernel in the benchmarks.
But do you have any idea why this flag is required?
https://github.com/intel/llvm/blob/283073a4f21aa44203fd49e25b4ff0379c91b29a/sycl/doc/UsersManual.md?plain=1#L429 |
intel-xpu-backend-for-triton | github_2023 | others | 1,905 | intel | whitneywhtsang | @@ -49,12 +57,28 @@ jobs:
run: |
pip install wheel
- - name: Setup PyTorch
+ - name: Setup PyTorch with IPEX
+ if: ${{ inputs.install_ipex }}
+ uses: ./.github/actions/setup-pytorch
+ with:
+ repository: Stonepia/pytorch
+ ref: ${{ inputs.pytorch_re... | Given that we are removing `import intel_extension_for_pytorch` in this PR, do we still need to setup no-op IPEX? |
intel-xpu-backend-for-triton | github_2023 | python | 3,637 | intel | pbchekin | @@ -111,23 +111,59 @@ def select_compiler():
return cxx
+def _cxx_compile_cmd(cxx: str, src: list, include_dirs: list, only_compile=True) -> list: | Nit: for consistency:
```suggestion
def _cxx_compile_cmd(cxx: str, src: list, include_dirs: list, only_compile: bool = True) -> list:
``` |
intel-xpu-backend-for-triton | github_2023 | python | 3,629 | intel | pbchekin | @@ -99,19 +101,34 @@ def kernel(C, A, B, M, N, K,
}"""
+def select_compiler():
+ gxx = shutil.which("g++")
+ icpx = shutil.which("icpx")
+ cl = shutil.which("cl")
+ cxx = icpx or cl if os.name == "nt" else icpx or gxx | Nit: for humble developers who don't know what's is operators priority on Python)
```suggestion
cxx = icpx or (cl if os.name == "nt" else icpx) or gxx
``` |
intel-xpu-backend-for-triton | github_2023 | python | 3,629 | intel | pbchekin | @@ -424,7 +446,7 @@ def test_compile_link_matmul_no_specialization():
# run test case
env = os.environ.copy()
env["LD_LIBRARY_PATH"] = tmp_dir + ":" + env.get("LD_LIBRARY_PATH", "")
- subprocess.run(["./test", a_path, b_path, c_path], env=env, check=True, cwd=tmp_dir)
+ subproce... | Good catch! |
intel-xpu-backend-for-triton | github_2023 | cpp | 3,497 | intel | etiotto | @@ -98,9 +98,6 @@ class TargetInfoBase {
virtual void storeOpAnnotation(triton::gpu::LocalStoreOp op,
size_t localStoreOpCount, Type type) const {}
- virtual Value getStackPointer(RewriterBase &rewriter, | Are they removing this upstream as well ? If not would be better to leave the declaration here. |
intel-xpu-backend-for-triton | github_2023 | cpp | 3,497 | intel | etiotto | @@ -61,9 +61,6 @@ class TargetInfo : public mlir::triton::TargetInfoBase {
int getSharedAddressSpace() const override;
- Value getStackPointer(RewriterBase &rewriter, | Why do we need to change an Nvidia file ? |
intel-xpu-backend-for-triton | github_2023 | cpp | 3,497 | intel | ienkovich | @@ -0,0 +1,101 @@
+#include "intel/include/Dialect/TritonIntelGPU/IR/Dialect.h"
+#include "intel/include/Dialect/TritonIntelGPU/Transforms/Passes.h"
+#include "mlir/Dialect/LLVMIR/LLVMDialect.h"
+#include "mlir/Dialect/LLVMIR/LLVMTypes.h"
+#include "mlir/Interfaces/FunctionInterfaces.h"
+#include "triton/Analysis/Alloc... | What is the purpose of this poison here? The usage of poison value is UB. I've encountered a case where a conditional call is optimized out because one of its arg is poison (generated by `TargetInfo::getStackPointer`). |
intel-xpu-backend-for-triton | github_2023 | others | 3,497 | intel | chengjunlu | @@ -375,4 +375,17 @@ tt.func @test(%arg0: tensor<16x32xf32, #mma>) -> tensor<16xf32, #ttg.slice<{dim
"mlir::triton::gpu::TritonGPUDialect"];
}
+def TritonIntelGPURewriteStackPtr
+ : Pass<"tritonintelgpu-rewrite-stack-ptr", "mlir::ModuleOp"> {
+ let summary = "intel rewrite getstackptr... | Add more background of the scratch space on SLM and the different of the calling convention. |
intel-xpu-backend-for-triton | github_2023 | cpp | 3,497 | intel | chengjunlu | @@ -0,0 +1,101 @@
+#include "intel/include/Dialect/TritonIntelGPU/IR/Dialect.h"
+#include "intel/include/Dialect/TritonIntelGPU/Transforms/Passes.h"
+#include "mlir/Dialect/LLVMIR/LLVMDialect.h"
+#include "mlir/Dialect/LLVMIR/LLVMTypes.h"
+#include "mlir/Interfaces/FunctionInterfaces.h"
+#include "triton/Analysis/Alloc... | The SLM parameter is not inserted at the expected place.
There is always a function arg to pass the global scratch spaces in this PR changes.
```
if (!isKernel) {
amendedInputTy.push_back(sharedPtrTy);
}
amendedInputTy.push_back(globalPtrTy);
```
It is not aligned to the launcher. It is not aligned for kerne... |
intel-xpu-backend-for-triton | github_2023 | cpp | 3,224 | intel | chengjunlu | @@ -333,6 +323,23 @@ Value TargetInfo::getGlobalStringStart(Location loc, RewriterBase &rewriter,
return b.gep(globalPtrType, i8_ty, globalPtr, LLVM::GEPArg{0});
}
+Value TargetInfo::getScratchOnSharedMemoryPtr(
+ RewriterBase &rewriter, FunctionOpInterface funcOp) const {
+ auto mod = funcOp->getParentOfType... | Raise error on Intel backend. We haven't support the global scratch memory so far. |
intel-xpu-backend-for-triton | github_2023 | others | 3,575 | intel | whitneywhtsang | @@ -1,6 +1,12 @@
add_mlir_library(TritonAMDGPUTestAnalysis
TestAMDRangeAnalysis.cpp
+ DEPENDS | Can we report or fix this issue upstream? |
intel-xpu-backend-for-triton | github_2023 | others | 3,575 | intel | whitneywhtsang | @@ -26,8 +26,8 @@ module attributes {"ttg.num-ctas" = 1 : i32, "ttg.num-warps" = 32 : i32, "ttg.th
%cst2 = arith.constant dense<0.000000e+00> : tensor<64x32xf16, #dpas2>
// CHECK: ttg.local_alloc
// CHECK: ttg.local_load
- // CHECK-NOT: ttg.convert_layout
%108 = ttg.convert_layout %cst1 : tensor<... | Doesn't this change what we originally wanted to test? |
intel-xpu-backend-for-triton | github_2023 | cpp | 3,575 | intel | whitneywhtsang | @@ -89,7 +75,7 @@ class TritonIntelGPUReduceDataDuplicationPass
sharedOrder.emplace_back(srcOrder[i]);
sharedOrder.emplace_back(0);
} else {
- sharedOrder = std::move(srcOrder);
+ sharedOrder = srcOrder; | keep this change, I think the move is intentionally added. |
intel-xpu-backend-for-triton | github_2023 | python | 2,846 | intel | chengjunlu | @@ -252,9 +252,7 @@ def make_ttgir(mod, metadata, opt, properties):
passes.common.add_cse(pm)
passes.ttgpuir.add_prefetch(pm)
passes.ttgpuir.add_optimize_dot_operands(pm, True)
- if os.getenv("TRITON_INTEL_OPTIMIZE_REDUCTION_LOCALITY", "0") == "1":
- intel.passes.ttgpuir.add... | Can we use `if os.getenv("TRITON_INTEL_OPTIMIZE_REDUCTION_LOCALITY", "1") == "1":` to allow the user to disable it? |
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