repo_name stringlengths 1 62 | dataset stringclasses 1
value | lang stringclasses 11
values | pr_id int64 1 20.1k | owner stringlengths 2 34 | reviewer stringlengths 2 39 | diff_hunk stringlengths 15 262k | code_review_comment stringlengths 1 99.6k |
|---|---|---|---|---|---|---|---|
intel-xpu-backend-for-triton | github_2023 | python | 3,114 | intel | guangyey | @@ -68,6 +69,7 @@ def do_bench_elapsed_time(fn, n_warmup=25, n_repeat=100, grad_to_none=None, quan
fn()
end_event.record()
synchronize()
+ triton.runtime.driver.active.utils.wait() | Yes, you are exactly right! This is a compiler unified runtime bug. I have reported to them and it will be fixed in the next release version. But now, we have to add a `queue.wait` before `elapsed_time` as a WA.
You can add some comments here and remove `queue.wait` after compiler uplift to next release version. |
intel-xpu-backend-for-triton | github_2023 | cpp | 3,165 | intel | LiyangLingIntel | @@ -641,8 +641,26 @@ struct TritonIntelGPUInferLayoutInterface
// Verify that the encodings are valid.
if (!aEncoding || !bEncoding)
return op->emitError("mismatching encoding between A and B operands");
- if (aEncoding.getKWidth() != bEncoding.getKWidth())
- return op->emitError("mismatching k... | ```suggestion
"mismatching parent encoding of B operands");
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 3,165 | intel | whitneywhtsang | @@ -1187,9 +1187,27 @@ LogicalResult DotOperandEncodingAttr::verify(
}
if (auto parentAttr = mlir::dyn_cast<intel::DpasEncodingAttr>(parent)) {
- if (kWidth != parentAttr.getOpsPerChannel())
- return emitError() << "ttg.dot_op kWidth parameter must match the "
- "parent's opsP... | ```suggestion
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 3,165 | intel | whitneywhtsang | @@ -1187,9 +1187,27 @@ LogicalResult DotOperandEncodingAttr::verify(
}
if (auto parentAttr = mlir::dyn_cast<intel::DpasEncodingAttr>(parent)) {
- if (kWidth != parentAttr.getOpsPerChannel())
- return emitError() << "ttg.dot_op kWidth parameter must match the "
- "parent's opsP... | ```suggestion
``` |
intel-xpu-backend-for-triton | github_2023 | others | 3,169 | intel | whitneywhtsang | @@ -249,7 +249,7 @@ jobs:
run: |
cd benchmarks/triton_kernels_benchmark
FA_KERNEL_MODE="bwd" \
- BENCHMARKING_METHOD="ELAPSED_TIME" python flash_attention_benchmark.py --reports $REPORTS
+ python flash_attention_benchmark.py --reports $REPORTS | also need to remove from test-triton.sh |
intel-xpu-backend-for-triton | github_2023 | python | 3,169 | intel | whitneywhtsang | @@ -476,43 +479,46 @@ def forward(ctx, q, k, v, causal, sm_scale):
@staticmethod
def backward(ctx, do):
- q, k, v, o, M = ctx.saved_tensors
- assert do.is_contiguous()
- assert q.stride() == k.stride() == v.stride() == o.stride() == do.stride()
- dq = torch.empty_like(q)
- ... | can we add a FIXME here to undo this change when the problem is fixed, assuming it is not the intended behavior. |
intel-xpu-backend-for-triton | github_2023 | others | 3,166 | intel | anmyachev | @@ -19,6 +19,10 @@ on:
- ELAPSED_TIME
- UPSTREAM_PYTORCH_PROFILER
default: UPSTREAM_PYTORCH_PROFILER
+ no_verify:
+ description: Skip verification of the benchmark results
+ type: boolean
+ default: false | Maybe to simplify? (we can avoid double negatives)
```suggestion
verify:
description: Skip verification of the benchmark results
type: boolean
default: true
``` |
intel-xpu-backend-for-triton | github_2023 | python | 3,166 | intel | anmyachev | @@ -2,9 +2,10 @@
import itertools
import os
-from triton.testing import Benchmark
+from triton.testing import assert_close as triton_assert_close, Benchmark
BENCHMARKING_METHOD = os.getenv("BENCHMARKING_METHOD", "UPSTREAM_PYTORCH_PROFILER")
+NO_VERIFY = os.getenv("NO_VERIFY", "0") == "1" | ```suggestion
VERIFY = os.getenv("VERIFY", "1") == "1"
``` |
intel-xpu-backend-for-triton | github_2023 | python | 3,166 | intel | anmyachev | @@ -161,6 +162,12 @@ def extract_kernels(funcs):
raise NotImplementedError(f"BENCHMARKING_METHOD: {BENCHMARKING_METHOD} isn't implemented")
+def assert_close(x_fn, y_fn, atol=None, rtol=None, err_msg=""):
+ if NO_VERIFY:
+ return
+ triton_assert_close(x_fn(), y_fn(), atol, rtol, err_msg) | ```suggestion
if VERIFY:
triton_assert_close(x_fn(), y_fn(), atol, rtol, err_msg)
``` |
intel-xpu-backend-for-triton | github_2023 | others | 3,166 | intel | anmyachev | @@ -46,6 +50,7 @@ permissions: read-all
env:
PYTHON_VERSION: "3.10"
BENCHMARKING_METHOD: ${{ inputs.benchmarking_method || 'UPSTREAM_PYTORCH_PROFILER' }}
+ NO_VERIFY: ${{ inputs.verify && '0' || '1' }} | ```suggestion
VERIFY: ${{ inputs.verify || '1' }}
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 3,137 | intel | jopperm | @@ -223,9 +223,11 @@ struct PrintOpConversion
llvm::SmallString<64> msgNewline(msg);
msgNewline.push_back('\n');
msgNewline.push_back('\0');
- Value msgValue = LLVM::intel::addStringToModule(
- UnknownLoc::get(rewriter.getContext()), rewriter, "printfFormat_",
- msgNewline, TritonGEN::Tr... | Can you change the member to this type, or does it have to remain a `TargetInfoBase`? |
intel-xpu-backend-for-triton | github_2023 | cpp | 3,137 | intel | jopperm | @@ -312,4 +315,50 @@ Value TargetInfo::getStackPointer(RewriterBase &rewriter,
return funcOp.getArgument(funcOp.getNumArguments() - 1);
}
+Value TargetInfo::getGlobalStringStart(Location loc, RewriterBase &rewriter,
+ StringRef name, StringRef value,
+ ... | Does it matter to have the symbols nicely numbered per name? A simpler way would be just taking `globals.size()`. |
intel-xpu-backend-for-triton | github_2023 | python | 3,135 | intel | anmyachev | @@ -6,15 +6,14 @@
import tempfile
from pathlib import Path
from functools import cached_property
-from typing import Optional
from triton.runtime.build import _build
from triton.runtime.cache import get_cache_manager
from triton.backends.compiler import GPUTarget
from triton.backends.driver import DriverBase
... | Are changes in this file necessary to fix `test_aot.py`? |
intel-xpu-backend-for-triton | github_2023 | python | 3,135 | intel | anmyachev | @@ -28,21 +27,27 @@ def find_sycl(include_dir: list[str]) -> tuple[list[str], Optional[str]]:
AssertionError: if library was not found.
"""
include_dir = include_dir.copy()
+ sycl_dir = None
assertion_message = ("sycl headers not found, please install `icpx` compiler, "
... | Is it easier to read?
```suggestion
compiler_root = os.path.abspath(f"{icpx_path}/../..")
``` |
intel-xpu-backend-for-triton | github_2023 | python | 3,135 | intel | anmyachev | @@ -28,21 +27,27 @@ def find_sycl(include_dir: list[str]) -> tuple[list[str], Optional[str]]:
AssertionError: if library was not found.
"""
include_dir = include_dir.copy()
+ sycl_dir = None
assertion_message = ("sycl headers not found, please install `icpx` compiler, "
... | Why do we need compiler top level include?
```suggestion
include_dir += [os.path.join(compiler_root, "include/sycl")]
``` |
intel-xpu-backend-for-triton | github_2023 | others | 3,108 | intel | chengjunlu | @@ -289,13 +289,25 @@ run_benchmark_attention() {
cd $TRITON_PROJ/benchmarks
python setup.py install
- echo "Default path:"
+ echo "Forward - Default path:"
python $TRITON_PROJ/benchmarks/triton_kernels_benchmark/flash_attention_fwd_benchmark.py
- echo "Advanced path:"
+ echo "Forward - Advanced path:"... | Remove comment out code. |
intel-xpu-backend-for-triton | github_2023 | others | 3,108 | intel | whitneywhtsang | @@ -234,7 +234,32 @@ jobs:
TAG="${TAG}-adv"
source ../../scripts/capture-hw-details.sh
- python ../../scripts/build_report.py $REPORTS/attn-performance.csv $REPORTS/attn-triton-advanced-report.csv --benchmark attn --compiler triton --param_cols "Z,H,N_CTX,D_HEAD,CAUSAL" --tflops_col Tri... | Do you know why? FYI @anmyachev |
intel-xpu-backend-for-triton | github_2023 | others | 3,108 | intel | whitneywhtsang | @@ -234,7 +234,32 @@ jobs:
TAG="${TAG}-adv"
source ../../scripts/capture-hw-details.sh
- python ../../scripts/build_report.py $REPORTS/attn-performance.csv $REPORTS/attn-triton-advanced-report.csv --benchmark attn --compiler triton --param_cols "Z,H,N_CTX,D_HEAD,CAUSAL" --tflops_col Tri... | ```suggestion
``` |
intel-xpu-backend-for-triton | github_2023 | others | 3,108 | intel | whitneywhtsang | @@ -289,13 +289,25 @@ run_benchmark_attention() {
cd $TRITON_PROJ/benchmarks
python setup.py install
- echo "Default path:"
+ echo "Forward - Default path:"
python $TRITON_PROJ/benchmarks/triton_kernels_benchmark/flash_attention_fwd_benchmark.py
- echo "Advanced path:"
+ echo "Forward - Advanced path:"... | ```suggestion
``` |
intel-xpu-backend-for-triton | github_2023 | others | 3,108 | intel | whitneywhtsang | @@ -234,7 +234,32 @@ jobs:
TAG="${TAG}-adv"
source ../../scripts/capture-hw-details.sh
- python ../../scripts/build_report.py $REPORTS/attn-performance.csv $REPORTS/attn-triton-advanced-report.csv --benchmark attn --compiler triton --param_cols "Z,H,N_CTX,D_HEAD,CAUSAL" --tflops_col Tri... | These two lines override attn forward results. |
intel-xpu-backend-for-triton | github_2023 | others | 3,108 | intel | whitneywhtsang | @@ -289,13 +289,18 @@ run_benchmark_attention() {
cd $TRITON_PROJ/benchmarks
python setup.py install
- echo "Default path:"
- python $TRITON_PROJ/benchmarks/triton_kernels_benchmark/flash_attention_fwd_benchmark.py
+ echo "Forward - Default path:"
+ python $TRITON_PROJ/benchmarks/triton_kernels_benchmark/fl... | ```suggestion
python $TRITON_PROJ/benchmarks/triton_kernels_benchmark/flash_attention_benchmark.py
``` |
intel-xpu-backend-for-triton | github_2023 | others | 3,108 | intel | whitneywhtsang | @@ -214,27 +214,39 @@ jobs:
source ../../scripts/capture-hw-details.sh
python ../../scripts/build_report.py $REPORTS/matmul-performance-postop-addmatrix.csv $REPORTS/gemm-postop-addmatrix-triton-report.csv --benchmark gemm-postop-addmatrix --compiler triton --param_cols "B,M,K,N" --tflops_col Trit... | Looks like the reports (attn-triton-report.csv, attn-xetla-report.csv) are still being override
|
intel-xpu-backend-for-triton | github_2023 | others | 3,133 | intel | pbchekin | @@ -113,7 +113,8 @@ runs:
cd pytorch
pip install wheel
pip install -r requirements.txt
- USE_STATIC_MKL=1 CFLAGS="-Wno-error=maybe-uninitialized" python setup.py bdist_wheel
+ USE_STATIC_MKL=1 CFLAGS="-Wno-error=maybe-uninitialized" python setup.py bdist_wheel 2>&1 | grep -v \ | We should try setting, for example, `TORCH_XPU_ARCH_LIST="pvc"` to reduce the number of architectures for AOT compilation. Also since pvc supports fp64 it is possible it will solve the issue you are trying to solve.
|
intel-xpu-backend-for-triton | github_2023 | cpp | 3,113 | intel | whitneywhtsang | @@ -124,8 +125,25 @@ Value createSPIRVGroupOp(RewriterBase &rewriter, Location loc, Type resultTy,
rewriter.getI32IntegerAttr(numLanesToReduce));
}
+ // Extend `i1` values if the operation is not a logical operation. | Should this be part of SPIRV dialect or verification code to ensure i1 is not allowed? |
intel-xpu-backend-for-triton | github_2023 | cpp | 3,113 | intel | whitneywhtsang | @@ -124,8 +125,25 @@ Value createSPIRVGroupOp(RewriterBase &rewriter, Location loc, Type resultTy,
rewriter.getI32IntegerAttr(numLanesToReduce));
}
+ // Extend `i1` values if the operation is not a logical operation.
+ bool isBoolType =
+ resultTy.isInteger() && resultTy.getIntOrFloatBitWidth() == ... | ```suggestion
assert(!(isBoolType && is_spirv_bitwise_group_op_v<GroupOp>) &&
"Unexpected bitwise operation on a Boolean type");
``` |
intel-xpu-backend-for-triton | github_2023 | others | 3,113 | intel | etiotto | @@ -1573,6 +1573,17 @@ module attributes {"ttg.num-ctas" = 1 : i32, "ttg.num-warps" = 1 : i32, "ttg.thr
tt.reduce.return %48 : i32
}) : (tensor<256x1xi32, #blocked>) -> tensor<1xi32, #slice>
+ // CHECK: llvm.zext
+ // CHECK-SAME: : i1 to i8
+ // CHECK: @_Z27__spirv_GroupNonUniformIAddiic | This is brittle because the checks aren't verifying that the extended value is used by the SPIRV call. |
intel-xpu-backend-for-triton | github_2023 | python | 3,040 | intel | whitneywhtsang | @@ -117,7 +130,7 @@ def matmul_kernel_with_block_pointers_batched(
stride_az: tl.constexpr, stride_am: tl.constexpr, stride_ak: tl.constexpr, #
stride_bz: tl.constexpr, stride_bk: tl.constexpr, stride_bn: tl.constexpr, #
stride_cz: tl.constexpr, stride_cm: tl.constexpr, stride_cn: tl.conste... | [nit]
```suggestion
stride_dz: tl.constexpr, stride_dm: tl.constexpr, stride_dn: tl.constexpr, #
ACCUMULATOR_DTYPE: tl.constexpr,
``` |
intel-xpu-backend-for-triton | github_2023 | python | 3,040 | intel | whitneywhtsang | @@ -209,31 +224,31 @@ def matmul(a, b, d, c):
@benchmark_suit.perf_report(
benchmark_suit.Benchmark(
# argument names to use as an x-axis for the plot
- x_names=['B', 'M', 'K', 'N'],
+ x_names=['B', 'M', 'K', 'N', 'dtype'],
# different possible values for `x_name`
- x_vals=[... | [nit] easier to command out shapes when debugging
```suggestion
for shape in [ #
[1, 1, 5120, 13824], #
``` |
intel-xpu-backend-for-triton | github_2023 | python | 3,040 | intel | whitneywhtsang | @@ -209,31 +224,31 @@ def matmul(a, b, d, c):
@benchmark_suit.perf_report(
benchmark_suit.Benchmark(
# argument names to use as an x-axis for the plot
- x_names=['B', 'M', 'K', 'N'],
+ x_names=['B', 'M', 'K', 'N', 'dtype'],
# different possible values for `x_name`
- x_vals=[... | [nit] easier to command out shapes when debugging
```suggestion
[4096, 8, 16384, 128] #
]
``` |
intel-xpu-backend-for-triton | github_2023 | python | 3,040 | intel | whitneywhtsang | @@ -247,29 +262,42 @@ def matmul(a, b, d, c):
# name for the plot. Used also as a file name for saving the plot.
args={},
))
-def benchmark(B, M, N, K, provider):
+def benchmark(B, M, N, K, dtype, provider):
+ res_dtype = torch.float32 if dtype is torch.bfloat16 else torch.int32 | to be consistent with the code above?
```suggestion
res_dtype = torch.float32 if a.dtype.is_floating_point else torch.int32
``` |
intel-xpu-backend-for-triton | github_2023 | python | 3,040 | intel | whitneywhtsang | @@ -247,29 +262,42 @@ def matmul(a, b, d, c):
# name for the plot. Used also as a file name for saving the plot.
args={},
))
-def benchmark(B, M, N, K, provider):
+def benchmark(B, M, N, K, dtype, provider):
+ res_dtype = torch.float32 if dtype is torch.bfloat16 else torch.int32
+ if dtype.... | Should we have a env var for all benchmarks to control if we verify the result?
Don't think we should skip checking correctness for some shapes. |
intel-xpu-backend-for-triton | github_2023 | cpp | 3,118 | intel | whitneywhtsang | @@ -889,6 +950,13 @@ struct TritonRaiseBlockPointer
return success();
}
+ llvm::dbgs() << "operand(line" << __LINE__ << "): " << operand << "\n"; | remove naked print. |
intel-xpu-backend-for-triton | github_2023 | others | 3,121 | intel | whitneywhtsang | @@ -74,6 +74,8 @@ jobs:
uses: ./.github/workflows/build-test-reusable.yml
with:
+ # For this workflow, use max1550 runners to reduce cache consumption on max1100 runners.
+ device: ${{ matrix.driver == 'rolling' && 'max1550' || 'max1100' }} | What's the motivation to control device by driver? |
intel-xpu-backend-for-triton | github_2023 | others | 3,057 | intel | chengjunlu | @@ -235,9 +237,10 @@ module attributes {"ttg.target" = "xpu", "ttg.num-ctas" = 1 : i32, "ttg.num-warp
tt.func @dot_scaled_fp8(%a: tensor<128x32xi8, #blocked2>, %scale: tensor<128x2xi8, #blocked1>, %b: tensor<64x128xf8E4M3FN, #blocked>) -> tensor<128x128xf32, #blocked> {
// CHECK: [[CST:%.*]] = arith.constant de... | There is still `ttg.convert_layout`?
Can we directly output the result type of `ttg.upcast_mxfp` as `tensor<128x64xbf16, #ttg.dot_op<{opIdx = 0, parent = [[DPAS]], kWidth = 2}>>`? So that we can omit the convert layout operation.
|
intel-xpu-backend-for-triton | github_2023 | cpp | 3,057 | intel | etiotto | @@ -63,10 +62,53 @@ class UpcastMXFPOpPattern : public ConvertOpToLLVMPattern<UpcastMXFPOp> {
if (fpType == ScaleDotElemType::E2M1)
xVals = LLVM::convertMxfp4x2ToBf16x2(rewriter, loc, xVals);
+ auto xType = cast<RankedTensorType>(op->getOperandTypes()[0]);
+ auto dotEnc = cast<DotOperandEncodingAttr... | add `constexpr` |
intel-xpu-backend-for-triton | github_2023 | cpp | 3,057 | intel | etiotto | @@ -63,10 +62,53 @@ class UpcastMXFPOpPattern : public ConvertOpToLLVMPattern<UpcastMXFPOp> {
if (fpType == ScaleDotElemType::E2M1)
xVals = LLVM::convertMxfp4x2ToBf16x2(rewriter, loc, xVals);
+ auto xType = cast<RankedTensorType>(op->getOperandTypes()[0]);
+ auto dotEnc = cast<DotOperandEncodingAttr... | add `constexpr` |
intel-xpu-backend-for-triton | github_2023 | cpp | 3,057 | intel | etiotto | @@ -297,83 +293,42 @@ class DecomposeScaledBlocked : public OpRewritePattern<tt::DotScaledOp> {
unsigned opsPerChannel = dpasEnc.getOpsPerChannel();
unsigned rank = retType.getRank();
- if (upcastMXFPUseDotOpEnc) {
- if (opDesc.elemType == tt::ScaleDotElemType::E2M1)
- opsPerChannel *= 2;
-
-... | Remove commented out code |
intel-xpu-backend-for-triton | github_2023 | cpp | 3,057 | intel | etiotto | @@ -531,6 +486,149 @@ static void decomposeMixedModeDotOp(ModuleOp mod) {
});
}
+static void updateValueType(Value v, Attribute encoding,
+ ArrayRef<int64_t> shape) {
+ auto tensorType = cast<RankedTensorType>(v.getType());
+ auto newType =
+ RankedTensorType::get(shape, tensorTy... | ```suggestion
return isa<ttg::ConvertLayoutOp>(op);
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 3,057 | intel | etiotto | @@ -531,6 +486,149 @@ static void decomposeMixedModeDotOp(ModuleOp mod) {
});
}
+static void updateValueType(Value v, Attribute encoding,
+ ArrayRef<int64_t> shape) {
+ auto tensorType = cast<RankedTensorType>(v.getType());
+ auto newType =
+ RankedTensorType::get(shape, tensorTy... | Assert that `dotOp` indeed has a scale in the RHS and no scale on the RHS operand. |
intel-xpu-backend-for-triton | github_2023 | cpp | 3,057 | intel | etiotto | @@ -531,6 +486,149 @@ static void decomposeMixedModeDotOp(ModuleOp mod) {
});
}
+static void updateValueType(Value v, Attribute encoding,
+ ArrayRef<int64_t> shape) {
+ auto tensorType = cast<RankedTensorType>(v.getType());
+ auto newType =
+ RankedTensorType::get(shape, tensorTy... | I think this comment is incorrect. you want to transpose dot operations that have a scale in the RHS, and not scale on the LHS. |
intel-xpu-backend-for-triton | github_2023 | cpp | 3,057 | intel | etiotto | @@ -543,6 +641,8 @@ class TritonIntelGPUAccelerateMatmulPass
ModuleOp m = getOperation();
auto &dpasAnalysis = getAnalysis<ttg::intel::DPASAnalysis>();
+ transposeDots(m); | Add a comment here, suggest: "Transpose `dotOp` operations that have a scale on the RHS. |
intel-xpu-backend-for-triton | github_2023 | cpp | 3,057 | intel | etiotto | @@ -531,6 +486,149 @@ static void decomposeMixedModeDotOp(ModuleOp mod) {
});
}
+static void updateValueType(Value v, Attribute encoding,
+ ArrayRef<int64_t> shape) {
+ auto tensorType = cast<RankedTensorType>(v.getType());
+ auto newType =
+ RankedTensorType::get(shape, tensorTy... | ```suggestion
for (tt::DotScaledOp &dotOp : toTranspose) {
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 3,057 | intel | etiotto | @@ -531,6 +486,149 @@ static void decomposeMixedModeDotOp(ModuleOp mod) {
});
}
+static void updateValueType(Value v, Attribute encoding,
+ ArrayRef<int64_t> shape) {
+ auto tensorType = cast<RankedTensorType>(v.getType());
+ auto newType =
+ RankedTensorType::get(shape, tensorTy... | I think this function should return `tt:TransOp` rather than a pointer (we always expect a transpose operation to be created when this function is invoked). |
intel-xpu-backend-for-triton | github_2023 | cpp | 3,057 | intel | etiotto | @@ -531,6 +486,149 @@ static void decomposeMixedModeDotOp(ModuleOp mod) {
});
}
+static void updateValueType(Value v, Attribute encoding,
+ ArrayRef<int64_t> shape) {
+ auto tensorType = cast<RankedTensorType>(v.getType());
+ auto newType =
+ RankedTensorType::get(shape, tensorTy... | Value -> auto |
intel-xpu-backend-for-triton | github_2023 | cpp | 3,057 | intel | etiotto | @@ -531,6 +486,149 @@ static void decomposeMixedModeDotOp(ModuleOp mod) {
});
}
+static void updateValueType(Value v, Attribute encoding,
+ ArrayRef<int64_t> shape) {
+ auto tensorType = cast<RankedTensorType>(v.getType());
+ auto newType =
+ RankedTensorType::get(shape, tensorTy... | Value -> auto |
intel-xpu-backend-for-triton | github_2023 | cpp | 3,057 | intel | etiotto | @@ -531,6 +486,149 @@ static void decomposeMixedModeDotOp(ModuleOp mod) {
});
}
+static void updateValueType(Value v, Attribute encoding,
+ ArrayRef<int64_t> shape) {
+ auto tensorType = cast<RankedTensorType>(v.getType());
+ auto newType =
+ RankedTensorType::get(shape, tensorTy... | Value -> auto |
intel-xpu-backend-for-triton | github_2023 | cpp | 3,057 | intel | etiotto | @@ -531,6 +486,149 @@ static void decomposeMixedModeDotOp(ModuleOp mod) {
});
}
+static void updateValueType(Value v, Attribute encoding,
+ ArrayRef<int64_t> shape) {
+ auto tensorType = cast<RankedTensorType>(v.getType());
+ auto newType =
+ RankedTensorType::get(shape, tensorTy... | Value -> auto |
intel-xpu-backend-for-triton | github_2023 | cpp | 3,057 | intel | etiotto | @@ -531,6 +486,149 @@ static void decomposeMixedModeDotOp(ModuleOp mod) {
});
}
+static void updateValueType(Value v, Attribute encoding,
+ ArrayRef<int64_t> shape) {
+ auto tensorType = cast<RankedTensorType>(v.getType());
+ auto newType =
+ RankedTensorType::get(shape, tensorTy... | Operation * -> auto |
intel-xpu-backend-for-triton | github_2023 | cpp | 3,057 | intel | etiotto | @@ -531,6 +486,149 @@ static void decomposeMixedModeDotOp(ModuleOp mod) {
});
}
+static void updateValueType(Value v, Attribute encoding,
+ ArrayRef<int64_t> shape) {
+ auto tensorType = cast<RankedTensorType>(v.getType());
+ auto newType =
+ RankedTensorType::get(shape, tensorTy... | Operation * -> tt::TransOp |
intel-xpu-backend-for-triton | github_2023 | cpp | 3,057 | intel | etiotto | @@ -531,6 +486,149 @@ static void decomposeMixedModeDotOp(ModuleOp mod) {
});
}
+static void updateValueType(Value v, Attribute encoding,
+ ArrayRef<int64_t> shape) {
+ auto tensorType = cast<RankedTensorType>(v.getType());
+ auto newType =
+ RankedTensorType::get(shape, tensorTy... | Operation * -> tt::TransOp |
intel-xpu-backend-for-triton | github_2023 | cpp | 3,057 | intel | etiotto | @@ -531,6 +486,149 @@ static void decomposeMixedModeDotOp(ModuleOp mod) {
});
}
+static void updateValueType(Value v, Attribute encoding,
+ ArrayRef<int64_t> shape) {
+ auto tensorType = cast<RankedTensorType>(v.getType());
+ auto newType =
+ RankedTensorType::get(shape, tensorTy... | Remove the cast here |
intel-xpu-backend-for-triton | github_2023 | cpp | 3,057 | intel | etiotto | @@ -531,6 +486,149 @@ static void decomposeMixedModeDotOp(ModuleOp mod) {
});
}
+static void updateValueType(Value v, Attribute encoding,
+ ArrayRef<int64_t> shape) {
+ auto tensorType = cast<RankedTensorType>(v.getType());
+ auto newType =
+ RankedTensorType::get(shape, tensorTy... | OK, add a TODO marker so is easy to grep for it. |
intel-xpu-backend-for-triton | github_2023 | cpp | 3,057 | intel | etiotto | @@ -531,6 +486,149 @@ static void decomposeMixedModeDotOp(ModuleOp mod) {
});
}
+static void updateValueType(Value v, Attribute encoding,
+ ArrayRef<int64_t> shape) {
+ auto tensorType = cast<RankedTensorType>(v.getType());
+ auto newType =
+ RankedTensorType::get(shape, tensorTy... | If `result` has no users in `slice` this function would return a bogus `TransOp`. This is not ideal. Can you make this function return `std::optional<tt::TransOp>` instead ? |
intel-xpu-backend-for-triton | github_2023 | cpp | 3,057 | intel | etiotto | @@ -531,6 +486,149 @@ static void decomposeMixedModeDotOp(ModuleOp mod) {
});
}
+static void updateValueType(Value v, Attribute encoding,
+ ArrayRef<int64_t> shape) {
+ auto tensorType = cast<RankedTensorType>(v.getType());
+ auto newType =
+ RankedTensorType::get(shape, tensorTy... | Add message to all assets. |
intel-xpu-backend-for-triton | github_2023 | cpp | 3,057 | intel | etiotto | @@ -531,6 +486,149 @@ static void decomposeMixedModeDotOp(ModuleOp mod) {
});
}
+static void updateValueType(Value v, Attribute encoding,
+ ArrayRef<int64_t> shape) {
+ auto tensorType = cast<RankedTensorType>(v.getType());
+ auto newType =
+ RankedTensorType::get(shape, tensorTy... | Instead of asserting the previous line can just `cast` instead of `dyn_cast`. |
intel-xpu-backend-for-triton | github_2023 | others | 2,746 | intel | LiyangLingIntel | @@ -23,43 +24,147 @@ The encoding is characterized by parameters:
- `systolicDepth` For PVC/ATSM, the size is 8.
- `executionSize` For PVC, the size is 16. For ATSM, the size is 8.
- `opsPerChannel` 4 for 8 bit scalar type, 2 for 16 bit scalar type, 1 for 32 bit scalar type.
- - `warps... | Yes, for rank 3 the order would be [2, 1, 0]. |
intel-xpu-backend-for-triton | github_2023 | others | 2,746 | intel | jopperm | @@ -23,43 +24,147 @@ The encoding is characterized by parameters:
- `systolicDepth` For PVC/ATSM, the size is 8.
- `executionSize` For PVC, the size is 16. For ATSM, the size is 8.
- `opsPerChannel` 4 for 8 bit scalar type, 2 for 16 bit scalar type, 1 for 32 bit scalar type.
- - `warps... | Typo: sugGroupSize |
intel-xpu-backend-for-triton | github_2023 | others | 2,746 | intel | jopperm | @@ -23,43 +24,147 @@ The encoding is characterized by parameters:
- `systolicDepth` For PVC/ATSM, the size is 8.
- `executionSize` For PVC, the size is 16. For ATSM, the size is 8.
- `opsPerChannel` 4 for 8 bit scalar type, 2 for 16 bit scalar type, 1 for 32 bit scalar type.
- - `warps... | What do you mean by "value name" here? |
intel-xpu-backend-for-triton | github_2023 | others | 2,746 | intel | jopperm | @@ -23,43 +24,147 @@ The encoding is characterized by parameters:
- `systolicDepth` For PVC/ATSM, the size is 8.
- `executionSize` For PVC, the size is 16. For ATSM, the size is 8.
- `opsPerChannel` 4 for 8 bit scalar type, 2 for 16 bit scalar type, 1 for 32 bit scalar type.
- - `warps... | Typo: sugGroupSize |
intel-xpu-backend-for-triton | github_2023 | others | 2,746 | intel | jopperm | @@ -23,43 +24,147 @@ The encoding is characterized by parameters:
- `systolicDepth` For PVC/ATSM, the size is 8.
- `executionSize` For PVC, the size is 16. For ATSM, the size is 8.
- `opsPerChannel` 4 for 8 bit scalar type, 2 for 16 bit scalar type, 1 for 32 bit scalar type.
- - `warps... | What does it mean to have fewer repetitions for the A and B tiles, and independent numbering? Shouldn't for example the top-left tile of B labeled something like "R0|R8"? |
intel-xpu-backend-for-triton | github_2023 | others | 2,746 | intel | etiotto | @@ -23,43 +24,147 @@ The encoding is characterized by parameters:
- `systolicDepth` For PVC/ATSM, the size is 8.
- `executionSize` For PVC, the size is 16. For ATSM, the size is 8.
- `opsPerChannel` 4 for 8 bit scalar type, 2 for 16 bit scalar type, 1 for 32 bit scalar type.
- - `warps... | In these examples, it would be helpful to fully declare the matrix. Here you say opsPerChannel==2, so the element type of the matrices would have to be 16 bits wide. So we would have:
```
A: tensor<8x16xfp16>
B: tensor<16x16xbf16>
D: tensor<8x16xbf16>
```
And the DPAS encoding would be:
```
DpasEncoding: tr... |
intel-xpu-backend-for-triton | github_2023 | others | 2,746 | intel | etiotto | @@ -23,43 +24,147 @@ The encoding is characterized by parameters:
- `systolicDepth` For PVC/ATSM, the size is 8.
- `executionSize` For PVC, the size is 16. For ATSM, the size is 8.
- `opsPerChannel` 4 for 8 bit scalar type, 2 for 16 bit scalar type, 1 for 32 bit scalar type.
- - `warps... | Same as my previous comment. I think this fits but please confirm:
```
A: tensor<8x8xf32>
B: tensor<8x16xf32>
D: tensor<8x8xf32>
dpasEncoding: triton_intel_gpu.dpas<{repeatCount = 8, systolicDepth = 8, executionSize = 16, opsPerChannel = 1, threadsPerWarp = 16, warpsPerCTA = [1,1] , repCluster = [1,1]}>
``` |
intel-xpu-backend-for-triton | github_2023 | others | 2,746 | intel | etiotto | @@ -23,43 +24,147 @@ The encoding is characterized by parameters:
- `systolicDepth` For PVC/ATSM, the size is 8.
- `executionSize` For PVC, the size is 16. For ATSM, the size is 8.
- `opsPerChannel` 4 for 8 bit scalar type, 2 for 16 bit scalar type, 1 for 32 bit scalar type.
- - `warps... | += --> = |
intel-xpu-backend-for-triton | github_2023 | others | 2,746 | intel | etiotto | @@ -23,43 +24,147 @@ The encoding is characterized by parameters:
- `systolicDepth` For PVC/ATSM, the size is 8.
- `executionSize` For PVC, the size is 16. For ATSM, the size is 8.
- `opsPerChannel` 4 for 8 bit scalar type, 2 for 16 bit scalar type, 1 for 32 bit scalar type.
- - `warps... | Why is `opsPerChannel` equal to 4 ? It depends on the type of the matrix element, not on the width of the column, right ? |
intel-xpu-backend-for-triton | github_2023 | others | 2,746 | intel | etiotto | @@ -23,43 +24,147 @@ The encoding is characterized by parameters:
- `systolicDepth` For PVC/ATSM, the size is 8.
- `executionSize` For PVC, the size is 16. For ATSM, the size is 8.
- `opsPerChannel` 4 for 8 bit scalar type, 2 for 16 bit scalar type, 1 for 32 bit scalar type. | Scalar type of which operand? Should be of the A and B operands (which must have the same element type). Please clarify |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,746 | intel | etiotto | @@ -168,7 +168,7 @@ emitOffsetForDpasLayoutPerCTA(const DpasEncodingAttr &dpasLayout,
sizePerThreads[rank - 2] / repCluster[rank - 2],
sizePerThreads[rank - 1] / repCluster[rank - 1]};
- unsigned rowsPerElem = dpasLayout.getSubGroupSize() / instShapeC[1];
+ unsigned rowsPerElem = dpasLayout.getThreads... | Why the trailing underscore ? |
intel-xpu-backend-for-triton | github_2023 | others | 2,746 | intel | whitneywhtsang | @@ -14,52 +14,168 @@ def DpasEncodingAttr : DistributedEncoding<"DpasEncoding", "intel_dpas_encoding"
let mnemonic = "dpas";
let description = [{
-An encoding for the tensors distributed across the threads for the C and D operands of XMX tensor core operation.
+An encoding for the tensors distributed across the... | When is it possible that threads per warp is different between the dpas layout and distributed layout? And is it possible that the layout threads per warp is different from the module threads per warp attribute? |
intel-xpu-backend-for-triton | github_2023 | others | 2,746 | intel | whitneywhtsang | @@ -14,52 +14,168 @@ def DpasEncodingAttr : DistributedEncoding<"DpasEncoding", "intel_dpas_encoding"
let mnemonic = "dpas";
let description = [{
-An encoding for the tensors distributed across the threads for the C and D operands of XMX tensor core operation.
+An encoding for the tensors distributed across the... | consistency
```suggestion
t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 | M = 8 (M = repeat count)
``` |
intel-xpu-backend-for-triton | github_2023 | others | 2,746 | intel | whitneywhtsang | @@ -14,52 +14,168 @@ def DpasEncodingAttr : DistributedEncoding<"DpasEncoding", "intel_dpas_encoding"
let mnemonic = "dpas";
let description = [{
-An encoding for the tensors distributed across the threads for the C and D operands of XMX tensor core operation.
+An encoding for the tensors distributed across the... | consistency
```suggestion
t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 | M = 8 (M = repeat count)
``` |
intel-xpu-backend-for-triton | github_2023 | others | 2,746 | intel | whitneywhtsang | @@ -14,52 +14,168 @@ def DpasEncodingAttr : DistributedEncoding<"DpasEncoding", "intel_dpas_encoding"
let mnemonic = "dpas";
let description = [{
-An encoding for the tensors distributed across the threads for the C and D operands of XMX tensor core operation.
+An encoding for the tensors distributed across the... | ```suggestion
t0 t1 t2 t3 t4 t5 t6 t7 | M = 8 (M = repeat count)
``` |
intel-xpu-backend-for-triton | github_2023 | others | 2,746 | intel | whitneywhtsang | @@ -14,52 +14,168 @@ def DpasEncodingAttr : DistributedEncoding<"DpasEncoding", "intel_dpas_encoding"
let mnemonic = "dpas";
let description = [{
-An encoding for the tensors distributed across the threads for the C and D operands of XMX tensor core operation.
+An encoding for the tensors distributed across the... | ```suggestion
t0 t0 t1 t1 t2 t2 t3 t3 t4 t4 t5 t5 t6 t6 t7 t7 t8 t8 t9 t9 t10 t10 t11 t11 t12 t12 t13 t13 t14 t14 t15 t15 | M = 8 (M = repeat count)
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,746 | intel | whitneywhtsang | @@ -334,7 +334,7 @@ struct ConvertLayoutOpConversion
size_t totalElems = elems.size();
auto numElemsPerOperand =
product<unsigned>(dpasLayout.getDPASInstShapeC()) /
- dpasLayout.getSubGroupSize();
+ product<unsigned>(dpasLayout.getThreadsPerWarp()); | why not use `getThreadsPerWarp_`? |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,746 | intel | whitneywhtsang | @@ -37,7 +37,7 @@ class DotOpDPASConversionHelper {
Type i16Ty = type::i16Ty(ctx);
Type s32Ty = IntegerType::get(ctx, 32, IntegerType::Signed);
- unsigned threadsPerWarp = layout.getSubGroupSize();
+ unsigned threadsPerWarp = product<unsigned>(layout.getThreadsPerWarp()); | why not use `getThreadsPerWarp_`? |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,746 | intel | whitneywhtsang | @@ -120,7 +120,8 @@ emitOffsetForDpasLayoutPerCTA(const DpasEncodingAttr &dpasLayout,
sizePerThreads[rank - 2] / repCluster[rank - 2],
sizePerThreads[rank - 1] / repCluster[rank - 1]};
- unsigned rowsPerElem = dpasLayout.getSubGroupSize() / instShapeC[1];
+ unsigned rowsPerElem =
+ product<unsign... | why not use `getThreadsPerWarp_`? |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,746 | intel | whitneywhtsang | @@ -237,11 +238,12 @@ struct DpasOperandPattern final : OpRewritePattern<ReduceOp> {
// We want to transpose matrices of N*threads_per_warpxthreads_per_warp
// shape.
+ unsigned threadsPerWarp = product<unsigned>(encoding.getThreadsPerWarp()); | why not use `getThreadsPerWarp_`? |
intel-xpu-backend-for-triton | github_2023 | python | 3,111 | intel | LiyangLingIntel | @@ -3308,7 +3308,10 @@ def test_dot(M, N, K, num_warps, col_a, col_b, epilogue, input_precision, in_dty
if in_dtype == 'bfloat16':
pytest.xfail("bfloat16 is not supported in the interpreter")
else:
- if not is_hip() and (M < 16 or N < 16 or K < 16):
+ if is_xpu():
+ i... | ```suggestion
if not is_hip() and (M < 16 or N < 16 or K < 16):
```
Use `if not is_hip()` to align with `if is_xpu` and `if is_cuda()` |
intel-xpu-backend-for-triton | github_2023 | python | 3,088 | intel | chengjunlu | @@ -6547,7 +6545,9 @@ def inject_layout(ir, src: torch.Tensor, axis, indices: torch.Tensor, src_layout
temp_file.write_text(ir)
kernel = triton.compile(str(temp_file))
- assert ("nvvm.shfl.sync.idx" in kernel.asm["llir"]) or ("llvm.amdgcn.ds.bpermute" in kernel.asm["llir"])
+ print(kernel.asm["llir"]) | Remove the extra `print` |
intel-xpu-backend-for-triton | github_2023 | c | 3,089 | intel | whitneywhtsang | @@ -31,7 +33,7 @@ static PyObject *parseDeviceArch(PyObject *self, PyObject *args) {
arch = "lnl";
break;
default:
- printf("sycl_arch = %d", sycl_arch);
+ std::cerr << "sycl_arch not recognized: " << (int)sycl_arch << std::endl; | Given that this is a C file, should we use `fprintf(stderr...`? |
intel-xpu-backend-for-triton | github_2023 | others | 2,953 | intel | pbchekin | @@ -197,6 +197,12 @@ run_core_tests() {
# run test_line_info.py separately with TRITON_DISABLE_LINE_INFO=0
TRITON_DISABLE_LINE_INFO=0 TRITON_TEST_SUITE=line_info \
pytest -k "not test_line_info_interpreter" --verbose --device xpu language/test_line_info.py
+
+ TRITON_DISABLE_LINE_INFO=1 TRITON_TEST_SUITE=to... | `TRITON_TEST_SUITE` needs to be unique, otherwise report from the first run will be overwritten by the second one.
```suggestion
TRITON_DISABLE_LINE_INFO=1 TRITON_TEST_SUITE=tools \
pytest --verbose --device xpu tools/test_disasm.py tools/test_aot.py
``` |
intel-xpu-backend-for-triton | github_2023 | python | 2,953 | intel | pbchekin | @@ -98,18 +101,37 @@ def kernel(C, A, B, M, N, K,
def gen_kernel_library(dir, libname):
- c_files = glob.glob(os.path.join(dir, "*.c"))
- subprocess.run(
- ["gcc"] + c_files + ["-I", include_dir[0], "-c", "-fPIC"],
- check=True,
- cwd=dir,
- )
- o_files = glob.glob(os.path.join(dir... | May be to minimize changes and simplify future potential merges
```suggestion
if is_xpu():
gen_kernel_library_xpu(dir, libname)
```
and keep the rest of the function as the original? |
intel-xpu-backend-for-triton | github_2023 | python | 2,953 | intel | pbchekin | @@ -330,7 +457,7 @@ def test_compile_link_matmul():
# run test case
env = os.environ.copy()
- env["LD_LIBRARY_PATH"] = tmp_dir
+ env["LD_LIBRARY_PATH"] = tmp_dir + ":" + env.get("LD_LIBRARY_PATH") | What if `LD_LIBRARY_PATH` is not set? At least we can do `env.get("LD_LIBRARY_PATH", "")`. |
intel-xpu-backend-for-triton | github_2023 | python | 2,953 | intel | pbchekin | @@ -361,7 +488,7 @@ def test_launcher_has_no_available_kernel():
# run test case
env = os.environ.copy()
- env["LD_LIBRARY_PATH"] = tmp_dir
+ env["LD_LIBRARY_PATH"] = tmp_dir + ":" + env.get("LD_LIBRARY_PATH") | What if `LD_LIBRARY_PATH` is not set? At least we can do `env.get("LD_LIBRARY_PATH", "")`. |
intel-xpu-backend-for-triton | github_2023 | python | 2,953 | intel | pbchekin | @@ -410,7 +537,7 @@ def test_compile_link_autotune_matmul():
gen_test_bin(tmp_dir, M, N, K, exe=test_name, algo_id=algo_id)
env = os.environ.copy()
- env["LD_LIBRARY_PATH"] = tmp_dir
+ env["LD_LIBRARY_PATH"] = tmp_dir + ":" + env.get("LD_LIBRARY_PATH") | What if `LD_LIBRARY_PATH` is not set? At least we can do `env.get("LD_LIBRARY_PATH", "")`.
|
intel-xpu-backend-for-triton | github_2023 | python | 2,953 | intel | pbchekin | @@ -75,12 +75,36 @@ def get_sass(cubin_asm, fun=None):
return sass
+@functools.lru_cache()
+def get_spvdis(spvbin_asm):
+ fd, path = tempfile.mkstemp()
+ try:
+ with open(fd, 'wb') as spvbin:
+ spvbin.write(spvbin_asm)
+ dis = extract_spvbin(path)
+ finally:
+ os.remove... | Does this work (looks simpler)?
```suggestion
spv_str = subprocess.check_output([dis, file_path], text=True)
``` |
intel-xpu-backend-for-triton | github_2023 | python | 2,953 | intel | pbchekin | @@ -36,7 +38,7 @@ def __init__(self) -> None:
# [name, hash, suffix]
self.kernel_name = re.compile("^([\\w]+)_([\\w]+)_([\\w]+)$")
# [(type, name)]
- self.c_sig = re.compile("[\\s]*(\\w+)\\s(\\w+)[,]?")
+ self.c_sig = re.compile(r"\s*(\w+\*?)\s+(\w+)[,]?\s*") | The regex is different from the original. Can you update a comment (or add an example) for what we are matching. Also:
```suggestion
self.c_sig = re.compile(r"\s*(\w+\*?)\s+(\w+),?\s*")
``` |
intel-xpu-backend-for-triton | github_2023 | python | 2,953 | intel | pbchekin | @@ -132,27 +134,46 @@ def gen_signature(m):
# generate declarations of kernels with meta-parameter and constant values
def make_algo_decls(name: str, metas: Sequence[KernelLinkerMeta]) -> str:
- return f"""
+ if is_cuda():
+ return f"""
CUresult {name}(CUstream stream, {gen_signature_with_full_args(me... | ```suggestion
src += f" return {meta.orig_kernel_name}(stream, {', '.join(meta.arg_names)}, 0);\n"
``` |
intel-xpu-backend-for-triton | github_2023 | python | 2,953 | intel | pbchekin | @@ -132,27 +134,46 @@ def gen_signature(m):
# generate declarations of kernels with meta-parameter and constant values
def make_algo_decls(name: str, metas: Sequence[KernelLinkerMeta]) -> str:
- return f"""
+ if is_cuda():
+ return f"""
CUresult {name}(CUstream stream, {gen_signature_with_full_args(me... | ```suggestion
src += f" return {meta.orig_kernel_name}(stream, {', '.join(meta.arg_names)}, 0);\n"
``` |
intel-xpu-backend-for-triton | github_2023 | python | 2,953 | intel | pbchekin | @@ -161,18 +182,32 @@ def make_default_algo_kernel(meta: KernelLinkerMeta) -> str:
def make_kernel_hints_dispatcher(name: str, metas: Sequence[KernelLinkerMeta]) -> str:
src = f"// launcher for: {name}\n"
for meta in sorted(metas, key=lambda m: -m.num_specs):
- src += f"CUresult {meta.orig_kernel_name... | ```suggestion
src += f"CUresult {name}(CUstream stream, {gen_signature_with_full_args(metas[-1])}){{"
``` |
intel-xpu-backend-for-triton | github_2023 | python | 2,953 | intel | pbchekin | @@ -161,18 +182,32 @@ def make_default_algo_kernel(meta: KernelLinkerMeta) -> str:
def make_kernel_hints_dispatcher(name: str, metas: Sequence[KernelLinkerMeta]) -> str:
src = f"// launcher for: {name}\n"
for meta in sorted(metas, key=lambda m: -m.num_specs):
- src += f"CUresult {meta.orig_kernel_name... | ```suggestion
src += f"int32_t {name}(sycl::queue &stream, {gen_signature_with_full_args(metas[-1])}){{"
``` |
intel-xpu-backend-for-triton | github_2023 | python | 2,953 | intel | etiotto | @@ -642,9 +642,9 @@ def run(self):
package_data = {
- "triton/tools": ["compile.h", "compile.c"], **{f"triton/backends/{b.name}": b.package_data
- for b in backends}, "triton/language/extra": sum(
- (b.language_package_data for b in backends), [])
+ "t... | Reduce formatting differences so that it is easier to compare the actual difference with upstream code. |
intel-xpu-backend-for-triton | github_2023 | python | 2,953 | intel | etiotto | @@ -5,10 +5,13 @@
import tempfile
import numpy as np
+import pytest | Do we need this import? It is not required upstream. |
intel-xpu-backend-for-triton | github_2023 | python | 2,953 | intel | etiotto | @@ -299,9 +428,9 @@ def test_compile_link_matmul_no_specialization():
# run test case
env = os.environ.copy()
- env["LD_LIBRARY_PATH"] = tmp_dir
- subprocess.run(["./test", a_path, b_path, c_path], env=env, check=True, cwd=tmp_dir)
+ env["LD_LIBRARY_PATH"] = tmp_dir + ":" + env.... | Remove empty line to minimize diffs |
intel-xpu-backend-for-triton | github_2023 | python | 2,953 | intel | etiotto | @@ -299,9 +428,9 @@ def test_compile_link_matmul_no_specialization():
# run test case
env = os.environ.copy()
- env["LD_LIBRARY_PATH"] = tmp_dir
- subprocess.run(["./test", a_path, b_path, c_path], env=env, check=True, cwd=tmp_dir)
+ env["LD_LIBRARY_PATH"] = tmp_dir + ":" + env.... | upstream the overwrite LD_LIBRARY_PATH while we need to prepend to it. What is the reason? |
intel-xpu-backend-for-triton | github_2023 | python | 2,953 | intel | etiotto | @@ -181,9 +216,15 @@ def make_kernel_hints_dispatcher(name: str, metas: Sequence[KernelLinkerMeta]) -
src += (f" if ({conds})\n" if any(meta.sizes) else "if (1)\n"
) # Edge case where no specializations hence no dispatching required
arg_names = [arg for arg, hint in zip(meta.arg_nam... | Can we use a variable rather than "-6" here ? |
intel-xpu-backend-for-triton | github_2023 | python | 2,953 | intel | etiotto | @@ -161,18 +182,32 @@ def make_default_algo_kernel(meta: KernelLinkerMeta) -> str:
def make_kernel_hints_dispatcher(name: str, metas: Sequence[KernelLinkerMeta]) -> str:
src = f"// launcher for: {name}\n"
for meta in sorted(metas, key=lambda m: -m.num_specs):
- src += f"CUresult {meta.orig_kernel_name... | split this line and put `if hint == 16 #` on the next line (similar to upstream implementation) |
intel-xpu-backend-for-triton | github_2023 | python | 2,953 | intel | etiotto | @@ -132,27 +134,46 @@ def gen_signature(m):
# generate declarations of kernels with meta-parameter and constant values
def make_algo_decls(name: str, metas: Sequence[KernelLinkerMeta]) -> str:
- return f"""
+ if is_cuda(): | Can we remove the check `is_cuda()` ? |
intel-xpu-backend-for-triton | github_2023 | python | 2,953 | intel | etiotto | @@ -132,27 +134,46 @@ def gen_signature(m):
# generate declarations of kernels with meta-parameter and constant values
def make_algo_decls(name: str, metas: Sequence[KernelLinkerMeta]) -> str:
- return f"""
+ if is_cuda():
+ return f"""
CUresult {name}(CUstream stream, {gen_signature_with_full_args(me... | Can we remove the check `is_cuda()` ? |
intel-xpu-backend-for-triton | github_2023 | others | 3,078 | intel | anmyachev | @@ -73,7 +73,21 @@ jobs:
- name: Pass rate
run: |
pip install defusedxml
- python scripts/pass_rate.py --reports reports --skip-list scripts/skiplist/a770
+ Invoke-BatchFile "C:\Program Files (x86)\Intel\oneAPI\setvars.bat"
+ bash -c "\
+ source ./scripts... | Do we need this? |
intel-xpu-backend-for-triton | github_2023 | cpp | 2,720 | intel | etiotto | @@ -27,11 +27,12 @@ class AxisInfo {
public:
AxisInfo() : AxisInfo({}, {}, {}) {}
- AxisInfo(DimVectorT contiguity, DimVectorT divisibility, DimVectorT constancy)
+ AxisInfo(ArrayRef<int64_t> contiguity, ArrayRef<int64_t> divisibility, | Common file so changes should be done upsrteam. |
intel-xpu-backend-for-triton | github_2023 | python | 2,264 | intel | etiotto | @@ -166,10 +166,10 @@ def do_bench(fn, warmup=25, rep=100, grad_to_none=None, quantiles=None, fast_flu
fn()
di.synchronize()
- # We maintain a buffer of 256 MB that we clear
+ # We maintain a buffer of 512 MB that we clear
# before each kernel call to make sure that the L2 cache
# doesn't co... | PyTorch passes device properties. Wondering if we can use `info::device::global_mem_cache_size` to determine the size of the cache here somehow |
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